board:origen: Enable device tree on Origen

This patch enables to run Origen board on device tree. Uart, DRAM and MMC init functions are removed as their generic replacements form the common board file are used. The config file is modified to contain only board specific options. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Chander Kashyap <k.chander@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

board:origen: Enable device tree on Origen
This patch enables to run Origen board on device tree. Uart, DRAM and MMC init functions are removed as their generic replacements form the common board file are used. The config file is modified to contain only board specific options. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Chander Kashyap <k.chander@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Piotr Wilczek · Minkyu Kang
1 parent 431a1c569c
Showing 4 changed files with 87 additions and 182 deletions Side-by-side Diff
arch/arm/dts/Makefile
arch/arm/dts/exynos4210-origen.dts
board/samsung/origen/origen.c
include/configs/origen.h
+dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb
+
 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 	exynos5250-snow.dtb \
 	exynos5250-smdk5250.dtb \
+/*
+ * Samsung's Exynos4210 based Origen board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+/include/ "exynos4.dtsi"
+
+/ {
+	model = "Insignal Origen evaluation board based on Exynos4210";
+	compatible = "insignal,origen", "samsung,exynos4210";
+
+	chosen {
+		bootargs ="";
+	};
+
+	aliases {
+		serial0 = "/serial@13800000";
+		console = "/serial@13820000";
+		mmc2 = "sdhci@12530000";
+	};
+
+	sdhci@12510000 {
+		status = "disabled";
+	};
+
+	sdhci@12520000 {
+		status = "disabled";
+	};
+
+	sdhci@12530000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		cd-gpios = <&gpio 0x2008002 0>;
+	};
+
+	sdhci@12540000 {
+		status = "disabled";
+	};
+};
@@ -11,130 +11,36 @@
 #include <asm/arch/mmc.h>
 #include <asm/arch/periph.h>
 #include <asm/arch/pinmux.h>
+#include <usb.h>
  
 DECLARE_GLOBAL_DATA_PTR;
-struct exynos4_gpio_part1 *gpio1;
-struct exynos4_gpio_part2 *gpio2;
  
-int board_init(void)
+u32 get_board_rev(void)
 {
-	gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
-	gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
-
-	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
 	return 0;
 }
  
-static int board_uart_init(void)
+int exynos_init(void)
 {
-	int err;
-
-	err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("UART0 not configured\n");
-		return err;
-	}
-
-	err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("UART1 not configured\n");
-		return err;
-	}
-
-	err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("UART2 not configured\n");
-		return err;
-	}
-
-	err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("UART3 not configured\n");
-		return err;
-	}
-
 	return 0;
 }
  
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
+int board_usb_init(int index, enum usb_init_type init)
 {
-	int err;
-	err = board_uart_init();
-	if (err) {
-		debug("UART init failed\n");
-		return err;
-	}
-	return err;
-}
-#endif
-
-int dram_init(void)
-{
-	gd->ram_size	= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
-			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
-			+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
-			+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
-
 	return 0;
 }
  
-void dram_init_banksize(void)
+#ifdef CONFIG_USB_CABLE_CHECK
+int usb_cable_connected(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
-							PHYS_SDRAM_1_SIZE);
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
-							PHYS_SDRAM_2_SIZE);
-	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
-	gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
-							PHYS_SDRAM_3_SIZE);
-	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
-	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
-							PHYS_SDRAM_4_SIZE);
-}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
-	printf("\nBoard: ORIGEN\n");
 	return 0;
 }
 #endif
  
-#ifdef CONFIG_GENERIC_MMC
-int board_mmc_init(bd_t *bis)
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int exynos_early_init_f(void)
 {
-	int i, err;
-
-	/*
-	 * MMC2 SD card GPIO:
-	 *
-	 * GPK2[0]	SD_2_CLK(2)
-	 * GPK2[1]	SD_2_CMD(2)
-	 * GPK2[2]	SD_2_CDn
-	 * GPK2[3:6]	SD_2_DATA[0:3](2)
-	 */
-	for (i = 0; i < 7; i++) {
-		/* GPK2[0:6] special function 2 */
-		s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
-
-		/* GPK2[0:6] drv 4x */
-		s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
-
-		/* GPK2[0:1] pull disable */
-		if (i == 0 || i == 1) {
-			s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
-			continue;
-		}
-
-		/* GPK2[2:6] pull up */
-		s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
-	}
-
-	err = s5p_mmc_init(2, 4);
-	return err;
+	return 0;
 }
 #endif
@@ -6,115 +6,71 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
  
-#ifndef __CONFIG_H
-#define __CONFIG_H
+#ifndef __CONFIG_ORIGEN_H
+#define __CONFIG_ORIGEN_H
  
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT		"ORIGEN # "
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-origen
+
 /* High Level Configuration Options */
-#define CONFIG_SAMSUNG			1	/* SAMSUNG core */
-#define CONFIG_S5P			1	/* S5P Family */
 #define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
 #define CONFIG_ORIGEN			1	/* working with ORIGEN*/
  
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-
-#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_EARLY_INIT_F
-
 #define CONFIG_SYS_DCACHE_OFF		1
  
+/* ORIGEN has 4 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS		4
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
-#define CONFIG_SYS_TEXT_BASE		0x43E00000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
  
-/* input clock of PLL: ORIGEN has 24MHz input clock */
-#define CONFIG_SYS_CLK_FREQ		24000000
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
  
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
  
 #define CONFIG_MACH_TYPE		MACH_TYPE_ORIGEN
  
-/* Power Down Modes */
-#define S5P_CHECK_SLEEP			0x00000BAD
-#define S5P_CHECK_DIDLE			0xBAD00000
-#define S5P_CHECK_LPA			0xABAD0000
-
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
  
 /* select serial console configuration */
-#define CONFIG_SERIAL2			1	/* use SERIAL 2 */
+#define CONFIG_SERIAL2
 #define CONFIG_BAUDRATE			115200
-#define EXYNOS4_DEFAULT_UART_OFFSET	0x020000
  
-#define CONFIG_SKIP_LOWLEVEL_INIT
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
  
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_S5P_SDHCI
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
  
-/* PWM */
-#define CONFIG_PWM			1
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
  
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
  
-/* Command definition*/
-#include <config_cmd_default.h>
-
 #undef CONFIG_CMD_PING
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_FAT
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_NFS
  
-#define CONFIG_BOOTDELAY		3
-#define CONFIG_ZERO_BOOTDELAY_CHECK
 /* MMC SPL */
 #define CONFIG_SPL
 #define COPY_BL2_FNPTR_ADDR	0x02020030
-
 #define CONFIG_SPL_TEXT_BASE	0x02021410
  
 #define CONFIG_BOOTCOMMAND	"fatload mmc 0 40007000 uImage; bootm 40007000"
  
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
-#define CONFIG_SYS_PROMPT		"ORIGEN # "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size*/
-#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
-/* ORIGEN has 4 bank of DRAM */
-#define CONFIG_NR_DRAM_BANKS	4
-#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
-#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
-#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
-#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
-#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
-#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
-
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH		1
-#undef CONFIG_CMD_IMLS
 #define CONFIG_IDENT_STRING		" for ORIGEN"
  
 #define CONFIG_CLK_1000_400_200
  
@@ -122,13 +78,12 @@
 /* MIU (Memory Interleaving Unit) */
 #define CONFIG_MIU_2BIT_21_7_INTERLEAVED
  
-#define CONFIG_ENV_IS_IN_MMC		1
+#define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KB */
 #define RESERVE_BLOCK_SIZE		(512)
 #define BL1_SIZE			(16 << 10) /*16 K reserved for BL1*/
 #define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
-#define CONFIG_DOS_PARTITION		1
  
 #define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
 #define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
@@ -139,9 +94,6 @@
 #define COPY_BL2_SIZE		0x80000
 #define BL2_START_OFFSET	((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
 #define BL2_SIZE_BLOC_COUNT	(COPY_BL2_SIZE/512)
-
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
  
 #endif	/* __CONFIG_H */
	1	+dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb
	2	+
1	3	dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
2	4	exynos5250-snow.dtb \
3	5	exynos5250-smdk5250.dtb \
	1	+/*
	2	+ * Samsung's Exynos4210 based Origen board device tree source
	3	+ *
	4	+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
	5	+ * http://www.samsung.com
	6	+ *
	7	+ * SPDX-License-Identifier: GPL-2.0+
	8	+ */
	9	+
	10	+/dts-v1/;
	11	+/include/ "skeleton.dtsi"
	12	+/include/ "exynos4.dtsi"
	13	+
	14	+/ {
	15	+ model = "Insignal Origen evaluation board based on Exynos4210";
	16	+ compatible = "insignal,origen", "samsung,exynos4210";
	17	+
	18	+ chosen {
	19	+ bootargs ="";
	20	+ };
	21	+
	22	+ aliases {
	23	+ serial0 = "/serial@13800000";
	24	+ console = "/serial@13820000";
	25	+ mmc2 = "sdhci@12530000";
	26	+ };
	27	+
	28	+ sdhci@12510000 {
	29	+ status = "disabled";
	30	+ };
	31	+
	32	+ sdhci@12520000 {
	33	+ status = "disabled";
	34	+ };
	35	+
	36	+ sdhci@12530000 {
	37	+ samsung,bus-width = <4>;
	38	+ samsung,timing = <1 2 3>;
	39	+ cd-gpios = <&gpio 0x2008002 0>;
	40	+ };
	41	+
	42	+ sdhci@12540000 {
	43	+ status = "disabled";
	44	+ };
	45	+};
...	...	@@ -11,130 +11,36 @@
11	11	#include <asm/arch/mmc.h>
12	12	#include <asm/arch/periph.h>
13	13	#include <asm/arch/pinmux.h>
	14	+#include <usb.h>
14	15
15	16	DECLARE_GLOBAL_DATA_PTR;
16		-struct exynos4_gpio_part1 *gpio1;
17		-struct exynos4_gpio_part2 *gpio2;
18	17
19		-int board_init(void)
	18	+u32 get_board_rev(void)
20	19	{
21		- gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
22		- gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
23		-
24		- gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
25	20	return 0;
26	21	}
27	22
28		-static int board_uart_init(void)
	23	+int exynos_init(void)
29	24	{
30		- int err;
31		-
32		- err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
33		- if (err) {
34		- debug("UART0 not configured\n");
35		- return err;
36		- }
37		-
38		- err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
39		- if (err) {
40		- debug("UART1 not configured\n");
41		- return err;
42		- }
43		-
44		- err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
45		- if (err) {
46		- debug("UART2 not configured\n");
47		- return err;
48		- }
49		-
50		- err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
51		- if (err) {
52		- debug("UART3 not configured\n");
53		- return err;
54		- }
55		-
56	25	return 0;
57	26	}
58	27
59		-#ifdef CONFIG_BOARD_EARLY_INIT_F
60		-int board_early_init_f(void)
	28	+int board_usb_init(int index, enum usb_init_type init)
61	29	{
62		- int err;
63		- err = board_uart_init();
64		- if (err) {
65		- debug("UART init failed\n");
66		- return err;
67		- }
68		- return err;
69		-}
70		-#endif
71		-
72		-int dram_init(void)
73		-{
74		- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
75		- + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
76		- + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
77		- + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
78		-
79	30	return 0;
80	31	}
81	32
82		-void dram_init_banksize(void)
	33	+#ifdef CONFIG_USB_CABLE_CHECK
	34	+int usb_cable_connected(void)
83	35	{
84		- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
85		- gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
86		- PHYS_SDRAM_1_SIZE);
87		- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
88		- gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
89		- PHYS_SDRAM_2_SIZE);
90		- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
91		- gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
92		- PHYS_SDRAM_3_SIZE);
93		- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
94		- gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
95		- PHYS_SDRAM_4_SIZE);
96		-}
97		-
98		-#ifdef CONFIG_DISPLAY_BOARDINFO
99		-int checkboard(void)
100		-{
101		- printf("\nBoard: ORIGEN\n");
102	36	return 0;
103	37	}
104	38	#endif
105	39
106		-#ifdef CONFIG_GENERIC_MMC
107		-int board_mmc_init(bd_t *bis)
	40	+#ifdef CONFIG_BOARD_EARLY_INIT_F
	41	+int exynos_early_init_f(void)
108	42	{
109		- int i, err;
110		-
111		- /*
112		- * MMC2 SD card GPIO:
113		- *
114		- * GPK2[0] SD_2_CLK(2)
115		- * GPK2[1] SD_2_CMD(2)
116		- * GPK2[2] SD_2_CDn
117		- * GPK2[3:6] SD_2_DATA[0:3](2)
118		- */
119		- for (i = 0; i < 7; i++) {
120		- /* GPK2[0:6] special function 2 */
121		- s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
122		-
123		- /* GPK2[0:6] drv 4x */
124		- s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
125		-
126		- /* GPK2[0:1] pull disable */
127		- if (i == 0 \|\| i == 1) {
128		- s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
129		- continue;
130		- }
131		-
132		- /* GPK2[2:6] pull up */
133		- s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
134		- }
135		-
136		- err = s5p_mmc_init(2, 4);
137		- return err;
	43	+ return 0;
138	44	}
139	45	#endif
...	...	@@ -6,115 +6,71 @@
6	6	* SPDX-License-Identifier: GPL-2.0+
7	7	*/
8	8
9		-#ifndef __CONFIG_H
10		-#define __CONFIG_H
	9	+#ifndef __CONFIG_ORIGEN_H
	10	+#define __CONFIG_ORIGEN_H
11	11
	12	+#include <configs/exynos4-dt.h>
	13	+
	14	+#define CONFIG_SYS_PROMPT "ORIGEN # "
	15	+
	16	+#undef CONFIG_DEFAULT_DEVICE_TREE
	17	+#define CONFIG_DEFAULT_DEVICE_TREE exynos4210-origen
	18	+
12	19	/* High Level Configuration Options */
13		-#define CONFIG_SAMSUNG 1 /* SAMSUNG core */
14		-#define CONFIG_S5P 1 /* S5P Family */
15	20	#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
16	21	#define CONFIG_ORIGEN 1 /* working with ORIGEN*/
17	22
18		-#include <asm/arch/cpu.h> /* get chip and board defs */
19		-
20		-#define CONFIG_ARCH_CPU_INIT
21		-#define CONFIG_DISPLAY_CPUINFO
22		-#define CONFIG_DISPLAY_BOARDINFO
23		-#define CONFIG_BOARD_EARLY_INIT_F
24		-
25	23	#define CONFIG_SYS_DCACHE_OFF 1
26	24
	25	+/* ORIGEN has 4 bank of DRAM */
	26	+#define CONFIG_NR_DRAM_BANKS 4
27	27	#define CONFIG_SYS_SDRAM_BASE 0x40000000
28		-#define CONFIG_SYS_TEXT_BASE 0x43E00000
	28	+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
	29	+#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
29	30
30		-/* input clock of PLL: ORIGEN has 24MHz input clock */
31		-#define CONFIG_SYS_CLK_FREQ 24000000
	31	+/* memtest works on */
	32	+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	33	+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
	34	+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
32	35
33		-#define CONFIG_SETUP_MEMORY_TAGS
34		-#define CONFIG_CMDLINE_TAG
35		-#define CONFIG_INITRD_TAG
36		-#define CONFIG_CMDLINE_EDITING
	36	+#define CONFIG_SYS_TEXT_BASE 0x43E00000
37	37
38	38	#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN
39	39
40		-/* Power Down Modes */
41		-#define S5P_CHECK_SLEEP 0x00000BAD
42		-#define S5P_CHECK_DIDLE 0xBAD00000
43		-#define S5P_CHECK_LPA 0xABAD0000
44		-
45	40	/* Size of malloc() pool */
46		-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
	41	+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
47	42
48	43	/* select serial console configuration */
49		-#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
	44	+#define CONFIG_SERIAL2
50	45	#define CONFIG_BAUDRATE 115200
51		-#define EXYNOS4_DEFAULT_UART_OFFSET 0x020000
52	46
53		-#define CONFIG_SKIP_LOWLEVEL_INIT
	47	+/* Console configuration */
	48	+#define CONFIG_SYS_CONSOLE_INFO_QUIET
	49	+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	50	+#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
54	51
55		-/* SD/MMC configuration */
56		-#define CONFIG_GENERIC_MMC
57		-#define CONFIG_MMC
58		-#define CONFIG_SDHCI
59		-#define CONFIG_S5P_SDHCI
	52	+#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
60	53
61		-/* PWM */
62		-#define CONFIG_PWM 1
	54	+#define CONFIG_SYS_MONITOR_BASE 0x00000000
63	55
64		-/* allow to overwrite serial and ethaddr */
65		-#define CONFIG_ENV_OVERWRITE
	56	+/* Power Down Modes */
	57	+#define S5P_CHECK_SLEEP 0x00000BAD
	58	+#define S5P_CHECK_DIDLE 0xBAD00000
	59	+#define S5P_CHECK_LPA 0xABAD0000
66	60
67		-/* Command definition*/
68		-#include <config_cmd_default.h>
69		-
70	61	#undef CONFIG_CMD_PING
71	62	#define CONFIG_CMD_ELF
72	63	#define CONFIG_CMD_DHCP
73		-#define CONFIG_CMD_MMC
74		-#define CONFIG_CMD_FAT
75	64	#undef CONFIG_CMD_NET
76	65	#undef CONFIG_CMD_NFS
77	66
78		-#define CONFIG_BOOTDELAY 3
79		-#define CONFIG_ZERO_BOOTDELAY_CHECK
80	67	/* MMC SPL */
81	68	#define CONFIG_SPL
82	69	#define COPY_BL2_FNPTR_ADDR 0x02020030
83		-
84	70	#define CONFIG_SPL_TEXT_BASE 0x02021410
85	71
86	72	#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
87	73
88		-/* Miscellaneous configurable options */
89		-#define CONFIG_SYS_LONGHELP /* undef to save memory */
90		-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
91		-#define CONFIG_SYS_PROMPT "ORIGEN # "
92		-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/
93		-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
94		-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
95		-#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
96		-/* Boot Argument Buffer Size */
97		-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
98		-/* memtest works on */
99		-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
100		-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
101		-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
102		-
103		-/* ORIGEN has 4 bank of DRAM */
104		-#define CONFIG_NR_DRAM_BANKS 4
105		-#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
106		-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
107		-#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
108		-#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
109		-#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
110		-#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
111		-#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
112		-#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
113		-#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
114		-
115		-/* FLASH and environment organization */
116		-#define CONFIG_SYS_NO_FLASH 1
117		-#undef CONFIG_CMD_IMLS
118	74	#define CONFIG_IDENT_STRING " for ORIGEN"
119	75
120	76	#define CONFIG_CLK_1000_400_200
121	77
...	...	@@ -122,13 +78,12 @@
122	78	/* MIU (Memory Interleaving Unit) */
123	79	#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
124	80
125		-#define CONFIG_ENV_IS_IN_MMC 1
	81	+#define CONFIG_ENV_IS_IN_MMC
126	82	#define CONFIG_SYS_MMC_ENV_DEV 0
127	83	#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
128	84	#define RESERVE_BLOCK_SIZE (512)
129	85	#define BL1_SIZE (16 << 10) /16 K reserved for BL1/
130	86	#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE)
131		-#define CONFIG_DOS_PARTITION 1
132	87
133	88	#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
134	89	#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
...	...	@@ -139,9 +94,6 @@
139	94	#define COPY_BL2_SIZE 0x80000
140	95	#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
141	96	#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
142		-
143		-/* Enable devicetree support */
144		-#define CONFIG_OF_LIBFDT
145	97
146	98	#endif /* __CONFIG_H */