arm: at91: add support for mini-box picosam9g45 board

Bootlog: U-Boot SPL 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21) mci: setting clock 258000 Hz, block size 512 mci: setting clock 258000 Hz, block size 512 mci: setting clock 258000 Hz, block size 512 mci: setting clock 33024000 Hz, block size 512 reading u-boot.img reading u-boot.img U-Boot 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21 +0000) CPU: AT91SAM9G45 Crystal frequency: 12 MHz CPU clock : 400 MHz Master clock : 133.333 MHz Watchdog enabled DRAM: 256 MiB WARNING: Caches not enabled MMC: mci: 0 mci: setting clock 260416 Hz, block size 512 mci: setting clock 260416 Hz, block size 512 mci: setting clock 260416 Hz, block size 512 mci: setting clock 33333333 Hz, block size 512 reading uboot.env In: serial Out: serial Err: serial Net: macb0 Error: macb0 address not set. Hit any key to stop autoboot: 0 U-Boot> Signed-off-by: Erik van Luijk <evanluijk@interact.nl> [add 'picosam9g45_defconfig' to MAINTAINERS] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

arm: at91: add support for mini-box picosam9g45 board
Bootlog: U-Boot SPL 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21) mci: setting clock 258000 Hz, block size 512 mci: setting clock 258000 Hz, block size 512 mci: setting clock 258000 Hz, block size 512 mci: setting clock 33024000 Hz, block size 512 reading u-boot.img reading u-boot.img U-Boot 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21 +0000) CPU: AT91SAM9G45 Crystal frequency: 12 MHz CPU clock : 400 MHz Master clock : 133.333 MHz Watchdog enabled DRAM: 256 MiB WARNING: Caches not enabled MMC: mci: 0 mci: setting clock 260416 Hz, block size 512 mci: setting clock 260416 Hz, block size 512 mci: setting clock 260416 Hz, block size 512 mci: setting clock 33333333 Hz, block size 512 reading uboot.env In: serial Out: serial Err: serial Net: macb0 Error: macb0 address not set. Hit any key to stop autoboot: 0 U-Boot> Signed-off-by: Erik van Luijk <evanluijk@interact.nl> [add 'picosam9g45_defconfig' to MAINTAINERS] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Erik van Luijk · Andreas Bießmann
1 parent c982f6b9bf
Showing 9 changed files with 646 additions and 0 deletions Side-by-side Diff
arch/arm/include/asm/mach-types.h
arch/arm/mach-at91/Kconfig
board/mini-box/picosam9g45/Kconfig
board/mini-box/picosam9g45/MAINTAINERS
board/mini-box/picosam9g45/Makefile
board/mini-box/picosam9g45/led.c
board/mini-box/picosam9g45/picosam9g45.c
configs/picosam9g45_defconfig
include/configs/picosam9g45.h
@@ -1105,6 +1105,7 @@
 #define MACH_TYPE_UBISYS_P9D_EVP       3493
 #define MACH_TYPE_ATDGP318             3494
 #define MACH_TYPE_OMAP5_SEVM           3777
+#define MACH_TYPE_PICOSAM9G45          3838
 #define MACH_TYPE_ARMADILLO_800EVA     3863
 #define MACH_TYPE_KZM9G                4140
 #define MACH_TYPE_COLIBRI_T30          4493
@@ -64,6 +64,11 @@
 	bool "Ronetix pm9g45 board"
 	select CPU_ARM926EJS
  
+config TARGET_PICOSAM9G45
+	bool "Mini-box picosam9g45 board"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
+
 config TARGET_AT91SAM9N12EK
 	bool "Atmel AT91SAM9N12-EK board"
 	select CPU_ARM926EJS
@@ -155,6 +160,7 @@
 source "board/esd/meesc/Kconfig"
 source "board/esd/otc570/Kconfig"
 source "board/eukrea/cpu9260/Kconfig"
+source "board/mini-box/picosam9g45/Kconfig"
 source "board/ronetix/pm9261/Kconfig"
 source "board/ronetix/pm9263/Kconfig"
 source "board/ronetix/pm9g45/Kconfig"
+if TARGET_PICOSAM9G45
+
+config SYS_BOARD
+	default "picosam9g45"
+
+config SYS_VENDOR
+	default "mini-box"
+
+config SYS_CONFIG_NAME
+	default "picosam9g45"
+
+endif
+PICOSAM9G45 BOARD
+M:	Erik van Luijk <evanluijk@interact.nl>
+S:	Maintained
+F:	board/mini-box/picosam9g45/
+F:	include/configs/picosam9g45.h
+F:	configs/picosam9g45_defconfig
+#
+# Makefile for mini-box PICOSAM9G45 (AT91SAM9G45) based board
+# (C) Copytight 2015 Inter Act B.V.
+#
+# Based on:
+# U-Boot file: board/atmel/at91sam9m10g45ek/Makefile
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += picosam9g45.o
+obj-y += led.o
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9g45.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+
+void coloured_LED_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
+
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+}
+/*
+ * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board
+ * (C) Copyright 2015 Inter Act B.V.
+ *
+ * Based on:
+ * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/at91sam9g45_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <linux/mtd/nand.h>
+#include <atmel_lcdc.h>
+#include <atmel_mci.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+
+void at91_spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	at91_mci_hw_init();
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_DQMS_SHARED |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+
+	ddr2->rtr = 0x24b;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+		      1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+		      1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct atmel_mpddr ddr2;
+	unsigned long csa;
+
+	ddr2_conf(&ddr2);
+
+	/* enable DDR2 clock */
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	/* Chip select 1 is for DDR2/SDRAM */
+	csa = readl(&mat->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+	csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
+	writel(csa, &mat->ebicsa);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
+	ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void picosam9g45_usb_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
+
+	at91_set_gpio_output(AT91_PIN_PD1, 0);
+	at91_set_gpio_output(AT91_PIN_PD3, 0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void picosam9g45_macb_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+	/*
+	 * Disable pull-up on:
+	 *      RXDV (PA15) => PHY normal mode (not Test mode)
+	 *      ERX0 (PA12) => PHY ADDR0
+	 *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	writel(pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA12) |
+	       pin_to_mask(AT91_PIN_PA13),
+	       &pioa->pudr);
+
+	at91_phy_reset();
+
+	/* Re-enable pull-up */
+	writel(pin_to_mask(AT91_PIN_PA15) |
+	       pin_to_mask(AT91_PIN_PA12) |
+	       pin_to_mask(AT91_PIN_PA13),
+	       &pioa->puer);
+
+	/* And the pins. */
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_LCD
+
+vidinfo_t panel_info = {
+	.vl_col =		480,
+	.vl_row =		272,
+	.vl_clk =		9000000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_NORMAL |
+				ATMEL_LCDC_INVFRAME_NORMAL,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		45,
+	.vl_left_margin =	1,
+	.vl_right_margin =	1,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	40,
+	.vl_lower_margin =	1,
+	.mmio =			ATMEL_BASE_LCDC,
+};
+
+
+void lcd_enable(void)
+{
+	at91_set_A_periph(AT91_PIN_PE6, 1);	/* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_A_periph(AT91_PIN_PE6, 0);	/* power down */
+}
+
+static void picosam9g45_lcd_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
+	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
+	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
+
+	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
+	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
+	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
+	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
+	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
+	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
+	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
+
+	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+
+	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size;
+	int i;
+	char temp[32];
+
+	lcd_printf("%s\n", U_BOOT_VERSION);
+	lcd_printf("(C) 2015 Inter Act B.V.\n");
+	lcd_printf("support@interact.nl\n");
+	lcd_printf("%s CPU at %s MHz\n",
+		   ATMEL_CPU_NAME,
+		   strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	lcd_printf("  %ld MB SDRAM\n", dram_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bis)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI0);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_seriald_hw_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_USB
+	picosam9g45_usb_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 4);
+#endif
+#ifdef CONFIG_MACB
+	picosam9g45_macb_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	picosam9g45_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+							PHYS_SDRAM_1_SIZE);
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
+							PHYS_SDRAM_2_SIZE);
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 1:
+		at91_set_gpio_output(AT91_PIN_PB18, 0);
+		break;
+	case 0:
+	default:
+		at91_set_gpio_output(AT91_PIN_PB3, 0);
+		break;
+	}
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 1:
+		at91_set_gpio_output(AT91_PIN_PB18, 1);
+		break;
+	case 0:
+	default:
+		at91_set_gpio_output(AT91_PIN_PB3, 1);
+	break;
+	}
+}
+#endif /* CONFIG_ATMEL_SPI */
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_PICOSAM9G45=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+/*
+ * Configuration settings for the mini-box PICOSAM9G45 board.
+ * (C) Copyright 2015 Inter Act B.V.
+ *
+ * Based on:
+ * U-Boot file: include/configs/at91sam9m10g45ek.h
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x23f00000
+
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+
+#define CONFIG_PICOSAM
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* LCD */
+#define CONFIG_LCD
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_LCD
+#define CONFIG_ATMEL_LCD_RGB565
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* board specific(not enough SRAM) */
+#define CONFIG_AT91SAM9G45_LCD_BASE		0x23E00000
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_GREEN_LED	AT91_PIN_PD31	/* this is the user1 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Enable the watchdog */
+#define CONFIG_AT91SAM9_WATCHDOG
+#define CONFIG_HW_WATCHDOG
+
+/*
+ * Command line configuration.
+ */
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_USB
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS	2
+#define PHYS_SDRAM_1		ATMEL_BASE_CS1	/* on DDRSDRC1 */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
+#define PHYS_SDRAM_2		ATMEL_BASE_CS6	/* on DDRSDRC0 */
+#define PHYS_SDRAM_2_SIZE       0x08000000	/* 128 MB */
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* MMC */
+#define CONFIG_CMD_MMC
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x23e00000
+
+#ifdef CONFIG_SYS_USE_MMC
+/* bootstrap + u-boot + env + linux in mmc */
+#define FAT_ENV_INTERFACE	"mmc"
+/*
+ * We don't specify the part number, if device 0 has partition table, it means
+ * the first partition; it no partition table, then take whole device as a
+ * FAT file system.
+ */
+#define FAT_ENV_DEVICE_AND_PART	"0"
+#define FAT_ENV_FILE		"uboot.env"
+#define CONFIG_ENV_IS_IN_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_ENV_SIZE		0x4000
+
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mmcblk0p2 rw rootwait"
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x21000000 dtb; " \
+				"fatload mmc 0:1 0x22000000 zImage; " \
+				"bootz 0x22000000 - 0x21000000"
+#endif
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "
+#define CONFIG_SYS_CBSIZE	256
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE  \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x300000
+#define CONFIG_SPL_MAX_SIZE		0x010000
+#define CONFIG_SPL_STACK		0x310000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
+#define CONFIG_SYS_MONITOR_LEN		0x80000
+
+#ifdef CONFIG_SYS_USE_MMC
+
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000
+
+#define CONFIG_SPL_LDSCRIPT	arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CONFIG_SYS_AT91_PLLA		0x20c73f03
+#define CONFIG_SYS_MCKR			0x1301
+#define CONFIG_SYS_MCKR_CSS		0x1302
+
+#endif
+#endif
...	...	@@ -1105,6 +1105,7 @@
1105	1105	#define MACH_TYPE_UBISYS_P9D_EVP 3493
1106	1106	#define MACH_TYPE_ATDGP318 3494
1107	1107	#define MACH_TYPE_OMAP5_SEVM 3777
	1108	+#define MACH_TYPE_PICOSAM9G45 3838
1108	1109	#define MACH_TYPE_ARMADILLO_800EVA 3863
1109	1110	#define MACH_TYPE_KZM9G 4140
1110	1111	#define MACH_TYPE_COLIBRI_T30 4493
...	...	@@ -64,6 +64,11 @@
64	64	bool "Ronetix pm9g45 board"
65	65	select CPU_ARM926EJS
66	66
	67	+config TARGET_PICOSAM9G45
	68	+ bool "Mini-box picosam9g45 board"
	69	+ select CPU_ARM926EJS
	70	+ select SUPPORT_SPL
	71	+
67	72	config TARGET_AT91SAM9N12EK
68	73	bool "Atmel AT91SAM9N12-EK board"
69	74	select CPU_ARM926EJS
...	...	@@ -155,6 +160,7 @@
155	160	source "board/esd/meesc/Kconfig"
156	161	source "board/esd/otc570/Kconfig"
157	162	source "board/eukrea/cpu9260/Kconfig"
	163	+source "board/mini-box/picosam9g45/Kconfig"
158	164	source "board/ronetix/pm9261/Kconfig"
159	165	source "board/ronetix/pm9263/Kconfig"
160	166	source "board/ronetix/pm9g45/Kconfig"
	1	+if TARGET_PICOSAM9G45
	2	+
	3	+config SYS_BOARD
	4	+ default "picosam9g45"
	5	+
	6	+config SYS_VENDOR
	7	+ default "mini-box"
	8	+
	9	+config SYS_CONFIG_NAME
	10	+ default "picosam9g45"
	11	+
	12	+endif
	1	+PICOSAM9G45 BOARD
	2	+M: Erik van Luijk <evanluijk@interact.nl>
	3	+S: Maintained
	4	+F: board/mini-box/picosam9g45/
	5	+F: include/configs/picosam9g45.h
	6	+F: configs/picosam9g45_defconfig
	1	+#
	2	+# Makefile for mini-box PICOSAM9G45 (AT91SAM9G45) based board
	3	+# (C) Copytight 2015 Inter Act B.V.
	4	+#
	5	+# Based on:
	6	+# U-Boot file: board/atmel/at91sam9m10g45ek/Makefile
	7	+#
	8	+# (C) Copyright 2003-2008
	9	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	10	+#
	11	+# (C) Copyright 2008
	12	+# Stelian Pop <stelian@popies.net>
	13	+# Lead Tech Design <www.leadtechdesign.com>
	14	+#
	15	+# SPDX-License-Identifier: GPL-2.0+
	16	+#
	17	+
	18	+obj-y += picosam9g45.o
	19	+obj-y += led.o
	1	+/*
	2	+ * (C) Copyright 2007-2008
	3	+ * Stelian Pop <stelian@popies.net>
	4	+ * Lead Tech Design <www.leadtechdesign.com>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#include <common.h>
	10	+#include <asm/io.h>
	11	+#include <asm/arch/at91sam9g45.h>
	12	+#include <asm/arch/at91_pmc.h>
	13	+#include <asm/arch/gpio.h>
	14	+
	15	+void coloured_LED_init(void)
	16	+{
	17	+ struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	18	+
	19	+ /* Enable clock */
	20	+ writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
	21	+
	22	+ at91_set_gpio_output(CONFIG_GREEN_LED, 1);
	23	+
	24	+ at91_set_gpio_value(CONFIG_GREEN_LED, 1);
	25	+}
	1	+/*
	2	+ * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board
	3	+ * (C) Copyright 2015 Inter Act B.V.
	4	+ *
	5	+ * Based on:
	6	+ * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
	7	+ * (C) Copyright 2007-2008
	8	+ * Stelian Pop <stelian@popies.net>
	9	+ * Lead Tech Design <www.leadtechdesign.com>
	10	+ *
	11	+ * SPDX-License-Identifier: GPL-2.0+
	12	+ */
	13	+
	14	+#include <common.h>
	15	+#include <asm/io.h>
	16	+#include <asm/arch/clk.h>
	17	+#include <asm/arch/at91sam9g45_matrix.h>
	18	+#include <asm/arch/at91sam9_smc.h>
	19	+#include <asm/arch/at91_common.h>
	20	+#include <asm/arch/at91_pmc.h>
	21	+#include <asm/arch/gpio.h>
	22	+#include <asm/arch/clk.h>
	23	+#include <lcd.h>
	24	+#include <linux/mtd/nand.h>
	25	+#include <atmel_lcdc.h>
	26	+#include <atmel_mci.h>
	27	+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
	28	+#include <net.h>
	29	+#endif
	30	+#include <netdev.h>
	31	+
	32	+DECLARE_GLOBAL_DATA_PTR;
	33	+
	34	+/* ------------------------------------------------------------------------- */
	35	+/*
	36	+ * Miscelaneous platform dependent initialisations
	37	+ */
	38	+
	39	+#if defined(CONFIG_SPL_BUILD)
	40	+#include <spl.h>
	41	+
	42	+void at91_spl_board_init(void)
	43	+{
	44	+#ifdef CONFIG_SYS_USE_MMC
	45	+ at91_mci_hw_init();
	46	+#endif
	47	+}
	48	+
	49	+#include <asm/arch/atmel_mpddrc.h>
	50	+static void ddr2_conf(struct atmel_mpddr *ddr2)
	51	+{
	52	+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS \| ATMEL_MPDDRC_MD_DDR2_SDRAM);
	53	+
	54	+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 \|
	55	+ ATMEL_MPDDRC_CR_NR_ROW_14 \|
	56	+ ATMEL_MPDDRC_CR_DQMS_SHARED \|
	57	+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
	58	+
	59	+ ddr2->rtr = 0x24b;
	60	+
	61	+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET \|/* 67.5 = 45 ns /
	62	+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \|/* 27.5 = 15 ns /
	63	+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET \| /* 27.5 = 15 ns /
	64	+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET \| /* 87.5 = 60 ns /
	65	+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET \| /* 27.5 = 15 ns /
	66	+ 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET \| /* 17.5= 7.5 ns/
	67	+ 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET \| /* 1 clk cycle */
	68	+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
	69	+
	70	+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET \| /* 27.5 = 15 ns /
	71	+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET \|
	72	+ 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET \|
	73	+ 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
	74	+
	75	+ ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET \|
	76	+ 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET \|
	77	+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET \|
	78	+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
	79	+}
	80	+
	81	+void mem_init(void)
	82	+{
	83	+ struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	84	+ struct at91_matrix mat = (struct at91_matrix )ATMEL_BASE_MATRIX;
	85	+ struct atmel_mpddr ddr2;
	86	+ unsigned long csa;
	87	+
	88	+ ddr2_conf(&ddr2);
	89	+
	90	+ /* enable DDR2 clock */
	91	+ writel(AT91_PMC_DDR, &pmc->scer);
	92	+
	93	+ /* Chip select 1 is for DDR2/SDRAM */
	94	+ csa = readl(&mat->ebicsa);
	95	+ csa \|= AT91_MATRIX_EBI_CS1A_SDRAMC;
	96	+ csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
	97	+ writel(csa, &mat->ebicsa);
	98	+
	99	+ /* DDRAM2 Controller initialize */
	100	+ ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
	101	+ ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2);
	102	+}
	103	+#endif
	104	+
	105	+#ifdef CONFIG_CMD_USB
	106	+static void picosam9g45_usb_hw_init(void)
	107	+{
	108	+ struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	109	+
	110	+ writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
	111	+
	112	+ at91_set_gpio_output(AT91_PIN_PD1, 0);
	113	+ at91_set_gpio_output(AT91_PIN_PD3, 0);
	114	+}
	115	+#endif
	116	+
	117	+#ifdef CONFIG_MACB
	118	+static void picosam9g45_macb_hw_init(void)
	119	+{
	120	+ struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	121	+ struct at91_port pioa = (struct at91_port )ATMEL_BASE_PIOA;
	122	+
	123	+ /* Enable clock */
	124	+ writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
	125	+
	126	+ /*
	127	+ * Disable pull-up on:
	128	+ * RXDV (PA15) => PHY normal mode (not Test mode)
	129	+ * ERX0 (PA12) => PHY ADDR0
	130	+ * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
	131	+ *
	132	+ * PHY has internal pull-down
	133	+ */
	134	+ writel(pin_to_mask(AT91_PIN_PA15) \|
	135	+ pin_to_mask(AT91_PIN_PA12) \|
	136	+ pin_to_mask(AT91_PIN_PA13),
	137	+ &pioa->pudr);
	138	+
	139	+ at91_phy_reset();
	140	+
	141	+ /* Re-enable pull-up */
	142	+ writel(pin_to_mask(AT91_PIN_PA15) \|
	143	+ pin_to_mask(AT91_PIN_PA12) \|
	144	+ pin_to_mask(AT91_PIN_PA13),
	145	+ &pioa->puer);
	146	+
	147	+ /* And the pins. */
	148	+ at91_macb_hw_init();
	149	+}
	150	+#endif
	151	+
	152	+#ifdef CONFIG_LCD
	153	+
	154	+vidinfo_t panel_info = {
	155	+ .vl_col = 480,
	156	+ .vl_row = 272,
	157	+ .vl_clk = 9000000,
	158	+ .vl_sync = ATMEL_LCDC_INVLINE_NORMAL \|
	159	+ ATMEL_LCDC_INVFRAME_NORMAL,
	160	+ .vl_bpix = 3,
	161	+ .vl_tft = 1,
	162	+ .vl_hsync_len = 45,
	163	+ .vl_left_margin = 1,
	164	+ .vl_right_margin = 1,
	165	+ .vl_vsync_len = 1,
	166	+ .vl_upper_margin = 40,
	167	+ .vl_lower_margin = 1,
	168	+ .mmio = ATMEL_BASE_LCDC,
	169	+};
	170	+
	171	+
	172	+void lcd_enable(void)
	173	+{
	174	+ at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
	175	+}
	176	+
	177	+void lcd_disable(void)
	178	+{
	179	+ at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
	180	+}
	181	+
	182	+static void picosam9g45_lcd_hw_init(void)
	183	+{
	184	+ struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	185	+
	186	+ at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
	187	+ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
	188	+ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
	189	+ at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
	190	+ at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
	191	+
	192	+ at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
	193	+ at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
	194	+ at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
	195	+ at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
	196	+ at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
	197	+ at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
	198	+ at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
	199	+ at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
	200	+ at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
	201	+ at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
	202	+ at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
	203	+ at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
	204	+ at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
	205	+ at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
	206	+ at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
	207	+ at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
	208	+ at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
	209	+ at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
	210	+ at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
	211	+ at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
	212	+ at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
	213	+ at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
	214	+ at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
	215	+ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
	216	+
	217	+ writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
	218	+
	219	+ gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
	220	+}
	221	+
	222	+#ifdef CONFIG_LCD_INFO
	223	+#include <nand.h>
	224	+#include <version.h>
	225	+
	226	+void lcd_show_board_info(void)
	227	+{
	228	+ ulong dram_size;
	229	+ int i;
	230	+ char temp[32];
	231	+
	232	+ lcd_printf("%s\n", U_BOOT_VERSION);
	233	+ lcd_printf("(C) 2015 Inter Act B.V.\n");
	234	+ lcd_printf("support@interact.nl\n");
	235	+ lcd_printf("%s CPU at %s MHz\n",
	236	+ ATMEL_CPU_NAME,
	237	+ strmhz(temp, get_cpu_clk_rate()));
	238	+
	239	+ dram_size = 0;
	240	+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
	241	+ dram_size += gd->bd->bi_dram[i].size;
	242	+ lcd_printf(" %ld MB SDRAM\n", dram_size >> 20);
	243	+}
	244	+#endif /* CONFIG_LCD_INFO */
	245	+#endif
	246	+
	247	+#ifdef CONFIG_GENERIC_ATMEL_MCI
	248	+int board_mmc_init(bd_t *bis)
	249	+{
	250	+ at91_mci_hw_init();
	251	+
	252	+ return atmel_mci_init((void *)ATMEL_BASE_MCI0);
	253	+}
	254	+#endif
	255	+
	256	+int board_early_init_f(void)
	257	+{
	258	+ at91_seriald_hw_init();
	259	+ return 0;
	260	+}
	261	+
	262	+int board_init(void)
	263	+{
	264	+ gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45;
	265	+
	266	+ /* adress of boot parameters */
	267	+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	268	+
	269	+#ifdef CONFIG_CMD_USB
	270	+ picosam9g45_usb_hw_init();
	271	+#endif
	272	+#ifdef CONFIG_HAS_DATAFLASH
	273	+ at91_spi0_hw_init(1 << 0);
	274	+#endif
	275	+#ifdef CONFIG_ATMEL_SPI
	276	+ at91_spi0_hw_init(1 << 4);
	277	+#endif
	278	+#ifdef CONFIG_MACB
	279	+ picosam9g45_macb_hw_init();
	280	+#endif
	281	+#ifdef CONFIG_LCD
	282	+ picosam9g45_lcd_hw_init();
	283	+#endif
	284	+ return 0;
	285	+}
	286	+
	287	+int dram_init(void)
	288	+{
	289	+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
	290	+ + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
	291	+
	292	+ return 0;
	293	+}
	294	+
	295	+void dram_init_banksize(void)
	296	+{
	297	+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	298	+ gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
	299	+ PHYS_SDRAM_1_SIZE);
	300	+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	301	+ gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
	302	+ PHYS_SDRAM_2_SIZE);
	303	+}
	304	+
	305	+#ifdef CONFIG_RESET_PHY_R
	306	+void reset_phy(void)
	307	+{
	308	+}
	309	+#endif
	310	+
	311	+int board_eth_init(bd_t *bis)
	312	+{
	313	+ int rc = 0;
	314	+#ifdef CONFIG_MACB
	315	+ rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
	316	+#endif
	317	+ return rc;
	318	+}
	319	+
	320	+/* SPI chip select control */
	321	+#ifdef CONFIG_ATMEL_SPI
	322	+#include <spi.h>
	323	+
	324	+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
	325	+{
	326	+ return bus == 0 && cs < 2;
	327	+}
	328	+
	329	+void spi_cs_activate(struct spi_slave *slave)
	330	+{
	331	+ switch (slave->cs) {
	332	+ case 1:
	333	+ at91_set_gpio_output(AT91_PIN_PB18, 0);
	334	+ break;
	335	+ case 0:
	336	+ default:
	337	+ at91_set_gpio_output(AT91_PIN_PB3, 0);
	338	+ break;
	339	+ }
	340	+}
	341	+
	342	+void spi_cs_deactivate(struct spi_slave *slave)
	343	+{
	344	+ switch (slave->cs) {
	345	+ case 1:
	346	+ at91_set_gpio_output(AT91_PIN_PB18, 1);
	347	+ break;
	348	+ case 0:
	349	+ default:
	350	+ at91_set_gpio_output(AT91_PIN_PB3, 1);
	351	+ break;
	352	+ }
	353	+}
	354	+#endif /* CONFIG_ATMEL_SPI */
	1	+CONFIG_ARM=y
	2	+CONFIG_ARCH_AT91=y
	3	+CONFIG_TARGET_PICOSAM9G45=y
	4	+CONFIG_SPL=y
	5	+CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
	6	+# CONFIG_CMD_BDI is not set
	7	+# CONFIG_CMD_IMI is not set
	8	+# CONFIG_CMD_IMLS is not set
	9	+# CONFIG_CMD_LOADS is not set
	10	+# CONFIG_CMD_FLASH is not set
	11	+# CONFIG_CMD_FPGA is not set
	12	+# CONFIG_CMD_SETEXPR is not set
	1	+/*
	2	+ * Configuration settings for the mini-box PICOSAM9G45 board.
	3	+ * (C) Copyright 2015 Inter Act B.V.
	4	+ *
	5	+ * Based on:
	6	+ * U-Boot file: include/configs/at91sam9m10g45ek.h
	7	+ * (C) Copyright 2007-2008
	8	+ * Stelian Pop <stelian@popies.net>
	9	+ * Lead Tech Design <www.leadtechdesign.com>
	10	+ *
	11	+ * SPDX-License-Identifier: GPL-2.0+
	12	+ */
	13	+
	14	+#ifndef __CONFIG_H
	15	+#define __CONFIG_H
	16	+
	17	+#include <asm/hardware.h>
	18	+
	19	+#define CONFIG_SYS_TEXT_BASE 0x23f00000
	20	+
	21	+#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
	22	+
	23	+/* ARM asynchronous clock */
	24	+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
	25	+#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
	26	+
	27	+#define CONFIG_PICOSAM
	28	+
	29	+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	30	+#define CONFIG_SETUP_MEMORY_TAGS
	31	+#define CONFIG_INITRD_TAG
	32	+#define CONFIG_SKIP_LOWLEVEL_INIT
	33	+#define CONFIG_BOARD_EARLY_INIT_F
	34	+#define CONFIG_DISPLAY_CPUINFO
	35	+
	36	+#define CONFIG_CMD_BOOTZ
	37	+#define CONFIG_OF_LIBFDT
	38	+
	39	+#define CONFIG_SYS_GENERIC_BOARD
	40	+
	41	+/* general purpose I/O */
	42	+#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
	43	+#define CONFIG_AT91_GPIO
	44	+#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
	45	+
	46	+/* serial console */
	47	+#define CONFIG_ATMEL_USART
	48	+#define CONFIG_USART_BASE ATMEL_BASE_DBGU
	49	+#define CONFIG_USART_ID ATMEL_ID_SYS
	50	+
	51	+/* LCD */
	52	+#define CONFIG_LCD
	53	+#define LCD_BPP LCD_COLOR8
	54	+#define CONFIG_LCD_LOGO
	55	+#undef LCD_TEST_PATTERN
	56	+#define CONFIG_LCD_INFO
	57	+#define CONFIG_LCD_INFO_BELOW_LOGO
	58	+#define CONFIG_SYS_WHITE_ON_BLACK
	59	+#define CONFIG_ATMEL_LCD
	60	+#define CONFIG_ATMEL_LCD_RGB565
	61	+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	62	+/* board specific(not enough SRAM) */
	63	+#define CONFIG_AT91SAM9G45_LCD_BASE 0x23E00000
	64	+
	65	+/* LED */
	66	+#define CONFIG_AT91_LED
	67	+#define CONFIG_GREEN_LED AT91_PIN_PD31 /* this is the user1 led */
	68	+
	69	+#define CONFIG_BOOTDELAY 3
	70	+
	71	+/*
	72	+ * BOOTP options
	73	+ */
	74	+#define CONFIG_BOOTP_BOOTFILESIZE
	75	+#define CONFIG_BOOTP_BOOTPATH
	76	+#define CONFIG_BOOTP_GATEWAY
	77	+#define CONFIG_BOOTP_HOSTNAME
	78	+
	79	+/* Enable the watchdog */
	80	+#define CONFIG_AT91SAM9_WATCHDOG
	81	+#define CONFIG_HW_WATCHDOG
	82	+
	83	+/*
	84	+ * Command line configuration.
	85	+ */
	86	+
	87	+/* No NOR flash */
	88	+#define CONFIG_SYS_NO_FLASH
	89	+#define CONFIG_CMD_PING
	90	+#define CONFIG_CMD_DHCP
	91	+#define CONFIG_CMD_USB
	92	+
	93	+/* SDRAM */
	94	+#define CONFIG_NR_DRAM_BANKS 2
	95	+#define PHYS_SDRAM_1 ATMEL_BASE_CS1 /* on DDRSDRC1 */
	96	+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
	97	+#define PHYS_SDRAM_2 ATMEL_BASE_CS6 /* on DDRSDRC0 */
	98	+#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
	99	+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	100	+
	101	+#define CONFIG_SYS_INIT_SP_ADDR \
	102	+ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
	103	+
	104	+/* MMC */
	105	+#define CONFIG_CMD_MMC
	106	+
	107	+#ifdef CONFIG_CMD_MMC
	108	+#define CONFIG_MMC
	109	+#define CONFIG_GENERIC_MMC
	110	+#define CONFIG_GENERIC_ATMEL_MCI
	111	+#endif
	112	+
	113	+#if defined(CONFIG_CMD_USB) \|\| defined(CONFIG_CMD_MMC)
	114	+#define CONFIG_CMD_FAT
	115	+#define CONFIG_DOS_PARTITION
	116	+#endif
	117	+
	118	+/* Ethernet */
	119	+#define CONFIG_MACB
	120	+#define CONFIG_RMII
	121	+#define CONFIG_NET_RETRY_COUNT 20
	122	+#define CONFIG_RESET_PHY_R
	123	+#define CONFIG_AT91_WANTS_COMMON_PHY
	124	+
	125	+/* USB */
	126	+#define CONFIG_USB_EHCI
	127	+#define CONFIG_USB_EHCI_ATMEL
	128	+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
	129	+#define CONFIG_USB_STORAGE
	130	+
	131	+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
	132	+
	133	+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	134	+#define CONFIG_SYS_MEMTEST_END 0x23e00000
	135	+
	136	+#ifdef CONFIG_SYS_USE_MMC
	137	+/* bootstrap + u-boot + env + linux in mmc */
	138	+#define FAT_ENV_INTERFACE "mmc"
	139	+/*
	140	+ * We don't specify the part number, if device 0 has partition table, it means
	141	+ * the first partition; it no partition table, then take whole device as a
	142	+ * FAT file system.
	143	+ */
	144	+#define FAT_ENV_DEVICE_AND_PART "0"
	145	+#define FAT_ENV_FILE "uboot.env"
	146	+#define CONFIG_ENV_IS_IN_FAT
	147	+#define CONFIG_FAT_WRITE
	148	+#define CONFIG_ENV_SIZE 0x4000
	149	+
	150	+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	151	+ "root=/dev/mmcblk0p2 rw rootwait"
	152	+#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \
	153	+ "fatload mmc 0:1 0x22000000 zImage; " \
	154	+ "bootz 0x22000000 - 0x21000000"
	155	+#endif
	156	+
	157	+#define CONFIG_BAUDRATE 115200
	158	+
	159	+#define CONFIG_SYS_PROMPT "U-Boot> "
	160	+#define CONFIG_SYS_CBSIZE 256
	161	+#define CONFIG_SYS_MAXARGS 16
	162	+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
	163	+ + sizeof(CONFIG_SYS_PROMPT) + 16)
	164	+#define CONFIG_SYS_LONGHELP
	165	+#define CONFIG_CMDLINE_EDITING
	166	+#define CONFIG_AUTO_COMPLETE
	167	+#define CONFIG_SYS_HUSH_PARSER
	168	+
	169	+/*
	170	+ * Size of malloc() pool
	171	+ */
	172	+#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
	173	+
	174	+/* Defines for SPL */
	175	+#define CONFIG_SPL_FRAMEWORK
	176	+#define CONFIG_SPL_TEXT_BASE 0x300000
	177	+#define CONFIG_SPL_MAX_SIZE 0x010000
	178	+#define CONFIG_SPL_STACK 0x310000
	179	+
	180	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	181	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	182	+#define CONFIG_SPL_SERIAL_SUPPORT
	183	+#define CONFIG_SPL_GPIO_SUPPORT
	184	+#define CONFIG_SPL_WATCHDOG_SUPPORT
	185	+
	186	+#define CONFIG_SYS_MONITOR_LEN 0x80000
	187	+
	188	+#ifdef CONFIG_SYS_USE_MMC
	189	+
	190	+#define CONFIG_SPL_BSS_START_ADDR 0x20000000
	191	+#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
	192	+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
	193	+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
	194	+
	195	+#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
	196	+#define CONFIG_SPL_MMC_SUPPORT
	197	+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
	198	+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
	199	+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
	200	+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
	201	+#define CONFIG_SPL_FAT_SUPPORT
	202	+#define CONFIG_SPL_LIBDISK_SUPPORT
	203	+
	204	+#define CONFIG_SPL_ATMEL_SIZE
	205	+#define CONFIG_SYS_MASTER_CLOCK 132096000
	206	+#define CONFIG_SYS_AT91_PLLA 0x20c73f03
	207	+#define CONFIG_SYS_MCKR 0x1301
	208	+#define CONFIG_SYS_MCKR_CSS 0x1302
	209	+
	210	+#endif
	211	+#endif