Eric Lee / smarc-uboot

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Commit c038fd0ea644c09191bc18cfb4736d6488580615

Authored by Rick Chen
Committed by Andes
1 parent cf3922dddc
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

configs: ax25-ae350: Support cfi flash 

Enable cfi flash driver and setup flash
parameters to support parallel nor flash
which type is JS28F00A-M29EWH.

Verification:
Size detection, data read, erase and write are all ok.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>

Showing 2 changed files with 43 additions and 0 deletions Side-by-side Diff

configs/ax25-ae350_defconfig
Diff comments   View file @ c038fd0
... ... @@ -4,8 +4,10 @@
4 4 CONFIG_TARGET_AX25_AE350=y
5 5 CONFIG_FIT=y
6 6 CONFIG_BOOTDELAY=3
  7 +CONFIG_BOARD_EARLY_INIT_F=y
7 8 # CONFIG_AUTO_COMPLETE is not set
8 9 CONFIG_SYS_PROMPT="RISC-V # "
  10 +CONFIG_CMD_IMLS=y
9 11 CONFIG_CMD_MMC=y
10 12 CONFIG_CMD_SF=y
11 13 CONFIG_CMD_SF_TEST=y
... ... @@ -25,6 +27,9 @@
25 27 CONFIG_DM_MMC=y
26 28 CONFIG_FTSDC010=y
27 29 CONFIG_FTSDC010_SDIO=y
  30 +CONFIG_MTD=y
  31 +CONFIG_MTD_NOR_FLASH=y
  32 +CONFIG_CFI_FLASH=y
28 33 CONFIG_DM_SPI_FLASH=y
29 34 CONFIG_SPI_FLASH=y
30 35 CONFIG_SPI_FLASH_MACRONIX=y
include/configs/ax25-ae350.h
Diff comments   View file @ c038fd0
... ... @@ -79,6 +79,44 @@
79 79 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
80 80 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
81 81  
  82 +/*
  83 + * FLASH and environment organization
  84 + */
  85 +
  86 +/* use CFI framework */
  87 +#define CONFIG_SYS_FLASH_CFI
  88 +#define CONFIG_FLASH_CFI_DRIVER
  89 +
  90 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  91 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  92 +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
  93 +
  94 +/* support JEDEC */
  95 +#ifdef CONFIG_CFI_FLASH
  96 +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
  97 +#endif/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
  98 +#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
  99 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  100 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
  101 +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
  102 +
  103 +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
  104 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
  105 +
  106 +/* max number of memory banks */
  107 +/*
  108 + * There are 4 banks supported for this Controller,
  109 + * but we have only 1 bank connected to flash on board
  110 +*/
  111 +#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
  112 +#define CONFIG_SYS_MAX_FLASH_BANKS 1
  113 +#endif
  114 +#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
  115 +
  116 +/* max number of sectors on one chip */
  117 +#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
  118 +#define CONFIG_SYS_MAX_FLASH_SECT 512
  119 +
82 120 /* environments */
83 121 #define CONFIG_ENV_SPI_BUS 0
84 122 #define CONFIG_ENV_SPI_CS 0