Eric Lee / smarc-uboot

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Commit c08aa771735a79efa48b2422295d88ca044ce71d

Authored by Heiko Schocher
Committed by Stefano Babic
1 parent 1204b9675e
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

imx6: aristainetos: add aristainetos 2b csl 

add aristainetso board version CSL.

Signed-off-by: Heiko Schocher <hs@denx.de>

Showing 14 changed files with 595 additions and 1 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ c08aa77
... ... @@ -580,6 +580,8 @@
580 580 imx6dl-aristainetos2_7.dtb \
581 581 imx6dl-aristainetos2b_4.dtb \
582 582 imx6dl-aristainetos2b_7.dtb \
  583 + imx6dl-aristainetos2b_csl_4.dtb \
  584 + imx6dl-aristainetos2b_csl_7.dtb \
583 585 imx6dl-brppt2.dtb \
584 586 imx6dl-dhcom-pdk2.dtb \
585 587 imx6dl-icore.dtb \
arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi
Diff comments   View file @ c08aa77
  1 +// SPDX-License-Identifier: GPL-2.0+ or X11
  2 +/*
  3 + * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
  4 + */
  5 +
  6 +#include <imx6qdl-aristainetos2b_csl-u-boot.dtsi>
  7 +
  8 +&lcd_panel {
  9 + pinctrl-names = "default";
  10 + pinctrl-0 = <&pinctrl_ipu_disp>;
  11 + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
  12 + backlight = <&backlight>;
  13 +};
arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts
Diff comments   View file @ c08aa77
  1 +// SPDX-License-Identifier: (GPL-2.0)
  2 +/*
  3 + * support for the imx6 based aristainetos2b csl board
  4 + * parts for 4.3 inch LG display on spi1 port1
  5 + *
  6 + * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
  7 + *
  8 + */
  9 +/dts-v1/;
  10 +
  11 +#include "imx6dl-aristainetos2_4.dtsi"
  12 +#include "imx6qdl-aristainetos2b_csl.dtsi"
  13 +
  14 +/ {
  15 + model = "aristainetos2b csl i.MX6 Dual Lite Board 4";
  16 + compatible = "fsl,imx6dl";
  17 +
  18 +};
  19 +
  20 +&ecspi1 {
  21 + lcd_panel: display@0 {
  22 + compatible = "lg,lg4573";
  23 + spi-max-frequency = <10000000>;
  24 + reg = <1>;
  25 + power-on-delay = <10>;
  26 +
  27 + display-timings {
  28 + 480x800p57 {
  29 + native-mode;
  30 + clock-frequency = <27000027>;
  31 + hactive = <480>;
  32 + vactive = <800>;
  33 + hfront-porch = <10>;
  34 + hback-porch = <59>;
  35 + hsync-len = <10>;
  36 + vback-porch = <15>;
  37 + vfront-porch = <15>;
  38 + vsync-len = <15>;
  39 + hsync-active = <1>;
  40 + vsync-active = <1>;
  41 + };
  42 + };
  43 +
  44 + port {
  45 + panel_in: endpoint {
  46 + remote-endpoint = <&display_out>;
  47 + };
  48 + };
  49 + };
  50 +};
arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi
Diff comments   View file @ c08aa77
  1 +// SPDX-License-Identifier: GPL-2.0+ or X11
  2 +/*
  3 + * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
  4 + */
  5 +
  6 +#include <imx6qdl-aristainetos2b_csl-u-boot.dtsi>
  7 +/ {
  8 + vdd_panel_reg: regulator-panel {
  9 + compatible = "regulator-fixed";
  10 + regulator-name = "panel_regulator";
  11 + regulator-min-microvolt = <3300000>;
  12 + regulator-max-microvolt = <3300000>;
  13 + regulator-always-on;
  14 + };
  15 +};
  16 +
  17 +&panel0 {
  18 + power-supply = <&vdd_panel_reg>;
  19 +};
arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts
Diff comments   View file @ c08aa77
  1 +// SPDX-License-Identifier: (GPL-2.0)
  2 +/*
  3 + * support for the imx6 based aristainetos2 board
  4 + *
  5 + * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
  6 + * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
  7 + *
  8 + */
  9 +/dts-v1/;
  10 +#include "imx6dl-aristainetos2_7.dtsi"
  11 +#include "imx6qdl-aristainetos2b_csl.dtsi"
  12 +
  13 +/ {
  14 + model = "aristainetos2b csl i.MX6 Dual Lite Board 7";
  15 + compatible = "fsl,imx6dl";
  16 +};
arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi
Diff comments   View file @ c08aa77
  1 +// SPDX-License-Identifier: GPL-2.0+ or X11
  2 +/*
  3 + * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
  4 + */
  5 +
  6 +/ {
  7 + chosen {
  8 + u-boot,dm-pre-reloc;
  9 + stdout-path = &uart1;
  10 + };
  11 +
  12 + wdt-reboot {
  13 + compatible = "wdt-reboot";
  14 + wdt = <&wdog1>;
  15 + };
  16 +};
  17 +
  18 +&uart1 {
  19 + u-boot,dm-pre-reloc;
  20 +};
  21 +
  22 +&pinctrl_gpio {
  23 + u-boot,dm-pre-reloc;
  24 +};
  25 +
  26 +&pinctrl_uart1 {
  27 + u-boot,dm-pre-reloc;
  28 +};
  29 +
  30 +&iomuxc {
  31 + u-boot,dm-pre-reloc;
  32 +};
  33 +
  34 +&aips1 {
  35 + u-boot,dm-pre-reloc;
  36 +};
  37 +
  38 +&backlight {
  39 + pwms = <&pwm1 0 300000>;
  40 + default-brightness-level = <2>;
  41 +};
  42 +
  43 +/*
  44 + * allow switching write protect / reset pin by gpio,
  45 + * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot
  46 + */
  47 +&gpio2 {
  48 + u-boot,dm-pre-reloc;
  49 +
  50 + wp_spi_nor {
  51 + gpio-hog;
  52 + output-high;
  53 + gpios = <15 GPIO_ACTIVE_HIGH>;
  54 + };
  55 +
  56 + reset_spi_nor {
  57 + gpio-hog;
  58 + output-high;
  59 + gpios = <28 GPIO_ACTIVE_HIGH>;
  60 + };
  61 +};
  62 +
  63 +&gpio4 {
  64 + u-boot,dm-pre-reloc;
  65 +};
  66 +
  67 +&ecspi1 {
  68 + u-boot,dm-pre-reloc;
  69 +};
  70 +
  71 +&flash {
  72 + u-boot,dm-pre-reloc;
  73 +};
  74 +
  75 +&pinctrl_ecspi1 {
  76 + u-boot,dm-pre-reloc;
  77 +};
arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi
Diff comments   View file @ c08aa77
  1 +// SPDX-License-Identifier: (GPL-2.0)
  2 +/*
  3 + * support for the imx6 based aristainetos2b-csl board
  4 + *
  5 + * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
  6 + * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
  7 + *
  8 + */
  9 +#include <dt-bindings/gpio/gpio.h>
  10 +#include <dt-bindings/clock/imx6qdl-clock.h>
  11 +
  12 +#include "imx6qdl-aristainetos2-common.dtsi"
  13 +
  14 +/ {
  15 + leds {
  16 + compatible = "gpio-leds";
  17 + pinctrl-names = "default";
  18 + pinctrl-0 = <&pinctrl_gpio>;
  19 +
  20 + LED_blue {
  21 + label = "led_blue";
  22 + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
  23 + };
  24 +
  25 + LED_green {
  26 + label = "led_green";
  27 + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
  28 + };
  29 +
  30 + LED_red {
  31 + label = "led_red";
  32 + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
  33 + };
  34 +
  35 + LED_yellow {
  36 + label = "led_yellow";
  37 + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
  38 + };
  39 +
  40 + LED_blue_2 {
  41 + label = "led_blue2";
  42 + gpios = <&expander 15 GPIO_ACTIVE_LOW>;
  43 + default-state = "off";
  44 + };
  45 +
  46 + LED_green_2 {
  47 + label = "led_green2";
  48 + gpios = <&expander 14 GPIO_ACTIVE_LOW>;
  49 + default-state = "off";
  50 + };
  51 +
  52 + LED_red_2 {
  53 + label = "led_red2";
  54 + gpios = <&expander 12 GPIO_ACTIVE_LOW>;
  55 + default-state = "off";
  56 + };
  57 +
  58 + LED_yellow_2 {
  59 + label = "led_yellow2";
  60 + gpios = <&expander 13 GPIO_ACTIVE_LOW>;
  61 + default-state = "off";
  62 + };
  63 +
  64 + LED_ena {
  65 + label = "led_ena";
  66 + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
  67 + };
  68 + };
  69 +};
  70 +
  71 +&ecspi1 {
  72 + fsl,spi-num-chipselects = <3>;
  73 + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH
  74 + &gpio4 10 GPIO_ACTIVE_HIGH
  75 + &gpio4 11 GPIO_ACTIVE_HIGH>;
  76 + pinctrl-names = "default";
  77 + pinctrl-0 = <&pinctrl_ecspi1>;
  78 + status = "okay";
  79 + pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
  80 + pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
  81 +
  82 + flash: m25p80@0 {
  83 + #address-cells = <1>;
  84 + #size-cells = <1>;
  85 + compatible = "micron,n25q128a11", "jedec,spi-nor";
  86 + spi-max-frequency = <20000000>;
  87 + reg = <0>;
  88 + };
  89 +};
  90 +
  91 +&ecspi4 {
  92 + fsl,spi-num-chipselects = <2>;
  93 + cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
  94 + pinctrl-names = "default";
  95 + pinctrl-0 = <&pinctrl_ecspi4>;
  96 + status = "okay";
  97 +};
  98 +
  99 +&i2c1 {
  100 + tpm@20 {
  101 + compatible = "infineon,slb9645tt";
  102 + reg = <0x20>;
  103 + };
  104 +};
  105 +
  106 +&gpio7 {
  107 + wlan_reset {
  108 + gpio-hog;
  109 + output-high;
  110 + gpios = <8 GPIO_ACTIVE_HIGH>;
  111 + };
  112 +};
  113 +
  114 +&gpmi {
  115 + pinctrl-names = "default";
  116 + pinctrl-0 = <&pinctrl_gpmi_nand>;
  117 + status = "okay";
  118 +};
  119 +
  120 +&usdhc1 {
  121 + pinctrl-names = "default";
  122 + pinctrl-0 = <&pinctrl_usdhc1>;
  123 + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
  124 + status = "okay";
  125 +};
  126 +
  127 +&usdhc2 {
  128 + pinctrl-names = "default";
  129 + pinctrl-0 = <&pinctrl_usdhc2>;
  130 + no-1-8-v;
  131 + status = "okay";
  132 +};
  133 +
  134 +&iomuxc {
  135 + pinctrl_ecspi1: ecspi1grp {
  136 + fsl,pins = <
  137 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
  138 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
  139 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
  140 + /* SS0# */
  141 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
  142 + /* SS1# */
  143 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1
  144 + /* SS2# */
  145 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1
  146 + /* WP pin NOR Flash */
  147 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0
  148 + /* Flash nReset */
  149 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0
  150 + >;
  151 + };
  152 +
  153 + pinctrl_ecspi4: ecspi4grp {
  154 + fsl,pins = <
  155 + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
  156 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
  157 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
  158 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */
  159 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
  160 + >;
  161 + };
  162 +
  163 + pinctrl_gpio: gpiogrp {
  164 + fsl,pins = <
  165 + /* led enable */
  166 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0
  167 + /* LCD power enable */
  168 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0
  169 + /* led yellow */
  170 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0
  171 + /* led red */
  172 + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0
  173 + /* led green */
  174 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0
  175 + /* led blue */
  176 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0
  177 + /* Profibus IRQ */
  178 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
  179 + /* FPGA IRQ currently unused*/
  180 + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
  181 + /* Display reset because of clock failure */
  182 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0
  183 + /* spi bus #2 SS driver enable */
  184 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0
  185 + /* RST_LOC# PHY reset input (has pull-down!)*/
  186 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0
  187 + /* Touchscreen IRQ */
  188 + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
  189 + /* PCIe reset */
  190 + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0
  191 + /* make sure pin is GPIO and not ENET_REF_CLK */
  192 + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0
  193 + /* WLAN Module Reset# */
  194 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0
  195 + >;
  196 + };
  197 +
  198 + pinctrl_gpmi_nand: gpmi-nand {
  199 + fsl,pins = <
  200 + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
  201 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
  202 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
  203 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
  204 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
  205 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
  206 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
  207 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
  208 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
  209 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
  210 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
  211 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
  212 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
  213 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
  214 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
  215 + >;
  216 + };
  217 +
  218 + pinctrl_usbotg: usbotggrp {
  219 + fsl,pins = <
  220 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  221 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
  222 + >;
  223 + };
  224 +
  225 + pinctrl_usdhc1: usdhc1grp {
  226 + fsl,pins = <
  227 + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
  228 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
  229 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
  230 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
  231 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
  232 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
  233 + /* SD1 card detect input */
  234 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
  235 + >;
  236 + };
  237 +
  238 + pinctrl_usdhc2: usdhc2grp {
  239 + fsl,pins = <
  240 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71
  241 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71
  242 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
  243 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
  244 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
  245 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
  246 + >;
  247 + };
  248 +};
arch/arm/mach-imx/mx6/Kconfig
Diff comments   View file @ c08aa77
... ... @@ -147,6 +147,17 @@
147 147 imply CMD_SATA
148 148 imply CMD_DM
149 149  
  150 +config TARGET_ARISTAINETOS2BCSL
  151 + bool "Support aristainetos2-revB CSL"
  152 + select BOARD_LATE_INIT
  153 + select MX6DL
  154 + select SYS_I2C_MXC
  155 + select MXC_UART
  156 + select FEC_MXC
  157 + select DM
  158 + imply CMD_SATA
  159 + imply CMD_DM
  160 +
150 161 config TARGET_CGTQMX6EVAL
151 162 bool "cgtqmx6eval"
152 163 select BOARD_LATE_INIT
board/aristainetos/Kconfig
Diff comments   View file @ c08aa77
... ... @@ -21,4 +21,16 @@
21 21 default 3
22 22  
23 23 endif
  24 +
  25 +if TARGET_ARISTAINETOS2BCSL
  26 +
  27 +source "board/aristainetos/common/Kconfig"
  28 +
  29 +config SYS_BOARD
  30 + default "aristainetos"
  31 +
  32 +config SYS_BOARD_VERSION
  33 + default 4
  34 +
  35 +endif
board/aristainetos/MAINTAINERS
Diff comments   View file @ c08aa77
... ... @@ -5,6 +5,7 @@
5 5 F: include/configs/aristainetos2.h
6 6 F: configs/aristainetos2_defconfig
7 7 F: configs/aristainetos2b_defconfig
  8 +F: configs/aristainetos2bcsl_defconfig
8 9 F: arch/arm/dts/imx6qdl-aristainetos2.dtsi
9 10 F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
10 11 F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
... ... @@ -20,4 +21,10 @@
20 21 F: arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi
21 22 F: arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi
22 23 F: arch/arm/dts/imx6qdl-aristainetos2b.dtsi
  24 +F: arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts
  25 +F: arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi
  26 +F: arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts
  27 +F: arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi
  28 +F: arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi
  29 +F: arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi
board/aristainetos/aristainetos.c
Diff comments   View file @ c08aa77
... ... @@ -490,7 +490,9 @@
490 490 .vmode = FB_VMODE_NONINTERLACED
491 491 }
492 492 }
493   -#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
  493 +#if ((CONFIG_SYS_BOARD_VERSION == 2) || \
  494 + (CONFIG_SYS_BOARD_VERSION == 3) || \
  495 + (CONFIG_SYS_BOARD_VERSION == 4))
494 496 , {
495 497 .bus = -1,
496 498 .addr = 0,
board/aristainetos/common/Kconfig
Diff comments   View file @ c08aa77
... ... @@ -4,6 +4,7 @@
4 4 version of aristainetos board version
5 5 2 version 2
6 6 3 version 2b
  7 + 4 version 2bcsl
7 8  
8 9 config SYS_I2C_MXC_I2C1
9 10 default y
configs/aristainetos2bcsl_defconfig
Diff comments   View file @ c08aa77
  1 +CONFIG_ARM=y
  2 +CONFIG_SYS_THUMB_BUILD=y
  3 +CONFIG_ARCH_MX6=y
  4 +CONFIG_SYS_TEXT_BASE=0x17800000
  5 +CONFIG_SYS_MALLOC_F_LEN=0xe000
  6 +CONFIG_ENV_SIZE=0x3000
  7 +CONFIG_ENV_OFFSET=0xD0000
  8 +CONFIG_TARGET_ARISTAINETOS2BCSL=y
  9 +CONFIG_NR_DRAM_BANKS=1
  10 +CONFIG_ENV_SECT_SIZE=0x10000
  11 +CONFIG_IMX_HAB=y
  12 +# CONFIG_CMD_DEKBLOB is not set
  13 +# CONFIG_CMD_NANDBCB is not set
  14 +CONFIG_FIT=y
  15 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg"
  16 +CONFIG_BOOTDELAY=3
  17 +CONFIG_USE_BOOTCOMMAND=y
  18 +CONFIG_BOOTCOMMAND="run ari_boot"
  19 +# CONFIG_CONSOLE_MUX is not set
  20 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  21 +CONFIG_SUPPORT_RAW_INITRD=y
  22 +CONFIG_VERSION_VARIABLE=y
  23 +CONFIG_BOUNCE_BUFFER=y
  24 +CONFIG_BOARD_TYPES=y
  25 +CONFIG_BOARD_EARLY_INIT_F=y
  26 +CONFIG_HUSH_PARSER=y
  27 +CONFIG_AUTOBOOT_KEYED=y
  28 +CONFIG_AUTOBOOT_ENCRYPTION=y
  29 +CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb"
  30 +CONFIG_CMD_BOOTZ=y
  31 +# CONFIG_BOOTM_NETBSD is not set
  32 +# CONFIG_BOOTM_PLAN9 is not set
  33 +# CONFIG_BOOTM_RTEMS is not set
  34 +# CONFIG_BOOTM_VXWORKS is not set
  35 +# CONFIG_CMD_FLASH is not set
  36 +CONFIG_CMD_GPIO=y
  37 +CONFIG_CMD_I2C=y
  38 +CONFIG_CMD_MMC=y
  39 +CONFIG_CMD_NAND_TRIMFFS=y
  40 +# CONFIG_CMD_PINMUX is not set
  41 +# CONFIG_CMD_SATA is not set
  42 +CONFIG_CMD_USB=y
  43 +CONFIG_CMD_DHCP=y
  44 +CONFIG_CMD_MII=y
  45 +CONFIG_CMD_PING=y
  46 +CONFIG_CMD_BMP=y
  47 +CONFIG_CMD_CACHE=y
  48 +# CONFIG_CMD_HASH is not set
  49 +CONFIG_CMD_EXT2=y
  50 +CONFIG_CMD_EXT4=y
  51 +CONFIG_CMD_EXT4_WRITE=y
  52 +CONFIG_CMD_FAT=y
  53 +CONFIG_CMD_FS_GENERIC=y
  54 +CONFIG_CMD_MTDPARTS=y
  55 +CONFIG_CMD_UBI=y
  56 +CONFIG_OF_CONTROL=y
  57 +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_csl_4"
  58 +CONFIG_OF_LIST="imx6dl-aristainetos2b_csl_4 imx6dl-aristainetos2b_csl_7"
  59 +CONFIG_DTB_RESELECT=y
  60 +CONFIG_MULTI_DTB_FIT=y
  61 +CONFIG_ENV_IS_IN_SPI_FLASH=y
  62 +CONFIG_ENV_SPI_EARLY=y
  63 +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
  64 +CONFIG_ENV_OFFSET_REDUND=0xE0000
  65 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  66 +CONFIG_DM_GPIO=y
  67 +CONFIG_GPIO_HOG=y
  68 +CONFIG_DM_PCA953X=y
  69 +CONFIG_DM_I2C=y
  70 +CONFIG_LED=y
  71 +CONFIG_LED_GPIO=y
  72 +CONFIG_MISC=y
  73 +CONFIG_I2C_EEPROM=y
  74 +CONFIG_DM_MMC=y
  75 +CONFIG_FSL_USDHC=y
  76 +CONFIG_MTD=y
  77 +CONFIG_NAND=y
  78 +CONFIG_NAND_MXS=y
  79 +CONFIG_DM_SPI_FLASH=y
  80 +CONFIG_SF_DEFAULT_MODE=0
  81 +CONFIG_SF_DEFAULT_SPEED=20000000
  82 +CONFIG_SPI_FLASH_STMICRO=y
  83 +CONFIG_SPI_FLASH_MTD=y
  84 +CONFIG_MTD_UBI_FASTMAP=y
  85 +CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
  86 +CONFIG_PHYLIB=y
  87 +CONFIG_PHY_MICREL=y
  88 +CONFIG_PHY_MICREL_KSZ90X1=y
  89 +CONFIG_DM_ETH=y
  90 +CONFIG_MII=y
  91 +CONFIG_PHY=y
  92 +CONFIG_PINCTRL=y
  93 +CONFIG_PINCTRL_IMX6=y
  94 +CONFIG_DM_PMIC=y
  95 +CONFIG_DM_REGULATOR=y
  96 +CONFIG_DM_REGULATOR_FIXED=y
  97 +CONFIG_DM_PWM=y
  98 +CONFIG_PWM_IMX=y
  99 +CONFIG_DM_RTC=y
  100 +CONFIG_RTC_DS1307=y
  101 +CONFIG_DM_SERIAL=y
  102 +CONFIG_SPI=y
  103 +CONFIG_DM_SPI=y
  104 +CONFIG_MXC_SPI=y
  105 +CONFIG_SYSRESET=y
  106 +CONFIG_SYSRESET_WATCHDOG=y
  107 +CONFIG_USB=y
  108 +CONFIG_DM_USB=y
  109 +CONFIG_USB_STORAGE=y
  110 +CONFIG_DM_VIDEO=y
  111 +CONFIG_SYS_WHITE_ON_BLACK=y
  112 +CONFIG_DISPLAY=y
  113 +CONFIG_VIDEO_IPUV3=y
  114 +CONFIG_IMX_WATCHDOG=y
  115 +# CONFIG_EFI_LOADER is not set
include/configs/aristainetos2.h
Diff comments   View file @ c08aa77
... ... @@ -107,6 +107,27 @@
107 107 "${fit_file}\0" \
108 108 "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \
109 109 "${fit_addr_r} ${rescue_fit_file}\0"
  110 +#elif (CONFIG_SYS_BOARD_VERSION == 4)
  111 +#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
  112 + "dead=led led_red on;led led_red2 on;\0" \
  113 + "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \
  114 + "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \
  115 + "-(ubi-nor);gpmi-nand:-(ubi)\0" \
  116 + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \
  117 + "bootmode=${bootmode} mmcpart=${mmcpart}\0" \
  118 + "mainboot=echo Booting from SD-card ...; " \
  119 + "run mainargs addmtd addmisc;" \
  120 + "if test -n ${addmiscM}; then run addmiscM;fi;" \
  121 + "if test -n ${addmiscC}; then run addmiscC;fi;" \
  122 + "if test -n ${addmiscD}; then run addmiscD;fi;" \
  123 + "run boot_board_type;" \
  124 + "bootm ${fit_addr_r}\0" \
  125 + "mainargs=setenv bootargs console=${console},${baudrate} " \
  126 + "root=${mmcroot}\0" \
  127 + "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
  128 + "${fit_file}\0" \
  129 + "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \
  130 + "${fit_addr_r} ${rescue_fit_file}\0"
110 131 #else
111 132 #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
112 133 "dead=led led_red on\0" \