mmc: Add support for UHS modes

Add UHS modes to the list of supported modes, get the UHS capabilites of the SDcard and implement the procedure to switch the voltage (UHS modes use 1v8 IO lines) During the voltage switch procedure, DAT0 is used by the card to signal when it's ready. The optional card_busy() callback can be used to get this information from the host driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>

mmc: Add support for UHS modes
Add UHS modes to the list of supported modes, get the UHS capabilites of the SDcard and implement the procedure to switch the voltage (UHS modes use 1v8 IO lines) During the voltage switch procedure, DAT0 is used by the card to signal when it's ready. The optional card_busy() callback can be used to get this information from the host driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Jean-Jacques Hiblot · Jaehoon Chung
1 parent 634d484940
Showing 3 changed files with 221 additions and 9 deletions Side-by-side Diff
drivers/mmc/mmc-uclass.c
drivers/mmc/mmc.c
include/mmc.h
@@ -64,6 +64,20 @@
 	dm_mmc_send_init_stream(mmc->dev);
 }
  
+int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout)
+{
+	struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+	if (!ops->wait_dat0)
+		return -ENOSYS;
+	return ops->wait_dat0(dev, state, timeout);
+}
+
+int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
+{
+	return dm_mmc_wait_dat0(mmc->dev, state, timeout);
+}
+
 int dm_mmc_get_wp(struct udevice *dev)
 {
 	struct dm_mmc_ops *ops = mmc_get_ops(dev);
@@ -57,6 +57,12 @@
 #endif
  
 #if !CONFIG_IS_ENABLED(DM_MMC)
+
+static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
+{
+	return -ENOSYS;
+}
+
 __weak int board_mmc_getwp(struct mmc *mmc)
 {
 	return -1;
  
@@ -402,8 +408,68 @@
 	return 0;
 }
  
-static int sd_send_op_cond(struct mmc *mmc)
+static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
 {
+	struct mmc_cmd cmd;
+	int err = 0;
+
+	/*
+	 * Send CMD11 only if the request is to switch the card to
+	 * 1.8V signalling.
+	 */
+	if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
+		return mmc_set_signal_voltage(mmc, signal_voltage);
+
+	cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
+	cmd.cmdarg = 0;
+	cmd.resp_type = MMC_RSP_R1;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err)
+		return err;
+
+	if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
+		return -EIO;
+
+	/*
+	 * The card should drive cmd and dat[0:3] low immediately
+	 * after the response of cmd11, but wait 100 us to be sure
+	 */
+	err = mmc_wait_dat0(mmc, 0, 100);
+	if (err == -ENOSYS)
+		udelay(100);
+	else if (err)
+		return -ETIMEDOUT;
+
+	/*
+	 * During a signal voltage level switch, the clock must be gated
+	 * for 5 ms according to the SD spec
+	 */
+	mmc_set_clock(mmc, mmc->clock, true);
+
+	err = mmc_set_signal_voltage(mmc, signal_voltage);
+	if (err)
+		return err;
+
+	/* Keep clock gated for at least 10 ms, though spec only says 5 ms */
+	mdelay(10);
+	mmc_set_clock(mmc, mmc->clock, false);
+
+	/*
+	 * Failure to switch is indicated by the card holding
+	 * dat[0:3] low. Wait for at least 1 ms according to spec
+	 */
+	err = mmc_wait_dat0(mmc, 1, 1000);
+	if (err == -ENOSYS)
+		udelay(1000);
+	else if (err)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
+{
 	int timeout = 1000;
 	int err;
 	struct mmc_cmd cmd;
@@ -434,6 +500,9 @@
 		if (mmc->version == SD_VERSION_2)
 			cmd.cmdarg |= OCR_HCS;
  
+		if (uhs_en)
+			cmd.cmdarg |= OCR_S18R;
+
 		err = mmc_send_cmd(mmc, &cmd, NULL);
  
 		if (err)
@@ -464,6 +533,13 @@
  
 	mmc->ocr = cmd.response[0];
  
+	if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
+	    == 0x41000000) {
+		err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
+		if (err)
+			return err;
+	}
+
 	mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
 	mmc->rca = 0;
  
@@ -977,6 +1053,7 @@
 	ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
 	struct mmc_data data;
 	int timeout;
+	u32 sd3_bus_mode;
  
 	mmc->card_caps = MMC_MODE_1BIT;
  
@@ -1058,6 +1135,22 @@
 	if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
 		mmc->card_caps |= MMC_CAP(SD_HS);
  
+	/* Version before 3.0 don't support UHS modes */
+	if (mmc->version < SD_VERSION_3)
+		return 0;
+
+	sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
+	if (sd3_bus_mode & SD_MODE_UHS_SDR104)
+		mmc->card_caps |= MMC_CAP(UHS_SDR104);
+	if (sd3_bus_mode & SD_MODE_UHS_SDR50)
+		mmc->card_caps |= MMC_CAP(UHS_SDR50);
+	if (sd3_bus_mode & SD_MODE_UHS_SDR25)
+		mmc->card_caps |= MMC_CAP(UHS_SDR25);
+	if (sd3_bus_mode & SD_MODE_UHS_SDR12)
+		mmc->card_caps |= MMC_CAP(UHS_SDR12);
+	if (sd3_bus_mode & SD_MODE_UHS_DDR50)
+		mmc->card_caps |= MMC_CAP(UHS_DDR50);
+
 	return 0;
 }
  
  
  
@@ -1066,12 +1159,35 @@
 	int err;
  
 	ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
+	int speed;
  
-	err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
+	switch (mode) {
+	case SD_LEGACY:
+	case UHS_SDR12:
+		speed = UHS_SDR12_BUS_SPEED;
+		break;
+	case SD_HS:
+	case UHS_SDR25:
+		speed = UHS_SDR25_BUS_SPEED;
+		break;
+	case UHS_SDR50:
+		speed = UHS_SDR50_BUS_SPEED;
+		break;
+	case UHS_DDR50:
+		speed = UHS_DDR50_BUS_SPEED;
+		break;
+	case UHS_SDR104:
+		speed = UHS_SDR104_BUS_SPEED;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
 	if (err)
 		return err;
  
-	if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) != 0x01000000)
+	if ((__be32_to_cpu(switch_status[4]) >> 24) != speed)
 		return -ENOTSUPP;
  
 	return 0;
  
@@ -1286,10 +1402,31 @@
  
 static const struct mode_width_tuning sd_modes_by_pref[] = {
 	{
+		.mode = UHS_SDR104,
+		.widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+		.tuning = MMC_CMD_SEND_TUNING_BLOCK
+	},
+	{
+		.mode = UHS_SDR50,
+		.widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+	},
+	{
+		.mode = UHS_DDR50,
+		.widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+	},
+	{
+		.mode = UHS_SDR25,
+		.widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+	},
+	{
 		.mode = SD_HS,
 		.widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
 	},
 	{
+		.mode = UHS_SDR12,
+		.widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+	},
+	{
 		.mode = SD_LEGACY,
 		.widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
 	}
  
  
  
  
@@ -1306,18 +1443,24 @@
 	int err;
 	uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
 	const struct mode_width_tuning *mwt;
+	bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
+	uint caps;
  
+
 	err = sd_get_capabilities(mmc);
 	if (err)
 		return err;
 	/* Restrict card's capabilities by what the host can do */
-	mmc->card_caps &= (mmc->cfg->host_caps | MMC_MODE_1BIT);
+	caps = mmc->card_caps & (mmc->cfg->host_caps | MMC_MODE_1BIT);
  
-	for_each_sd_mode_by_pref(mmc->card_caps, mwt) {
+	if (!uhs_en)
+		caps &= ~UHS_CAPS;
+
+	for_each_sd_mode_by_pref(caps, mwt) {
 		uint *w;
  
 		for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
-			if (*w & mmc->card_caps & mwt->widths) {
+			if (*w & caps & mwt->widths) {
 				debug("trying mode %s width %d (at %d MHz)\n",
 				      mmc_mode_name(mwt->mode),
 				      bus_width(*w),
@@ -1338,6 +1481,16 @@
 				mmc_select_mode(mmc, mwt->mode);
 				mmc_set_clock(mmc, mmc->tran_speed, false);
  
+				/* execute tuning if needed */
+				if (mwt->tuning && !mmc_host_is_spi(mmc)) {
+					err = mmc_execute_tuning(mmc,
+								 mwt->tuning);
+					if (err) {
+						debug("tuning failed\n");
+						goto error;
+					}
+				}
+
 				err = sd_read_ssr(mmc);
 				if (!err)
 					return 0;
@@ -2000,7 +2153,7 @@
 		int ret = regulator_set_enable(mmc->vmmc_supply, false);
  
 		if (ret) {
-			puts("Error disabling VMMC supply\n");
+			debug("Error disabling VMMC supply\n");
 			return ret;
 		}
 	}
@@ -2026,6 +2179,7 @@
 int mmc_start_init(struct mmc *mmc)
 {
 	bool no_card;
+	bool uhs_en = supports_uhs(mmc->cfg->host_caps);
 	int err;
  
 	/* we pretend there's no card when init is NULL */
@@ -2065,6 +2219,7 @@
 #endif
 	mmc->ddr_mode = 0;
  
+retry:
 	mmc_set_initial_state(mmc);
 	mmc_send_init_stream(mmc);
  
@@ -2081,7 +2236,12 @@
 	err = mmc_send_if_cond(mmc);
  
 	/* Now try to get the SD card's operating condition */
-	err = sd_send_op_cond(mmc);
+	err = sd_send_op_cond(mmc, uhs_en);
+	if (err && uhs_en) {
+		uhs_en = false;
+		mmc_power_cycle(mmc);
+		goto retry;
+	}
  
 	/* If the command timed out, we check for an MMC card */
 	if (err == -ETIMEDOUT) {
@@ -87,6 +87,7 @@
 #define MMC_CMD_SET_BLOCKLEN		16
 #define MMC_CMD_READ_SINGLE_BLOCK	17
 #define MMC_CMD_READ_MULTIPLE_BLOCK	18
+#define MMC_CMD_SEND_TUNING_BLOCK		19
 #define MMC_CMD_SEND_TUNING_BLOCK_HS200	21
 #define MMC_CMD_SET_BLOCK_COUNT         23
 #define MMC_CMD_WRITE_SINGLE_BLOCK	24
@@ -117,7 +118,8 @@
  
 static inline bool mmc_is_tuning_cmd(uint cmdidx)
 {
-	if (cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
+	if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
+	    (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
 		return true;
 	return false;
 }
  
@@ -126,8 +128,22 @@
 #define SD_HIGHSPEED_BUSY	0x00020000
 #define SD_HIGHSPEED_SUPPORTED	0x00020000
  
+#define UHS_SDR12_BUS_SPEED	0
+#define HIGH_SPEED_BUS_SPEED	1
+#define UHS_SDR25_BUS_SPEED	1
+#define UHS_SDR50_BUS_SPEED	2
+#define UHS_SDR104_BUS_SPEED	3
+#define UHS_DDR50_BUS_SPEED	4
+
+#define SD_MODE_UHS_SDR12	BIT(UHS_SDR12_BUS_SPEED)
+#define SD_MODE_UHS_SDR25	BIT(UHS_SDR25_BUS_SPEED)
+#define SD_MODE_UHS_SDR50	BIT(UHS_SDR50_BUS_SPEED)
+#define SD_MODE_UHS_SDR104	BIT(UHS_SDR104_BUS_SPEED)
+#define SD_MODE_UHS_DDR50	BIT(UHS_DDR50_BUS_SPEED)
+
 #define OCR_BUSY		0x80000000
 #define OCR_HCS			0x40000000
+#define OCR_S18R		0x1000000
 #define OCR_VOLTAGE_MASK	0x007FFF80
 #define OCR_ACCESS_MODE		0x60000000
  
@@ -410,6 +426,17 @@
 	 * @return 0 if OK, -ve on error
 	 */
 	int (*execute_tuning)(struct udevice *dev, uint opcode);
+
+	/**
+	 * wait_dat0() - wait until dat0 is in the target state
+	 *		(CLK must be running during the wait)
+	 *
+	 * @dev:	Device to check
+	 * @state:	target state
+	 * @timeout:	timeout in us
+	 * @return 0 if dat0 is in the target state, -ve on error
+	 */
+	int (*wait_dat0)(struct udevice *dev, int state, int timeout);
 };
  
 #define mmc_get_ops(dev)        ((struct dm_mmc_ops *)(dev)->driver->ops)
@@ -421,6 +448,7 @@
 int dm_mmc_get_cd(struct udevice *dev);
 int dm_mmc_get_wp(struct udevice *dev);
 int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
+int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
  
 /* Transition functions for compatibility */
 int mmc_set_ios(struct mmc *mmc);
@@ -428,6 +456,7 @@
 int mmc_getcd(struct mmc *mmc);
 int mmc_getwp(struct mmc *mmc);
 int mmc_execute_tuning(struct mmc *mmc, uint opcode);
+int mmc_wait_dat0(struct mmc *mmc, int state, int timeout);
  
 #else
 struct mmc_ops {
@@ -484,6 +513,15 @@
 		return true;
 	else
 		return false;
+}
+
+#define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
+		  MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
+		  MMC_CAP(UHS_DDR50))
+
+static inline bool supports_uhs(uint caps)
+{
+	return (caps & UHS_CAPS) ? true : false;
 }
  
 /*
...	...	@@ -64,6 +64,20 @@
64	64	dm_mmc_send_init_stream(mmc->dev);
65	65	}
66	66
	67	+int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout)
	68	+{
	69	+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
	70	+
	71	+ if (!ops->wait_dat0)
	72	+ return -ENOSYS;
	73	+ return ops->wait_dat0(dev, state, timeout);
	74	+}
	75	+
	76	+int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
	77	+{
	78	+ return dm_mmc_wait_dat0(mmc->dev, state, timeout);
	79	+}
	80	+
67	81	int dm_mmc_get_wp(struct udevice *dev)
68	82	{
69	83	struct dm_mmc_ops *ops = mmc_get_ops(dev);
...	...	@@ -57,6 +57,12 @@
57	57	#endif
58	58
59	59	#if !CONFIG_IS_ENABLED(DM_MMC)
	60	+
	61	+static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
	62	+{
	63	+ return -ENOSYS;
	64	+}
	65	+
60	66	__weak int board_mmc_getwp(struct mmc *mmc)
61	67	{
62	68	return -1;
63	69
...	...	@@ -402,8 +408,68 @@
402	408	return 0;
403	409	}
404	410
405		-static int sd_send_op_cond(struct mmc *mmc)
	411	+static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
406	412	{
	413	+ struct mmc_cmd cmd;
	414	+ int err = 0;
	415	+
	416	+ /*
	417	+ * Send CMD11 only if the request is to switch the card to
	418	+ * 1.8V signalling.
	419	+ */
	420	+ if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
	421	+ return mmc_set_signal_voltage(mmc, signal_voltage);
	422	+
	423	+ cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
	424	+ cmd.cmdarg = 0;
	425	+ cmd.resp_type = MMC_RSP_R1;
	426	+
	427	+ err = mmc_send_cmd(mmc, &cmd, NULL);
	428	+ if (err)
	429	+ return err;
	430	+
	431	+ if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
	432	+ return -EIO;
	433	+
	434	+ /*
	435	+ * The card should drive cmd and dat[0:3] low immediately
	436	+ * after the response of cmd11, but wait 100 us to be sure
	437	+ */
	438	+ err = mmc_wait_dat0(mmc, 0, 100);
	439	+ if (err == -ENOSYS)
	440	+ udelay(100);
	441	+ else if (err)
	442	+ return -ETIMEDOUT;
	443	+
	444	+ /*
	445	+ * During a signal voltage level switch, the clock must be gated
	446	+ * for 5 ms according to the SD spec
	447	+ */
	448	+ mmc_set_clock(mmc, mmc->clock, true);
	449	+
	450	+ err = mmc_set_signal_voltage(mmc, signal_voltage);
	451	+ if (err)
	452	+ return err;
	453	+
	454	+ /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
	455	+ mdelay(10);
	456	+ mmc_set_clock(mmc, mmc->clock, false);
	457	+
	458	+ /*
	459	+ * Failure to switch is indicated by the card holding
	460	+ * dat[0:3] low. Wait for at least 1 ms according to spec
	461	+ */
	462	+ err = mmc_wait_dat0(mmc, 1, 1000);
	463	+ if (err == -ENOSYS)
	464	+ udelay(1000);
	465	+ else if (err)
	466	+ return -ETIMEDOUT;
	467	+
	468	+ return 0;
	469	+}
	470	+
	471	+static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
	472	+{
407	473	int timeout = 1000;
408	474	int err;
409	475	struct mmc_cmd cmd;
...	...	@@ -434,6 +500,9 @@
434	500	if (mmc->version == SD_VERSION_2)
435	501	cmd.cmdarg \|= OCR_HCS;
436	502
	503	+ if (uhs_en)
	504	+ cmd.cmdarg \|= OCR_S18R;
	505	+
437	506	err = mmc_send_cmd(mmc, &cmd, NULL);
438	507
439	508	if (err)
...	...	@@ -464,6 +533,13 @@
464	533
465	534	mmc->ocr = cmd.response[0];
466	535
	536	+ if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
	537	+ == 0x41000000) {
	538	+ err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
	539	+ if (err)
	540	+ return err;
	541	+ }
	542	+
467	543	mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
468	544	mmc->rca = 0;
469	545
...	...	@@ -977,6 +1053,7 @@
977	1053	ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
978	1054	struct mmc_data data;
979	1055	int timeout;
	1056	+ u32 sd3_bus_mode;
980	1057
981	1058	mmc->card_caps = MMC_MODE_1BIT;
982	1059
...	...	@@ -1058,6 +1135,22 @@
1058	1135	if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1059	1136	mmc->card_caps \|= MMC_CAP(SD_HS);
1060	1137
	1138	+ /* Version before 3.0 don't support UHS modes */
	1139	+ if (mmc->version < SD_VERSION_3)
	1140	+ return 0;
	1141	+
	1142	+ sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
	1143	+ if (sd3_bus_mode & SD_MODE_UHS_SDR104)
	1144	+ mmc->card_caps \|= MMC_CAP(UHS_SDR104);
	1145	+ if (sd3_bus_mode & SD_MODE_UHS_SDR50)
	1146	+ mmc->card_caps \|= MMC_CAP(UHS_SDR50);
	1147	+ if (sd3_bus_mode & SD_MODE_UHS_SDR25)
	1148	+ mmc->card_caps \|= MMC_CAP(UHS_SDR25);
	1149	+ if (sd3_bus_mode & SD_MODE_UHS_SDR12)
	1150	+ mmc->card_caps \|= MMC_CAP(UHS_SDR12);
	1151	+ if (sd3_bus_mode & SD_MODE_UHS_DDR50)
	1152	+ mmc->card_caps \|= MMC_CAP(UHS_DDR50);
	1153	+
1061	1154	return 0;
1062	1155	}
1063	1156
1064	1157
1065	1158
...	...	@@ -1066,12 +1159,35 @@
1066	1159	int err;
1067	1160
1068	1161	ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
	1162	+ int speed;
1069	1163
1070		- err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
	1164	+ switch (mode) {
	1165	+ case SD_LEGACY:
	1166	+ case UHS_SDR12:
	1167	+ speed = UHS_SDR12_BUS_SPEED;
	1168	+ break;
	1169	+ case SD_HS:
	1170	+ case UHS_SDR25:
	1171	+ speed = UHS_SDR25_BUS_SPEED;
	1172	+ break;
	1173	+ case UHS_SDR50:
	1174	+ speed = UHS_SDR50_BUS_SPEED;
	1175	+ break;
	1176	+ case UHS_DDR50:
	1177	+ speed = UHS_DDR50_BUS_SPEED;
	1178	+ break;
	1179	+ case UHS_SDR104:
	1180	+ speed = UHS_SDR104_BUS_SPEED;
	1181	+ break;
	1182	+ default:
	1183	+ return -EINVAL;
	1184	+ }
	1185	+
	1186	+ err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1071	1187	if (err)
1072	1188	return err;
1073	1189
1074		- if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) != 0x01000000)
	1190	+ if ((__be32_to_cpu(switch_status[4]) >> 24) != speed)
1075	1191	return -ENOTSUPP;
1076	1192
1077	1193	return 0;
1078	1194
...	...	@@ -1286,10 +1402,31 @@
1286	1402
1287	1403	static const struct mode_width_tuning sd_modes_by_pref[] = {
1288	1404	{
	1405	+ .mode = UHS_SDR104,
	1406	+ .widths = MMC_MODE_4BIT \| MMC_MODE_1BIT,
	1407	+ .tuning = MMC_CMD_SEND_TUNING_BLOCK
	1408	+ },
	1409	+ {
	1410	+ .mode = UHS_SDR50,
	1411	+ .widths = MMC_MODE_4BIT \| MMC_MODE_1BIT,
	1412	+ },
	1413	+ {
	1414	+ .mode = UHS_DDR50,
	1415	+ .widths = MMC_MODE_4BIT \| MMC_MODE_1BIT,
	1416	+ },
	1417	+ {
	1418	+ .mode = UHS_SDR25,
	1419	+ .widths = MMC_MODE_4BIT \| MMC_MODE_1BIT,
	1420	+ },
	1421	+ {
1289	1422	.mode = SD_HS,
1290	1423	.widths = MMC_MODE_4BIT \| MMC_MODE_1BIT,
1291	1424	},
1292	1425	{
	1426	+ .mode = UHS_SDR12,
	1427	+ .widths = MMC_MODE_4BIT \| MMC_MODE_1BIT,
	1428	+ },
	1429	+ {
1293	1430	.mode = SD_LEGACY,
1294	1431	.widths = MMC_MODE_4BIT \| MMC_MODE_1BIT,
1295	1432	}
1296	1433
1297	1434
1298	1435
1299	1436
...	...	@@ -1306,18 +1443,24 @@
1306	1443	int err;
1307	1444	uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1308	1445	const struct mode_width_tuning *mwt;
	1446	+ bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
	1447	+ uint caps;
1309	1448
	1449	+
1310	1450	err = sd_get_capabilities(mmc);
1311	1451	if (err)
1312	1452	return err;
1313	1453	/* Restrict card's capabilities by what the host can do */
1314		- mmc->card_caps &= (mmc->cfg->host_caps \| MMC_MODE_1BIT);
	1454	+ caps = mmc->card_caps & (mmc->cfg->host_caps \| MMC_MODE_1BIT);
1315	1455
1316		- for_each_sd_mode_by_pref(mmc->card_caps, mwt) {
	1456	+ if (!uhs_en)
	1457	+ caps &= ~UHS_CAPS;
	1458	+
	1459	+ for_each_sd_mode_by_pref(caps, mwt) {
1317	1460	uint *w;
1318	1461
1319	1462	for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1320		- if (*w & mmc->card_caps & mwt->widths) {
	1463	+ if (*w & caps & mwt->widths) {
1321	1464	debug("trying mode %s width %d (at %d MHz)\n",
1322	1465	mmc_mode_name(mwt->mode),
1323	1466	bus_width(*w),
...	...	@@ -1338,6 +1481,16 @@
1338	1481	mmc_select_mode(mmc, mwt->mode);
1339	1482	mmc_set_clock(mmc, mmc->tran_speed, false);
1340	1483
	1484	+ /* execute tuning if needed */
	1485	+ if (mwt->tuning && !mmc_host_is_spi(mmc)) {
	1486	+ err = mmc_execute_tuning(mmc,
	1487	+ mwt->tuning);
	1488	+ if (err) {
	1489	+ debug("tuning failed\n");
	1490	+ goto error;
	1491	+ }
	1492	+ }
	1493	+
1341	1494	err = sd_read_ssr(mmc);
1342	1495	if (!err)
1343	1496	return 0;
...	...	@@ -2000,7 +2153,7 @@
2000	2153	int ret = regulator_set_enable(mmc->vmmc_supply, false);
2001	2154
2002	2155	if (ret) {
2003		- puts("Error disabling VMMC supply\n");
	2156	+ debug("Error disabling VMMC supply\n");
2004	2157	return ret;
2005	2158	}
2006	2159	}
...	...	@@ -2026,6 +2179,7 @@
2026	2179	int mmc_start_init(struct mmc *mmc)
2027	2180	{
2028	2181	bool no_card;
	2182	+ bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2029	2183	int err;
2030	2184
2031	2185	/* we pretend there's no card when init is NULL */
...	...	@@ -2065,6 +2219,7 @@
2065	2219	#endif
2066	2220	mmc->ddr_mode = 0;
2067	2221
	2222	+retry:
2068	2223	mmc_set_initial_state(mmc);
2069	2224	mmc_send_init_stream(mmc);
2070	2225
...	...	@@ -2081,7 +2236,12 @@
2081	2236	err = mmc_send_if_cond(mmc);
2082	2237
2083	2238	/* Now try to get the SD card's operating condition */
2084		- err = sd_send_op_cond(mmc);
	2239	+ err = sd_send_op_cond(mmc, uhs_en);
	2240	+ if (err && uhs_en) {
	2241	+ uhs_en = false;
	2242	+ mmc_power_cycle(mmc);
	2243	+ goto retry;
	2244	+ }
2085	2245
2086	2246	/* If the command timed out, we check for an MMC card */
2087	2247	if (err == -ETIMEDOUT) {
...	...	@@ -87,6 +87,7 @@
87	87	#define MMC_CMD_SET_BLOCKLEN 16
88	88	#define MMC_CMD_READ_SINGLE_BLOCK 17
89	89	#define MMC_CMD_READ_MULTIPLE_BLOCK 18
	90	+#define MMC_CMD_SEND_TUNING_BLOCK 19
90	91	#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
91	92	#define MMC_CMD_SET_BLOCK_COUNT 23
92	93	#define MMC_CMD_WRITE_SINGLE_BLOCK 24
...	...	@@ -117,7 +118,8 @@
117	118
118	119	static inline bool mmc_is_tuning_cmd(uint cmdidx)
119	120	{
120		- if (cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
	121	+ if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) \|\|
	122	+ (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
121	123	return true;
122	124	return false;
123	125	}
124	126
...	...	@@ -126,8 +128,22 @@
126	128	#define SD_HIGHSPEED_BUSY 0x00020000
127	129	#define SD_HIGHSPEED_SUPPORTED 0x00020000
128	130
	131	+#define UHS_SDR12_BUS_SPEED 0
	132	+#define HIGH_SPEED_BUS_SPEED 1
	133	+#define UHS_SDR25_BUS_SPEED 1
	134	+#define UHS_SDR50_BUS_SPEED 2
	135	+#define UHS_SDR104_BUS_SPEED 3
	136	+#define UHS_DDR50_BUS_SPEED 4
	137	+
	138	+#define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
	139	+#define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
	140	+#define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
	141	+#define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
	142	+#define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
	143	+
129	144	#define OCR_BUSY 0x80000000
130	145	#define OCR_HCS 0x40000000
	146	+#define OCR_S18R 0x1000000
131	147	#define OCR_VOLTAGE_MASK 0x007FFF80
132	148	#define OCR_ACCESS_MODE 0x60000000
133	149
...	...	@@ -410,6 +426,17 @@
410	426	* @return 0 if OK, -ve on error
411	427	*/
412	428	int (execute_tuning)(struct udevice dev, uint opcode);
	429	+
	430	+ /**
	431	+ * wait_dat0() - wait until dat0 is in the target state
	432	+ * (CLK must be running during the wait)
	433	+ *
	434	+ * @dev: Device to check
	435	+ * @state: target state
	436	+ * @timeout: timeout in us
	437	+ * @return 0 if dat0 is in the target state, -ve on error
	438	+ */
	439	+ int (wait_dat0)(struct udevice dev, int state, int timeout);
413	440	};
414	441
415	442	#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
...	...	@@ -421,6 +448,7 @@
421	448	int dm_mmc_get_cd(struct udevice *dev);
422	449	int dm_mmc_get_wp(struct udevice *dev);
423	450	int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
	451	+int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
424	452
425	453	/* Transition functions for compatibility */
426	454	int mmc_set_ios(struct mmc *mmc);
...	...	@@ -428,6 +456,7 @@
428	456	int mmc_getcd(struct mmc *mmc);
429	457	int mmc_getwp(struct mmc *mmc);
430	458	int mmc_execute_tuning(struct mmc *mmc, uint opcode);
	459	+int mmc_wait_dat0(struct mmc *mmc, int state, int timeout);
431	460
432	461	#else
433	462	struct mmc_ops {
...	...	@@ -484,6 +513,15 @@
484	513	return true;
485	514	else
486	515	return false;
	516	+}
	517	+
	518	+#define UHS_CAPS (MMC_CAP(UHS_SDR12) \| MMC_CAP(UHS_SDR25) \| \
	519	+ MMC_CAP(UHS_SDR50) \| MMC_CAP(UHS_SDR104) \| \
	520	+ MMC_CAP(UHS_DDR50))
	521	+
	522	+static inline bool supports_uhs(uint caps)
	523	+{
	524	+ return (caps & UHS_CAPS) ? true : false;
487	525	}
488	526
489	527	/*