Eric Lee / smarc-uboot

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Commit c133c1fb0b590662206b0eba70f4478ee0300a9a

Authored by Yusuke Goda
Committed by Nobuhiro Iwamatsu
1 parent 1a2334a4eb
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

sh: Add support Renesas Solutions R7780MP 

Renesas Solutions R7780MP is a reference board on SH7780.
This board has serial, 10/100 base Ethernet deivice, CF slot
and VGA devices. This board can set extension board.
Extension board has 10/100/1000 base Ethernet device, PCI slot,
S-ATA, iDVR slot.

Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Showing 10 changed files with 959 additions and 4 deletions Side-by-side Diff

... ... @@ -700,6 +700,7 @@
700 700 ms7750se \
701 701 ms7722se \
702 702 Migo-R \
  703 + r7780mp \
703 704 "
704 705  
705 706 LIST_sh3=" \
... ... @@ -2857,6 +2857,11 @@
2857 2857 @echo "#define CONFIG_MIGO_R 1" >> include/config.h
2858 2858 @./mkconfig -a $(@:_config=) sh sh4 MigoR
2859 2859  
  2860 +r7780mp_config: unconfig
  2861 + @ >include/config.h
  2862 + @echo "#define CONFIG_R7780MP 1" >> include/config.h
  2863 + @./mkconfig -a $(@:_config=) sh sh4 r7780mp
  2864 +
2860 2865 #########################################################################
2861 2866 #########################################################################
2862 2867 #########################################################################
board/r7780mp/Makefile
Diff comments   View file @ c133c1f
  1 +#
  2 +# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
  3 +#
  4 +# board/r7780mp/Makefile
  5 +#
  6 +# This program is free software; you can redistribute it and/or
  7 +# modify it under the terms of the GNU General Public License as
  8 +# published by the Free Software Foundation; either version 2 of
  9 +# the License, or (at your option) any later version.
  10 +#
  11 +# This program is distributed in the hope that it will be useful,
  12 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 +# GNU General Public License for more details.
  15 +#
  16 +# You should have received a copy of the GNU General Public License
  17 +# along with this program; if not, write to the Free Software
  18 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 +# MA 02111-1307 USA
  20 +
  21 +include $(TOPDIR)/config.mk
  22 +
  23 +LIB = lib$(BOARD).a
  24 +
  25 +OBJS := r7780mp.o
  26 +SOBJS := lowlevel_init.o
  27 +
  28 +$(LIB): $(OBJS) $(SOBJS)
  29 + $(AR) crv $@ $(OBJS) $(SOBJS)
  30 +
  31 +clean:
  32 + rm -f $(SOBJS) $(OBJS)
  33 +
  34 +distclean: clean
  35 + rm -f $(LIB) core *.bak .depend
  36 +
  37 +#########################################################################
  38 +
  39 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  40 + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  41 +
  42 +-include .depend
  43 +
  44 +#########################################################################
board/r7780mp/config.mk
Diff comments   View file @ c133c1f
  1 +#
  2 +# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
  3 +#
  4 +# board/r77870mp/config.mk
  5 +#
  6 +# This program is free software; you can redistribute it and/or
  7 +# modify it under the terms of the GNU General Public License as
  8 +# published by the Free Software Foundation; either version 2 of
  9 +# the License, or (at your option) any later version.
  10 +#
  11 +# This program is distributed in the hope that it will be useful,
  12 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 +# GNU General Public License for more details.
  15 +#
  16 +# You should have received a copy of the GNU General Public License
  17 +# along with this program; if not, write to the Free Software
  18 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 +# MA 02111-1307 USA
  20 +
  21 +#
  22 +# TEXT_BASE refers to image _after_ relocation.
  23 +#
  24 +# NOTE: Must match value used in u-boot.lds (in this directory).
  25 +#
  26 +
  27 +TEXT_BASE = 0x0FFC0000
board/r7780mp/lowlevel_init.S
Diff comments   View file @ c133c1f
  1 +/*
  2 + * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
  3 + *
  4 + * u-boot/board/r7780mp/lowlevel_init.S
  5 + *
  6 + * This program is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU General Public License as
  8 + * published by the Free Software Foundation; either version 2 of
  9 + * the License, or (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License
  17 + * along with this program; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 + * MA 02111-1307 USA
  20 + */
  21 +
  22 +#include <config.h>
  23 +#include <version.h>
  24 +#include <asm/processor.h>
  25 +
  26 +/*
  27 + * Board specific low level init code, called _very_ early in the
  28 + * startup sequence. Relocation to SDRAM has not happened yet, no
  29 + * stack is available, bss section has not been initialised, etc.
  30 + *
  31 + * (Note: As no stack is available, no subroutines can be called...).
  32 + */
  33 +
  34 + .global lowlevel_init
  35 +
  36 + .text
  37 + .align 2
  38 +
  39 +lowlevel_init:
  40 +
  41 + mov.l CCR_A, r1 /* Address of Cache Control Register */
  42 + mov.l CCR_D, r0 /* Instruction Cache Invalidate */
  43 + mov.l r0, @r1
  44 +
  45 + mov.l FRQCR_A, r1 /* Frequency control register */
  46 + mov.l FRQCR_D, r0
  47 + mov.l r0, @r1
  48 +
  49 + /* pin_multi_setting */
  50 + mov.l BBG_PMMR_A,r1
  51 + mov.l BBG_PMMR_D_PMSR1,r0
  52 + mov.l r0,@r1
  53 +
  54 + mov.l BBG_PMSR1_A,r1
  55 + mov.l BBG_PMSR1_D,r0
  56 + mov.l r0,@r1
  57 +
  58 + mov.l BBG_PMMR_A,r1
  59 + mov.l BBG_PMMR_D_PMSR2,r0
  60 + mov.l r0,@r1
  61 +
  62 + mov.l BBG_PMSR2_A,r1
  63 + mov.l BBG_PMSR2_D,r0
  64 + mov.l r0,@r1
  65 +
  66 + mov.l BBG_PMMR_A,r1
  67 + mov.l BBG_PMMR_D_PMSR3,r0
  68 + mov.l r0,@r1
  69 +
  70 + mov.l BBG_PMSR3_A,r1
  71 + mov.l BBG_PMSR3_D,r0
  72 + mov.l r0,@r1
  73 +
  74 + mov.l BBG_PMMR_A,r1
  75 + mov.l BBG_PMMR_D_PMSR4,r0
  76 + mov.l r0,@r1
  77 +
  78 + mov.l BBG_PMSR4_A,r1
  79 + mov.l BBG_PMSR4_D,r0
  80 + mov.l r0,@r1
  81 +
  82 + mov.l BBG_PMMR_A,r1
  83 + mov.l BBG_PMMR_D_PMSRG,r0
  84 + mov.l r0,@r1
  85 +
  86 + mov.l BBG_PMSRG_A,r1
  87 + mov.l BBG_PMSRG_D,r0
  88 + mov.l r0,@r1
  89 +
  90 + /* cpg_setting */
  91 + mov.l FRQCR_A,r1
  92 + mov.l FRQCR_D,r0
  93 + mov.l r0,@r1
  94 +
  95 + mov.l DLLCSR_A,r1
  96 + mov.l DLLCSR_D,r0
  97 + mov.l r0,@r1
  98 +
  99 + nop
  100 + nop
  101 + nop
  102 + nop
  103 + nop
  104 + nop
  105 + nop
  106 + nop
  107 + nop
  108 + nop
  109 +
  110 + /* wait 200us */
  111 + mov.l REPEAT0_R3,r3
  112 + mov #0,r2
  113 +repeat0:
  114 + add #1,r2
  115 + cmp/hs r3,r2
  116 + bf repeat0
  117 + nop
  118 +
  119 + /* bsc_setting */
  120 + mov.l MMSELR_A,r1
  121 + mov.l MMSELR_D,r0
  122 + mov.l r0,@r1
  123 +
  124 + mov.l BCR_A,r1
  125 + mov.l BCR_D,r0
  126 + mov.l r0,@r1
  127 +
  128 + mov.l CS0BCR_A,r1
  129 + mov.l CS0BCR_D,r0
  130 + mov.l r0,@r1
  131 +
  132 + mov.l CS1BCR_A,r1
  133 + mov.l CS1BCR_D,r0
  134 + mov.l r0,@r1
  135 +
  136 + mov.l CS2BCR_A,r1
  137 + mov.l CS2BCR_D,r0
  138 + mov.l r0,@r1
  139 +
  140 + mov.l CS4BCR_A,r1
  141 + mov.l CS4BCR_D,r0
  142 + mov.l r0,@r1
  143 +
  144 + mov.l CS5BCR_A,r1
  145 + mov.l CS5BCR_D,r0
  146 + mov.l r0,@r1
  147 +
  148 + mov.l CS6BCR_A,r1
  149 + mov.l CS6BCR_D,r0
  150 + mov.l r0,@r1
  151 +
  152 + mov.l CS0WCR_A,r1
  153 + mov.l CS0WCR_D,r0
  154 + mov.l r0,@r1
  155 +
  156 + mov.l CS1WCR_A,r1
  157 + mov.l CS1WCR_D,r0
  158 + mov.l r0,@r1
  159 +
  160 + mov.l CS2WCR_A,r1
  161 + mov.l CS2WCR_D,r0
  162 + mov.l r0,@r1
  163 +
  164 + mov.l CS4WCR_A,r1
  165 + mov.l CS4WCR_D,r0
  166 + mov.l r0,@r1
  167 +
  168 + mov.l CS5WCR_A,r1
  169 + mov.l CS5WCR_D,r0
  170 + mov.l r0,@r1
  171 +
  172 + mov.l CS6WCR_A,r1
  173 + mov.l CS6WCR_D,r0
  174 + mov.l r0,@r1
  175 +
  176 + mov.l CS5PCR_A,r1
  177 + mov.l CS5PCR_D,r0
  178 + mov.l r0,@r1
  179 +
  180 + mov.l CS6PCR_A,r1
  181 + mov.l CS6PCR_D,r0
  182 + mov.l r0,@r1
  183 +
  184 + /* ddr_setting */
  185 + /* wait 200us */
  186 + mov.l REPEAT0_R3,r3
  187 + mov #0,r2
  188 +repeat1:
  189 + add #1,r2
  190 + cmp/hs r3,r2
  191 + bf repeat1
  192 + nop
  193 +
  194 + mov.l MIM_U_A,r0
  195 + mov.l MIM_U_D,r1
  196 + synco
  197 + mov.l r1,@r0
  198 + synco
  199 +
  200 + mov.l MIM_L_A,r0
  201 + mov.l MIM_L_D0,r1
  202 + synco
  203 + mov.l r1,@r0
  204 + synco
  205 +
  206 + mov.l STR_L_A,r0
  207 + mov.l STR_L_D,r1
  208 + synco
  209 + mov.l r1,@r0
  210 + synco
  211 +
  212 + mov.l SDR_L_A,r0
  213 + mov.l SDR_L_D,r1
  214 + synco
  215 + mov.l r1,@r0
  216 + synco
  217 +
  218 + nop
  219 + nop
  220 + nop
  221 + nop
  222 +
  223 + mov.l SCR_L_A,r0
  224 + mov.l SCR_L_D0,r1
  225 + synco
  226 + mov.l r1,@r0
  227 + synco
  228 +
  229 + mov.l SCR_L_A,r0
  230 + mov.l SCR_L_D1,r1
  231 + synco
  232 + mov.l r1,@r0
  233 + synco
  234 +
  235 + nop
  236 + nop
  237 + nop
  238 +
  239 + mov.l EMRS_A,r0
  240 + mov.l EMRS_D,r1
  241 + synco
  242 + mov.l r1,@r0
  243 + synco
  244 +
  245 + nop
  246 + nop
  247 + nop
  248 +
  249 + mov.l MRS1_A,r0
  250 + mov.l MRS1_D,r1
  251 + synco
  252 + mov.l r1,@r0
  253 + synco
  254 +
  255 + nop
  256 + nop
  257 + nop
  258 +
  259 + mov.l SCR_L_A,r0
  260 + mov.l SCR_L_D2,r1
  261 + synco
  262 + mov.l r1,@r0
  263 + synco
  264 +
  265 + nop
  266 + nop
  267 + nop
  268 +
  269 + mov.l SCR_L_A,r0
  270 + mov.l SCR_L_D3,r1
  271 + synco
  272 + mov.l r1,@r0
  273 + synco
  274 +
  275 + nop
  276 + nop
  277 + nop
  278 +
  279 + mov.l SCR_L_A,r0
  280 + mov.l SCR_L_D4,r1
  281 + synco
  282 + mov.l r1,@r0
  283 + synco
  284 +
  285 + nop
  286 + nop
  287 + nop
  288 +
  289 + mov.l MRS2_A,r0
  290 + mov.l MRS2_D,r1
  291 + synco
  292 + mov.l r1,@r0
  293 + synco
  294 +
  295 + nop
  296 + nop
  297 + nop
  298 +
  299 + mov.l SCR_L_A,r0
  300 + mov.l SCR_L_D5,r1
  301 + synco
  302 + mov.l r1,@r0
  303 + synco
  304 +
  305 + /* wait 200us */
  306 + mov.l REPEAT0_R1,r3
  307 + mov #0,r2
  308 +repeat2:
  309 + add #1,r2
  310 + cmp/hs r3,r2
  311 + bf repeat2
  312 +
  313 + synco
  314 +
  315 + mov.l MIM_L_A,r0
  316 + mov.l MIM_L_D1,r1
  317 + synco
  318 + mov.l r1,@r0
  319 + synco
  320 +
  321 + rts
  322 + nop
  323 + .align 4
  324 +
  325 +RWTCSR_D_1: .word 0xA507
  326 +RWTCSR_D_2: .word 0xA507
  327 +RWTCNT_D: .word 0x5A00
  328 +
  329 +BBG_PMMR_A: .long 0xFF800010
  330 +BBG_PMSR1_A: .long 0xFF800014
  331 +BBG_PMSR2_A: .long 0xFF800018
  332 +BBG_PMSR3_A: .long 0xFF80001C
  333 +BBG_PMSR4_A: .long 0xFF800020
  334 +BBG_PMSRG_A: .long 0xFF800024
  335 +
  336 +BBG_PMMR_D_PMSR1: .long 0xffffbffd
  337 +BBG_PMSR1_D: .long 0x00004002
  338 +BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
  339 +BBG_PMSR2_D: .long 0x03de5800
  340 +BBG_PMMR_D_PMSR3: .long 0xfffffff8
  341 +BBG_PMSR3_D: .long 0x00000007
  342 +BBG_PMMR_D_PMSR4: .long 0xdffdfff9
  343 +BBG_PMSR4_D: .long 0x20020006
  344 +BBG_PMMR_D_PMSRG: .long 0xffffffff
  345 +BBG_PMSRG_D: .long 0x00000000
  346 +
  347 +FRQCR_A: .long FRQCR
  348 +DLLCSR_A: .long 0xffc40010
  349 +FRQCR_D: .long 0x40233035
  350 +DLLCSR_D: .long 0x00000000
  351 +
  352 +/* for DDR-SDRAM */
  353 +MIM_U_A: .long MIM_1
  354 +MIM_L_A: .long MIM_2
  355 +SCR_U_A: .long SCR_1
  356 +SCR_L_A: .long SCR_2
  357 +STR_U_A: .long STR_1
  358 +STR_L_A: .long STR_2
  359 +SDR_U_A: .long SDR_1
  360 +SDR_L_A: .long SDR_2
  361 +
  362 +EMRS_A: .long 0xFEC02000
  363 +MRS1_A: .long 0xFEC00B08
  364 +MRS2_A: .long 0xFEC00308
  365 +
  366 +MIM_U_D: .long 0x00004000
  367 +MIM_L_D0: .long 0x03e80009
  368 +MIM_L_D1: .long 0x03e80209
  369 +SCR_L_D0: .long 0x3
  370 +SCR_L_D1: .long 0x2
  371 +SCR_L_D2: .long 0x2
  372 +SCR_L_D3: .long 0x4
  373 +SCR_L_D4: .long 0x4
  374 +SCR_L_D5: .long 0x0
  375 +STR_L_D: .long 0x000f0000
  376 +SDR_L_D: .long 0x00000400
  377 +EMRS_D: .long 0x0
  378 +MRS1_D: .long 0x0
  379 +MRS2_D: .long 0x0
  380 +
  381 +/* Cache Controller */
  382 +CCR_A: .long CCR
  383 +MMUCR_A: .long MMUCR
  384 +RWTCNT_A: .long WTCNT
  385 +
  386 +CCR_D: .long 0x0000090b
  387 +CCR_D_2: .long 0x00000103
  388 +MMUCR_D: .long 0x00000004
  389 +MSTPCR0_D: .long 0x00001001
  390 +MSTPCR2_D: .long 0xffffffff
  391 +
  392 +/* local Bus State Controller */
  393 +MMSELR_A: .long MMSELR
  394 +BCR_A: .long BCR
  395 +CS0BCR_A: .long CS0BCR
  396 +CS1BCR_A: .long CS1BCR
  397 +CS2BCR_A: .long CS2BCR
  398 +CS4BCR_A: .long CS4BCR
  399 +CS5BCR_A: .long CS5BCR
  400 +CS6BCR_A: .long CS6BCR
  401 +CS0WCR_A: .long CS0WCR
  402 +CS1WCR_A: .long CS1WCR
  403 +CS2WCR_A: .long CS2WCR
  404 +CS4WCR_A: .long CS4WCR
  405 +CS5WCR_A: .long CS5WCR
  406 +CS6WCR_A: .long CS6WCR
  407 +CS5PCR_A: .long CS5PCR
  408 +CS6PCR_A: .long CS6PCR
  409 +
  410 +MMSELR_D: .long 0xA5A50003
  411 +BCR_D: .long 0x00000000
  412 +CS0BCR_D: .long 0x77777770
  413 +CS1BCR_D: .long 0x77777670
  414 +CS2BCR_D: .long 0x77777770
  415 +CS4BCR_D: .long 0x77777770
  416 +CS5BCR_D: .long 0x77777670
  417 +CS6BCR_D: .long 0x77777770
  418 +CS0WCR_D: .long 0x00020006
  419 +CS1WCR_D: .long 0x00232304
  420 +CS2WCR_D: .long 0x7777770F
  421 +CS4WCR_D: .long 0x7777770F
  422 +CS5WCR_D: .long 0x00101006
  423 +CS6WCR_D: .long 0x77777703
  424 +CS5PCR_D: .long 0x77000000
  425 +CS6PCR_D: .long 0x77000000
  426 +
  427 +REPEAT0_R3: .long 0x00002000
  428 +REPEAT0_R1: .long 0x0000200
board/r7780mp/r7780mp.c
Diff comments   View file @ c133c1f
  1 +/*
  2 + * Copyright (C) 2007 Nobuhiro Iwamatsu
  3 + * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
  4 + *
  5 + * This program is free software; you can redistribute it and/or
  6 + * modify it under the terms of the GNU General Public License as
  7 + * published by the Free Software Foundation; either version 2 of
  8 + * the License, or (at your option) any later version.
  9 + *
  10 + * This program is distributed in the hope that it will be useful,
  11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 + * GNU General Public License for more details.
  14 + *
  15 + * You should have received a copy of the GNU General Public License
  16 + * along with this program; if not, write to the Free Software
  17 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 + * MA 02111-1307 USA
  19 + */
  20 +
  21 +#include <common.h>
  22 +#include <ide.h>
  23 +#include <asm/processor.h>
  24 +#include <asm/io.h>
  25 +#include <asm/pci.h>
  26 +#include "r7780mp.h"
  27 +
  28 +int checkboard(void)
  29 +{
  30 +#if defined(CONFIG_R7780MP)
  31 + puts("BOARD: Renesas Solutions R7780MP\n");
  32 +#else
  33 + puts("BOARD: Renesas Solutions R7780RP\n");
  34 +#endif
  35 + return 0;
  36 +}
  37 +
  38 +int board_init(void)
  39 +{
  40 + /* SCIF Enable */
  41 + *(vu_short*)PHCR = 0x0000;
  42 +
  43 + /* Disable Control-C */
  44 + disable_ctrlc(1);
  45 +
  46 + return 0;
  47 +}
  48 +
  49 +int dram_init (void)
  50 +{
  51 + DECLARE_GLOBAL_DATA_PTR;
  52 +
  53 + gd->bd->bi_memstart = CFG_SDRAM_BASE;
  54 + gd->bd->bi_memsize = CFG_SDRAM_SIZE;
  55 + printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
  56 + return 0;
  57 +}
  58 +
  59 +void led_set_state (unsigned short value)
  60 +{
  61 +
  62 +}
  63 +
  64 +void ide_set_reset (int idereset)
  65 +{
  66 + /* if reset = 1 IDE reset will be asserted */
  67 + if (idereset){
  68 + (*(vu_short *)FPGA_CFCTL) = 0x432;
  69 +#if defined(CONFIG_R7780MP)
  70 + (*(vu_short *)FPGA_CFPOW) |= 0x01;
  71 +#else
  72 + (*(vu_short *)FPGA_CFPOW) |= 0x02;
  73 +#endif
  74 + (*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
  75 + }
  76 +}
  77 +
  78 +#if defined(CONFIG_PCI)
  79 +static struct pci_controller hose;
  80 +void pci_init_board(void)
  81 +{
  82 + pci_sh7780_init( &hose );
  83 +}
  84 +#endif
board/r7780mp/r7780mp.h
Diff comments   View file @ c133c1f
  1 +/*
  2 + * Copyright (C) 2007 Nobuhiro Iwamatsu
  3 + * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
  4 + *
  5 + * u-boot/board/r7780mp/r7780mp.h
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +#ifndef _BOARD_R7780MP_R7780MP_H_
  24 +#define _BOARD_R7780MP_R7780MP_H_
  25 +
  26 +/* R7780MP's FPGA register map */
  27 +#define FPGA_BASE 0xa4000000
  28 +#define FPGA_IRLMSK (FPGA_BASE + 0x00)
  29 +#define FPGA_IRLMON (FPGA_BASE + 0x02)
  30 +#define FPGA_IRLPRI1 (FPGA_BASE + 0x04)
  31 +#define FPGA_IRLPRI2 (FPGA_BASE + 0x06)
  32 +#define FPGA_IRLPRI3 (FPGA_BASE + 0x08)
  33 +#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A)
  34 +#define FPGA_RSTCTL (FPGA_BASE + 0x0C)
  35 +#define FPGA_PCIBD (FPGA_BASE + 0x0E)
  36 +#define FPGA_PCICD (FPGA_BASE + 0x10)
  37 +#define FPGA_EXTGIO (FPGA_BASE + 0x16)
  38 +#define FPGA_IVDRMON (FPGA_BASE + 0x18)
  39 +#define FPGA_IVDRCR (FPGA_BASE + 0x1A)
  40 +#define FPGA_OBLED (FPGA_BASE + 0x1C)
  41 +#define FPGA_OBSW (FPGA_BASE + 0x1E)
  42 +#define FPGA_TPCTL (FPGA_BASE + 0x100)
  43 +#define FPGA_TPDCKCTL (FPGA_BASE + 0x102)
  44 +#define FPGA_TPCLR (FPGA_BASE + 0x104)
  45 +#define FPGA_TPXPOS (FPGA_BASE + 0x106)
  46 +#define FPGA_TPYPOS (FPGA_BASE + 0x108)
  47 +#define FPGA_DBSW (FPGA_BASE + 0x200)
  48 +#define FPGA_VERSION (FPGA_BASE + 0x700)
  49 +#define FPGA_CFCTL (FPGA_BASE + 0x300)
  50 +#define FPGA_CFPOW (FPGA_BASE + 0x302)
  51 +#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304)
  52 +#define FPGA_PMR (FPGA_BASE + 0x900)
  53 +
  54 +#endif /* _BOARD_R7780RP_R7780RP_H_ */
board/r7780mp/u-boot.lds
Diff comments   View file @ c133c1f
  1 +/*
  2 + * Copyrigth (c) 2007,2008
  3 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
  25 +OUTPUT_ARCH(sh)
  26 +ENTRY(_start)
  27 +
  28 +SECTIONS
  29 +{
  30 + /*
  31 + Base address of internal SDRAM is 0x0C000000.
  32 + Although size of SDRAM can be either 16 or 32 MBytes,
  33 + we assume 16 MBytes (ie ignore upper half if the full
  34 + 32 MBytes is present).
  35 +
  36 + NOTE: This address must match with the definition of
  37 + TEXT_BASE in config.mk (in this directory).
  38 +
  39 + */
  40 + . = 0x08000000 + (128*1024*1024) - (256*1024);
  41 +
  42 + PROVIDE (reloc_dst = .);
  43 +
  44 + PROVIDE (_ftext = .);
  45 + PROVIDE (_fcode = .);
  46 + PROVIDE (_start = .);
  47 +
  48 + .text :
  49 + {
  50 + cpu/sh4/start.o (.text)
  51 + . = ALIGN(8192);
  52 + common/environment.o (.ppcenv)
  53 + . = ALIGN(8192);
  54 + common/environment.o (.ppcenvr)
  55 + . = ALIGN(8192);
  56 + *(.text)
  57 + . = ALIGN(4);
  58 + } =0xFF
  59 + PROVIDE (_ecode = .);
  60 + .rodata :
  61 + {
  62 + *(.rodata)
  63 + . = ALIGN(4);
  64 + }
  65 + PROVIDE (_etext = .);
  66 +
  67 +
  68 + PROVIDE (_fdata = .);
  69 + .data :
  70 + {
  71 + *(.data)
  72 + . = ALIGN(4);
  73 + }
  74 + PROVIDE (_edata = .);
  75 +
  76 + PROVIDE (_fgot = .);
  77 + .got :
  78 + {
  79 + *(.got)
  80 + . = ALIGN(4);
  81 + }
  82 + PROVIDE (_egot = .);
  83 +
  84 + PROVIDE (__u_boot_cmd_start = .);
  85 + .u_boot_cmd :
  86 + {
  87 + *(.u_boot_cmd)
  88 + . = ALIGN(4);
  89 + }
  90 + PROVIDE (__u_boot_cmd_end = .);
  91 +
  92 + PROVIDE (reloc_dst_end = .);
  93 + /* _reloc_dst_end = .; */
  94 +
  95 + PROVIDE (bss_start = .);
  96 + PROVIDE (__bss_start = .);
  97 + .bss :
  98 + {
  99 + *(.bss)
  100 + . = ALIGN(4);
  101 + }
  102 + PROVIDE (bss_end = .);
  103 +
  104 + PROVIDE (_end = .);
  105 +}
1 1  
2 2 U-Boot for Renesas SuperH
3   - Last update 08/10/2007 by Nobuhiro Iwamatsu
  3 + Last update 01/18/2008 by Nobuhiro Iwamatsu
4 4  
5 5 ================================================================================
6 6 0. What's this?
7 7  
8 8  
9 9  
10 10  
11 11  
... ... @@ -18,19 +18,63 @@
18 18 2. Supported CPUs
19 19  
20 20 2.1. Renesas SH7750/SH7750R
  21 + This CPU has the SH4 core.
  22 +
21 23 2.2. Renesas SH7722
  24 + This CPU has the SH4AL-DSP core.
22 25  
  26 + 2.3. Renesas SH7720
  27 + This CPU has the SH3 core.
  28 +
  29 + 2.4. Renesas SH7710/SH7712
  30 + This CPU has the SH3-DSP core and Ethernet controller.
  31 +
  32 + 2.5. Renesas SH7780
  33 + This CPU has the SH4A core.
  34 +
23 35 ================================================================================
24 36 3. Supported Boards
25 37  
26 38 3.1. Hitachi UL MS7750SE01/MS7750RSE01
27 39 Board specific code is in board/ms7750se
28 40 To use this board, type "make ms7750se_config".
  41 + Support devices are :
  42 + - SCIF
  43 + - SDRAM
  44 + - NOR Flash
  45 + - Marubun PCMCIA
29 46  
30 47 3.2. Hitachi UL MS7722SE01
31 48 Board specific code is in board/ms7722se
32 49 To use this board, type "make ms7722se_config".
  50 + Support devices are :
  51 + - SCIF
  52 + - SDRAM
  53 + - NOR Flash
  54 + - Marubun PCMCIA
  55 + - SMC91x ethernet
33 56  
  57 + 3.2. Hitachi UL MS7720ERP01
  58 + Board specific code is in board/ms7720se
  59 + To use this board, type "make ms7720se_config".
  60 + Support devices are :
  61 + - SCIF
  62 + - SDRAM
  63 + - NOR Flash
  64 + - Marubun PCMCIA
  65 +
  66 + 3.3. Renesas R7780MP
  67 + Board specific code is in board/r7780mp
  68 + To use this board, type "make r7780mp_config".
  69 + Support devices are :
  70 + - SCIF
  71 + - DDR-SDRAM
  72 + - NOR Flash
  73 + - Compact Flash
  74 + - ASIX ethernet
  75 + - SH7780 PCI bridge
  76 + - RTL8110 ethernet
  77 +
34 78 ** README **
35 79 In SuperH, S-record and binary of made u-boot work on the memory.
36 80 When u-boot is written in the flash, it is necessary to change the
37 81  
... ... @@ -49,14 +93,13 @@
49 93 5. Future
50 94 I plan to support the following CPUs and boards.
51 95 5.1. CPUs
52   - - SH7710/SH7712 (SH3)
53   - - SH7780(SH4)
  96 + - SH7751R(SH4)
54 97 - SH7785(SH4)
55 98  
56 99 5.2. Boards
57 100 - Many boards ;-)
58 101  
59 102 ================================================================================
60   -Copyright (c) 2007
  103 +Copyright (c) 2007,2008
61 104 Nobuhiro Iwamatsu <iwamatsu@nigaur.org>
include/configs/r7780mp.h
Diff comments   View file @ c133c1f
  1 +/*
  2 + * Configuation settings for the Renesas R7780MP board
  3 + *
  4 + * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  5 + * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
  6 + *
  7 + * See file CREDITS for list of people who contributed to this
  8 + * project.
  9 + *
  10 + * This program is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License as
  12 + * published by the Free Software Foundation; either version 2 of
  13 + * the License, or (at your option) any later version.
  14 + *
  15 + * This program is distributed in the hope that it will be useful,
  16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 + * GNU General Public License for more details.
  19 + *
  20 + * You should have received a copy of the GNU General Public License
  21 + * along with this program; if not, write to the Free Software
  22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 + * MA 02111-1307 USA
  24 + */
  25 +
  26 +#ifndef __R7780RP_H
  27 +#define __R7780RP_H
  28 +
  29 +#undef DEBUG
  30 +#define CONFIG_SH 1
  31 +#define CONFIG_SH4A 1
  32 +#define CONFIG_CPU_SH7780 1
  33 +#define CONFIG_R7780MP 1
  34 +#define __LITTLE_ENDIAN 1
  35 +
  36 +/*
  37 + * Command line configuration.
  38 + */
  39 +#define CONFIG_CMD_SDRAM
  40 +#define CONFIG_CMD_FLASH
  41 +#define CONFIG_CMD_MEMORY
  42 +#define CONFIG_CMD_PCI
  43 +#define CONFIG_CMD_NET
  44 +#define CONFIG_CMD_PING
  45 +#define CONFIG_CMD_ENV
  46 +#define CONFIG_CMD_NFS
  47 +#define CONFIG_CMD_IDE
  48 +#define CONFIG_CMD_EXT2
  49 +#define CONFIG_DOS_PARTITION
  50 +
  51 +#define CFG_SCIF_CONSOLE 1
  52 +#define CONFIG_BAUDRATE 115200
  53 +#define CONFIG_CONS_SCIF0 1
  54 +
  55 +#define CONFIG_BOOTDELAY 3
  56 +#define CONFIG_BOOTARGS "console=ttySC0,115200"
  57 +#define CONFIG_ENV_OVERWRITE 1
  58 +
  59 +/* check for keypress on bootdelay==0 */
  60 +/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
  61 +
  62 +/* Network setting */
  63 +#define CONFIG_NETMASK 255.0.0.0
  64 +#define CONFIG_IPADDR 10.0.192.82
  65 +#define CONFIG_SERVERIP 10.0.0.1
  66 +#define CONFIG_GATEWAYIP 10.0.0.1
  67 +
  68 +#define CFG_SDRAM_BASE (0x08000000)
  69 +#define CFG_SDRAM_SIZE (128 * 1024 * 1024)
  70 +
  71 +#define CFG_LONGHELP
  72 +#define CFG_PROMPT "=> "
  73 +#define CFG_CBSIZE 256
  74 +#define CFG_PBSIZE 256
  75 +#define CFG_MAXARGS 16
  76 +#define CFG_BARGSIZE 512
  77 +/* List of legal baudrate settings for this board */
  78 +#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
  79 +
  80 +#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
  81 +#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
  82 +
  83 +/* NOR Flash (S29PL127J60TFI130) */
  84 +#define CFG_FLASH_BASE (0xA0000000)
  85 +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
  86 +#define CFG_MAX_FLASH_BANKS (2)
  87 +#define CFG_MAX_FLASH_SECT 270
  88 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
  89 + CFG_FLASH_BASE + 0x100000,\
  90 + CFG_FLASH_BASE + 0x400000,\
  91 + CFG_FLASH_BASE + 0x700000, }
  92 +
  93 +#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
  94 +/* Address of u-boot image in Flash */
  95 +#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
  96 +#define CFG_MONITOR_LEN (112 * 1024)
  97 +/* Size of DRAM reserved for malloc() use */
  98 +#define CFG_MALLOC_LEN (256 * 1024)
  99 +
  100 +/* size in bytes reserved for initial data */
  101 +#define CFG_GBL_DATA_SIZE (256)
  102 +#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
  103 +#define CFG_RX_ETH_BUFFER (8)
  104 +
  105 +#define CFG_FLASH_CFI
  106 +#define CFG_FLASH_CFI_DRIVER
  107 +#undef CFG_FLASH_CFI_BROKEN_TABLE
  108 +#undef CFG_FLASH_QUIET_TEST
  109 +/* print 'E' for empty sector on flinfo */
  110 +#define CFG_FLASH_EMPTY_INFO
  111 +
  112 +#define CFG_ENV_IS_IN_FLASH
  113 +#define CFG_ENV_SECT_SIZE (16 * 1024)
  114 +#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
  115 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
  116 +#define CFG_FLASH_ERASE_TOUT 120000
  117 +#define CFG_FLASH_WRITE_TOUT 500
  118 +
  119 +/* Board Clock */
  120 +#define CONFIG_SYS_CLK_FREQ 33333333
  121 +#define TMU_CLK_DIVIDER 4
  122 +#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
  123 +
  124 +/* PCI Controller */
  125 +#if defined(CONFIG_CMD_PCI)
  126 +#define CONFIG_PCI
  127 +#define CONFIG_SH4_PCI
  128 +#define CONFIG_PCI_PNP
  129 +#define CONFIG_PCI_SCAN_SHOW 1
  130 +#define __io
  131 +#define __mem_pci
  132 +
  133 +#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
  134 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
  135 +#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
  136 +
  137 +#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
  138 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
  139 +#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
  140 +#endif /* CONFIG_CMD_PCI */
  141 +
  142 +#if defined(CONFIG_CMD_NET)
  143 +/* #define CONFIG_NET_MULTI
  144 + #define CONFIG_RTL8169 */
  145 +/* AX88696L Support(NE2000 base chip) */
  146 +#define CONFIG_DRIVER_NE2000
  147 +#define CONFIG_DRIVER_AX88796L
  148 +#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
  149 +#endif
  150 +
  151 +/* Compact flash Support */
  152 +#if defined(CONFIG_CMD_IDE)
  153 +#define CONFIG_IDE_RESET 1
  154 +#define CFG_PIO_MODE 1
  155 +#define CFG_IDE_MAXBUS 1 /* IDE bus */
  156 +#define CFG_IDE_MAXDEVICE 1
  157 +#define CFG_ATA_BASE_ADDR 0xb4000000
  158 +#define CFG_ATA_STRIDE 2 /* 1bit shift */
  159 +#define CFG_ATA_DATA_OFFSET 0x1000 /* data reg offset */
  160 +#define CFG_ATA_REG_OFFSET 0x1000 /* reg offset */
  161 +#define CFG_ATA_ALT_OFFSET 0x800 /* alternate register offset */
  162 +#endif /* CONFIG_CMD_IDE */
  163 +
  164 +#endif /* __R7780RP_H */