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Commit c1393bb3def33b8ec154e4b6f06ed1ad81e052a1

Authored by Veli-Pekka Peltola
Committed by Albert ARIBAUD
1 parent b0261b1212
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Add support for Bluegiga APX4 Development Kit 

This adds support for Bluegiga APX4 Development Kit. It is built around
Freescale i.MX28. Currently supported features are: ethernet, I2C, MMC,
RTC and USB. APX4 has only one ethernet port.

Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Cc: Stefano Babic <sbabic@denx.de>

Showing 7 changed files with 618 additions and 0 deletions Side-by-side Diff

... ... @@ -796,6 +796,10 @@
796 796 integratorap various
797 797 integratorcp various
798 798  
  799 +Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
  800 +
  801 + apx4devkit i.MX28
  802 +
799 803 Luka Perkov <uboot@lukaperkov.net>
800 804  
801 805 ib62x0 ARM926EJS
board/bluegiga/apx4devkit/Makefile
Diff comments   View file @ c1393bb
  1 +#
  2 +# (C) Copyright 2000-2006
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = $(obj)lib$(BOARD).o
  27 +
  28 +ifndef CONFIG_SPL_BUILD
  29 +COBJS := apx4devkit.o
  30 +else
  31 +COBJS := spl_boot.o
  32 +endif
  33 +
  34 +SRCS := $(COBJS:.o=.c)
  35 +OBJS := $(addprefix $(obj),$(COBJS))
  36 +
  37 +$(LIB): $(obj).depend $(OBJS)
  38 + $(call cmd_link_o_target, $(OBJS))
  39 +
  40 +#########################################################################
  41 +
  42 +# defines $(obj).depend target
  43 +include $(SRCTREE)/rules.mk
  44 +
  45 +sinclude $(obj).depend
  46 +
  47 +#########################################################################
board/bluegiga/apx4devkit/apx4devkit.c
Diff comments   View file @ c1393bb
  1 +/*
  2 + * Bluegiga APX4 Development Kit
  3 + *
  4 + * Copyright (C) 2012 Bluegiga Technologies Oy
  5 + *
  6 + * Authors:
  7 + * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
  8 + * Lauri Hintsala <lauri.hintsala@bluegiga.com>
  9 + *
  10 + * Based on m28evk.c:
  11 + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  12 + * on behalf of DENX Software Engineering GmbH
  13 + *
  14 + * See file CREDITS for list of people who contributed to this
  15 + * project.
  16 + *
  17 + * This program is free software; you can redistribute it and/or
  18 + * modify it under the terms of the GNU General Public License as
  19 + * published by the Free Software Foundation; either version 2 of
  20 + * the License, or (at your option) any later version.
  21 + *
  22 + * This program is distributed in the hope that it will be useful,
  23 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25 + * GNU General Public License for more details.
  26 + */
  27 +
  28 +#include <common.h>
  29 +#include <asm/gpio.h>
  30 +#include <asm/io.h>
  31 +#include <asm/arch/imx-regs.h>
  32 +#include <asm/arch/iomux-mx28.h>
  33 +#include <asm/arch/clock.h>
  34 +#include <asm/arch/sys_proto.h>
  35 +#include <linux/mii.h>
  36 +#include <miiphy.h>
  37 +#include <netdev.h>
  38 +#include <errno.h>
  39 +
  40 +DECLARE_GLOBAL_DATA_PTR;
  41 +
  42 +/* Functions */
  43 +int board_early_init_f(void)
  44 +{
  45 + /* IO0 clock at 480MHz */
  46 + mx28_set_ioclk(MXC_IOCLK0, 480000);
  47 + /* IO1 clock at 480MHz */
  48 + mx28_set_ioclk(MXC_IOCLK1, 480000);
  49 +
  50 + /* SSP0 clock at 96MHz */
  51 + mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
  52 +
  53 + return 0;
  54 +}
  55 +
  56 +int dram_init(void)
  57 +{
  58 + return mx28_dram_init();
  59 +}
  60 +
  61 +int board_init(void)
  62 +{
  63 + /* Adress of boot parameters */
  64 + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  65 +
  66 + return 0;
  67 +}
  68 +
  69 +#ifdef CONFIG_CMD_MMC
  70 +int board_mmc_init(bd_t *bis)
  71 +{
  72 + return mxsmmc_initialize(bis, 0, NULL);
  73 +}
  74 +#endif
  75 +
  76 +
  77 +#ifdef CONFIG_CMD_NET
  78 +
  79 +#define MII_PHY_CTRL2 0x1f
  80 +int fecmxc_mii_postcall(int phy)
  81 +{
  82 + /* change PHY RMII clock to 50MHz */
  83 + miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180);
  84 +
  85 + return 0;
  86 +}
  87 +
  88 +int board_eth_init(bd_t *bis)
  89 +{
  90 + int ret;
  91 + struct eth_device *dev;
  92 +
  93 + ret = cpu_eth_init(bis);
  94 + if (ret) {
  95 + printf("FEC MXS: Unable to init FEC clocks\n");
  96 + return ret;
  97 + }
  98 +
  99 + ret = fecmxc_initialize(bis);
  100 + if (ret) {
  101 + printf("FEC MXS: Unable to init FEC\n");
  102 + return ret;
  103 + }
  104 +
  105 + dev = eth_get_dev_by_name("FEC");
  106 + if (!dev) {
  107 + printf("FEC MXS: Unable to get FEC device entry\n");
  108 + return -EINVAL;
  109 + }
  110 +
  111 + ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
  112 + if (ret) {
  113 + printf("FEC MXS: Unable to register FEC MII postcall\n");
  114 + return ret;
  115 + }
  116 +
  117 + return ret;
  118 +}
  119 +#endif
  120 +
  121 +#ifdef CONFIG_SERIAL_TAG
  122 +#define MXS_OCOTP_MAX_TIMEOUT 1000000
  123 +void get_board_serial(struct tag_serialnr *serialnr)
  124 +{
  125 + struct mx28_ocotp_regs *ocotp_regs =
  126 + (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
  127 +
  128 + serialnr->high = 0;
  129 + serialnr->low = 0;
  130 +
  131 + writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
  132 +
  133 + if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
  134 + MXS_OCOTP_MAX_TIMEOUT)) {
  135 + printf("MXS: Can't get serial number from OCOTP\n");
  136 + return;
  137 + }
  138 +
  139 + serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3);
  140 +}
  141 +#endif
  142 +
  143 +#ifdef CONFIG_REVISION_TAG
  144 +u32 get_board_rev(void)
  145 +{
  146 + if (getenv("revision#") != NULL)
  147 + return simple_strtoul(getenv("revision#"), NULL, 10);
  148 + return 0;
  149 +}
  150 +#endif
board/bluegiga/apx4devkit/spl_boot.c
Diff comments   View file @ c1393bb
  1 +/*
  2 + * Bluegiga APX4 Development Kit
  3 + *
  4 + * Copyright (C) 2012 Bluegiga Technologies Oy
  5 + *
  6 + * Authors:
  7 + * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
  8 + * Lauri Hintsala <lauri.hintsala@bluegiga.com>
  9 + *
  10 + * Based on spl_boot.c:
  11 + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  12 + * on behalf of DENX Software Engineering GmbH
  13 + *
  14 + * See file CREDITS for list of people who contributed to this
  15 + * project.
  16 + *
  17 + * This program is free software; you can redistribute it and/or
  18 + * modify it under the terms of the GNU General Public License as
  19 + * published by the Free Software Foundation; either version 2 of
  20 + * the License, or (at your option) any later version.
  21 + *
  22 + * This program is distributed in the hope that it will be useful,
  23 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25 + * GNU General Public License for more details.
  26 + */
  27 +
  28 +#include <common.h>
  29 +#include <config.h>
  30 +#include <asm/gpio.h>
  31 +#include <asm/io.h>
  32 +#include <asm/arch/iomux-mx28.h>
  33 +#include <asm/arch/imx-regs.h>
  34 +#include <asm/arch/sys_proto.h>
  35 +
  36 +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
  37 +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
  38 +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
  39 +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
  40 +
  41 +const iomux_cfg_t iomux_setup[] = {
  42 + /* DUART */
  43 + MX28_PAD_PWM0__DUART_RX,
  44 + MX28_PAD_PWM1__DUART_TX,
  45 +
  46 + /* LED */
  47 + MX28_PAD_PWM3__GPIO_3_28,
  48 +
  49 + /* MMC0 */
  50 + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
  51 + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
  52 + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
  53 + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
  54 + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
  55 + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
  56 + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL),
  57 + MX28_PAD_SSP0_SCK__SSP0_SCK |
  58 + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
  59 +
  60 + /* GPMI NAND */
  61 + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
  62 + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
  63 + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
  64 + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
  65 + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
  66 + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
  67 + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
  68 + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
  69 + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
  70 + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
  71 + MX28_PAD_GPMI_RDN__GPMI_RDN |
  72 + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
  73 + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
  74 + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
  75 + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
  76 + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
  77 +
  78 + /* FEC0 */
  79 + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
  80 + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
  81 + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
  82 + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
  83 + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
  84 + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
  85 + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
  86 + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
  87 + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
  88 +
  89 + /* I2C */
  90 + MX28_PAD_I2C0_SCL__I2C0_SCL,
  91 + MX28_PAD_I2C0_SDA__I2C0_SDA,
  92 +
  93 + /* EMI */
  94 + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
  95 + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
  96 + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
  97 + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
  98 + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
  99 + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
  100 + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
  101 + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
  102 + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
  103 + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
  104 + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
  105 + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
  106 + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
  107 + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
  108 + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
  109 + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
  110 + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
  111 + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
  112 + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
  113 + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
  114 + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
  115 + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
  116 + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
  117 + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
  118 + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
  119 +
  120 + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
  121 + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
  122 + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
  123 + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
  124 + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
  125 + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
  126 + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
  127 + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
  128 + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
  129 + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
  130 + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
  131 + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
  132 + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
  133 + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
  134 + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
  135 + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
  136 + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
  137 + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
  138 + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
  139 + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
  140 + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
  141 + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
  142 + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
  143 + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
  144 +};
  145 +
  146 +void board_init_ll(void)
  147 +{
  148 + mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
  149 +
  150 + /* switch LED on */
  151 + gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
  152 +}
  153 +
  154 +void mx28_adjust_memory_params(uint32_t *dram_vals)
  155 +{
  156 + /*
  157 + * All address lines are routed from CPU to memory chip.
  158 + * ADDR_PINS field is set to zero.
  159 + */
  160 + dram_vals[0x74 >> 2] = 0x0f02000a;
  161 +
  162 + /* Used memory has 4 banks. EIGHT_BANK_MODE bit is disabled. */
  163 + dram_vals[0x7c >> 2] = 0x00000101;
  164 +}
board/bluegiga/apx4devkit/u-boot.bd
Diff comments   View file @ c1393bb
  1 +sources {
  2 + u_boot_spl="spl/u-boot-spl.bin";
  3 + u_boot="u-boot.bin";
  4 +}
  5 +
  6 +section (0) {
  7 + load u_boot_spl > 0x0000;
  8 + load ivt (entry = 0x0014) > 0x8000;
  9 + hab call 0x8000;
  10 +
  11 + load u_boot > 0x40000100;
  12 + load ivt (entry = 0x40000100) > 0x8000;
  13 + hab call 0x8000;
  14 +}
... ... @@ -179,6 +179,7 @@
179 179 zmx25 arm arm926ejs zmx25 syteco mx25
180 180 imx27lite arm arm926ejs imx27lite logicpd mx27
181 181 magnesium arm arm926ejs imx27lite logicpd mx27
  182 +apx4devkit arm arm926ejs - bluegiga mx28
182 183 m28evk arm arm926ejs - denx mx28
183 184 mx28evk arm arm926ejs - freescale mx28
184 185 nhk8815 arm arm926ejs nhk8815 st nomadik
include/configs/apx4devkit.h
Diff comments   View file @ c1393bb
  1 +/*
  2 + * Copyright (C) 2012 Bluegiga Technologies Oy
  3 + *
  4 + * Authors:
  5 + * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
  6 + * Lauri Hintsala <lauri.hintsala@bluegiga.com>
  7 + *
  8 + * Based on m28evk.h:
  9 + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  10 + * on behalf of DENX Software Engineering GmbH
  11 + *
  12 + * This program is free software; you can redistribute it and/or
  13 + * modify it under the terms of the GNU General Public License as
  14 + * published by the Free Software Foundation; either version 2 of
  15 + * the License, or (at your option) any later version.
  16 + *
  17 + * This program is distributed in the hope that it will be useful,
  18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20 + * GNU General Public License for more details.
  21 + */
  22 +#ifndef __CONFIG_H
  23 +#define __CONFIG_H
  24 +
  25 +#include <asm/arch/regs-base.h>
  26 +
  27 +/* SoC configurations */
  28 +#define CONFIG_MX28 /* i.MX28 SoC */
  29 +#define CONFIG_MXS_GPIO /* GPIO control */
  30 +#define CONFIG_SYS_HZ 1000 /* Ticks per second */
  31 +
  32 +#define MACH_TYPE_APX4DEVKIT 3712
  33 +#define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT
  34 +
  35 +#define CONFIG_SYS_NO_FLASH
  36 +#define CONFIG_SYS_ICACHE_OFF
  37 +#define CONFIG_SYS_DCACHE_OFF
  38 +#define CONFIG_BOARD_EARLY_INIT_F
  39 +#define CONFIG_ARCH_CPU_INIT
  40 +#define CONFIG_ARCH_MISC_INIT
  41 +
  42 +/* SPL */
  43 +#define CONFIG_SPL
  44 +#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
  45 +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mx28"
  46 +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
  47 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  48 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
  49 +#define CONFIG_SPL_GPIO_SUPPORT
  50 +
  51 +/* U-Boot Commands */
  52 +#include <config_cmd_default.h>
  53 +#define CONFIG_DISPLAY_CPUINFO
  54 +#define CONFIG_DOS_PARTITION
  55 +
  56 +#define CONFIG_CMD_CACHE
  57 +#define CONFIG_CMD_DATE
  58 +#define CONFIG_CMD_DHCP
  59 +#define CONFIG_CMD_EXT2
  60 +#define CONFIG_CMD_FAT
  61 +#define CONFIG_CMD_I2C
  62 +#define CONFIG_CMD_MII
  63 +#define CONFIG_CMD_MMC
  64 +#define CONFIG_CMD_NAND
  65 +#define CONFIG_CMD_NET
  66 +#define CONFIG_CMD_NFS
  67 +#define CONFIG_CMD_PING
  68 +#define CONFIG_CMD_SAVEENV
  69 +#define CONFIG_CMD_USB
  70 +
  71 +/* Memory configurations */
  72 +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
  73 +#define PHYS_SDRAM_1 0x40000000 /* Base address */
  74 +#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
  75 +#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
  76 +#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
  77 +#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
  78 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  79 +
  80 +/* Point initial SP in SRAM so SPL can use it too. */
  81 +#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
  82 +#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
  83 +
  84 +#define CONFIG_SYS_INIT_SP_OFFSET \
  85 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  86 +#define CONFIG_SYS_INIT_SP_ADDR \
  87 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  88 +
  89 +/*
  90 + * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
  91 + * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
  92 + * binary. In case there was more of this mess, 0x100 bytes are skipped.
  93 + */
  94 +#define CONFIG_SYS_TEXT_BASE 0x40000100
  95 +
  96 +#define CONFIG_ENV_OVERWRITE
  97 +
  98 +/* U-Boot general configurations */
  99 +#define CONFIG_SYS_LONGHELP
  100 +#define CONFIG_SYS_PROMPT "=> "
  101 +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
  102 +#define CONFIG_SYS_PBSIZE \
  103 + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  104 + /* Print buffer size */
  105 +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
  106 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  107 + /* Boot argument buffer size */
  108 +#define CONFIG_VERSION_VARIABLE /* U-Boot version */
  109 +#define CONFIG_AUTO_COMPLETE /* Command auto complete */
  110 +#define CONFIG_CMDLINE_EDITING /* Command history etc. */
  111 +#define CONFIG_SYS_HUSH_PARSER
  112 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  113 +#define CONFIG_OF_LIBFDT
  114 +#define CONFIG_ENV_IS_IN_NAND
  115 +
  116 +/* Serial Driver */
  117 +#define CONFIG_PL011_SERIAL
  118 +#define CONFIG_PL011_CLOCK 24000000
  119 +#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
  120 +#define CONFIG_CONS_INDEX 0
  121 +#define CONFIG_BAUDRATE 115200 /* Default baud rate */
  122 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  123 +
  124 +/* DMA */
  125 +#define CONFIG_APBH_DMA
  126 +
  127 +/* MMC Driver */
  128 +#ifdef CONFIG_ENV_IS_IN_MMC
  129 +#define CONFIG_ENV_OFFSET (256 * 1024)
  130 +#define CONFIG_ENV_SIZE (16 * 1024)
  131 +#define CONFIG_SYS_MMC_ENV_DEV 0
  132 +#endif
  133 +
  134 +#ifdef CONFIG_CMD_MMC
  135 +#define CONFIG_MMC
  136 +#define CONFIG_GENERIC_MMC
  137 +#define CONFIG_MMC_BOUNCE_BUFFER
  138 +#define CONFIG_MXS_MMC
  139 +#endif
  140 +
  141 +/* NAND Driver */
  142 +#ifdef CONFIG_ENV_IS_IN_NAND
  143 +#define CONFIG_ENV_SECT_SIZE (128 * 1024)
  144 +#define CONFIG_ENV_SIZE (128 * 1024)
  145 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  146 +#define CONFIG_ENV_RANGE (384 * 1024)
  147 +#define CONFIG_ENV_OFFSET 0x120000
  148 +#define CONFIG_ENV_OFFSET_REDUND \
  149 + (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
  150 +#endif
  151 +
  152 +#ifdef CONFIG_CMD_NAND
  153 +#define CONFIG_NAND_MXS
  154 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  155 +#define CONFIG_SYS_NAND_BASE 0x60000000
  156 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  157 +
  158 +#define CONFIG_CMD_UBI
  159 +#define CONFIG_CMD_UBIFS
  160 +#define CONFIG_CMD_MTDPARTS
  161 +#define CONFIG_RBTREE
  162 +#define CONFIG_LZO
  163 +#define CONFIG_MTD_DEVICE
  164 +#define CONFIG_MTD_PARTITIONS
  165 +#define MTDIDS_DEFAULT "nand0=gpmi-nand"
  166 +#define MTDPARTS_DEFAULT \
  167 + "mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env),-(root)"
  168 +#else
  169 +#define MTDPARTS_DEFAULT ""
  170 +#endif
  171 +
  172 +/* Ethernet on SOC (FEC) */
  173 +#ifdef CONFIG_CMD_NET
  174 +#define CONFIG_NET_MULTI
  175 +#define CONFIG_ETHPRIME "FEC"
  176 +#define CONFIG_FEC_MXC
  177 +#define CONFIG_FEC_MXC_PHYADDR 0
  178 +#define IMX_FEC_BASE MXS_ENET0_BASE
  179 +#define CONFIG_MII
  180 +#define CONFIG_DISCOVER_PHY
  181 +#define CONFIG_FEC_XCV_TYPE RMII
  182 +#endif
  183 +
  184 +/* USB */
  185 +#ifdef CONFIG_CMD_USB
  186 +#define CONFIG_USB_EHCI
  187 +#define CONFIG_USB_EHCI_MXS
  188 +#define CONFIG_EHCI_MXS_PORT 1
  189 +#define CONFIG_EHCI_IS_TDI
  190 +#define CONFIG_USB_STORAGE
  191 +#endif
  192 +
  193 +/* I2C */
  194 +#ifdef CONFIG_CMD_I2C
  195 +#define CONFIG_I2C_MXS
  196 +#define CONFIG_HARD_I2C
  197 +#define CONFIG_SYS_I2C_SPEED 400000
  198 +#endif
  199 +
  200 +/* RTC */
  201 +#if defined(CONFIG_CMD_DATE)
  202 +#define CONFIG_RTC_PCF8563
  203 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51
  204 +#endif
  205 +
  206 +/* Boot Linux */
  207 +#define CONFIG_CMDLINE_TAG
  208 +#define CONFIG_SETUP_MEMORY_TAGS
  209 +#define CONFIG_BOOTDELAY 1
  210 +#define CONFIG_BOOTFILE "uImage"
  211 +#define CONFIG_BOOTCOMMAND "run bootcmd_nand"
  212 +#define CONFIG_LOADADDR 0x41000000
  213 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  214 +#define CONFIG_SERIAL_TAG
  215 +#define CONFIG_REVISION_TAG
  216 +
  217 +/* Extra Environments */
  218 +#define CONFIG_EXTRA_ENV_SETTINGS \
  219 + "mtdparts=" MTDPARTS_DEFAULT "\0" \
  220 + "verify=no\0" \
  221 + "bootcmd=run bootcmd_nand\0" \
  222 + "kernelargs=console=tty0 console=ttyAMA0,115200 consoleblank=0\0" \
  223 + "bootargs_nand=" \
  224 + "setenv bootargs ${kernelargs} ubi.mtd=3,2048 " \
  225 + "root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \
  226 + "bootcmd_nand=" \
  227 + "run bootargs_nand && ubi part root 2048 && " \
  228 + "ubifsmount rootfs && ubifsload 41000000 boot/uImage && " \
  229 + "bootm 41000000\0" \
  230 + "bootargs_mmc=" \
  231 + "setenv bootargs ${kernelargs} " \
  232 + "root=/dev/mmcblk0p2 rootwait ${mtdparts} rw\0" \
  233 + "bootcmd_mmc=" \
  234 + "run bootargs_mmc && mmc rescan && " \
  235 + "ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \
  236 +""
  237 +
  238 +#endif /* __CONFIG_H */