Eric Lee / smarc-uboot

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Commit c13dcb3dc7aeaf0a78daff0a3d28eaaa94ad1f28

Authored by Simon Glass
Committed by Bin Meng
1 parent 0adf8d3548
Exists in v2017.01-smarct4x and in 29 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

x86: dts: Update the pinctrl binding a little 

Make a few minor updates to make the meaning clearer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Showing 1 changed file with 11 additions and 10 deletions Side-by-side Diff

doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
Diff comments   View file @ c13dcb3
... ... @@ -8,17 +8,18 @@
8 8  
9 9 Pin nodes must be children of the pinctrl master node and can
10 10 contain the following properties:
11   -- pad-offset - (required) offset in the IOBASE for the pin to configured.
12   -- gpio-offset - (required) offset in the GPIOBASE for the pin to configured and
13   - also the bit shift in this register.
14   -- mode-gpio - (optional) standalone property to force the pin into GPIO mode.
15   -- mode-func - (optional) function number to assign to the pin. if 'mode-gpio'
16   - is set, this property will be ignored.
  11 +- pad-offset - (required) offset in the IOBASE for the pin to configure
  12 +- gpio-offset - (required) 2 cells
  13 + - offset in the GPIOBASE for the pin to configure
  14 + - the bit shift in this register (4 = bit 4)
  15 +- mode-gpio - (optional) standalone property to force the pin into GPIO mode
  16 +- mode-func - (optional) function number to assign to the pin. If
  17 + 'mode-gpio' is set, this property will be ignored.
17 18 in case of 'mode-gpio' property set:
18   -- output-value - (optional) this set the default output value of the GPIO.
19   -- direction - (optional) this set the direction of the gpio.
20   -- pull-str - (optional) this set the pull strength of the pin.
21   -- pull-assign - (optional) this set the pull assignement (up/down) of the pin.
  19 +- output-value - (optional) this set the default output value of the GPIO
  20 +- direction - (optional) this set the direction of the gpio
  21 +- pull-str - (optional) this set the pull strength of the pin
  22 +- pull-assign - (optional) this set the pull assignement (up/down) of the pin
22 23 - invert - (optional) this input pin is inverted
23 24  
24 25 Example: