Eric Lee / smarc-uboot

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Commit c15438eaea8b854d89455ebf7a1c7c4f06fa92f5

Authored by Tom Rini
2 parents d62a89bd5b 1dc793dd2b
Exists in master and in 53 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge branch 'master' of git://www.denx.de/git/u-boot-video

Showing 25 changed files Side-by-side Diff

arch/arm/include/asm/arch-am33xx/hardware.h
Diff comments   View file @ c15438e
... ... @@ -78,5 +78,6 @@
78 78 #define USB0_OTG_BASE 0x47401000
79 79 #define USB1_OTG_BASE 0x47401800
80 80  
  81 +int clk_get(int clk);
81 82 #endif /* __AM33XX_HARDWARE_H */
arch/arm/include/asm/arch-davinci/da8xx-fb.h
View file @ c15438e
1   -/*
2   - * Porting to u-boot:
3   - *
4   - * (C) Copyright 2011
5   - * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
6   - *
7   - * Copyright (C) 2008-2009 MontaVista Software Inc.
8   - * Copyright (C) 2008-2009 Texas Instruments Inc
9   - *
10   - * Based on the LCD driver for TI Avalanche processors written by
11   - * Ajay Singh and Shalom Hai.
12   - *
13   - * SPDX-License-Identifier: GPL-2.0+
14   - */
15   -
16   -#ifndef DA8XX_FB_H
17   -#define DA8XX_FB_H
18   -
19   -enum panel_type {
20   - QVGA = 0
21   -};
22   -
23   -enum panel_shade {
24   - MONOCHROME = 0,
25   - COLOR_ACTIVE,
26   - COLOR_PASSIVE,
27   -};
28   -
29   -enum raster_load_mode {
30   - LOAD_DATA = 1,
31   - LOAD_PALETTE,
32   -};
33   -
34   -struct display_panel {
35   - enum panel_type panel_type; /* QVGA */
36   - int max_bpp;
37   - int min_bpp;
38   - enum panel_shade panel_shade;
39   -};
40   -
41   -struct da8xx_panel {
42   - const char name[25]; /* Full name <vendor>_<model> */
43   - unsigned short width;
44   - unsigned short height;
45   - int hfp; /* Horizontal front porch */
46   - int hbp; /* Horizontal back porch */
47   - int hsw; /* Horizontal Sync Pulse Width */
48   - int vfp; /* Vertical front porch */
49   - int vbp; /* Vertical back porch */
50   - int vsw; /* Vertical Sync Pulse Width */
51   - unsigned int pxl_clk; /* Pixel clock */
52   - unsigned char invert_pxl_clk; /* Invert Pixel clock */
53   -};
54   -
55   -struct da8xx_lcdc_platform_data {
56   - const char manu_name[10];
57   - void *controller_data;
58   - const char type[25];
59   - void (*panel_power_ctrl)(int);
60   -};
61   -
62   -struct lcd_ctrl_config {
63   - const struct display_panel *p_disp_panel;
64   -
65   - /* AC Bias Pin Frequency */
66   - int ac_bias;
67   -
68   - /* AC Bias Pin Transitions per Interrupt */
69   - int ac_bias_intrpt;
70   -
71   - /* DMA burst size */
72   - int dma_burst_sz;
73   -
74   - /* Bits per pixel */
75   - int bpp;
76   -
77   - /* FIFO DMA Request Delay */
78   - int fdd;
79   -
80   - /* TFT Alternative Signal Mapping (Only for active) */
81   - unsigned char tft_alt_mode;
82   -
83   - /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
84   - unsigned char stn_565_mode;
85   -
86   - /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
87   - unsigned char mono_8bit_mode;
88   -
89   - /* Invert line clock */
90   - unsigned char invert_line_clock;
91   -
92   - /* Invert frame clock */
93   - unsigned char invert_frm_clock;
94   -
95   - /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
96   - unsigned char sync_edge;
97   -
98   - /* Horizontal and Vertical Sync: Control: 0=ignore */
99   - unsigned char sync_ctrl;
100   -
101   - /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
102   - unsigned char raster_order;
103   -};
104   -
105   -struct lcd_sync_arg {
106   - int back_porch;
107   - int front_porch;
108   - int pulse_width;
109   -};
110   -
111   -void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel);
112   -
113   -#endif /* ifndef DA8XX_FB_H */
arch/arm/include/asm/arch-exynos/mipi_dsim.h
Diff comments   View file @ c15438e
... ... @@ -291,7 +291,7 @@
291 291 */
292 292 struct mipi_dsim_master_ops {
293 293 int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id,
294   - unsigned int data0, unsigned int data1);
  294 + const unsigned char *data0, unsigned int data1);
295 295 int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id,
296 296 unsigned int data0, unsigned int data1);
297 297 int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim);
arch/arm/include/asm/imx-common/dma.h
Diff comments   View file @ c15438e
... ... @@ -161,5 +161,7 @@
161 161 int mxs_dma_init_channel(int chan);
162 162 int mxs_dma_release(int chan);
163 163  
  164 +void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc);
  165 +
164 166 #endif /* __DMA_H__ */
arch/powerpc/cpu/mpc8xx/video.c
Diff comments   View file @ c15438e
... ... @@ -109,7 +109,6 @@
109 109 /************************************************************************/
110 110  
111 111 #include <video_font.h> /* Get font data, width and height */
112   -#include <video_font_data.h>
113 112  
114 113 #ifdef CONFIG_VIDEO_LOGO
115 114 #include <video_logo.h> /* Get logo data, width and height */
board/davinci/ea20/ea20.c
Diff comments   View file @ c15438e
... ... @@ -24,7 +24,7 @@
24 24 #include <asm/io.h>
25 25 #include <asm/arch/davinci_misc.h>
26 26 #include <asm/gpio.h>
27   -#include <asm/arch/da8xx-fb.h>
  27 +#include "../../../drivers/video/da8xx-fb.h"
28 28  
29 29 DECLARE_GLOBAL_DATA_PTR;
30 30  
... ... @@ -43,6 +43,30 @@
43 43 .invert_pxl_clk = 0,
44 44 };
45 45  
  46 +static const struct display_panel disp_panel = {
  47 + QVGA,
  48 + 16,
  49 + 16,
  50 + COLOR_ACTIVE,
  51 +};
  52 +
  53 +static const struct lcd_ctrl_config lcd_cfg = {
  54 + &disp_panel,
  55 + .ac_bias = 255,
  56 + .ac_bias_intrpt = 0,
  57 + .dma_burst_sz = 16,
  58 + .bpp = 16,
  59 + .fdd = 255,
  60 + .tft_alt_mode = 0,
  61 + .stn_565_mode = 0,
  62 + .mono_8bit_mode = 0,
  63 + .invert_line_clock = 1,
  64 + .invert_frm_clock = 1,
  65 + .sync_edge = 0,
  66 + .sync_ctrl = 1,
  67 + .raster_order = 0,
  68 +};
  69 +
46 70 /* SPI0 pin muxer settings */
47 71 static const struct pinmux_config spi1_pins[] = {
48 72 { pinmux(5), 1, 1 },
... ... @@ -259,7 +283,7 @@
259 283 /* address of boot parameters */
260 284 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
261 285  
262   - da8xx_video_init(&lcd_panel, 16);
  286 + da8xx_video_init(&lcd_panel, &lcd_cfg, 16);
263 287  
264 288 return 0;
265 289 }
... ... @@ -51,7 +51,6 @@
51 51 /* ** FONT DATA */
52 52 /************************************************************************/
53 53 #include <video_font.h> /* Get font data, width and height */
54   -#include <video_font_data.h>
55 54  
56 55 /************************************************************************/
57 56 /* ** LOGO DATA */
drivers/dma/apbh_dma.c
Diff comments   View file @ c15438e
... ... @@ -545,6 +545,28 @@
545 545 }
546 546  
547 547 /*
  548 + * Execute a continuously running circular DMA descriptor.
  549 + * NOTE: This is not intended for general use, but rather
  550 + * for the LCD driver in Smart-LCD mode. It allows
  551 + * continuous triggering of the RUN bit there.
  552 + */
  553 +void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc)
  554 +{
  555 + struct mxs_apbh_regs *apbh_regs =
  556 + (struct mxs_apbh_regs *)MXS_APBH_BASE;
  557 +
  558 + mxs_dma_flush_desc(pdesc);
  559 +
  560 + mxs_dma_enable_irq(chan, 1);
  561 +
  562 + writel(mxs_dma_cmd_address(pdesc),
  563 + &apbh_regs->ch[chan].hw_apbh_ch_nxtcmdar);
  564 + writel(1, &apbh_regs->ch[chan].hw_apbh_ch_sema);
  565 + writel(1 << (chan + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
  566 + &apbh_regs->hw_apbh_ctrl0_clr);
  567 +}
  568 +
  569 +/*
548 570 * Initialize the DMA hardware
549 571 */
550 572 void mxs_dma_init(void)
drivers/video/Makefile
Diff comments   View file @ c15438e
... ... @@ -19,6 +19,7 @@
19 19 exynos_mipi_dsi_lowlevel.o
20 20 COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
21 21 COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
  22 +COBJS-$(CONFIG_L5F31188) += l5f31188.o
22 23 COBJS-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o
23 24 COBJS-$(CONFIG_PXA_LCD) += pxa_lcd.o
24 25 COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o
drivers/video/cfb_console.c
Diff comments   View file @ c15438e
... ... @@ -197,7 +197,6 @@
197 197 #include <linux/types.h>
198 198 #include <stdio_dev.h>
199 199 #include <video_font.h>
200   -#include <video_font_data.h>
201 200  
202 201 #if defined(CONFIG_CMD_DATE)
203 202 #include <rtc.h>
... ... @@ -431,6 +430,16 @@
431 430 {0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff}
432 431 };
433 432  
  433 +/*
  434 + * Implement a weak default function for boards that optionally
  435 + * need to skip the cfb initialization.
  436 + */
  437 +__weak int board_cfb_skip(void)
  438 +{
  439 + /* As default, don't skip cfb init */
  440 + return 0;
  441 +}
  442 +
434 443 static void video_drawchars(int xx, int yy, unsigned char *s, int count)
435 444 {
436 445 u8 *cdat, *dest, *dest0;
... ... @@ -452,6 +461,10 @@
452 461 ((u32 *) dest)[0] =
453 462 (video_font_draw_table8[bits >> 4] &
454 463 eorx) ^ bgx;
  464 +
  465 + if (VIDEO_FONT_WIDTH == 4)
  466 + continue;
  467 +
455 468 ((u32 *) dest)[1] =
456 469 (video_font_draw_table8[bits & 15] &
457 470 eorx) ^ bgx;
... ... @@ -477,6 +490,10 @@
477 490 SHORTSWAP32((video_font_draw_table15
478 491 [bits >> 4 & 3] & eorx) ^
479 492 bgx);
  493 +
  494 + if (VIDEO_FONT_WIDTH == 4)
  495 + continue;
  496 +
480 497 ((u32 *) dest)[2] =
481 498 SHORTSWAP32((video_font_draw_table15
482 499 [bits >> 2 & 3] & eorx) ^
... ... @@ -507,6 +524,10 @@
507 524 SHORTSWAP32((video_font_draw_table16
508 525 [bits >> 4 & 3] & eorx) ^
509 526 bgx);
  527 +
  528 + if (VIDEO_FONT_WIDTH == 4)
  529 + continue;
  530 +
510 531 ((u32 *) dest)[2] =
511 532 SHORTSWAP32((video_font_draw_table16
512 533 [bits >> 2 & 3] & eorx) ^
... ... @@ -541,6 +562,11 @@
541 562 ((u32 *) dest)[3] =
542 563 SWAP32((video_font_draw_table32
543 564 [bits >> 4][3] & eorx) ^ bgx);
  565 +
  566 +
  567 + if (VIDEO_FONT_WIDTH == 4)
  568 + continue;
  569 +
544 570 ((u32 *) dest)[4] =
545 571 SWAP32((video_font_draw_table32
546 572 [bits & 15][0] & eorx) ^ bgx);
... ... @@ -576,6 +602,10 @@
576 602 ((u32 *) dest)[2] =
577 603 (video_font_draw_table24[bits >> 4][2]
578 604 & eorx) ^ bgx;
  605 +
  606 + if (VIDEO_FONT_WIDTH == 4)
  607 + continue;
  608 +
579 609 ((u32 *) dest)[3] =
580 610 (video_font_draw_table24[bits & 15][0]
581 611 & eorx) ^ bgx;
... ... @@ -1996,6 +2026,8 @@
1996 2026 return video_fb_address + video_logo_height * VIDEO_LINE_LEN;
1997 2027 }
1998 2028 #endif
  2029 + if (board_cfb_skip())
  2030 + return 0;
1999 2031  
2000 2032 sprintf(info, " %s", version_string);
2001 2033  
... ... @@ -2204,6 +2236,9 @@
2204 2236  
2205 2237 /* Init video chip - returns with framebuffer cleared */
2206 2238 skip_dev_init = (video_init() == -1);
  2239 +
  2240 + if (board_cfb_skip())
  2241 + return 0;
2207 2242  
2208 2243 #if !defined(CONFIG_VGA_AS_SINGLE_DEVICE)
2209 2244 debug("KBD: Keyboard init ...\n");
drivers/video/da8xx-fb.c
Diff comments   View file @ c15438e
... ... @@ -24,10 +24,17 @@
24 24 #include <asm/arch/hardware.h>
25 25  
26 26 #include "videomodes.h"
27   -#include <asm/arch/da8xx-fb.h>
  27 +#include "da8xx-fb.h"
28 28  
  29 +#if !defined(DA8XX_LCD_CNTL_BASE)
  30 +#define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE
  31 +#endif
  32 +
29 33 #define DRIVER_NAME "da8xx_lcdc"
30 34  
  35 +#define LCD_VERSION_1 1
  36 +#define LCD_VERSION_2 2
  37 +
31 38 /* LCD Status Register */
32 39 #define LCD_END_OF_FRAME1 (1 << 9)
33 40 #define LCD_END_OF_FRAME0 (1 << 8)
34 41  
... ... @@ -42,9 +49,14 @@
42 49 #define LCD_DMA_BURST_4 0x2
43 50 #define LCD_DMA_BURST_8 0x3
44 51 #define LCD_DMA_BURST_16 0x4
45   -#define LCD_END_OF_FRAME_INT_ENA (1 << 2)
  52 +#define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2)
  53 +#define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8)
  54 +#define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9)
46 55 #define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
47 56  
  57 +#define LCD_V2_TFT_24BPP_MODE (1 << 25)
  58 +#define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
  59 +
48 60 /* LCD Control Register */
49 61 #define LCD_CLK_DIVISOR(x) ((x) << 8)
50 62 #define LCD_RASTER_MODE 0x01
51 63  
... ... @@ -58,12 +70,20 @@
58 70 #define LCD_MONO_8BIT_MODE (1 << 9)
59 71 #define LCD_RASTER_ORDER (1 << 8)
60 72 #define LCD_TFT_MODE (1 << 7)
61   -#define LCD_UNDERFLOW_INT_ENA (1 << 6)
62   -#define LCD_PL_ENABLE (1 << 4)
  73 +#define LCD_V1_UNDERFLOW_INT_ENA (1 << 6)
  74 +#define LCD_V2_UNDERFLOW_INT_ENA (1 << 5)
  75 +#define LCD_V1_PL_INT_ENA (1 << 4)
  76 +#define LCD_V2_PL_INT_ENA (1 << 6)
63 77 #define LCD_MONOCHROME_MODE (1 << 1)
64 78 #define LCD_RASTER_ENABLE (1 << 0)
65 79 #define LCD_TFT_ALT_ENABLE (1 << 23)
66 80 #define LCD_STN_565_ENABLE (1 << 24)
  81 +#define LCD_V2_DMA_CLK_EN (1 << 2)
  82 +#define LCD_V2_LIDD_CLK_EN (1 << 1)
  83 +#define LCD_V2_CORE_CLK_EN (1 << 0)
  84 +#define LCD_V2_LPP_B10 26
  85 +#define LCD_V2_TFT_24BPP_MODE (1 << 25)
  86 +#define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
67 87  
68 88 /* LCD Raster Timing 2 Register */
69 89 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
... ... @@ -74,6 +94,8 @@
74 94 #define LCD_INVERT_LINE_CLOCK (1 << 21)
75 95 #define LCD_INVERT_FRAME_CLOCK (1 << 20)
76 96  
  97 +/* Clock registers available only on Version 2 */
  98 +#define LCD_CLK_MAIN_RESET (1 << 3)
77 99 /* LCD Block */
78 100 struct da8xx_lcd_regs {
79 101 u32 revid;
... ... @@ -97,6 +119,15 @@
97 119 u32 dma_frm_buf_ceiling_addr_0;
98 120 u32 dma_frm_buf_base_addr_1;
99 121 u32 dma_frm_buf_ceiling_addr_1;
  122 + u32 resv1;
  123 + u32 raw_stat;
  124 + u32 masked_stat;
  125 + u32 int_ena_set;
  126 + u32 int_ena_clr;
  127 + u32 end_of_int_ind;
  128 + /* Clock registers available only on Version 2 */
  129 + u32 clk_ena;
  130 + u32 clk_reset;
100 131 };
101 132  
102 133 #define LCD_NUM_BUFFERS 1
... ... @@ -107,6 +138,8 @@
107 138 #define RIGHT_MARGIN 64
108 139 #define UPPER_MARGIN 32
109 140 #define LOWER_MARGIN 32
  141 +#define WAIT_FOR_FRAME_DONE true
  142 +#define NO_WAIT_FOR_FRAME_DONE false
110 143  
111 144 #define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
112 145  
... ... @@ -119,6 +152,8 @@
119 152 static const struct da8xx_panel *lcd_panel;
120 153 static struct fb_info *da8xx_fb_info;
121 154 static int bits_x_pixel;
  155 +static unsigned int lcd_revision;
  156 +const struct lcd_ctrl_config *da8xx_lcd_cfg;
122 157  
123 158 static inline unsigned int lcdc_read(u32 *addr)
124 159 {
125 160  
... ... @@ -179,35 +214,24 @@
179 214 .accel = FB_ACCEL_NONE
180 215 };
181 216  
182   -static const struct display_panel disp_panel = {
183   - QVGA,
184   - 16,
185   - 16,
186   - COLOR_ACTIVE,
187   -};
188   -
189   -static const struct lcd_ctrl_config lcd_cfg = {
190   - &disp_panel,
191   - .ac_bias = 255,
192   - .ac_bias_intrpt = 0,
193   - .dma_burst_sz = 16,
194   - .bpp = 16,
195   - .fdd = 255,
196   - .tft_alt_mode = 0,
197   - .stn_565_mode = 0,
198   - .mono_8bit_mode = 0,
199   - .invert_line_clock = 1,
200   - .invert_frm_clock = 1,
201   - .sync_edge = 0,
202   - .sync_ctrl = 1,
203   - .raster_order = 0,
204   -};
205   -
206 217 /* Enable the Raster Engine of the LCD Controller */
207 218 static inline void lcd_enable_raster(void)
208 219 {
209 220 u32 reg;
210 221  
  222 + /* Put LCDC in reset for several cycles */
  223 + if (lcd_revision == LCD_VERSION_2)
  224 + lcdc_write(LCD_CLK_MAIN_RESET,
  225 + &da8xx_fb_reg_base->clk_reset);
  226 +
  227 + udelay(1000);
  228 + /* Bring LCDC out of reset */
  229 + if (lcd_revision == LCD_VERSION_2)
  230 + lcdc_write(0,
  231 + &da8xx_fb_reg_base->clk_reset);
  232 +
  233 + udelay(1000);
  234 +
211 235 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
212 236 if (!(reg & LCD_RASTER_ENABLE))
213 237 lcdc_write(reg | LCD_RASTER_ENABLE,
214 238  
215 239  
216 240  
... ... @@ -215,14 +239,40 @@
215 239 }
216 240  
217 241 /* Disable the Raster Engine of the LCD Controller */
218   -static inline void lcd_disable_raster(void)
  242 +static inline void lcd_disable_raster(bool wait_for_frame_done)
219 243 {
220 244 u32 reg;
  245 + u32 loop_cnt = 0;
  246 + u32 stat;
  247 + u32 i = 0;
221 248  
  249 + if (wait_for_frame_done)
  250 + loop_cnt = 5000;
  251 +
222 252 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
223 253 if (reg & LCD_RASTER_ENABLE)
224 254 lcdc_write(reg & ~LCD_RASTER_ENABLE,
225 255 &da8xx_fb_reg_base->raster_ctrl);
  256 +
  257 + /* Wait for the current frame to complete */
  258 + do {
  259 + if (lcd_revision == LCD_VERSION_1)
  260 + stat = lcdc_read(&da8xx_fb_reg_base->stat);
  261 + else
  262 + stat = lcdc_read(&da8xx_fb_reg_base->raw_stat);
  263 +
  264 + mdelay(1);
  265 + } while (!(stat & 0x01) && (i++ < loop_cnt));
  266 +
  267 + if (lcd_revision == LCD_VERSION_1)
  268 + lcdc_write(stat, &da8xx_fb_reg_base->stat);
  269 + else
  270 + lcdc_write(stat, &da8xx_fb_reg_base->raw_stat);
  271 +
  272 + if ((loop_cnt != 0) && (i >= loop_cnt)) {
  273 + printf("LCD Controller timed out\n");
  274 + return;
  275 + }
226 276 }
227 277  
228 278 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
... ... @@ -231,6 +281,7 @@
231 281 u32 end;
232 282 u32 reg_ras;
233 283 u32 reg_dma;
  284 + u32 reg_int;
234 285  
235 286 /* init reg to clear PLM (loading mode) fields */
236 287 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
... ... @@ -243,7 +294,15 @@
243 294 end = par->dma_end;
244 295  
245 296 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
246   - reg_dma |= LCD_END_OF_FRAME_INT_ENA;
  297 + if (lcd_revision == LCD_VERSION_1) {
  298 + reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
  299 + } else {
  300 + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
  301 + LCD_V2_END_OF_FRAME0_INT_ENA |
  302 + LCD_V2_END_OF_FRAME1_INT_ENA |
  303 + LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
  304 + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
  305 + }
247 306  
248 307 #if (LCD_NUM_BUFFERS == 2)
249 308 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
... ... @@ -264,7 +323,13 @@
264 323 end = start + par->palette_sz - 1;
265 324  
266 325 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
267   - reg_ras |= LCD_PL_ENABLE;
  326 + if (lcd_revision == LCD_VERSION_1) {
  327 + reg_ras |= LCD_V1_PL_INT_ENA;
  328 + } else {
  329 + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
  330 + LCD_V2_PL_INT_ENA;
  331 + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
  332 + }
268 333  
269 334 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
270 335 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
... ... @@ -348,6 +413,7 @@
348 413 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
349 414 {
350 415 u32 reg;
  416 + u32 reg_int;
351 417  
352 418 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
353 419 LCD_MONO_8BIT_MODE |
... ... @@ -375,7 +441,13 @@
375 441 }
376 442  
377 443 /* enable additional interrupts here */
378   - reg |= LCD_UNDERFLOW_INT_ENA;
  444 + if (lcd_revision == LCD_VERSION_1) {
  445 + reg |= LCD_V1_UNDERFLOW_INT_ENA;
  446 + } else {
  447 + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
  448 + LCD_V2_UNDERFLOW_INT_ENA;
  449 + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
  450 + }
379 451  
380 452 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
381 453  
382 454  
383 455  
384 456  
385 457  
... ... @@ -413,22 +485,53 @@
413 485  
414 486 /* Set the Panel Width */
415 487 /* Pixels per line = (PPL + 1)*16 */
416   - /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
417   - width &= 0x3f0;
  488 + if (lcd_revision == LCD_VERSION_1) {
  489 + /*
  490 + * 0x3F in bits 4..9 gives max horisontal resolution = 1024
  491 + * pixels
  492 + */
  493 + width &= 0x3f0;
  494 + } else {
  495 + /*
  496 + * 0x7F in bits 4..10 gives max horizontal resolution = 2048
  497 + * pixels.
  498 + */
  499 + width &= 0x7f0;
  500 + }
418 501 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
419 502 reg &= 0xfffffc00;
420   - reg |= ((width >> 4) - 1) << 4;
  503 + if (lcd_revision == LCD_VERSION_1) {
  504 + reg |= ((width >> 4) - 1) << 4;
  505 + } else {
  506 + width = (width >> 4) - 1;
  507 + reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
  508 + }
421 509 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
422 510  
423 511 /* Set the Panel Height */
  512 + /* Set bits 9:0 of Lines Per Pixel */
424 513 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
425 514 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
426 515 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
427 516  
  517 + /* Set bit 10 of Lines Per Pixel */
  518 + if (lcd_revision == LCD_VERSION_2) {
  519 + reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
  520 + reg |= ((height - 1) & 0x400) << 16;
  521 + lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
  522 + }
  523 +
428 524 /* Set the Raster Order of the Frame Buffer */
429 525 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
430 526 if (raster_order)
431 527 reg |= LCD_RASTER_ORDER;
  528 +
  529 + if (bpp == 24)
  530 + reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
  531 + else if (bpp == 32)
  532 + reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
  533 + | LCD_V2_TFT_24BPP_UNPACK);
  534 +
432 535 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
433 536  
434 537 switch (bpp) {
... ... @@ -436,6 +539,8 @@
436 539 case 2:
437 540 case 4:
438 541 case 16:
  542 + case 24:
  543 + case 32:
439 544 par->palette_sz = 16 * 2;
440 545 break;
441 546  
... ... @@ -494,6 +599,23 @@
494 599 update_hw = 1;
495 600 palette[0] = 0x4000;
496 601 }
  602 + } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
  603 + ((info->var.bits_per_pixel == 24) && regno < 24)) {
  604 + red >>= (24 - info->var.red.length);
  605 + red <<= info->var.red.offset;
  606 +
  607 + green >>= (24 - info->var.green.length);
  608 + green <<= info->var.green.offset;
  609 +
  610 + blue >>= (24 - info->var.blue.length);
  611 + blue <<= info->var.blue.offset;
  612 +
  613 + par->pseudo_palette[regno] = red | green | blue;
  614 +
  615 + if (palette[0] != 0x4000) {
  616 + update_hw = 1;
  617 + palette[0] = 0x4000;
  618 + }
497 619 }
498 620  
499 621 /* Update the palette in the h/w as needed. */
500 622  
... ... @@ -506,11 +628,18 @@
506 628 static void lcd_reset(struct da8xx_fb_par *par)
507 629 {
508 630 /* Disable the Raster if previously Enabled */
509   - lcd_disable_raster();
  631 + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
510 632  
511 633 /* DMA has to be disabled */
512 634 lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
513 635 lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
  636 +
  637 + if (lcd_revision == LCD_VERSION_2) {
  638 + lcdc_write(0, &da8xx_fb_reg_base->int_ena_set);
  639 + /* Write 1 to reset */
  640 + lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
  641 + lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
  642 + }
514 643 }
515 644  
516 645 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
517 646  
... ... @@ -521,12 +650,17 @@
521 650 lcd_clk = clk_get(2);
522 651  
523 652 div = lcd_clk / par->pxl_clk;
524   - debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n",
525   - lcd_clk, div, par->pxl_clk);
  653 + debug("LCD Clock: %d Divider: %d PixClk: %d\n",
  654 + lcd_clk, div, par->pxl_clk);
526 655  
527 656 /* Configure the LCD clock divisor. */
528 657 lcdc_write(LCD_CLK_DIVISOR(div) |
529 658 (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
  659 +
  660 + if (lcd_revision == LCD_VERSION_2)
  661 + lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
  662 + LCD_V2_CORE_CLK_EN,
  663 + &da8xx_fb_reg_base->clk_ena);
530 664 }
531 665  
532 666 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
... ... @@ -566,7 +700,8 @@
566 700 if (ret < 0)
567 701 return ret;
568 702  
569   - if (QVGA != cfg->p_disp_panel->panel_type)
  703 + if ((QVGA != cfg->p_disp_panel->panel_type) &&
  704 + (WVGA != cfg->p_disp_panel->panel_type))
570 705 return -EINVAL;
571 706  
572 707 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
... ... @@ -602,7 +737,7 @@
602 737 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
603 738 }
604 739  
605   -static u32 lcdc_irq_handler(void)
  740 +static u32 lcdc_irq_handler_rev01(void)
606 741 {
607 742 struct da8xx_fb_par *par = da8xx_fb_info->par;
608 743 u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
... ... @@ -610,7 +745,7 @@
610 745  
611 746 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
612 747 debug("LCD_SYNC_LOST\n");
613   - lcd_disable_raster();
  748 + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
614 749 lcdc_write(stat, &da8xx_fb_reg_base->stat);
615 750 lcd_enable_raster();
616 751 return LCD_SYNC_LOST;
617 752  
... ... @@ -622,13 +757,13 @@
622 757 * interrupt via the following write to the status register. If
623 758 * this is done after then one gets multiple PL done interrupts.
624 759 */
625   - lcd_disable_raster();
  760 + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
626 761  
627 762 lcdc_write(stat, &da8xx_fb_reg_base->stat);
628 763  
629 764 /* Disable PL completion inerrupt */
630 765 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
631   - reg_ras &= ~LCD_PL_ENABLE;
  766 + reg_ras &= ~LCD_V1_PL_INT_ENA;
632 767 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
633 768  
634 769 /* Setup and start data loading mode */
... ... @@ -650,6 +785,66 @@
650 785 return stat;
651 786 }
652 787  
  788 +static u32 lcdc_irq_handler_rev02(void)
  789 +{
  790 + struct da8xx_fb_par *par = da8xx_fb_info->par;
  791 + u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
  792 + u32 reg_int;
  793 +
  794 + if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
  795 + debug("LCD_SYNC_LOST\n");
  796 + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  797 + lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
  798 + lcd_enable_raster();
  799 + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  800 + return LCD_SYNC_LOST;
  801 + } else if (stat & LCD_PL_LOAD_DONE) {
  802 + debug("LCD_PL_LOAD_DONE\n");
  803 + /*
  804 + * Must disable raster before changing state of any control bit.
  805 + * And also must be disabled before clearing the PL loading
  806 + * interrupt via the following write to the status register. If
  807 + * this is done after then one gets multiple PL done interrupts.
  808 + */
  809 + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  810 +
  811 + lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
  812 +
  813 + /* Disable PL completion inerrupt */
  814 + reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) |
  815 + (LCD_V2_PL_INT_ENA);
  816 + lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
  817 +
  818 + /* Setup and start data loading mode */
  819 + lcd_blit(LOAD_DATA, par);
  820 + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  821 + return LCD_PL_LOAD_DONE;
  822 + } else {
  823 + lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
  824 +
  825 + if (stat & LCD_END_OF_FRAME0)
  826 + debug("LCD_END_OF_FRAME0\n");
  827 +
  828 + lcdc_write(par->dma_start,
  829 + &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  830 + lcdc_write(par->dma_end,
  831 + &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  832 + par->vsync_flag = 1;
  833 + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  834 + return LCD_END_OF_FRAME0;
  835 + }
  836 + lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  837 + return stat;
  838 +}
  839 +
  840 +static u32 lcdc_irq_handler(void)
  841 +{
  842 + if (lcd_revision == LCD_VERSION_1)
  843 + return lcdc_irq_handler_rev01();
  844 + else
  845 + return lcdc_irq_handler_rev02();
  846 +}
  847 +
653 848 static u32 wait_for_event(u32 event)
654 849 {
655 850 u32 timeout = 50000;
... ... @@ -673,6 +868,7 @@
673 868 {
674 869 struct da8xx_fb_par *par;
675 870 u32 size;
  871 + u32 rev;
676 872 char *p;
677 873  
678 874 if (!lcd_panel) {
... ... @@ -685,6 +881,10 @@
685 881 gpanel.plnSizeY = lcd_panel->height;
686 882  
687 883 switch (bits_x_pixel) {
  884 + case 32:
  885 + gpanel.gdfBytesPP = 4;
  886 + gpanel.gdfIndex = GDF_32BIT_X888RGB;
  887 + break;
688 888 case 24:
689 889 gpanel.gdfBytesPP = 4;
690 890 gpanel.gdfIndex = GDF_32BIT_X888RGB;
691 891  
692 892  
... ... @@ -699,13 +899,30 @@
699 899 break;
700 900 }
701 901  
702   - da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE;
  902 + da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE;
703 903  
704   - debug("Resolution: %dx%d %x\n",
705   - gpanel.winSizeX,
706   - gpanel.winSizeY,
707   - lcd_cfg.bpp);
  904 + /* Determine LCD IP Version */
  905 + rev = lcdc_read(&da8xx_fb_reg_base->revid);
  906 + switch (rev) {
  907 + case 0x4C100102:
  908 + lcd_revision = LCD_VERSION_1;
  909 + break;
  910 + case 0x4F200800:
  911 + case 0x4F201000:
  912 + lcd_revision = LCD_VERSION_2;
  913 + break;
  914 + default:
  915 + printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n",
  916 + rev);
  917 + lcd_revision = LCD_VERSION_1;
  918 + break;
  919 + }
708 920  
  921 + debug("rev: 0x%x Resolution: %dx%d %d\n", rev,
  922 + gpanel.winSizeX,
  923 + gpanel.winSizeY,
  924 + da8xx_lcd_cfg->bpp);
  925 +
709 926 size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
710 927 da8xx_fb_info = malloc(size);
711 928 debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
712 929  
... ... @@ -722,13 +939,14 @@
722 939 par = da8xx_fb_info->par;
723 940 par->pxl_clk = lcd_panel->pxl_clk;
724 941  
725   - if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) {
  942 + if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) {
726 943 printf("lcd_init failed\n");
727 944 goto err_release_fb;
728 945 }
729 946  
730 947 /* allocate frame buffer */
731   - par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp;
  948 + par->vram_size = lcd_panel->width * lcd_panel->height *
  949 + da8xx_lcd_cfg->bpp;
732 950 par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
733 951  
734 952 par->vram_virt = malloc(par->vram_size);
735 953  
... ... @@ -741,12 +959,13 @@
741 959 printf("GLCD: malloc for frame buffer failed\n");
742 960 goto err_release_fb;
743 961 }
  962 + gd->fb_base = (int)par->vram_virt;
744 963  
745 964 gpanel.frameAdrs = (unsigned int)par->vram_virt;
746 965 da8xx_fb_info->screen_base = (char *) par->vram_virt;
747 966 da8xx_fb_fix.smem_start = gpanel.frameAdrs;
748 967 da8xx_fb_fix.smem_len = par->vram_size;
749   - da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8;
  968 + da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8;
750 969  
751 970 par->dma_start = par->vram_phys;
752 971 par->dma_end = par->dma_start + lcd_panel->height *
... ... @@ -762,7 +981,7 @@
762 981 par->p_palette_base = (unsigned int)par->v_palette_base;
763 982  
764 983 /* Initialize par */
765   - da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp;
  984 + da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp;
766 985  
767 986 da8xx_fb_var.xres = lcd_panel->width;
768 987 da8xx_fb_var.xres_virtual = lcd_panel->width;
... ... @@ -771,8 +990,8 @@
771 990 da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
772 991  
773 992 da8xx_fb_var.grayscale =
774   - lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
775   - da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp;
  993 + da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
  994 + da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp;
776 995  
777 996 da8xx_fb_var.hsync_len = lcd_panel->hsw;
778 997 da8xx_fb_var.vsync_len = lcd_panel->vsw;
... ... @@ -787,8 +1006,11 @@
787 1006  
788 1007 /* Clear interrupt */
789 1008 memset((void *)par->vram_virt, 0, par->vram_size);
790   - lcd_disable_raster();
791   - lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
  1009 + lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  1010 + if (lcd_revision == LCD_VERSION_1)
  1011 + lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
  1012 + else
  1013 + lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat);
792 1014 debug("Palette at 0x%x size %d\n", par->p_palette_base,
793 1015 par->palette_sz);
794 1016 lcdc_dma_start();
795 1017  
... ... @@ -823,9 +1045,11 @@
823 1045 return;
824 1046 }
825 1047  
826   -void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel)
  1048 +void da8xx_video_init(const struct da8xx_panel *panel,
  1049 + const struct lcd_ctrl_config *lcd_cfg, int bits_pixel)
827 1050 {
828 1051 lcd_panel = panel;
  1052 + da8xx_lcd_cfg = lcd_cfg;
829 1053 bits_x_pixel = bits_pixel;
830 1054 }
drivers/video/da8xx-fb.h
Diff comments   View file @ c15438e
  1 +/*
  2 + * Porting to u-boot:
  3 + *
  4 + * (C) Copyright 2011
  5 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  6 + *
  7 + * Copyright (C) 2008-2009 MontaVista Software Inc.
  8 + * Copyright (C) 2008-2009 Texas Instruments Inc
  9 + *
  10 + * Based on the LCD driver for TI Avalanche processors written by
  11 + * Ajay Singh and Shalom Hai.
  12 + *
  13 + * SPDX-License-Identifier: GPL-2.0+
  14 + */
  15 +
  16 +#ifndef DA8XX_FB_H
  17 +#define DA8XX_FB_H
  18 +
  19 +enum panel_type {
  20 + QVGA = 0,
  21 + WVGA
  22 +};
  23 +
  24 +enum panel_shade {
  25 + MONOCHROME = 0,
  26 + COLOR_ACTIVE,
  27 + COLOR_PASSIVE,
  28 +};
  29 +
  30 +enum raster_load_mode {
  31 + LOAD_DATA = 1,
  32 + LOAD_PALETTE,
  33 +};
  34 +
  35 +struct display_panel {
  36 + enum panel_type panel_type; /* QVGA */
  37 + int max_bpp;
  38 + int min_bpp;
  39 + enum panel_shade panel_shade;
  40 +};
  41 +
  42 +struct da8xx_panel {
  43 + const char name[25]; /* Full name <vendor>_<model> */
  44 + unsigned short width;
  45 + unsigned short height;
  46 + int hfp; /* Horizontal front porch */
  47 + int hbp; /* Horizontal back porch */
  48 + int hsw; /* Horizontal Sync Pulse Width */
  49 + int vfp; /* Vertical front porch */
  50 + int vbp; /* Vertical back porch */
  51 + int vsw; /* Vertical Sync Pulse Width */
  52 + unsigned int pxl_clk; /* Pixel clock */
  53 + unsigned char invert_pxl_clk; /* Invert Pixel clock */
  54 +};
  55 +
  56 +struct da8xx_lcdc_platform_data {
  57 + const char manu_name[10];
  58 + void *controller_data;
  59 + const char type[25];
  60 + void (*panel_power_ctrl)(int);
  61 +};
  62 +
  63 +struct lcd_ctrl_config {
  64 + const struct display_panel *p_disp_panel;
  65 +
  66 + /* AC Bias Pin Frequency */
  67 + int ac_bias;
  68 +
  69 + /* AC Bias Pin Transitions per Interrupt */
  70 + int ac_bias_intrpt;
  71 +
  72 + /* DMA burst size */
  73 + int dma_burst_sz;
  74 +
  75 + /* Bits per pixel */
  76 + int bpp;
  77 +
  78 + /* FIFO DMA Request Delay */
  79 + int fdd;
  80 +
  81 + /* TFT Alternative Signal Mapping (Only for active) */
  82 + unsigned char tft_alt_mode;
  83 +
  84 + /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
  85 + unsigned char stn_565_mode;
  86 +
  87 + /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
  88 + unsigned char mono_8bit_mode;
  89 +
  90 + /* Invert line clock */
  91 + unsigned char invert_line_clock;
  92 +
  93 + /* Invert frame clock */
  94 + unsigned char invert_frm_clock;
  95 +
  96 + /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
  97 + unsigned char sync_edge;
  98 +
  99 + /* Horizontal and Vertical Sync: Control: 0=ignore */
  100 + unsigned char sync_ctrl;
  101 +
  102 + /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
  103 + unsigned char raster_order;
  104 +};
  105 +
  106 +struct lcd_sync_arg {
  107 + int back_porch;
  108 + int front_porch;
  109 + int pulse_width;
  110 +};
  111 +
  112 +void da8xx_video_init(const struct da8xx_panel *panel,
  113 + const struct lcd_ctrl_config *lcd_cfg,
  114 + int bits_pixel);
  115 +
  116 +#endif /* ifndef DA8XX_FB_H */
drivers/video/exynos_mipi_dsi_common.c
Diff comments   View file @ c15438e
... ... @@ -50,7 +50,7 @@
50 50 };
51 51  
52 52 static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
53   - unsigned int data0, unsigned int data1)
  53 + const unsigned char *data0, unsigned int data1)
54 54 {
55 55 unsigned int data_cnt = 0, payload = 0;
56 56  
57 57  
58 58  
59 59  
60 60  
61 61  
62 62  
63 63  
... ... @@ -62,42 +62,40 @@
62 62 */
63 63 if ((data1 - data_cnt) < 4) {
64 64 if ((data1 - data_cnt) == 3) {
65   - payload = *(u8 *)(data0 + data_cnt) |
66   - (*(u8 *)(data0 + (data_cnt + 1))) << 8 |
67   - (*(u8 *)(data0 + (data_cnt + 2))) << 16;
  65 + payload = data0[data_cnt] |
  66 + data0[data_cnt + 1] << 8 |
  67 + data0[data_cnt + 2] << 16;
68 68 debug("count = 3 payload = %x, %x %x %x\n",
69   - payload, *(u8 *)(data0 + data_cnt),
70   - *(u8 *)(data0 + (data_cnt + 1)),
71   - *(u8 *)(data0 + (data_cnt + 2)));
  69 + payload, data0[data_cnt],
  70 + data0[data_cnt + 1],
  71 + data0[data_cnt + 2]);
72 72 } else if ((data1 - data_cnt) == 2) {
73   - payload = *(u8 *)(data0 + data_cnt) |
74   - (*(u8 *)(data0 + (data_cnt + 1))) << 8;
  73 + payload = data0[data_cnt] |
  74 + data0[data_cnt + 1] << 8;
75 75 debug("count = 2 payload = %x, %x %x\n", payload,
76   - *(u8 *)(data0 + data_cnt),
77   - *(u8 *)(data0 + (data_cnt + 1)));
  76 + data0[data_cnt], data0[data_cnt + 1]);
78 77 } else if ((data1 - data_cnt) == 1) {
79   - payload = *(u8 *)(data0 + data_cnt);
  78 + payload = data0[data_cnt];
80 79 }
81 80 } else {
82 81 /* send 4bytes per one time. */
83   - payload = *(u8 *)(data0 + data_cnt) |
84   - (*(u8 *)(data0 + (data_cnt + 1))) << 8 |
85   - (*(u8 *)(data0 + (data_cnt + 2))) << 16 |
86   - (*(u8 *)(data0 + (data_cnt + 3))) << 24;
  82 + payload = data0[data_cnt] |
  83 + data0[data_cnt + 1] << 8 |
  84 + data0[data_cnt + 2] << 16 |
  85 + data0[data_cnt + 3] << 24;
87 86  
88 87 debug("count = 4 payload = %x, %x %x %x %x\n",
89 88 payload, *(u8 *)(data0 + data_cnt),
90   - *(u8 *)(data0 + (data_cnt + 1)),
91   - *(u8 *)(data0 + (data_cnt + 2)),
92   - *(u8 *)(data0 + (data_cnt + 3)));
93   -
  89 + data0[data_cnt + 1],
  90 + data0[data_cnt + 2],
  91 + data0[data_cnt + 3]);
94 92 }
95 93 exynos_mipi_dsi_wr_tx_data(dsim, payload);
96 94 }
97 95 }
98 96  
99 97 int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
100   - unsigned int data0, unsigned int data1)
  98 + const unsigned char *data0, unsigned int data1)
101 99 {
102 100 unsigned int timeout = TRY_GET_FIFO_TIMEOUT;
103 101 unsigned long delay_val, delay;
... ... @@ -136,8 +134,8 @@
136 134 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
137 135 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
138 136 debug("data0 = %x data1 = %x\n",
139   - data0, data1);
140   - exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
  137 + data0[0], data0[1]);
  138 + exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
141 139 if (check_rx_ack) {
142 140 /* process response func should be implemented */
143 141 return 0;
... ... @@ -150,7 +148,7 @@
150 148 case MIPI_DSI_COLOR_MODE_ON:
151 149 case MIPI_DSI_SHUTDOWN_PERIPHERAL:
152 150 case MIPI_DSI_TURN_ON_PERIPHERAL:
153   - exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
  151 + exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
154 152 if (check_rx_ack) {
155 153 /* process response func should be implemented. */
156 154 return 0;
... ... @@ -172,7 +170,7 @@
172 170 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
173 171 case MIPI_DSI_DCS_READ:
174 172 exynos_mipi_dsi_clear_all_interrupt(dsim);
175   - exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0, data1);
  173 + exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
176 174 /* process response func should be implemented. */
177 175 return 0;
178 176  
179 177  
180 178  
... ... @@ -183,21 +181,19 @@
183 181 case MIPI_DSI_GENERIC_LONG_WRITE:
184 182 case MIPI_DSI_DCS_LONG_WRITE:
185 183 {
186   - unsigned int data_cnt = 0, payload = 0;
  184 + unsigned int payload = 0;
187 185  
188 186 /* if data count is less then 4, then send 3bytes data. */
189 187 if (data1 < 4) {
190   - payload = *(u8 *)(data0) |
191   - *(u8 *)(data0 + 1) << 8 |
192   - *(u8 *)(data0 + 2) << 16;
  188 + payload = data0[0] |
  189 + data0[1] << 8 |
  190 + data0[2] << 16;
193 191  
194 192 exynos_mipi_dsi_wr_tx_data(dsim, payload);
195 193  
196 194 debug("count = %d payload = %x,%x %x %x\n",
197   - data1, payload,
198   - *(u8 *)(data0 + data_cnt),
199   - *(u8 *)(data0 + (data_cnt + 1)),
200   - *(u8 *)(data0 + (data_cnt + 2)));
  195 + data1, payload, data0[0],
  196 + data0[1], data0[2]);
201 197 } else {
202 198 /* in case that data count is more then 4 */
203 199 exynos_mipi_dsi_long_data_wr(dsim, data0, data1);
drivers/video/exynos_mipi_dsi_common.h
Diff comments   View file @ c15438e
... ... @@ -13,7 +13,7 @@
13 13 #define _EXYNOS_MIPI_DSI_COMMON_H
14 14  
15 15 int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
16   - unsigned int data0, unsigned int data1);
  16 + const unsigned char *data0, unsigned int data1);
17 17 int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable);
18 18 unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
19 19 unsigned int pre_divider, unsigned int main_divider,
drivers/video/exynos_mipi_dsi_lowlevel.c
Diff comments   View file @ c15438e
... ... @@ -600,7 +600,7 @@
600 600 }
601 601  
602 602 void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
603   - unsigned int di, unsigned int data0, unsigned int data1)
  603 + unsigned int di, const unsigned char data0, const unsigned char data1)
604 604 {
605 605 struct exynos_mipi_dsim *mipi_dsim =
606 606 (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
drivers/video/exynos_mipi_dsi_lowlevel.h
Diff comments   View file @ c15438e
... ... @@ -91,7 +91,7 @@
91 91 *dsim);
92 92 void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim);
93 93 void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
94   - unsigned int di, unsigned int data0, unsigned int data1);
  94 + unsigned int di, const unsigned char data0, const unsigned char data1);
95 95 void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
96 96 unsigned int tx_data);
97 97  
drivers/video/l5f31188.c
Diff comments   View file @ c15438e
  1 +/*
  2 + * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved.
  3 + * Hyungwon Hwang <human.hwang@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <asm/arch/mipi_dsim.h>
  10 +
  11 +#define SCAN_FROM_LEFT_TO_RIGHT 0
  12 +#define SCAN_FROM_RIGHT_TO_LEFT 1
  13 +#define SCAN_FROM_TOP_TO_BOTTOM 0
  14 +#define SCAN_FROM_BOTTOM_TO_TOP 1
  15 +
  16 +static void l5f31188_sleep_in(struct mipi_dsim_device *dev,
  17 + struct mipi_dsim_master_ops *ops)
  18 +{
  19 + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x10, 0x00);
  20 +}
  21 +
  22 +static void l5f31188_sleep_out(struct mipi_dsim_device *dev,
  23 + struct mipi_dsim_master_ops *ops)
  24 +{
  25 + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x11, 0x00);
  26 +}
  27 +
  28 +static void l5f31188_set_gamma(struct mipi_dsim_device *dev,
  29 + struct mipi_dsim_master_ops *ops)
  30 +{
  31 + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x26, 0x00);
  32 +}
  33 +
  34 +static void l5f31188_display_off(struct mipi_dsim_device *dev,
  35 + struct mipi_dsim_master_ops *ops)
  36 +{
  37 + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x28, 0x00);
  38 +}
  39 +
  40 +static void l5f31188_display_on(struct mipi_dsim_device *dev,
  41 + struct mipi_dsim_master_ops *ops)
  42 +{
  43 + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE, 0x29, 0x00);
  44 +}
  45 +
  46 +static void l5f31188_ctl_memory_access(struct mipi_dsim_device *dev,
  47 + struct mipi_dsim_master_ops *ops,
  48 + int h_direction, int v_direction)
  49 +{
  50 + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x36,
  51 + (((h_direction & 0x1) << 1) | (v_direction & 0x1)));
  52 +}
  53 +
  54 +static void l5f31188_set_pixel_format(struct mipi_dsim_device *dev,
  55 + struct mipi_dsim_master_ops *ops)
  56 +{
  57 + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x3A, 0x70);
  58 +}
  59 +
  60 +static void l5f31188_write_disbv(struct mipi_dsim_device *dev,
  61 + struct mipi_dsim_master_ops *ops, unsigned int brightness)
  62 +{
  63 + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x51, brightness);
  64 +}
  65 +
  66 +static void l5f31188_write_ctrld(struct mipi_dsim_device *dev,
  67 + struct mipi_dsim_master_ops *ops)
  68 +{
  69 + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x53, 0x2C);
  70 +}
  71 +
  72 +static void l5f31188_write_cabc(struct mipi_dsim_device *dev,
  73 + struct mipi_dsim_master_ops *ops,
  74 + unsigned int wm_mode)
  75 +{
  76 + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x55, wm_mode);
  77 +}
  78 +
  79 +static void l5f31188_write_cabcmb(struct mipi_dsim_device *dev,
  80 + struct mipi_dsim_master_ops *ops, unsigned int min_brightness)
  81 +{
  82 + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0x5E,
  83 + min_brightness);
  84 +}
  85 +
  86 +static void l5f31188_set_extension(struct mipi_dsim_device *dev,
  87 + struct mipi_dsim_master_ops *ops)
  88 +{
  89 + const unsigned char data_to_send[] = {
  90 + 0xB9, 0xFF, 0x83, 0x94
  91 + };
  92 +
  93 + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE,
  94 + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
  95 +}
  96 +
  97 +static void l5f31188_set_dgc_lut(struct mipi_dsim_device *dev,
  98 + struct mipi_dsim_master_ops *ops)
  99 +{
  100 + const unsigned char data_to_send[] = {
  101 + 0xC1, 0x01, 0x00, 0x04, 0x0E, 0x18, 0x1E, 0x26,
  102 + 0x2F, 0x36, 0x3E, 0x47, 0x4E, 0x56, 0x5D, 0x65,
  103 + 0x6D, 0x75, 0x7D, 0x84, 0x8C, 0x94, 0x9C, 0xA4,
  104 + 0xAD, 0xB5, 0xBD, 0xC5, 0xCC, 0xD4, 0xDE, 0xE5,
  105 + 0xEE, 0xF7, 0xFF, 0x3F, 0x9A, 0xCE, 0xD4, 0x21,
  106 + 0xA1, 0x26, 0x54, 0x00, 0x00, 0x04, 0x0E, 0x19,
  107 + 0x1F, 0x27, 0x30, 0x37, 0x40, 0x48, 0x50, 0x58,
  108 + 0x60, 0x67, 0x6F, 0x77, 0x7F, 0x87, 0x8F, 0x97,
  109 + 0x9F, 0xA7, 0xB0, 0xB8, 0xC0, 0xC8, 0xCE, 0xD8,
  110 + 0xE0, 0xE7, 0xF0, 0xF7, 0xFF, 0x3C, 0xEB, 0xFD,
  111 + 0x2F, 0x66, 0xA8, 0x2C, 0x46, 0x00, 0x00, 0x04,
  112 + 0x0E, 0x18, 0x1E, 0x26, 0x30, 0x38, 0x41, 0x4A,
  113 + 0x52, 0x5A, 0x62, 0x6B, 0x73, 0x7B, 0x83, 0x8C,
  114 + 0x94, 0x9C, 0xA5, 0xAD, 0xB6, 0xBD, 0xC5, 0xCC,
  115 + 0xD4, 0xDD, 0xE3, 0xEB, 0xF2, 0xF9, 0xFF, 0x3F,
  116 + 0xA4, 0x8A, 0x8F, 0xC7, 0x33, 0xF5, 0xE9, 0x00
  117 + };
  118 + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE,
  119 + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
  120 +}
  121 +
  122 +static void l5f31188_set_tcon(struct mipi_dsim_device *dev,
  123 + struct mipi_dsim_master_ops *ops)
  124 +{
  125 + const unsigned char data_to_send[] = {
  126 + 0xC7, 0x00, 0x20
  127 + };
  128 + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE,
  129 + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
  130 +}
  131 +
  132 +static void l5f31188_set_ptba(struct mipi_dsim_device *dev,
  133 + struct mipi_dsim_master_ops *ops)
  134 +{
  135 + const unsigned char data_to_send[] = {
  136 + 0xBF, 0x06, 0x10
  137 + };
  138 + ops->cmd_write(dev, MIPI_DSI_DCS_LONG_WRITE,
  139 + (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
  140 +}
  141 +
  142 +static void l5f31188_set_eco(struct mipi_dsim_device *dev,
  143 + struct mipi_dsim_master_ops *ops)
  144 +{
  145 + ops->cmd_write(dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xC6, 0x0C);
  146 +}
  147 +
  148 +static int l5f31188_panel_init(struct mipi_dsim_device *dev)
  149 +{
  150 + struct mipi_dsim_master_ops *ops = dev->master_ops;
  151 +
  152 + l5f31188_set_extension(dev, ops);
  153 + l5f31188_set_dgc_lut(dev, ops);
  154 +
  155 + l5f31188_set_eco(dev, ops);
  156 + l5f31188_set_tcon(dev, ops);
  157 + l5f31188_set_ptba(dev, ops);
  158 + l5f31188_set_gamma(dev, ops);
  159 + l5f31188_ctl_memory_access(dev, ops,
  160 + SCAN_FROM_LEFT_TO_RIGHT, SCAN_FROM_TOP_TO_BOTTOM);
  161 + l5f31188_set_pixel_format(dev, ops);
  162 + l5f31188_write_disbv(dev, ops, 0xFF);
  163 + l5f31188_write_ctrld(dev, ops);
  164 + l5f31188_write_cabc(dev, ops, 0x0);
  165 + l5f31188_write_cabcmb(dev, ops, 0x0);
  166 +
  167 + l5f31188_sleep_out(dev, ops);
  168 +
  169 + /* 120 msec */
  170 + udelay(120 * 1000);
  171 +
  172 + return 0;
  173 +}
  174 +
  175 +static void l5f31188_display_enable(struct mipi_dsim_device *dev)
  176 +{
  177 + struct mipi_dsim_master_ops *ops = dev->master_ops;
  178 + l5f31188_display_on(dev, ops);
  179 +}
  180 +
  181 +static struct mipi_dsim_lcd_driver l5f31188_dsim_ddi_driver = {
  182 + .name = "l5f31188",
  183 + .id = -1,
  184 +
  185 + .mipi_panel_init = l5f31188_panel_init,
  186 + .mipi_display_on = l5f31188_display_enable,
  187 +};
  188 +
  189 +void l5f31188_init(void)
  190 +{
  191 + exynos_mipi_dsi_register_lcd_driver(&l5f31188_dsim_ddi_driver);
  192 +}
drivers/video/mxsfb.c
Diff comments   View file @ c15438e
... ... @@ -15,12 +15,26 @@
15 15 #include <asm/errno.h>
16 16 #include <asm/io.h>
17 17  
  18 +#include <asm/imx-common/dma.h>
  19 +
18 20 #include "videomodes.h"
19 21  
20 22 #define PS2KHZ(ps) (1000000000UL / (ps))
21 23  
22 24 static GraphicDevice panel;
  25 +struct mxs_dma_desc desc;
23 26  
  27 +/**
  28 + * mxsfb_system_setup() - Fine-tune LCDIF configuration
  29 + *
  30 + * This function is used to adjust the LCDIF configuration. This is usually
  31 + * needed when driving the controller in System-Mode to operate an 8080 or
  32 + * 6800 connected SmartLCD.
  33 + */
  34 +__weak void mxsfb_system_setup(void)
  35 +{
  36 +}
  37 +
24 38 /*
25 39 * DENX M28EVK:
26 40 * setenv videomode
... ... @@ -75,6 +89,9 @@
75 89  
76 90 writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
77 91 &regs->hw_lcdif_ctrl1);
  92 +
  93 + mxsfb_system_setup();
  94 +
78 95 writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
79 96 &regs->hw_lcdif_transfer_count);
80 97  
81 98  
... ... @@ -102,8 +119,10 @@
102 119 /* Flush FIFO first */
103 120 writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
104 121  
  122 +#ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
105 123 /* Sync signals ON */
106 124 setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
  125 +#endif
107 126  
108 127 /* FIFO cleared */
109 128 writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
... ... @@ -161,7 +180,8 @@
161 180 panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
162 181  
163 182 /* Allocate framebuffer */
164   - fb = malloc(panel.memSize);
  183 + fb = memalign(ARCH_DMA_MINALIGN,
  184 + roundup(panel.memSize, ARCH_DMA_MINALIGN));
165 185 if (!fb) {
166 186 printf("MXSFB: Error allocating framebuffer!\n");
167 187 return NULL;
... ... @@ -176,6 +196,29 @@
176 196  
177 197 /* Start framebuffer */
178 198 mxs_lcd_init(&panel, &mode, bpp);
  199 +
  200 +#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
  201 + /*
  202 + * If the LCD runs in system mode, the LCD refresh has to be triggered
  203 + * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
  204 + * having to set this bit manually after every single change in the
  205 + * framebuffer memory, we set up specially crafted circular DMA, which
  206 + * sets the RUN bit, then waits until it gets cleared and repeats this
  207 + * infinitelly. This way, we get smooth continuous updates of the LCD.
  208 + */
  209 + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  210 +
  211 + memset(&desc, 0, sizeof(struct mxs_dma_desc));
  212 + desc.address = (dma_addr_t)&desc;
  213 + desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  214 + MXS_DMA_DESC_WAIT4END |
  215 + (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  216 + desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
  217 + desc.cmd.next = (uint32_t)&desc.cmd;
  218 +
  219 + /* Execute the DMA chain. */
  220 + mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
  221 +#endif
179 222  
180 223 return (void *)&panel;
181 224 }
drivers/video/s6e8ax0.c
Diff comments   View file @ c15438e
... ... @@ -34,11 +34,11 @@
34 34  
35 35 if (reverse) {
36 36 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
37   - (unsigned int)data_to_send_reverse,
  37 + data_to_send_reverse,
38 38 ARRAY_SIZE(data_to_send_reverse));
39 39 } else {
40 40 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
41   - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
  41 + data_to_send, ARRAY_SIZE(data_to_send));
42 42 }
43 43 }
44 44  
... ... @@ -50,8 +50,7 @@
50 50 };
51 51  
52 52 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
53   - (unsigned int)data_to_send,
54   - ARRAY_SIZE(data_to_send));
  53 + data_to_send, ARRAY_SIZE(data_to_send));
55 54 }
56 55  
57 56 static void s6e8ax0_gamma_cond(struct mipi_dsim_device *dsim_dev)
58 57  
59 58  
... ... @@ -65,15 +64,18 @@
65 64 };
66 65  
67 66 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
68   - (unsigned int)data_to_send,
69   - ARRAY_SIZE(data_to_send));
  67 + data_to_send, ARRAY_SIZE(data_to_send));
70 68 }
71 69  
72 70 static void s6e8ax0_gamma_update(struct mipi_dsim_device *dsim_dev)
73 71 {
74 72 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
  73 + static const unsigned char data_to_send[] = {
  74 + 0xf7, 0x03
  75 + };
75 76  
76   - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xf7, 0x3);
  77 + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send,
  78 + ARRAY_SIZE(data_to_send));
77 79 }
78 80  
79 81 static void s6e8ax0_etc_source_control(struct mipi_dsim_device *dsim_dev)
... ... @@ -84,8 +86,7 @@
84 86 };
85 87  
86 88 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
87   - (unsigned int)data_to_send,
88   - ARRAY_SIZE(data_to_send));
  89 + data_to_send, ARRAY_SIZE(data_to_send));
89 90 }
90 91  
91 92 static void s6e8ax0_etc_pentile_control(struct mipi_dsim_device *dsim_dev)
... ... @@ -97,8 +98,7 @@
97 98 };
98 99  
99 100 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
100   - (unsigned int)data_to_send,
101   - ARRAY_SIZE(data_to_send));
  101 + data_to_send, ARRAY_SIZE(data_to_send));
102 102 }
103 103  
104 104 static void s6e8ax0_etc_mipi_control1(struct mipi_dsim_device *dsim_dev)
... ... @@ -109,8 +109,7 @@
109 109 };
110 110  
111 111 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
112   - (unsigned int)data_to_send,
113   - ARRAY_SIZE(data_to_send));
  112 + data_to_send, ARRAY_SIZE(data_to_send));
114 113 }
115 114  
116 115 static void s6e8ax0_etc_mipi_control2(struct mipi_dsim_device *dsim_dev)
... ... @@ -121,8 +120,7 @@
121 120 };
122 121  
123 122 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
124   - (unsigned int)data_to_send,
125   - ARRAY_SIZE(data_to_send));
  123 + data_to_send, ARRAY_SIZE(data_to_send));
126 124 }
127 125  
128 126 static void s6e8ax0_etc_power_control(struct mipi_dsim_device *dsim_dev)
129 127  
130 128  
... ... @@ -133,14 +131,18 @@
133 131 };
134 132  
135 133 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
136   - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
  134 + data_to_send, ARRAY_SIZE(data_to_send));
137 135 }
138 136  
139 137 static void s6e8ax0_etc_mipi_control3(struct mipi_dsim_device *dsim_dev)
140 138 {
141 139 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
  140 + static const unsigned char data_to_send[] = {
  141 + 0xe3, 0x40
  142 + };
142 143  
143   - ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xe3, 0x40);
  144 + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE_PARAM, data_to_send,
  145 + ARRAY_SIZE(data_to_send));
144 146 }
145 147  
146 148 static void s6e8ax0_etc_mipi_control4(struct mipi_dsim_device *dsim_dev)
... ... @@ -151,7 +153,7 @@
151 153 };
152 154  
153 155 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
154   - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
  156 + data_to_send, ARRAY_SIZE(data_to_send));
155 157 }
156 158  
157 159 static void s6e8ax0_elvss_set(struct mipi_dsim_device *dsim_dev)
158 160  
159 161  
160 162  
161 163  
... ... @@ -162,24 +164,29 @@
162 164 };
163 165  
164 166 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
165   - (unsigned int)data_to_send,
166   - ARRAY_SIZE(data_to_send));
  167 + data_to_send, ARRAY_SIZE(data_to_send));
167 168 }
168 169  
169 170 static void s6e8ax0_display_on(struct mipi_dsim_device *dsim_dev)
170 171 {
171 172 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
  173 + static const unsigned char data_to_send[] = {
  174 + 0x29, 0x00
  175 + };
172 176  
173   - ops->cmd_write(dsim_dev,
174   - MIPI_DSI_DCS_SHORT_WRITE, 0x29, 0x00);
  177 + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send,
  178 + ARRAY_SIZE(data_to_send));
175 179 }
176 180  
177 181 static void s6e8ax0_sleep_out(struct mipi_dsim_device *dsim_dev)
178 182 {
179 183 struct mipi_dsim_master_ops *ops = dsim_dev->master_ops;
  184 + static const unsigned char data_to_send[] = {
  185 + 0x11, 0x00
  186 + };
180 187  
181   - ops->cmd_write(dsim_dev,
182   - MIPI_DSI_DCS_SHORT_WRITE, 0x11, 0x00);
  188 + ops->cmd_write(dsim_dev, MIPI_DSI_DCS_SHORT_WRITE, data_to_send,
  189 + ARRAY_SIZE(data_to_send));
183 190 }
184 191  
185 192 static void s6e8ax0_apply_level1_key(struct mipi_dsim_device *dsim_dev)
... ... @@ -190,7 +197,7 @@
190 197 };
191 198  
192 199 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
193   - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
  200 + data_to_send, ARRAY_SIZE(data_to_send));
194 201 }
195 202  
196 203 static void s6e8ax0_apply_mtp_key(struct mipi_dsim_device *dsim_dev)
... ... @@ -201,7 +208,7 @@
201 208 };
202 209  
203 210 ops->cmd_write(dsim_dev, MIPI_DSI_DCS_LONG_WRITE,
204   - (unsigned int)data_to_send, ARRAY_SIZE(data_to_send));
  211 + data_to_send, ARRAY_SIZE(data_to_send));
205 212 }
206 213  
207 214 static void s6e8ax0_panel_init(struct mipi_dsim_device *dsim_dev)
drivers/video/sed156x.c
Diff comments   View file @ c15438e
... ... @@ -25,7 +25,6 @@
25 25  
26 26 /* include the font data */
27 27 #include <video_font.h>
28   -#include <video_font_data.h>
29 28  
30 29 #if VIDEO_FONT_WIDTH != 8 || VIDEO_FONT_HEIGHT != 16
31 30 #error Expecting VIDEO_FONT_WIDTH == 8 && VIDEO_FONT_HEIGHT == 16
... ... @@ -54,7 +54,7 @@
54 54 (_x).vertical_blanking)
55 55 unsigned char hsync_offset;
56 56 unsigned char hsync_pulse_width;
57   - unsigned char sync_offset_pulse_width;
  57 + unsigned char vsync_offset_pulse_width;
58 58 unsigned char hsync_vsync_offset_pulse_width_hi;
59 59 #define EDID_DETAILED_TIMING_HSYNC_OFFSET(_x) \
60 60 ((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 7, 6) << 8) + \
include/video_font.h
Diff comments   View file @ c15438e
... ... @@ -8,10 +8,11 @@
8 8 #ifndef _VIDEO_FONT_
9 9 #define _VIDEO_FONT_
10 10  
11   -#define VIDEO_FONT_CHARS 256
12   -#define VIDEO_FONT_WIDTH 8
13   -#define VIDEO_FONT_HEIGHT 16
14   -#define VIDEO_FONT_SIZE (VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT)
  11 +#ifdef CONFIG_VIDEO_FONT_4X6
  12 +#include <video_font_4x6.h>
  13 +#else
  14 +#include <video_font_data.h>
  15 +#endif
15 16  
16 17 #endif /* _VIDEO_FONT_ */
include/video_font_4x6.h
Diff comments   View file @ c15438e
No preview for this file type
include/video_font_data.h
Diff comments   View file @ c15438e
No preview for this file type
... ... @@ -179,7 +179,7 @@
179 179 printf("unsigned char bmp_logo_bitmap[] = {\n");
180 180 for (i=(b->height-1)*b->width; i>=0; i-=b->width) {
181 181 for (x = 0; x < b->width; x++) {
182   - b->data[(uint16_t) i + x] = (uint8_t) fgetc (fp) \
  182 + b->data[i + x] = (uint8_t) fgetc(fp)
183 183 + DEFAULT_CMAP_SIZE;
184 184 }
185 185 }