Eric Lee / smarc-uboot

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Commit c1c4fabdc091a918e2217fd95e25c1ff2808742b

Authored by Han Xu
Committed by Ye Li
1 parent 68fbb20f0d
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-12815: mx6ul_14x14_evk: add new NAND config for i.MX6UL 14x14 EVK board 

add new NAND config for i.MX6UL 14x14 EVK board, and disable USDHC2 when
NAND enabled due to pin conflict.

Signed-off-by: Han Xu <han.xu@nxp.com>
(cherry picked from commit 81e175bcc07792fab6010761daf6576bd600edda)

Showing 2 changed files with 9 additions and 0 deletions Inline Diff

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
Diff comments   View file @ c1c4fab
1 /* 1 /*
2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <asm/arch/clock.h> 7 #include <asm/arch/clock.h>
8 #include <asm/arch/iomux.h> 8 #include <asm/arch/iomux.h>
9 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/crm_regs.h> 10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6ul_pins.h> 11 #include <asm/arch/mx6ul_pins.h>
12 #include <asm/arch/mx6-pins.h> 12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h> 13 #include <asm/arch/sys_proto.h>
14 #include <asm/gpio.h> 14 #include <asm/gpio.h>
15 #include <asm/imx-common/iomux-v3.h> 15 #include <asm/imx-common/iomux-v3.h>
16 #include <asm/imx-common/boot_mode.h> 16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/mxc_i2c.h> 17 #include <asm/imx-common/mxc_i2c.h>
18 #include <asm/io.h> 18 #include <asm/io.h>
19 #include <common.h> 19 #include <common.h>
20 #include <fsl_esdhc.h> 20 #include <fsl_esdhc.h>
21 #include <i2c.h> 21 #include <i2c.h>
22 #include <miiphy.h> 22 #include <miiphy.h>
23 #include <linux/sizes.h> 23 #include <linux/sizes.h>
24 #include <mmc.h> 24 #include <mmc.h>
25 #include <mxsfb.h> 25 #include <mxsfb.h>
26 #include <netdev.h> 26 #include <netdev.h>
27 #include <power/pmic.h> 27 #include <power/pmic.h>
28 #include <power/pfuze3000_pmic.h> 28 #include <power/pfuze3000_pmic.h>
29 #include "../common/pfuze.h" 29 #include "../common/pfuze.h"
30 #include <usb.h> 30 #include <usb.h>
31 #include <usb/ehci-fsl.h> 31 #include <usb/ehci-fsl.h>
32 #include <asm/imx-common/video.h> 32 #include <asm/imx-common/video.h>
33 33
34 #ifdef CONFIG_FSL_FASTBOOT 34 #ifdef CONFIG_FSL_FASTBOOT
35 #include <fsl_fastboot.h> 35 #include <fsl_fastboot.h>
36 #ifdef CONFIG_ANDROID_RECOVERY 36 #ifdef CONFIG_ANDROID_RECOVERY
37 #include <recovery.h> 37 #include <recovery.h>
38 #endif 38 #endif
39 #endif /*CONFIG_FSL_FASTBOOT*/ 39 #endif /*CONFIG_FSL_FASTBOOT*/
40 40
41 DECLARE_GLOBAL_DATA_PTR; 41 DECLARE_GLOBAL_DATA_PTR;
42 42
43 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 43 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
44 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 44 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
45 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 45 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46 46
47 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 47 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
48 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 48 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
49 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 49 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
50 50
51 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 51 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
52 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ 52 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
53 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 53 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
54 54
55 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 55 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
56 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 56 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
57 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 57 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
58 PAD_CTL_ODE) 58 PAD_CTL_ODE)
59 59
60 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 60 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
61 PAD_CTL_SPEED_HIGH | \ 61 PAD_CTL_SPEED_HIGH | \
62 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 62 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
63 63
64 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 64 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
65 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) 65 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
66 66
67 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 67 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
68 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) 68 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
69 69
70 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 70 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
71 71
72 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 72 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
73 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) 73 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
74 74
75 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) 75 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
76 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ 76 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
77 PAD_CTL_SRE_FAST) 77 PAD_CTL_SRE_FAST)
78 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) 78 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
79 79
80 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 80 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
81 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 81 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
82 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 82 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
83 83
84 #define SPI_PAD_CTRL (PAD_CTL_HYS | \ 84 #define SPI_PAD_CTRL (PAD_CTL_HYS | \
85 PAD_CTL_SPEED_MED | \ 85 PAD_CTL_SPEED_MED | \
86 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 86 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
87 87
88 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 88 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
89 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 89 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
90 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 90 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
91 91
92 #define IOX_SDI IMX_GPIO_NR(5, 10) 92 #define IOX_SDI IMX_GPIO_NR(5, 10)
93 #define IOX_STCP IMX_GPIO_NR(5, 7) 93 #define IOX_STCP IMX_GPIO_NR(5, 7)
94 #define IOX_SHCP IMX_GPIO_NR(5, 11) 94 #define IOX_SHCP IMX_GPIO_NR(5, 11)
95 #define IOX_OE IMX_GPIO_NR(5, 8) 95 #define IOX_OE IMX_GPIO_NR(5, 8)
96 96
97 static iomux_v3_cfg_t const iox_pads[] = { 97 static iomux_v3_cfg_t const iox_pads[] = {
98 /* IOX_SDI */ 98 /* IOX_SDI */
99 MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 99 MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
100 /* IOX_SHCP */ 100 /* IOX_SHCP */
101 MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 101 MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
102 /* IOX_STCP */ 102 /* IOX_STCP */
103 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 103 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
104 /* IOX_nOE */ 104 /* IOX_nOE */
105 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), 105 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
106 }; 106 };
107 107
108 /* 108 /*
109 * HDMI_nRST --> Q0 109 * HDMI_nRST --> Q0
110 * ENET1_nRST --> Q1 110 * ENET1_nRST --> Q1
111 * ENET2_nRST --> Q2 111 * ENET2_nRST --> Q2
112 * CAN1_2_STBY --> Q3 112 * CAN1_2_STBY --> Q3
113 * BT_nPWD --> Q4 113 * BT_nPWD --> Q4
114 * CSI_RST --> Q5 114 * CSI_RST --> Q5
115 * CSI_PWDN --> Q6 115 * CSI_PWDN --> Q6
116 * LCD_nPWREN --> Q7 116 * LCD_nPWREN --> Q7
117 */ 117 */
118 enum qn { 118 enum qn {
119 HDMI_NRST, 119 HDMI_NRST,
120 ENET1_NRST, 120 ENET1_NRST,
121 ENET2_NRST, 121 ENET2_NRST,
122 CAN1_2_STBY, 122 CAN1_2_STBY,
123 BT_NPWD, 123 BT_NPWD,
124 CSI_RST, 124 CSI_RST,
125 CSI_PWDN, 125 CSI_PWDN,
126 LCD_NPWREN, 126 LCD_NPWREN,
127 }; 127 };
128 128
129 enum qn_func { 129 enum qn_func {
130 qn_reset, 130 qn_reset,
131 qn_enable, 131 qn_enable,
132 qn_disable, 132 qn_disable,
133 }; 133 };
134 134
135 enum qn_level { 135 enum qn_level {
136 qn_low = 0, 136 qn_low = 0,
137 qn_high = 1, 137 qn_high = 1,
138 }; 138 };
139 139
140 static enum qn_level seq[3][2] = { 140 static enum qn_level seq[3][2] = {
141 {0, 1}, {1, 1}, {0, 0} 141 {0, 1}, {1, 1}, {0, 0}
142 }; 142 };
143 143
144 static enum qn_func qn_output[8] = { 144 static enum qn_func qn_output[8] = {
145 qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, 145 qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
146 qn_disable, qn_disable 146 qn_disable, qn_disable
147 }; 147 };
148 148
149 static void iox74lv_init(void) 149 static void iox74lv_init(void)
150 { 150 {
151 int i; 151 int i;
152 152
153 gpio_direction_output(IOX_OE, 0); 153 gpio_direction_output(IOX_OE, 0);
154 154
155 for (i = 7; i >= 0; i--) { 155 for (i = 7; i >= 0; i--) {
156 gpio_direction_output(IOX_SHCP, 0); 156 gpio_direction_output(IOX_SHCP, 0);
157 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 157 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
158 udelay(500); 158 udelay(500);
159 gpio_direction_output(IOX_SHCP, 1); 159 gpio_direction_output(IOX_SHCP, 1);
160 udelay(500); 160 udelay(500);
161 } 161 }
162 162
163 gpio_direction_output(IOX_STCP, 0); 163 gpio_direction_output(IOX_STCP, 0);
164 udelay(500); 164 udelay(500);
165 /* 165 /*
166 * shift register will be output to pins 166 * shift register will be output to pins
167 */ 167 */
168 gpio_direction_output(IOX_STCP, 1); 168 gpio_direction_output(IOX_STCP, 1);
169 169
170 for (i = 7; i >= 0; i--) { 170 for (i = 7; i >= 0; i--) {
171 gpio_direction_output(IOX_SHCP, 0); 171 gpio_direction_output(IOX_SHCP, 0);
172 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 172 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
173 udelay(500); 173 udelay(500);
174 gpio_direction_output(IOX_SHCP, 1); 174 gpio_direction_output(IOX_SHCP, 1);
175 udelay(500); 175 udelay(500);
176 } 176 }
177 gpio_direction_output(IOX_STCP, 0); 177 gpio_direction_output(IOX_STCP, 0);
178 udelay(500); 178 udelay(500);
179 /* 179 /*
180 * shift register will be output to pins 180 * shift register will be output to pins
181 */ 181 */
182 gpio_direction_output(IOX_STCP, 1); 182 gpio_direction_output(IOX_STCP, 1);
183 }; 183 };
184 184
185 void iox74lv_set(int index) 185 void iox74lv_set(int index)
186 { 186 {
187 int i; 187 int i;
188 188
189 for (i = 7; i >= 0; i--) { 189 for (i = 7; i >= 0; i--) {
190 gpio_direction_output(IOX_SHCP, 0); 190 gpio_direction_output(IOX_SHCP, 0);
191 191
192 if (i == index) 192 if (i == index)
193 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); 193 gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
194 else 194 else
195 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 195 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
196 udelay(500); 196 udelay(500);
197 gpio_direction_output(IOX_SHCP, 1); 197 gpio_direction_output(IOX_SHCP, 1);
198 udelay(500); 198 udelay(500);
199 } 199 }
200 200
201 gpio_direction_output(IOX_STCP, 0); 201 gpio_direction_output(IOX_STCP, 0);
202 udelay(500); 202 udelay(500);
203 /* 203 /*
204 * shift register will be output to pins 204 * shift register will be output to pins
205 */ 205 */
206 gpio_direction_output(IOX_STCP, 1); 206 gpio_direction_output(IOX_STCP, 1);
207 207
208 for (i = 7; i >= 0; i--) { 208 for (i = 7; i >= 0; i--) {
209 gpio_direction_output(IOX_SHCP, 0); 209 gpio_direction_output(IOX_SHCP, 0);
210 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); 210 gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
211 udelay(500); 211 udelay(500);
212 gpio_direction_output(IOX_SHCP, 1); 212 gpio_direction_output(IOX_SHCP, 1);
213 udelay(500); 213 udelay(500);
214 } 214 }
215 215
216 gpio_direction_output(IOX_STCP, 0); 216 gpio_direction_output(IOX_STCP, 0);
217 udelay(500); 217 udelay(500);
218 /* 218 /*
219 * shift register will be output to pins 219 * shift register will be output to pins
220 */ 220 */
221 gpio_direction_output(IOX_STCP, 1); 221 gpio_direction_output(IOX_STCP, 1);
222 }; 222 };
223 223
224 224
225 #ifdef CONFIG_SYS_I2C_MXC 225 #ifdef CONFIG_SYS_I2C_MXC
226 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 226 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
227 /* I2C1 for PMIC and EEPROM */ 227 /* I2C1 for PMIC and EEPROM */
228 static struct i2c_pads_info i2c_pad_info1 = { 228 static struct i2c_pads_info i2c_pad_info1 = {
229 .scl = { 229 .scl = {
230 .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, 230 .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
231 .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, 231 .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
232 .gp = IMX_GPIO_NR(1, 28), 232 .gp = IMX_GPIO_NR(1, 28),
233 }, 233 },
234 .sda = { 234 .sda = {
235 .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, 235 .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
236 .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, 236 .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
237 .gp = IMX_GPIO_NR(1, 29), 237 .gp = IMX_GPIO_NR(1, 29),
238 }, 238 },
239 }; 239 };
240 240
241 #ifdef CONFIG_POWER 241 #ifdef CONFIG_POWER
242 #define I2C_PMIC 0 242 #define I2C_PMIC 0
243 int power_init_board(void) 243 int power_init_board(void)
244 { 244 {
245 if (is_mx6ul_9x9_evk()) { 245 if (is_mx6ul_9x9_evk()) {
246 struct pmic *pfuze; 246 struct pmic *pfuze;
247 int ret; 247 int ret;
248 unsigned int reg, rev_id; 248 unsigned int reg, rev_id;
249 249
250 ret = power_pfuze3000_init(I2C_PMIC); 250 ret = power_pfuze3000_init(I2C_PMIC);
251 if (ret) 251 if (ret)
252 return ret; 252 return ret;
253 253
254 pfuze = pmic_get("PFUZE3000"); 254 pfuze = pmic_get("PFUZE3000");
255 ret = pmic_probe(pfuze); 255 ret = pmic_probe(pfuze);
256 if (ret) 256 if (ret)
257 return ret; 257 return ret;
258 258
259 pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg); 259 pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
260 pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); 260 pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
261 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", 261 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
262 reg, rev_id); 262 reg, rev_id);
263 263
264 /* disable Low Power Mode during standby mode */ 264 /* disable Low Power Mode during standby mode */
265 pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg); 265 pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
266 reg |= 0x1; 266 reg |= 0x1;
267 pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); 267 pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
268 268
269 /* SW1B step ramp up time from 2us to 4us/25mV */ 269 /* SW1B step ramp up time from 2us to 4us/25mV */
270 reg = 0x40; 270 reg = 0x40;
271 pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); 271 pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
272 272
273 /* SW1B mode to APS/PFM */ 273 /* SW1B mode to APS/PFM */
274 reg = 0xc; 274 reg = 0xc;
275 pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); 275 pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
276 276
277 /* SW1B standby voltage set to 0.975V */ 277 /* SW1B standby voltage set to 0.975V */
278 reg = 0xb; 278 reg = 0xb;
279 pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); 279 pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
280 } 280 }
281 281
282 return 0; 282 return 0;
283 } 283 }
284 284
285 #ifdef CONFIG_LDO_BYPASS_CHECK 285 #ifdef CONFIG_LDO_BYPASS_CHECK
286 void ldo_mode_set(int ldo_bypass) 286 void ldo_mode_set(int ldo_bypass)
287 { 287 {
288 unsigned int value; 288 unsigned int value;
289 u32 vddarm; 289 u32 vddarm;
290 290
291 struct pmic *p = pmic_get("PFUZE3000"); 291 struct pmic *p = pmic_get("PFUZE3000");
292 292
293 if (!p) { 293 if (!p) {
294 printf("No PMIC found!\n"); 294 printf("No PMIC found!\n");
295 return; 295 return;
296 } 296 }
297 297
298 /* switch to ldo_bypass mode */ 298 /* switch to ldo_bypass mode */
299 if (ldo_bypass) { 299 if (ldo_bypass) {
300 prep_anatop_bypass(); 300 prep_anatop_bypass();
301 /* decrease VDDARM to 1.275V */ 301 /* decrease VDDARM to 1.275V */
302 pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value); 302 pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value);
303 value &= ~0x1f; 303 value &= ~0x1f;
304 value |= PFUZE3000_SW1AB_SETP(1275); 304 value |= PFUZE3000_SW1AB_SETP(1275);
305 pmic_reg_write(p, PFUZE3000_SW1BVOLT, value); 305 pmic_reg_write(p, PFUZE3000_SW1BVOLT, value);
306 306
307 set_anatop_bypass(1); 307 set_anatop_bypass(1);
308 vddarm = PFUZE3000_SW1AB_SETP(1175); 308 vddarm = PFUZE3000_SW1AB_SETP(1175);
309 309
310 pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value); 310 pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value);
311 value &= ~0x1f; 311 value &= ~0x1f;
312 value |= vddarm; 312 value |= vddarm;
313 pmic_reg_write(p, PFUZE3000_SW1BVOLT, value); 313 pmic_reg_write(p, PFUZE3000_SW1BVOLT, value);
314 314
315 finish_anatop_bypass(); 315 finish_anatop_bypass();
316 316
317 printf("switch to ldo_bypass mode!\n"); 317 printf("switch to ldo_bypass mode!\n");
318 } 318 }
319 } 319 }
320 #endif 320 #endif
321 #endif 321 #endif
322 #endif 322 #endif
323 323
324 int dram_init(void) 324 int dram_init(void)
325 { 325 {
326 gd->ram_size = imx_ddr_size(); 326 gd->ram_size = imx_ddr_size();
327 327
328 return 0; 328 return 0;
329 } 329 }
330 330
331 static iomux_v3_cfg_t const uart1_pads[] = { 331 static iomux_v3_cfg_t const uart1_pads[] = {
332 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 332 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
333 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 333 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
334 }; 334 };
335 335
336 static iomux_v3_cfg_t const usdhc1_pads[] = { 336 static iomux_v3_cfg_t const usdhc1_pads[] = {
337 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 337 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
338 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 338 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
339 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 339 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
340 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 340 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
341 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 341 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
342 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 342 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
343 343
344 /* VSELECT */ 344 /* VSELECT */
345 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), 345 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
346 /* CD */ 346 /* CD */
347 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 347 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
348 /* RST_B */ 348 /* RST_B */
349 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 349 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
350 }; 350 };
351 351
352 /* 352 /*
353 * mx6ul_14x14_evk board default supports sd card. If want to use 353 * mx6ul_14x14_evk board default supports sd card. If want to use
354 * EMMC, need to do board rework for sd2. 354 * EMMC, need to do board rework for sd2.
355 * Introduce CONFIG_MX6UL_EVK_EMMC_REWORK, if sd2 reworked to support 355 * Introduce CONFIG_MX6UL_EVK_EMMC_REWORK, if sd2 reworked to support
356 * emmc, need to define this macro. 356 * emmc, need to define this macro.
357 */ 357 */
358 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK) 358 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK)
359 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { 359 static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
360 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 360 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
361 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 361 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
362 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 362 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
363 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 363 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
364 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 364 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
365 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 365 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
366 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 366 MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
367 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 367 MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
368 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 368 MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
369 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 369 MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
370 370
371 /* 371 /*
372 * RST_B 372 * RST_B
373 */ 373 */
374 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), 374 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
375 }; 375 };
376 #else 376 #else
377 static iomux_v3_cfg_t const usdhc2_pads[] = { 377 static iomux_v3_cfg_t const usdhc2_pads[] = {
378 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 378 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
379 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 379 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
380 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 380 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
381 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 381 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
382 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 382 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
383 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 383 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
384 }; 384 };
385 385
386 static iomux_v3_cfg_t const usdhc2_cd_pads[] = { 386 static iomux_v3_cfg_t const usdhc2_cd_pads[] = {
387 /* 387 /*
388 * The evk board uses DAT3 to detect CD card plugin, 388 * The evk board uses DAT3 to detect CD card plugin,
389 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. 389 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
390 */ 390 */
391 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), 391 MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
392 }; 392 };
393 393
394 static iomux_v3_cfg_t const usdhc2_dat3_pads[] = { 394 static iomux_v3_cfg_t const usdhc2_dat3_pads[] = {
395 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | 395 MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
396 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL), 396 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
397 }; 397 };
398 #endif 398 #endif
399 399
400 static void setup_iomux_uart(void) 400 static void setup_iomux_uart(void)
401 { 401 {
402 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 402 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
403 } 403 }
404 404
405 #ifdef CONFIG_FSL_QSPI 405 #ifdef CONFIG_FSL_QSPI
406 406
407 #define QSPI_PAD_CTRL1 \ 407 #define QSPI_PAD_CTRL1 \
408 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ 408 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
409 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) 409 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
410 410
411 static iomux_v3_cfg_t const quadspi_pads[] = { 411 static iomux_v3_cfg_t const quadspi_pads[] = {
412 MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 412 MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
413 MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 413 MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
414 MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 414 MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
415 MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 415 MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
416 MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 416 MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
417 MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), 417 MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
418 }; 418 };
419 419
420 static int board_qspi_init(void) 420 static int board_qspi_init(void)
421 { 421 {
422 /* Set the iomux */ 422 /* Set the iomux */
423 imx_iomux_v3_setup_multiple_pads(quadspi_pads, 423 imx_iomux_v3_setup_multiple_pads(quadspi_pads,
424 ARRAY_SIZE(quadspi_pads)); 424 ARRAY_SIZE(quadspi_pads));
425 /* Set the clock */ 425 /* Set the clock */
426 enable_qspi_clk(0); 426 enable_qspi_clk(0);
427 427
428 return 0; 428 return 0;
429 } 429 }
430 #endif 430 #endif
431 431
432 #ifdef CONFIG_FSL_ESDHC 432 #ifdef CONFIG_FSL_ESDHC
433 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 433 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
434 {USDHC1_BASE_ADDR, 0, 4}, 434 {USDHC1_BASE_ADDR, 0, 4},
435 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK) 435 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK)
436 {USDHC2_BASE_ADDR, 0, 8}, 436 {USDHC2_BASE_ADDR, 0, 8},
437 #else 437 #else
438 {USDHC2_BASE_ADDR, 0, 4}, 438 {USDHC2_BASE_ADDR, 0, 4},
439 #endif 439 #endif
440 }; 440 };
441 441
442 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) 442 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
443 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) 443 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
444 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5) 444 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
445 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) 445 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
446 446
447 int board_mmc_get_env_dev(int devno) 447 int board_mmc_get_env_dev(int devno)
448 { 448 {
449 if (devno == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR)) 449 if (devno == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
450 devno = 0; 450 devno = 0;
451 451
452 return devno; 452 return devno;
453 } 453 }
454 454
455 int mmc_map_to_kernel_blk(int devno) 455 int mmc_map_to_kernel_blk(int devno)
456 { 456 {
457 if (devno == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR)) 457 if (devno == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
458 devno = 1; 458 devno = 1;
459 459
460 return devno; 460 return devno;
461 } 461 }
462 462
463 int board_mmc_getcd(struct mmc *mmc) 463 int board_mmc_getcd(struct mmc *mmc)
464 { 464 {
465 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 465 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
466 int ret = 0; 466 int ret = 0;
467 467
468 switch (cfg->esdhc_base) { 468 switch (cfg->esdhc_base) {
469 case USDHC1_BASE_ADDR: 469 case USDHC1_BASE_ADDR:
470 ret = !gpio_get_value(USDHC1_CD_GPIO); 470 ret = !gpio_get_value(USDHC1_CD_GPIO);
471 break; 471 break;
472 case USDHC2_BASE_ADDR: 472 case USDHC2_BASE_ADDR:
473 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK) 473 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK)
474 ret = 1; 474 ret = 1;
475 #else 475 #else
476 imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads, 476 imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads,
477 ARRAY_SIZE(usdhc2_cd_pads)); 477 ARRAY_SIZE(usdhc2_cd_pads));
478 gpio_direction_input(USDHC2_CD_GPIO); 478 gpio_direction_input(USDHC2_CD_GPIO);
479 479
480 /* 480 /*
481 * Since it is the DAT3 pin, this pin is pulled to 481 * Since it is the DAT3 pin, this pin is pulled to
482 * low voltage if no card 482 * low voltage if no card
483 */ 483 */
484 ret = gpio_get_value(USDHC2_CD_GPIO); 484 ret = gpio_get_value(USDHC2_CD_GPIO);
485 485
486 imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads, 486 imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads,
487 ARRAY_SIZE(usdhc2_dat3_pads)); 487 ARRAY_SIZE(usdhc2_dat3_pads));
488 #endif 488 #endif
489 break; 489 break;
490 } 490 }
491 491
492 return ret; 492 return ret;
493 } 493 }
494 494
495 int board_mmc_init(bd_t *bis) 495 int board_mmc_init(bd_t *bis)
496 { 496 {
497 #ifdef CONFIG_SPL_BUILD 497 #ifdef CONFIG_SPL_BUILD
498 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK) 498 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK)
499 imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads, 499 imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
500 ARRAY_SIZE(usdhc2_emmc_pads)); 500 ARRAY_SIZE(usdhc2_emmc_pads));
501 #else 501 #else
502 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 502 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
503 #endif 503 #endif
504 gpio_direction_output(USDHC2_PWR_GPIO, 0); 504 gpio_direction_output(USDHC2_PWR_GPIO, 0);
505 udelay(500); 505 udelay(500);
506 gpio_direction_output(USDHC2_PWR_GPIO, 1); 506 gpio_direction_output(USDHC2_PWR_GPIO, 1);
507 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 507 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
508 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); 508 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
509 #else 509 #else
510 int i, ret; 510 int i, ret;
511 511
512 /* 512 /*
513 * According to the board_mmc_init() the following map is done: 513 * According to the board_mmc_init() the following map is done:
514 * (U-Boot device node) (Physical Port) 514 * (U-Boot device node) (Physical Port)
515 * mmc0 USDHC1 515 * mmc0 USDHC1
516 * mmc1 USDHC2 516 * mmc1 USDHC2
517 */ 517 */
518 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 518 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
519 switch (i) { 519 switch (i) {
520 case 0: 520 case 0:
521 imx_iomux_v3_setup_multiple_pads( 521 imx_iomux_v3_setup_multiple_pads(
522 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 522 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
523 gpio_direction_input(USDHC1_CD_GPIO); 523 gpio_direction_input(USDHC1_CD_GPIO);
524 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 524 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
525 525
526 gpio_direction_output(USDHC1_PWR_GPIO, 0); 526 gpio_direction_output(USDHC1_PWR_GPIO, 0);
527 udelay(500); 527 udelay(500);
528 gpio_direction_output(USDHC1_PWR_GPIO, 1); 528 gpio_direction_output(USDHC1_PWR_GPIO, 1);
529 break; 529 break;
530 case 1: 530 case 1:
531 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK) 531 #if defined(CONFIG_MX6UL_EVK_EMMC_REWORK)
532 imx_iomux_v3_setup_multiple_pads( 532 imx_iomux_v3_setup_multiple_pads(
533 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); 533 usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
534 #else 534 #else
535 #ifndef CONFIG_SYS_USE_NAND
535 imx_iomux_v3_setup_multiple_pads( 536 imx_iomux_v3_setup_multiple_pads(
536 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 537 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
538 #endif
537 #endif 539 #endif
538 gpio_direction_output(USDHC2_PWR_GPIO, 0); 540 gpio_direction_output(USDHC2_PWR_GPIO, 0);
539 udelay(500); 541 udelay(500);
540 gpio_direction_output(USDHC2_PWR_GPIO, 1); 542 gpio_direction_output(USDHC2_PWR_GPIO, 1);
541 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 543 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
542 break; 544 break;
543 default: 545 default:
544 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); 546 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
545 return -EINVAL; 547 return -EINVAL;
546 } 548 }
547 549
548 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 550 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
549 if (ret) { 551 if (ret) {
550 printf("Warning: failed to initialize mmc dev %d\n", i); 552 printf("Warning: failed to initialize mmc dev %d\n", i);
551 } 553 }
552 } 554 }
553 #endif 555 #endif
554 return 0; 556 return 0;
555 } 557 }
556 #endif 558 #endif
557 559
558 #ifdef CONFIG_USB_EHCI_MX6 560 #ifdef CONFIG_USB_EHCI_MX6
559 #define USB_OTHERREGS_OFFSET 0x800 561 #define USB_OTHERREGS_OFFSET 0x800
560 #define UCTRL_PWR_POL (1 << 9) 562 #define UCTRL_PWR_POL (1 << 9)
561 563
562 static iomux_v3_cfg_t const usb_otg_pads[] = { 564 static iomux_v3_cfg_t const usb_otg_pads[] = {
563 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), 565 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
564 }; 566 };
565 567
566 /* At default the 3v3 enables the MIC2026 for VBUS power */ 568 /* At default the 3v3 enables the MIC2026 for VBUS power */
567 static void setup_usb(void) 569 static void setup_usb(void)
568 { 570 {
569 imx_iomux_v3_setup_multiple_pads(usb_otg_pads, 571 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
570 ARRAY_SIZE(usb_otg_pads)); 572 ARRAY_SIZE(usb_otg_pads));
571 } 573 }
572 574
573 int board_usb_phy_mode(int port) 575 int board_usb_phy_mode(int port)
574 { 576 {
575 if (port == 1) 577 if (port == 1)
576 return USB_INIT_HOST; 578 return USB_INIT_HOST;
577 else 579 else
578 return usb_phy_mode(port); 580 return usb_phy_mode(port);
579 } 581 }
580 582
581 int board_ehci_hcd_init(int port) 583 int board_ehci_hcd_init(int port)
582 { 584 {
583 u32 *usbnc_usb_ctrl; 585 u32 *usbnc_usb_ctrl;
584 586
585 if (port > 1) 587 if (port > 1)
586 return -EINVAL; 588 return -EINVAL;
587 589
588 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 590 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
589 port * 4); 591 port * 4);
590 592
591 /* Set Power polarity */ 593 /* Set Power polarity */
592 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 594 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
593 595
594 return 0; 596 return 0;
595 } 597 }
596 #endif 598 #endif
597 599
598 #ifdef CONFIG_NAND_MXS 600 #ifdef CONFIG_NAND_MXS
599 static iomux_v3_cfg_t const nand_pads[] = { 601 static iomux_v3_cfg_t const nand_pads[] = {
600 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 602 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
601 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 603 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
602 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 604 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
603 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 605 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
604 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 606 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
605 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 607 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
606 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 608 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
607 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 609 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
608 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 610 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
609 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 611 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
610 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 612 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
611 MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 613 MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
612 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 614 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
613 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 615 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
614 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 616 MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
615 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 617 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
616 MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), 618 MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
617 }; 619 };
618 620
619 static void setup_gpmi_nand(void) 621 static void setup_gpmi_nand(void)
620 { 622 {
621 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 623 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
622 624
623 /* config gpmi nand iomux */ 625 /* config gpmi nand iomux */
624 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); 626 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
625 627
626 setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | 628 setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
627 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); 629 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
628 630
629 /* enable apbh clock gating */ 631 /* enable apbh clock gating */
630 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 632 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
631 } 633 }
632 #endif 634 #endif
633 635
634 #ifdef CONFIG_FEC_MXC 636 #ifdef CONFIG_FEC_MXC
635 /* 637 /*
636 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only 638 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
637 * be used for ENET1 or ENET2, cannot be used for both. 639 * be used for ENET1 or ENET2, cannot be used for both.
638 */ 640 */
639 static iomux_v3_cfg_t const fec1_pads[] = { 641 static iomux_v3_cfg_t const fec1_pads[] = {
640 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 642 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
641 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 643 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
642 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 644 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
643 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 645 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
644 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 646 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
645 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 647 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
646 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 648 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
647 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 649 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
648 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 650 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
649 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 651 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
650 }; 652 };
651 653
652 static iomux_v3_cfg_t const fec2_pads[] = { 654 static iomux_v3_cfg_t const fec2_pads[] = {
653 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 655 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
654 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 656 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
655 657
656 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 658 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
657 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 659 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
658 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 660 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
659 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 661 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
660 662
661 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 663 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
662 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 664 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
663 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 665 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
664 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 666 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
665 }; 667 };
666 668
667 static void setup_iomux_fec(int fec_id) 669 static void setup_iomux_fec(int fec_id)
668 { 670 {
669 if (fec_id == 0) 671 if (fec_id == 0)
670 imx_iomux_v3_setup_multiple_pads(fec1_pads, 672 imx_iomux_v3_setup_multiple_pads(fec1_pads,
671 ARRAY_SIZE(fec1_pads)); 673 ARRAY_SIZE(fec1_pads));
672 else 674 else
673 imx_iomux_v3_setup_multiple_pads(fec2_pads, 675 imx_iomux_v3_setup_multiple_pads(fec2_pads,
674 ARRAY_SIZE(fec2_pads)); 676 ARRAY_SIZE(fec2_pads));
675 } 677 }
676 678
677 int board_eth_init(bd_t *bis) 679 int board_eth_init(bd_t *bis)
678 { 680 {
679 setup_iomux_fec(CONFIG_FEC_ENET_DEV); 681 setup_iomux_fec(CONFIG_FEC_ENET_DEV);
680 682
681 return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, 683 return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
682 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 684 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
683 } 685 }
684 686
685 static int setup_fec(int fec_id) 687 static int setup_fec(int fec_id)
686 { 688 {
687 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 689 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
688 int ret; 690 int ret;
689 691
690 if (fec_id == 0) { 692 if (fec_id == 0) {
691 if (check_module_fused(MX6_MODULE_ENET1)) 693 if (check_module_fused(MX6_MODULE_ENET1))
692 return -1; 694 return -1;
693 695
694 /* 696 /*
695 * Use 50M anatop loopback REF_CLK1 for ENET1, 697 * Use 50M anatop loopback REF_CLK1 for ENET1,
696 * clear gpr1[13], set gpr1[17]. 698 * clear gpr1[13], set gpr1[17].
697 */ 699 */
698 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 700 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
699 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); 701 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
700 } else { 702 } else {
701 if (check_module_fused(MX6_MODULE_ENET2)) 703 if (check_module_fused(MX6_MODULE_ENET2))
702 return -1; 704 return -1;
703 705
704 /* 706 /*
705 * Use 50M anatop loopback REF_CLK2 for ENET2, 707 * Use 50M anatop loopback REF_CLK2 for ENET2,
706 * clear gpr1[14], set gpr1[18]. 708 * clear gpr1[14], set gpr1[18].
707 */ 709 */
708 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 710 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
709 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); 711 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
710 } 712 }
711 713
712 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); 714 ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
713 if (ret) 715 if (ret)
714 return ret; 716 return ret;
715 717
716 enable_enet_clk(1); 718 enable_enet_clk(1);
717 719
718 return 0; 720 return 0;
719 } 721 }
720 722
721 int board_phy_config(struct phy_device *phydev) 723 int board_phy_config(struct phy_device *phydev)
722 { 724 {
723 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); 725 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
724 726
725 if (phydev->drv->config) 727 if (phydev->drv->config)
726 phydev->drv->config(phydev); 728 phydev->drv->config(phydev);
727 729
728 return 0; 730 return 0;
729 } 731 }
730 #endif 732 #endif
731 733
732 #ifdef CONFIG_VIDEO_MXS 734 #ifdef CONFIG_VIDEO_MXS
733 static iomux_v3_cfg_t const lcd_pads[] = { 735 static iomux_v3_cfg_t const lcd_pads[] = {
734 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 736 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
735 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 737 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
736 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 738 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
737 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 739 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
738 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), 740 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
739 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), 741 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
740 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), 742 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
741 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), 743 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
742 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), 744 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
743 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), 745 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
744 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), 746 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
745 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), 747 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
746 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), 748 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
747 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), 749 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
748 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 750 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
749 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 751 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
750 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 752 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
751 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 753 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
752 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 754 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
753 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 755 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
754 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 756 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
755 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 757 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
756 MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), 758 MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
757 MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), 759 MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
758 MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), 760 MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
759 MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), 761 MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
760 MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), 762 MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
761 MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), 763 MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
762 764
763 /* LCD_RST */ 765 /* LCD_RST */
764 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 766 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
765 767
766 /* Use GPIO for Brightness adjustment, duty cycle = period. */ 768 /* Use GPIO for Brightness adjustment, duty cycle = period. */
767 MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), 769 MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
768 }; 770 };
769 771
770 void do_enable_parallel_lcd(struct display_info_t const *dev) 772 void do_enable_parallel_lcd(struct display_info_t const *dev)
771 { 773 {
772 enable_lcdif_clock(dev->bus); 774 enable_lcdif_clock(dev->bus);
773 775
774 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 776 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
775 777
776 /* Reset the LCD */ 778 /* Reset the LCD */
777 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); 779 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
778 udelay(500); 780 udelay(500);
779 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); 781 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
780 782
781 /* Set Brightness to high */ 783 /* Set Brightness to high */
782 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); 784 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
783 } 785 }
784 786
785 struct display_info_t const displays[] = {{ 787 struct display_info_t const displays[] = {{
786 .bus = MX6UL_LCDIF1_BASE_ADDR, 788 .bus = MX6UL_LCDIF1_BASE_ADDR,
787 .addr = 0, 789 .addr = 0,
788 .pixfmt = 24, 790 .pixfmt = 24,
789 .detect = NULL, 791 .detect = NULL,
790 .enable = do_enable_parallel_lcd, 792 .enable = do_enable_parallel_lcd,
791 .mode = { 793 .mode = {
792 .name = "TFT43AB", 794 .name = "TFT43AB",
793 .xres = 480, 795 .xres = 480,
794 .yres = 272, 796 .yres = 272,
795 .pixclock = 108695, 797 .pixclock = 108695,
796 .left_margin = 8, 798 .left_margin = 8,
797 .right_margin = 4, 799 .right_margin = 4,
798 .upper_margin = 2, 800 .upper_margin = 2,
799 .lower_margin = 4, 801 .lower_margin = 4,
800 .hsync_len = 41, 802 .hsync_len = 41,
801 .vsync_len = 10, 803 .vsync_len = 10,
802 .sync = 0, 804 .sync = 0,
803 .vmode = FB_VMODE_NONINTERLACED 805 .vmode = FB_VMODE_NONINTERLACED
804 } } }; 806 } } };
805 size_t display_count = ARRAY_SIZE(displays); 807 size_t display_count = ARRAY_SIZE(displays);
806 #endif 808 #endif
807 809
808 int board_early_init_f(void) 810 int board_early_init_f(void)
809 { 811 {
810 setup_iomux_uart(); 812 setup_iomux_uart();
811 813
812 return 0; 814 return 0;
813 } 815 }
814 816
815 int board_init(void) 817 int board_init(void)
816 { 818 {
817 /* Address of boot parameters */ 819 /* Address of boot parameters */
818 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 820 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
819 821
820 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); 822 imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
821 823
822 iox74lv_init(); 824 iox74lv_init();
823 825
824 #ifdef CONFIG_SYS_I2C_MXC 826 #ifdef CONFIG_SYS_I2C_MXC
825 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 827 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
826 #endif 828 #endif
827 829
828 #ifdef CONFIG_FEC_MXC 830 #ifdef CONFIG_FEC_MXC
829 setup_fec(CONFIG_FEC_ENET_DEV); 831 setup_fec(CONFIG_FEC_ENET_DEV);
830 #endif 832 #endif
831 833
832 #ifdef CONFIG_USB_EHCI_MX6 834 #ifdef CONFIG_USB_EHCI_MX6
833 setup_usb(); 835 setup_usb();
834 #endif 836 #endif
835 837
836 #ifdef CONFIG_FSL_QSPI 838 #ifdef CONFIG_FSL_QSPI
837 board_qspi_init(); 839 board_qspi_init();
838 #endif 840 #endif
839 841
840 #ifdef CONFIG_NAND_MXS 842 #ifdef CONFIG_NAND_MXS
841 setup_gpmi_nand(); 843 setup_gpmi_nand();
842 #endif 844 #endif
843 845
844 return 0; 846 return 0;
845 } 847 }
846 848
847 #ifdef CONFIG_CMD_BMODE 849 #ifdef CONFIG_CMD_BMODE
848 static const struct boot_mode board_boot_modes[] = { 850 static const struct boot_mode board_boot_modes[] = {
849 /* 4 bit bus width */ 851 /* 4 bit bus width */
850 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, 852 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
851 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, 853 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
852 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, 854 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
853 {NULL, 0}, 855 {NULL, 0},
854 }; 856 };
855 #endif 857 #endif
856 858
857 int board_late_init(void) 859 int board_late_init(void)
858 { 860 {
859 #ifdef CONFIG_CMD_BMODE 861 #ifdef CONFIG_CMD_BMODE
860 add_board_boot_modes(board_boot_modes); 862 add_board_boot_modes(board_boot_modes);
861 #endif 863 #endif
862 864
863 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 865 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
864 setenv("board_name", "EVK"); 866 setenv("board_name", "EVK");
865 867
866 if (is_mx6ul_9x9_evk()) 868 if (is_mx6ul_9x9_evk())
867 setenv("board_rev", "9X9"); 869 setenv("board_rev", "9X9");
868 else 870 else
869 setenv("board_rev", "14X14"); 871 setenv("board_rev", "14X14");
870 #endif 872 #endif
871 873
872 #ifdef CONFIG_ENV_IS_IN_MMC 874 #ifdef CONFIG_ENV_IS_IN_MMC
873 board_late_mmc_env_init(); 875 board_late_mmc_env_init();
874 #endif 876 #endif
875 877
876 set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); 878 set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
877 879
878 return 0; 880 return 0;
879 } 881 }
880 882
881 int checkboard(void) 883 int checkboard(void)
882 { 884 {
883 if (is_mx6ul_9x9_evk()) 885 if (is_mx6ul_9x9_evk())
884 puts("Board: MX6UL 9x9 EVK\n"); 886 puts("Board: MX6UL 9x9 EVK\n");
885 else 887 else
886 puts("Board: MX6UL 14x14 EVK\n"); 888 puts("Board: MX6UL 14x14 EVK\n");
887 889
888 return 0; 890 return 0;
889 } 891 }
890 892
891 #ifdef CONFIG_FSL_FASTBOOT 893 #ifdef CONFIG_FSL_FASTBOOT
892 void board_fastboot_setup(void) 894 void board_fastboot_setup(void)
893 { 895 {
894 switch (get_boot_device()) { 896 switch (get_boot_device()) {
895 #if defined(CONFIG_FASTBOOT_STORAGE_MMC) 897 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
896 case SD1_BOOT: 898 case SD1_BOOT:
897 case MMC1_BOOT: 899 case MMC1_BOOT:
898 if (!getenv("fastboot_dev")) 900 if (!getenv("fastboot_dev"))
899 setenv("fastboot_dev", "mmc0"); 901 setenv("fastboot_dev", "mmc0");
900 if (!getenv("bootcmd")) 902 if (!getenv("bootcmd"))
901 setenv("bootcmd", "boota mmc0"); 903 setenv("bootcmd", "boota mmc0");
902 break; 904 break;
903 case SD2_BOOT: 905 case SD2_BOOT:
904 case MMC2_BOOT: 906 case MMC2_BOOT:
905 if (!getenv("fastboot_dev")) 907 if (!getenv("fastboot_dev"))
906 setenv("fastboot_dev", "mmc1"); 908 setenv("fastboot_dev", "mmc1");
907 if (!getenv("bootcmd")) 909 if (!getenv("bootcmd"))
908 setenv("bootcmd", "boota mmc1"); 910 setenv("bootcmd", "boota mmc1");
909 break; 911 break;
910 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ 912 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
911 #if defined(CONFIG_FASTBOOT_STORAGE_NAND) 913 #if defined(CONFIG_FASTBOOT_STORAGE_NAND)
912 case NAND_BOOT: 914 case NAND_BOOT:
913 if (!getenv("fastboot_dev")) 915 if (!getenv("fastboot_dev"))
914 setenv("fastboot_dev", "nand"); 916 setenv("fastboot_dev", "nand");
915 if (!getenv("fbparts")) 917 if (!getenv("fbparts"))
916 setenv("fbparts", ANDROID_FASTBOOT_NAND_PARTS); 918 setenv("fbparts", ANDROID_FASTBOOT_NAND_PARTS);
917 if (!getenv("bootcmd")) 919 if (!getenv("bootcmd"))
918 setenv("bootcmd", 920 setenv("bootcmd",
919 "nand read ${loadaddr} ${boot_nand_offset} " 921 "nand read ${loadaddr} ${boot_nand_offset} "
920 "${boot_nand_size};boota ${loadaddr}"); 922 "${boot_nand_size};boota ${loadaddr}");
921 break; 923 break;
922 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/ 924 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
923 925
924 default: 926 default:
925 printf("unsupported boot devices\n"); 927 printf("unsupported boot devices\n");
926 break; 928 break;
927 } 929 }
928 } 930 }
929 931
930 #ifdef CONFIG_ANDROID_RECOVERY 932 #ifdef CONFIG_ANDROID_RECOVERY
931 int check_recovery_cmd_file(void) 933 int check_recovery_cmd_file(void)
932 { 934 {
933 int recovery_mode = 0; 935 int recovery_mode = 0;
934 936
935 recovery_mode = recovery_check_and_clean_flag(); 937 recovery_mode = recovery_check_and_clean_flag();
936 938
937 return recovery_mode; 939 return recovery_mode;
938 } 940 }
939 941
940 void board_recovery_setup(void) 942 void board_recovery_setup(void)
941 { 943 {
942 int bootdev = get_boot_device(); 944 int bootdev = get_boot_device();
943 945
944 switch (bootdev) { 946 switch (bootdev) {
945 #if defined(CONFIG_FASTBOOT_STORAGE_MMC) 947 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
946 case SD1_BOOT: 948 case SD1_BOOT:
947 case MMC1_BOOT: 949 case MMC1_BOOT:
948 if (!getenv("bootcmd_android_recovery")) 950 if (!getenv("bootcmd_android_recovery"))
949 setenv("bootcmd_android_recovery", "boota mmc0 recovery"); 951 setenv("bootcmd_android_recovery", "boota mmc0 recovery");
950 break; 952 break;
951 case SD2_BOOT: 953 case SD2_BOOT:
952 case MMC2_BOOT: 954 case MMC2_BOOT:
953 if (!getenv("bootcmd_android_recovery")) 955 if (!getenv("bootcmd_android_recovery"))
954 setenv("bootcmd_android_recovery", "boota mmc1 recovery"); 956 setenv("bootcmd_android_recovery", "boota mmc1 recovery");
955 break; 957 break;
956 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ 958 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
957 #if defined(CONFIG_FASTBOOT_STORAGE_NAND) 959 #if defined(CONFIG_FASTBOOT_STORAGE_NAND)
958 case NAND_BOOT: 960 case NAND_BOOT:
959 if (!getenv("bootcmd_android_recovery")) 961 if (!getenv("bootcmd_android_recovery"))
960 setenv("bootcmd_android_recovery", 962 setenv("bootcmd_android_recovery",
961 "nand read ${loadaddr} ${recovery_nand_offset} " 963 "nand read ${loadaddr} ${recovery_nand_offset} "
962 "${recovery_nand_size};boota ${loadaddr}"); 964 "${recovery_nand_size};boota ${loadaddr}");
963 break; 965 break;
964 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/ 966 #endif /*CONFIG_FASTBOOT_STORAGE_NAND*/
965 967
966 default: 968 default:
967 printf("Unsupported bootup device for recovery: dev: %d\n", 969 printf("Unsupported bootup device for recovery: dev: %d\n",
968 bootdev); 970 bootdev);
969 return; 971 return;
970 } 972 }
971 973
972 printf("setup env for recovery..\n"); 974 printf("setup env for recovery..\n");
973 setenv("bootcmd", "run bootcmd_android_recovery"); 975 setenv("bootcmd", "run bootcmd_android_recovery");
974 } 976 }
975 #endif /*CONFIG_ANDROID_RECOVERY*/ 977 #endif /*CONFIG_ANDROID_RECOVERY*/
976 978
977 #endif /*CONFIG_FSL_FASTBOOT*/ 979 #endif /*CONFIG_FSL_FASTBOOT*/
978 980
979 #ifdef CONFIG_SPL_BUILD 981 #ifdef CONFIG_SPL_BUILD
980 #include <libfdt.h> 982 #include <libfdt.h>
981 #include <spl.h> 983 #include <spl.h>
982 #include <asm/arch/mx6-ddr.h> 984 #include <asm/arch/mx6-ddr.h>
983 985
984 986
985 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 987 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
986 .grp_addds = 0x00000030, 988 .grp_addds = 0x00000030,
987 .grp_ddrmode_ctl = 0x00020000, 989 .grp_ddrmode_ctl = 0x00020000,
988 .grp_b0ds = 0x00000030, 990 .grp_b0ds = 0x00000030,
989 .grp_ctlds = 0x00000030, 991 .grp_ctlds = 0x00000030,
990 .grp_b1ds = 0x00000030, 992 .grp_b1ds = 0x00000030,
991 .grp_ddrpke = 0x00000000, 993 .grp_ddrpke = 0x00000000,
992 .grp_ddrmode = 0x00020000, 994 .grp_ddrmode = 0x00020000,
993 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK 995 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
994 .grp_ddr_type = 0x00080000, 996 .grp_ddr_type = 0x00080000,
995 #else 997 #else
996 .grp_ddr_type = 0x000c0000, 998 .grp_ddr_type = 0x000c0000,
997 #endif 999 #endif
998 }; 1000 };
999 1001
1000 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK 1002 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
1001 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 1003 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
1002 .dram_dqm0 = 0x00000030, 1004 .dram_dqm0 = 0x00000030,
1003 .dram_dqm1 = 0x00000030, 1005 .dram_dqm1 = 0x00000030,
1004 .dram_ras = 0x00000030, 1006 .dram_ras = 0x00000030,
1005 .dram_cas = 0x00000030, 1007 .dram_cas = 0x00000030,
1006 .dram_odt0 = 0x00000000, 1008 .dram_odt0 = 0x00000000,
1007 .dram_odt1 = 0x00000000, 1009 .dram_odt1 = 0x00000000,
1008 .dram_sdba2 = 0x00000000, 1010 .dram_sdba2 = 0x00000000,
1009 .dram_sdclk_0 = 0x00000030, 1011 .dram_sdclk_0 = 0x00000030,
1010 .dram_sdqs0 = 0x00003030, 1012 .dram_sdqs0 = 0x00003030,
1011 .dram_sdqs1 = 0x00003030, 1013 .dram_sdqs1 = 0x00003030,
1012 .dram_reset = 0x00000030, 1014 .dram_reset = 0x00000030,
1013 }; 1015 };
1014 1016
1015 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 1017 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
1016 .p0_mpwldectrl0 = 0x00000000, 1018 .p0_mpwldectrl0 = 0x00000000,
1017 .p0_mpdgctrl0 = 0x20000000, 1019 .p0_mpdgctrl0 = 0x20000000,
1018 .p0_mprddlctl = 0x4040484f, 1020 .p0_mprddlctl = 0x4040484f,
1019 .p0_mpwrdlctl = 0x40405247, 1021 .p0_mpwrdlctl = 0x40405247,
1020 .mpzqlp2ctl = 0x1b4700c7, 1022 .mpzqlp2ctl = 0x1b4700c7,
1021 }; 1023 };
1022 1024
1023 static struct mx6_lpddr2_cfg mem_ddr = { 1025 static struct mx6_lpddr2_cfg mem_ddr = {
1024 .mem_speed = 800, 1026 .mem_speed = 800,
1025 .density = 2, 1027 .density = 2,
1026 .width = 16, 1028 .width = 16,
1027 .banks = 4, 1029 .banks = 4,
1028 .rowaddr = 14, 1030 .rowaddr = 14,
1029 .coladdr = 10, 1031 .coladdr = 10,
1030 .trcd_lp = 1500, 1032 .trcd_lp = 1500,
1031 .trppb_lp = 1500, 1033 .trppb_lp = 1500,
1032 .trpab_lp = 2000, 1034 .trpab_lp = 2000,
1033 .trasmin = 4250, 1035 .trasmin = 4250,
1034 }; 1036 };
1035 1037
1036 struct mx6_ddr_sysinfo ddr_sysinfo = { 1038 struct mx6_ddr_sysinfo ddr_sysinfo = {
1037 .dsize = 0, 1039 .dsize = 0,
1038 .cs_density = 18, 1040 .cs_density = 18,
1039 .ncs = 1, 1041 .ncs = 1,
1040 .cs1_mirror = 0, 1042 .cs1_mirror = 0,
1041 .walat = 0, 1043 .walat = 0,
1042 .ralat = 5, 1044 .ralat = 5,
1043 .mif3_mode = 3, 1045 .mif3_mode = 3,
1044 .bi_on = 1, 1046 .bi_on = 1,
1045 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ 1047 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
1046 .rtt_nom = 0, 1048 .rtt_nom = 0,
1047 .sde_to_rst = 0, /* LPDDR2 does not need this field */ 1049 .sde_to_rst = 0, /* LPDDR2 does not need this field */
1048 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ 1050 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
1049 .ddr_type = DDR_TYPE_LPDDR2, 1051 .ddr_type = DDR_TYPE_LPDDR2,
1050 }; 1052 };
1051 1053
1052 #else 1054 #else
1053 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 1055 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
1054 .dram_dqm0 = 0x00000030, 1056 .dram_dqm0 = 0x00000030,
1055 .dram_dqm1 = 0x00000030, 1057 .dram_dqm1 = 0x00000030,
1056 .dram_ras = 0x00000030, 1058 .dram_ras = 0x00000030,
1057 .dram_cas = 0x00000030, 1059 .dram_cas = 0x00000030,
1058 .dram_odt0 = 0x00000030, 1060 .dram_odt0 = 0x00000030,
1059 .dram_odt1 = 0x00000030, 1061 .dram_odt1 = 0x00000030,
1060 .dram_sdba2 = 0x00000000, 1062 .dram_sdba2 = 0x00000000,
1061 .dram_sdclk_0 = 0x00000008, 1063 .dram_sdclk_0 = 0x00000008,
1062 .dram_sdqs0 = 0x00000038, 1064 .dram_sdqs0 = 0x00000038,
1063 .dram_sdqs1 = 0x00000030, 1065 .dram_sdqs1 = 0x00000030,
1064 .dram_reset = 0x00000030, 1066 .dram_reset = 0x00000030,
1065 }; 1067 };
1066 1068
1067 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 1069 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
1068 .p0_mpwldectrl0 = 0x00070007, 1070 .p0_mpwldectrl0 = 0x00070007,
1069 .p0_mpdgctrl0 = 0x41490145, 1071 .p0_mpdgctrl0 = 0x41490145,
1070 .p0_mprddlctl = 0x40404546, 1072 .p0_mprddlctl = 0x40404546,
1071 .p0_mpwrdlctl = 0x4040524D, 1073 .p0_mpwrdlctl = 0x4040524D,
1072 }; 1074 };
1073 1075
1074 struct mx6_ddr_sysinfo ddr_sysinfo = { 1076 struct mx6_ddr_sysinfo ddr_sysinfo = {
1075 .dsize = 0, 1077 .dsize = 0,
1076 .cs_density = 20, 1078 .cs_density = 20,
1077 .ncs = 1, 1079 .ncs = 1,
1078 .cs1_mirror = 0, 1080 .cs1_mirror = 0,
1079 .rtt_wr = 2, 1081 .rtt_wr = 2,
1080 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 1082 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
1081 .walat = 1, /* Write additional latency */ 1083 .walat = 1, /* Write additional latency */
1082 .ralat = 5, /* Read additional latency */ 1084 .ralat = 5, /* Read additional latency */
1083 .mif3_mode = 3, /* Command prediction working mode */ 1085 .mif3_mode = 3, /* Command prediction working mode */
1084 .bi_on = 1, /* Bank interleaving enabled */ 1086 .bi_on = 1, /* Bank interleaving enabled */
1085 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 1087 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
1086 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 1088 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
1087 .ddr_type = DDR_TYPE_DDR3, 1089 .ddr_type = DDR_TYPE_DDR3,
1088 }; 1090 };
1089 1091
1090 static struct mx6_ddr3_cfg mem_ddr = { 1092 static struct mx6_ddr3_cfg mem_ddr = {
1091 .mem_speed = 800, 1093 .mem_speed = 800,
1092 .density = 4, 1094 .density = 4,
1093 .width = 16, 1095 .width = 16,
1094 .banks = 8, 1096 .banks = 8,
1095 .rowaddr = 15, 1097 .rowaddr = 15,
1096 .coladdr = 10, 1098 .coladdr = 10,
1097 .pagesz = 2, 1099 .pagesz = 2,
1098 .trcd = 1375, 1100 .trcd = 1375,
1099 .trcmin = 4875, 1101 .trcmin = 4875,
1100 .trasmin = 3500, 1102 .trasmin = 3500,
1101 }; 1103 };
1102 #endif 1104 #endif
1103 1105
1104 static void ccgr_init(void) 1106 static void ccgr_init(void)
1105 { 1107 {
1106 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 1108 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1107 1109
1108 writel(0xFFFFFFFF, &ccm->CCGR0); 1110 writel(0xFFFFFFFF, &ccm->CCGR0);
1109 writel(0xFFFFFFFF, &ccm->CCGR1); 1111 writel(0xFFFFFFFF, &ccm->CCGR1);
1110 writel(0xFFFFFFFF, &ccm->CCGR2); 1112 writel(0xFFFFFFFF, &ccm->CCGR2);
1111 writel(0xFFFFFFFF, &ccm->CCGR3); 1113 writel(0xFFFFFFFF, &ccm->CCGR3);
1112 writel(0xFFFFFFFF, &ccm->CCGR4); 1114 writel(0xFFFFFFFF, &ccm->CCGR4);
1113 writel(0xFFFFFFFF, &ccm->CCGR5); 1115 writel(0xFFFFFFFF, &ccm->CCGR5);
1114 writel(0xFFFFFFFF, &ccm->CCGR6); 1116 writel(0xFFFFFFFF, &ccm->CCGR6);
1115 writel(0xFFFFFFFF, &ccm->CCGR7); 1117 writel(0xFFFFFFFF, &ccm->CCGR7);
1116 } 1118 }
1117 1119
1118 static void spl_dram_init(void) 1120 static void spl_dram_init(void)
1119 { 1121 {
1120 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 1122 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
1121 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 1123 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
1122 } 1124 }
1123 1125
1124 void board_init_f(ulong dummy) 1126 void board_init_f(ulong dummy)
1125 { 1127 {
1126 /* setup AIPS and disable watchdog */ 1128 /* setup AIPS and disable watchdog */
1127 arch_cpu_init(); 1129 arch_cpu_init();
1128 1130
1129 ccgr_init(); 1131 ccgr_init();
1130 1132
1131 /* iomux and setup of i2c */ 1133 /* iomux and setup of i2c */
1132 board_early_init_f(); 1134 board_early_init_f();
1133 1135
1134 /* setup GP timer */ 1136 /* setup GP timer */
1135 timer_init(); 1137 timer_init();
1136 1138
1137 /* UART clocks enabled and gd valid - init serial console */ 1139 /* UART clocks enabled and gd valid - init serial console */
1138 preloader_console_init(); 1140 preloader_console_init();
1139 1141
1140 /* DDR initialization */ 1142 /* DDR initialization */
1141 spl_dram_init(); 1143 spl_dram_init();
1142 1144
1143 /* Clear the BSS. */ 1145 /* Clear the BSS. */
1144 memset(__bss_start, 0, __bss_end - __bss_start); 1146 memset(__bss_start, 0, __bss_end - __bss_start);
1145 1147
1146 /* load/boot image from boot device */ 1148 /* load/boot image from boot device */
1147 board_init_r(NULL, 0); 1149 board_init_r(NULL, 0);
1148 } 1150 }
1149 #endif 1151 #endif
1150 1152
configs/mx6ul_14x14_evk_nand_defconfig
Diff comments   View file @ c1c4fab
File was created 1 CONFIG_ARM=y
2 CONFIG_ARCH_MX6=y
3 CONFIG_TARGET_MX6UL_14X14_EVK=y
4 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg,SYS_BOOT_NAND"
5 CONFIG_CMD_GPIO=y
6 CONFIG_CMD_DHCP=y
7 CONFIG_CMD_PING=y
8