Eric Lee / smarc-uboot

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Commit c251cbece893b9206301218ecc81242e2b5b2c0b

Authored by Ye Li
1 parent aafacf1b5f
Exists in smarc_8mq-imx_v2020.04_5.4.24_2.1.0 and in 3 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, smarc-8m-android-10.0.0_2.6.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0

MLK-23574-46 imx8qxp: Add iMX8QXP/iMX8DX validation board support 

Add the validation board support for iMX8QXP/iMX8DX platforms.
    - iMX8QXP 21x21 DDR3 board
    - iMX8QXP 21x21 LPDDR4 board
    - iMX8QXP 17x17 LPDDR4 board
    - iMX8DX 17x17 DDR3 board

Ready functions:  SD/eMMC, flexspi, ENET, USB, i2c and NAND

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 21 changed files with 2811 additions and 0 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ c251cbe
... ... @@ -735,6 +735,10 @@
735 735 fsl-imx8qxp-ai_ml.dtb \
736 736 fsl-imx8qxp-colibri.dtb \
737 737 fsl-imx8qxp-mek.dtb \
  738 + fsl-imx8qxp-lpddr4-val.dtb \
  739 + fsl-imx8qxp-lpddr4-val-gpmi-nand.dtb \
  740 + fsl-imx8qxp-17x17-val.dtb \
  741 + fsl-imx8dx-17x17-val.dtb \
738 742 fsl-imx8dx-mek.dtb \
739 743 fsl-imx8dxl-phantom-mek.dtb \
740 744 fsl-imx8dxl-evk.dtb \
arch/arm/dts/fsl-imx8dx-17x17-val.dts
Diff comments   View file @ c251cbe
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * This program is free software; you can redistribute it and/or
  5 + * modify it under the terms of the GNU General Public License
  6 + * as published by the Free Software Foundation; either version 2
  7 + * of the License, or (at your option) any later version.
  8 + *
  9 + * This program is distributed in the hope that it will be useful,
  10 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12 + * GNU General Public License for more details.
  13 + */
  14 +
  15 +#include "fsl-imx8qxp-17x17-val.dts"
  16 +
  17 +/ {
  18 + model = "NXP i.MX8DX 17x17 Validation board";
  19 +};
arch/arm/dts/fsl-imx8qxp-17x17-val-u-boot.dtsi
Diff comments   View file @ c251cbe
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +/ {
  7 + aliases {
  8 + usbgadget0 = &usbg1;
  9 + };
  10 +
  11 + usbg1: usbg1 {
  12 + compatible = "fsl,imx27-usb-gadget";
  13 + dr_mode = "peripheral";
  14 + chipidea,usb = <&usbotg1>;
  15 + status = "okay";
  16 + u-boot,dm-spl;
  17 + };
  18 +};
  19 +
  20 +&{/imx8qx-pm} {
  21 +
  22 + u-boot,dm-spl;
  23 +};
  24 +
  25 +&mu {
  26 + u-boot,dm-spl;
  27 +};
  28 +
  29 +&clk {
  30 + u-boot,dm-spl;
  31 +};
  32 +
  33 +&iomuxc {
  34 + u-boot,dm-spl;
  35 +};
  36 +
  37 +&{/mu@5d1c0000/iomuxc/imx8qxp-val} {
  38 + u-boot,dm-spl;
  39 +};
  40 +
  41 +&pinctrl_lpuart0 {
  42 + u-boot,dm-spl;
  43 +};
  44 +
  45 +&pinctrl_usdhc1 {
  46 + u-boot,dm-spl;
  47 +};
  48 +
  49 +&pinctrl_usdhc1_100mhz {
  50 + u-boot,dm-spl;
  51 +};
  52 +
  53 +&pinctrl_usdhc1_200mhz {
  54 + u-boot,dm-spl;
  55 +};
  56 +
  57 +&pd_conn {
  58 + u-boot,dm-spl;
  59 +};
  60 +
  61 +&pd_dma {
  62 + u-boot,dm-spl;
  63 +};
  64 +
  65 +&pd_dma_lpuart0 {
  66 + u-boot,dm-spl;
  67 +};
  68 +
  69 +&pd_conn_sdch0 {
  70 + u-boot,dm-spl;
  71 +};
  72 +
  73 +&pd_conn_usbotg0 {
  74 + u-boot,dm-spl;
  75 +};
  76 +
  77 +&pd_conn_usbotg0_phy {
  78 + u-boot,dm-spl;
  79 +};
  80 +
  81 +&lpuart0 {
  82 + u-boot,dm-spl;
  83 +};
  84 +
  85 +&usbmisc1 {
  86 + u-boot,dm-spl;
  87 +};
  88 +
  89 +&usbphy1 {
  90 + u-boot,dm-spl;
  91 +};
  92 +
  93 +&usbotg1 {
  94 + u-boot,dm-spl;
  95 +};
  96 +
  97 +&usdhc1 {
  98 + u-boot,dm-spl;
  99 + mmc-hs400-1_8v;
  100 + mmc-hs400-enhanced-strobe;
  101 +};
arch/arm/dts/fsl-imx8qxp-17x17-val.dts
Diff comments   View file @ c251cbe
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2018-2019 NXP
  4 + *
  5 + */
  6 +
  7 +#include "fsl-imx8qxp-lpddr4-val.dts"
  8 +
  9 +/ {
  10 + model = "NXP i.MX8QXP 17x17 Validation board";
  11 +};
  12 +
  13 +&i2c1 {
  14 + #address-cells = <1>;
  15 + #size-cells = <0>;
  16 + clock-frequency = <100000>;
  17 + pinctrl-names = "default";
  18 + pinctrl-0 = <&pinctrl_lpi2c1>;
  19 + status = "okay";
  20 +
  21 + pca9557_a: gpio@18 {
  22 + compatible = "nxp,pca9557";
  23 + reg = <0x18>;
  24 + gpio-controller;
  25 + #gpio-cells = <2>;
  26 + };
  27 +
  28 + pca9557_b: gpio@19 {
  29 + compatible = "nxp,pca9557";
  30 + reg = <0x19>;
  31 + gpio-controller;
  32 + #gpio-cells = <2>;
  33 + };
  34 +};
  35 +
  36 +&i2c3 {
  37 + status = "disabled";
  38 +
  39 + /delete-node/ gpio@18;
  40 + /delete-node/ gpio@19;
  41 +};
  42 +
  43 +&usdhc2 {
  44 + status = "disabled";
  45 +};
  46 +
  47 +&usbotg3 {
  48 + status = "disabled";
  49 +};
arch/arm/dts/fsl-imx8qxp-lpddr4-val-gpmi-nand.dts
Diff comments   View file @ c251cbe
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2017-2019 NXP
  4 + */
  5 +
  6 +#include "fsl-imx8qxp-lpddr4-val.dts"
  7 +
  8 +&iomuxc {
  9 + imx8qxp-val {
  10 + pinctrl_gpmi_nand_1: gpmi-nand-1 {
  11 + fsl,pins = <
  12 + SC_P_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c
  13 + SC_P_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c
  14 + SC_P_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c
  15 + SC_P_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c
  16 + SC_P_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c
  17 + SC_P_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c
  18 + SC_P_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c
  19 + SC_P_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c
  20 + SC_P_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c
  21 + SC_P_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c
  22 + SC_P_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c
  23 +
  24 + SC_P_USDHC1_DATA0_CONN_NAND_CE1_B 0x0e00004c
  25 + SC_P_USDHC1_DATA2_CONN_NAND_WE_B 0x0e00004c
  26 + SC_P_USDHC1_DATA3_CONN_NAND_ALE 0x0e00004c
  27 + SC_P_USDHC1_CMD_CONN_NAND_CE0_B 0x0e00004c
  28 +
  29 + /* i.MX8QXP NAND use nand_re_dqs_pins */
  30 + SC_P_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c
  31 + SC_P_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c
  32 +
  33 + >;
  34 + };
  35 + };
  36 +};
  37 +
  38 +&gpmi {
  39 + pinctrl-names = "default";
  40 + pinctrl-0 = <&pinctrl_gpmi_nand_1>;
  41 + status = "okay";
  42 + nand-on-flash-bbt;
  43 +};
  44 +
  45 +/* Disabled the usdhc1/usdhc2 since pin conflict */
  46 +&usdhc1 {
  47 + status = "disabled";
  48 +};
  49 +
  50 +&usdhc2 {
  51 + status = "disabled";
  52 +};
arch/arm/dts/fsl-imx8qxp-lpddr4-val-u-boot.dtsi
Diff comments   View file @ c251cbe
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +/ {
  7 +
  8 + aliases {
  9 + usbhost1 = &usbh3;
  10 + usbgadget0 = &usbg1;
  11 + };
  12 +
  13 + usbh3: usbh3 {
  14 + compatible = "Cadence,usb3-host";
  15 + dr_mode = "host";
  16 + cdns3,usb = <&usbotg3>;
  17 + status = "okay";
  18 + };
  19 +
  20 + usbg1: usbg1 {
  21 + compatible = "fsl,imx27-usb-gadget";
  22 + dr_mode = "peripheral";
  23 + chipidea,usb = <&usbotg1>;
  24 + status = "okay";
  25 + u-boot,dm-spl;
  26 + };
  27 +
  28 +};
  29 +
  30 +&{/imx8qx-pm} {
  31 +
  32 + u-boot,dm-spl;
  33 +};
  34 +
  35 +&mu {
  36 + u-boot,dm-spl;
  37 +};
  38 +
  39 +&clk {
  40 + u-boot,dm-spl;
  41 +};
  42 +
  43 +&iomuxc {
  44 + u-boot,dm-spl;
  45 +};
  46 +
  47 +&{/regulators} {
  48 + u-boot,dm-spl;
  49 +};
  50 +
  51 +&reg_usdhc2_vmmc {
  52 + u-boot,dm-spl;
  53 +};
  54 +
  55 +&{/mu@5d1c0000/iomuxc/imx8qxp-val} {
  56 + u-boot,dm-spl;
  57 +};
  58 +
  59 +&pinctrl_usdhc2_gpio {
  60 + u-boot,dm-spl;
  61 +};
  62 +
  63 +&pinctrl_usdhc2 {
  64 + u-boot,dm-spl;
  65 +};
  66 +
  67 +&pinctrl_usdhc2_100mhz {
  68 + u-boot,dm-spl;
  69 +};
  70 +
  71 +&pinctrl_usdhc2_200mhz {
  72 + u-boot,dm-spl;
  73 +};
  74 +
  75 +&pinctrl_lpuart0 {
  76 + u-boot,dm-spl;
  77 +};
  78 +
  79 +&pinctrl_usdhc1 {
  80 + u-boot,dm-spl;
  81 +};
  82 +
  83 +&pinctrl_usdhc1_100mhz {
  84 + u-boot,dm-spl;
  85 +};
  86 +
  87 +&pinctrl_usdhc1_200mhz {
  88 + u-boot,dm-spl;
  89 +};
  90 +
  91 +&pinctrl_flexspi0 {
  92 + u-boot,dm-spl;
  93 +};
  94 +
  95 +&pd_lsio {
  96 + u-boot,dm-spl;
  97 +};
  98 +
  99 +&pd_lsio_gpio0 {
  100 + u-boot,dm-spl;
  101 +};
  102 +
  103 +&pd_lsio_gpio3 {
  104 + u-boot,dm-spl;
  105 +};
  106 +
  107 +&pd_lsio_gpio4 {
  108 + u-boot,dm-spl;
  109 +};
  110 +
  111 +&pd_conn {
  112 + u-boot,dm-spl;
  113 +};
  114 +
  115 +&pd_dma {
  116 + u-boot,dm-spl;
  117 +};
  118 +
  119 +&pd_dma_lpuart0 {
  120 + u-boot,dm-spl;
  121 +};
  122 +
  123 +&pd_conn_sdch0 {
  124 + u-boot,dm-spl;
  125 +};
  126 +
  127 +&pd_conn_sdch1 {
  128 + u-boot,dm-spl;
  129 +};
  130 +
  131 +&pd_conn_sdch2 {
  132 + u-boot,dm-spl;
  133 +};
  134 +
  135 +&pd_conn_usbotg0 {
  136 + u-boot,dm-spl;
  137 +};
  138 +
  139 +&pd_conn_usbotg0_phy {
  140 + u-boot,dm-spl;
  141 +};
  142 +
  143 +&pd_conn_usb2 {
  144 + u-boot,dm-spl;
  145 +};
  146 +
  147 +&pd_conn_usb2_phy {
  148 + u-boot,dm-spl;
  149 +};
  150 +
  151 +&pd_lsio_flexspi0 {
  152 + u-boot,dm-spl;
  153 +};
  154 +
  155 +&gpio0 {
  156 + u-boot,dm-spl;
  157 +};
  158 +
  159 +&gpio3 {
  160 + u-boot,dm-spl;
  161 +};
  162 +
  163 +&gpio4 {
  164 + u-boot,dm-spl;
  165 +};
  166 +
  167 +&lpuart0 {
  168 + u-boot,dm-spl;
  169 +};
  170 +
  171 +&usbmisc1 {
  172 + u-boot,dm-spl;
  173 +};
  174 +
  175 +&usbphy1 {
  176 + u-boot,dm-spl;
  177 +};
  178 +
  179 +&usbotg1 {
  180 + u-boot,dm-spl;
  181 +};
  182 +
  183 +&usbotg3 {
  184 + phys = <&usbphynop1>;
  185 + u-boot,dm-spl;
  186 +};
  187 +
  188 +&usbphynop1 {
  189 + compatible = "cdns,usb3-phy";
  190 + reg = <0x0 0x5B160000 0x0 0x40000>;
  191 + #phy-cells = <0>;
  192 + u-boot,dm-spl;
  193 +};
  194 +
  195 +&usdhc1 {
  196 + u-boot,dm-spl;
  197 + mmc-hs400-1_8v;
  198 + mmc-hs400-enhanced-strobe;
  199 +};
  200 +
  201 +&usdhc2 {
  202 + u-boot,dm-spl;
  203 + sd-uhs-sdr104;
  204 + sd-uhs-ddr50;
  205 +};
  206 +
  207 +&flexspi0 {
  208 + u-boot,dm-spl;
  209 +};
  210 +
  211 +&flash0 {
  212 + u-boot,dm-spl;
  213 +};
  214 +
  215 +&wu {
  216 + u-boot,dm-spl;
  217 +};
arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts
Diff comments   View file @ c251cbe
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2017-2019 NXP
  4 + */
  5 +
  6 +/dts-v1/;
  7 +
  8 +#include "fsl-imx8qxp.dtsi"
  9 +
  10 +/ {
  11 + model = "NXP i.MX8QXP LPDDR4 VAL";
  12 + compatible = "fsl,imx8qxp-lpddr4-val", "fsl,imx8qxp";
  13 +
  14 + aliases {
  15 + gpio8 = &pca9557_a;
  16 + gpio9 = &pca9557_b;
  17 + gpio10 = &pca9557_c;
  18 + };
  19 +
  20 + chosen {
  21 + bootargs = "console=ttyLP0,115200 earlycon";
  22 + stdout-path = &lpuart0;
  23 + };
  24 +
  25 + regulators {
  26 + compatible = "simple-bus";
  27 + #address-cells = <1>;
  28 + #size-cells = <0>;
  29 +
  30 + reg_usb_otg1_vbus: regulator@0 {
  31 + compatible = "regulator-fixed";
  32 + reg = <0>;
  33 + regulator-name = "usb_otg1_vbus";
  34 + regulator-min-microvolt = <5000000>;
  35 + regulator-max-microvolt = <5000000>;
  36 + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
  37 + enable-active-high;
  38 + };
  39 +
  40 + reg_usdhc2_vmmc: usdhc2_vmmc {
  41 + compatible = "regulator-fixed";
  42 + regulator-name = "SD1_SPWR";
  43 + regulator-min-microvolt = <3000000>;
  44 + regulator-max-microvolt = <3000000>;
  45 + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
  46 + enable-active-high;
  47 + startup-delay-us = <300>;
  48 + off-on-delay-us = <5000>;
  49 + };
  50 + };
  51 +};
  52 +
  53 +&iomuxc {
  54 + pinctrl-names = "default";
  55 + pinctrl-0 = <&pinctrl_hog_1>;
  56 +
  57 + imx8qxp-val {
  58 + pinctrl_hog_1: hoggrp-1 {
  59 + fsl,pins = <
  60 + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048
  61 + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
  62 + >;
  63 + };
  64 +
  65 + pinctrl_fec1: fec1grp {
  66 + fsl,pins = <
  67 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
  68 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
  69 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
  70 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
  71 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
  72 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
  73 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
  74 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
  75 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
  76 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
  77 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
  78 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
  79 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
  80 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
  81 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
  82 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
  83 + >;
  84 + };
  85 +
  86 + pinctrl_fec2: fec2grp {
  87 + fsl,pins = <
  88 + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060
  89 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060
  90 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
  91 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
  92 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060
  93 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060
  94 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060
  95 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
  96 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
  97 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
  98 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060
  99 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060
  100 + >;
  101 + };
  102 +
  103 + pinctrl_lpi2c1: lpi1cgrp {
  104 + fsl,pins = <
  105 + SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021
  106 + SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021
  107 + >;
  108 + };
  109 +
  110 + pinctrl_lpi2c3: lpi2cgrp {
  111 + fsl,pins = <
  112 + SC_P_SPI3_CS1_ADMA_I2C3_SCL 0x06000020
  113 + SC_P_MCLK_IN1_ADMA_I2C3_SDA 0x06000020
  114 + >;
  115 + };
  116 +
  117 + pinctrl_lpuart0: lpuart0grp {
  118 + fsl,pins = <
  119 + SC_P_UART0_RX_ADMA_UART0_RX 0x0600002c
  120 + SC_P_UART0_TX_ADMA_UART0_TX 0x0600002c
  121 + >;
  122 + };
  123 +
  124 + pinctrl_usdhc1: usdhc1grp {
  125 + fsl,pins = <
  126 + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
  127 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
  128 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
  129 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
  130 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
  131 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
  132 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
  133 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
  134 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
  135 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
  136 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
  137 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
  138 + >;
  139 + };
  140 +
  141 + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
  142 + fsl,pins = <
  143 + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
  144 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
  145 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
  146 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
  147 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
  148 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
  149 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
  150 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
  151 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
  152 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
  153 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
  154 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
  155 + >;
  156 + };
  157 +
  158 + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  159 + fsl,pins = <
  160 + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
  161 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
  162 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
  163 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
  164 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
  165 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
  166 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
  167 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
  168 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
  169 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
  170 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
  171 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
  172 + >;
  173 + };
  174 +
  175 + pinctrl_usdhc2_gpio: usdhc2gpiogrp {
  176 + fsl,pins = <
  177 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021
  178 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021
  179 + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021
  180 + >;
  181 + };
  182 +
  183 + pinctrl_usdhc2: usdhc2grp {
  184 + fsl,pins = <
  185 + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
  186 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
  187 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
  188 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
  189 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
  190 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
  191 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
  192 + >;
  193 + };
  194 +
  195 + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  196 + fsl,pins = <
  197 + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
  198 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
  199 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
  200 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
  201 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
  202 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
  203 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
  204 + >;
  205 + };
  206 +
  207 + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  208 + fsl,pins = <
  209 + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
  210 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
  211 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
  212 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
  213 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
  214 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
  215 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
  216 + >;
  217 + };
  218 +
  219 + pinctrl_flexspi0: flexspi0grp {
  220 + fsl,pins = <
  221 + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
  222 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
  223 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
  224 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
  225 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
  226 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
  227 + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
  228 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
  229 + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
  230 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
  231 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
  232 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
  233 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
  234 + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
  235 + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
  236 + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
  237 + >;
  238 + };
  239 +
  240 + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp {
  241 + fsl,pins = <
  242 + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
  243 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
  244 + >;
  245 + };
  246 +
  247 + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp {
  248 + fsl,pins = <
  249 + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
  250 + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
  251 + >;
  252 + };
  253 + };
  254 +};
  255 +
  256 +&gpio0 {
  257 + status = "okay";
  258 +};
  259 +
  260 +&gpio3 {
  261 + status = "okay";
  262 +};
  263 +
  264 +&gpio4 {
  265 + status = "okay";
  266 +};
  267 +
  268 +&fec1 {
  269 + pinctrl-names = "default";
  270 + pinctrl-0 = <&pinctrl_fec1>;
  271 + phy-mode = "rgmii-txid";
  272 + phy-handle = <&ethphy0>;
  273 + fsl,magic-packet;
  274 + fsl,rgmii_rxc_dly;
  275 + status = "okay";
  276 + phy-reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>;
  277 + phy-reset-duration = <10>;
  278 + phy-reset-post-delay = <150>;
  279 +
  280 + mdio {
  281 + #address-cells = <1>;
  282 + #size-cells = <0>;
  283 +
  284 + ethphy0: ethernet-phy@0 {
  285 + compatible = "ethernet-phy-ieee802.3-c22";
  286 + reg = <0>;
  287 + at803x,eee-disabled;
  288 + at803x,vddio-1p8v;
  289 + };
  290 +
  291 + ethphy1: ethernet-phy@1 {
  292 + compatible = "ethernet-phy-ieee802.3-c22";
  293 + reg = <1>;
  294 + at803x,eee-disabled;
  295 + at803x,vddio-1p8v;
  296 + status = "disabled";
  297 + };
  298 + };
  299 +};
  300 +
  301 +&fec2 {
  302 + pinctrl-names = "default";
  303 + pinctrl-0 = <&pinctrl_fec2>;
  304 + phy-mode = "rgmii-txid";
  305 + phy-handle = <&ethphy1>;
  306 + fsl,magic-packet;
  307 + fsl,rgmii_rxc_dly;
  308 + status = "disabled";
  309 + phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>;
  310 + phy-reset-duration = <10>;
  311 + phy-reset-post-delay = <150>;
  312 +};
  313 +
  314 +&flexspi0 {
  315 + pinctrl-names = "default";
  316 + pinctrl-0 = <&pinctrl_flexspi0>;
  317 + status = "okay";
  318 +
  319 + flash0: mt35xu512aba@0 {
  320 + reg = <0>;
  321 + #address-cells = <1>;
  322 + #size-cells = <1>;
  323 + compatible = "spi-flash";
  324 + spi-max-frequency = <29000000>;
  325 + spi-nor,ddr-quad-read-dummy = <8>;
  326 + };
  327 +};
  328 +
  329 +&i2c1 {
  330 + clock-frequency = <100000>;
  331 + pinctrl-names = "default";
  332 + pinctrl-0 = <&pinctrl_lpi2c1>;
  333 + status = "okay";
  334 +};
  335 +
  336 +&i2c3 {
  337 + #address-cells = <1>;
  338 + #size-cells = <0>;
  339 + clock-frequency = <100000>;
  340 + pinctrl-names = "default";
  341 + pinctrl-0 = <&pinctrl_lpi2c3>;
  342 + status = "okay";
  343 +
  344 + pca9557_a: gpio@18 {
  345 + compatible = "nxp,pca9557";
  346 + reg = <0x18>;
  347 + gpio-controller;
  348 + #gpio-cells = <2>;
  349 + };
  350 +
  351 + pca9557_b: gpio@19 {
  352 + compatible = "nxp,pca9557";
  353 + reg = <0x19>;
  354 + gpio-controller;
  355 + #gpio-cells = <2>;
  356 + };
  357 +
  358 + pca9557_c: gpio@1b {
  359 + compatible = "nxp,pca9557";
  360 + reg = <0x1b>;
  361 + gpio-controller;
  362 + #gpio-cells = <2>;
  363 + };
  364 +};
  365 +
  366 +&i2c0_mipi_lvds0 {
  367 + #address-cells = <1>;
  368 + #size-cells = <0>;
  369 + pinctrl-names = "default";
  370 + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>;
  371 + clock-frequency = <100000>;
  372 + status = "okay";
  373 +
  374 + it6263-0@4c {
  375 + compatible = "ITE,it6263";
  376 + reg = <0x4c>;
  377 + };
  378 +};
  379 +
  380 +&i2c0_mipi_lvds1 {
  381 + #address-cells = <1>;
  382 + #size-cells = <0>;
  383 + pinctrl-names = "default";
  384 + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>;
  385 + clock-frequency = <100000>;
  386 + status = "okay";
  387 +
  388 + it6263-1@4c {
  389 + compatible = "ITE,it6263";
  390 + reg = <0x4c>;
  391 + };
  392 +};
  393 +
  394 +&lpuart0 {
  395 + pinctrl-names = "default";
  396 + pinctrl-0 = <&pinctrl_lpuart0>;
  397 + status = "okay";
  398 +};
  399 +
  400 +&usdhc1 {
  401 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  402 + pinctrl-0 = <&pinctrl_usdhc1>;
  403 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  404 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  405 + bus-width = <8>;
  406 + non-removable;
  407 + status = "okay";
  408 +};
  409 +
  410 +&usdhc2 {
  411 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  412 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  413 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  414 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  415 + bus-width = <4>;
  416 + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
  417 + wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
  418 + vmmc-supply = <&reg_usdhc2_vmmc>;
  419 + status = "okay";
  420 +};
  421 +
  422 +&usbotg1 {
  423 + vbus-supply = <&reg_usb_otg1_vbus>;
  424 + srp-disable;
  425 + hnp-disable;
  426 + adp-disable;
  427 + disable-over-current;
  428 + status = "okay";
  429 +};
  430 +
  431 +&usbotg3 {
  432 + status = "okay";
  433 +};
arch/arm/mach-imx/imx8/Kconfig
Diff comments   View file @ c251cbe
... ... @@ -117,6 +117,21 @@
117 117 select BOARD_LATE_INIT
118 118 select IMX8QXP
119 119  
  120 +config TARGET_IMX8QXP_LPDDR4_VAL
  121 + bool "Support i.MX8QXP lpddr4 validation board"
  122 + select BOARD_LATE_INIT
  123 + select IMX8QXP
  124 +
  125 +config TARGET_IMX8QXP_DDR3_VAL
  126 + bool "Support i.MX8QXP ddr3 validation board"
  127 + select BOARD_LATE_INIT
  128 + select IMX8QXP
  129 +
  130 +config TARGET_IMX8X_17X17_VAL
  131 + bool "Support i.MX8QXP/DX 17x17 validation board"
  132 + select BOARD_LATE_INIT
  133 + select IMX8QXP
  134 +
120 135 config TARGET_IMX8DXL_PHANTOM_MEK
121 136 bool "Support i.MX8DXL PHANTOM MEK board"
122 137 select BOARD_LATE_INIT
... ... @@ -143,6 +158,7 @@
143 158 source "board/freescale/imx8qm_mek/Kconfig"
144 159 source "board/freescale/imx8qxp_mek/Kconfig"
145 160 source "board/freescale/imx8qm_val/Kconfig"
  161 +source "board/freescale/imx8qxp_val/Kconfig"
146 162 source "board/freescale/imx8dxl_phantom_mek/Kconfig"
147 163 source "board/freescale/imx8dxl_evk/Kconfig"
148 164 source "board/advantech/imx8qm_rom7720_a1/Kconfig"
board/freescale/imx8qxp_val/Kconfig
Diff comments   View file @ c251cbe
  1 +if TARGET_IMX8QXP_LPDDR4_VAL || TARGET_IMX8QXP_DDR3_VAL || TARGET_IMX8X_17X17_VAL
  2 +
  3 +config SYS_BOARD
  4 + default "imx8qxp_val"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "imx8qxp_val"
  11 +
  12 +endif
board/freescale/imx8qxp_val/Makefile
Diff comments   View file @ c251cbe
  1 +#
  2 +# Copyright 2017-2019 NXP
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y += imx8qxp_val.o
  8 +obj-$(CONFIG_SPL_BUILD) += spl.o
board/freescale/imx8qxp_val/imx8qxp_val.c
Diff comments   View file @ c251cbe
  1 +/*
  2 + * Copyright 2017-2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +#include <common.h>
  7 +#include <malloc.h>
  8 +#include <errno.h>
  9 +#include <netdev.h>
  10 +#include <fsl_ifc.h>
  11 +#include <fdt_support.h>
  12 +#include <linux/libfdt.h>
  13 +#include <cpu_func.h>
  14 +#include <env.h>
  15 +#include <fsl_esdhc.h>
  16 +#include <i2c.h>
  17 +#include "pca953x.h"
  18 +
  19 +#include <asm/io.h>
  20 +#include <asm/gpio.h>
  21 +#include <asm/arch/clock.h>
  22 +#include <asm/arch/sci/sci.h>
  23 +#include <asm/arch/imx8-pins.h>
  24 +#include <asm/arch/snvs_security_sc.h>
  25 +#include <dm.h>
  26 +#include <imx8_hsio.h>
  27 +#include <usb.h>
  28 +#include <asm/arch/iomux.h>
  29 +#include <asm/arch/sys_proto.h>
  30 +#include <asm/mach-imx/dma.h>
  31 +#include <power-domain.h>
  32 +#include <asm/arch/lpcg.h>
  33 +#include <bootm.h>
  34 +
  35 +DECLARE_GLOBAL_DATA_PTR;
  36 +
  37 +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  38 + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  39 +
  40 +#define GPMI_NAND_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \
  41 + | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  42 +
  43 +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  44 + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  45 +
  46 +
  47 +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  48 + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  49 +
  50 +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  51 + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  52 +
  53 +
  54 +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  55 + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  56 +
  57 +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  58 + | (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  59 +
  60 +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  61 + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  62 +
  63 +#ifdef CONFIG_SPL_BUILD
  64 +#ifdef CONFIG_NAND_MXS
  65 +static iomux_cfg_t gpmi_nand_pads[] = {
  66 + SC_P_EMMC0_CLK | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  67 + SC_P_EMMC0_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  68 + SC_P_EMMC0_DATA1 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  69 + SC_P_EMMC0_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  70 + SC_P_EMMC0_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  71 + SC_P_EMMC0_DATA4 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  72 + SC_P_EMMC0_DATA5 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  73 + SC_P_EMMC0_DATA6 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  74 + SC_P_EMMC0_DATA7 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  75 + SC_P_EMMC0_STROBE | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  76 + SC_P_EMMC0_RESET_B | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  77 + SC_P_USDHC1_CMD | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  78 + SC_P_USDHC1_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  79 + SC_P_USDHC1_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  80 + SC_P_USDHC1_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  81 +
  82 + /* i.MX8QXP NAND use nand_re_dqs_pins */
  83 + SC_P_USDHC1_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  84 + SC_P_USDHC1_VSELECT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
  85 +
  86 +};
  87 +
  88 +static void setup_iomux_gpmi_nand(void)
  89 +{
  90 + imx8_iomux_setup_multiple_pads(gpmi_nand_pads, ARRAY_SIZE(gpmi_nand_pads));
  91 +}
  92 +
  93 +static void imx8qxp_gpmi_nand_initialize(void)
  94 +{
  95 + int ret;
  96 +
  97 + ret = sc_pm_set_resource_power_mode(-1, SC_R_NAND, SC_PM_PW_MODE_ON);
  98 + if (ret != SC_ERR_NONE)
  99 + return;
  100 +
  101 + init_clk_gpmi_nand();
  102 + setup_iomux_gpmi_nand();
  103 +}
  104 +#endif
  105 +#endif
  106 +
  107 +static iomux_cfg_t uart0_pads[] = {
  108 + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  109 + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  110 +};
  111 +
  112 +static void setup_iomux_uart(void)
  113 +{
  114 + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
  115 +}
  116 +
  117 +int board_early_init_f(void)
  118 +{
  119 + sc_pm_clock_rate_t rate = SC_80MHZ;
  120 + int ret;
  121 +
  122 + /* Set UART0 clock root to 80 MHz */
  123 + ret = sc_pm_setup_uart(SC_R_UART_0, rate);
  124 + if (ret)
  125 + return ret;
  126 +
  127 + setup_iomux_uart();
  128 +
  129 +#ifdef CONFIG_SPL_BUILD
  130 +#ifdef CONFIG_NAND_MXS
  131 + imx8qxp_gpmi_nand_initialize();
  132 +#endif
  133 +#endif
  134 +
  135 + return 0;
  136 +}
  137 +
  138 +#if IS_ENABLED(CONFIG_FEC_MXC)
  139 +#include <miiphy.h>
  140 +
  141 +#ifndef CONFIG_DM_ETH
  142 +static iomux_cfg_t pad_enet1[] = {
  143 + SC_P_SPDIF0_TX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  144 + SC_P_SPDIF0_RX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  145 + SC_P_ESAI0_TX3_RX2 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  146 + SC_P_ESAI0_TX2_RX3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  147 + SC_P_ESAI0_TX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  148 + SC_P_ESAI0_TX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  149 + SC_P_ESAI0_SCKR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  150 + SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  151 + SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  152 + SC_P_ESAI0_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  153 + SC_P_ESAI0_SCKT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  154 + SC_P_ESAI0_FSR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  155 +
  156 + /* Shared MDIO */
  157 + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  158 + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  159 +};
  160 +
  161 +static iomux_cfg_t pad_enet0[] = {
  162 + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  163 + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  164 + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  165 + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  166 + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  167 + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  168 + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  169 + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  170 + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  171 + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  172 + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  173 + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  174 +
  175 + /* Shared MDIO */
  176 + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  177 + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  178 +};
  179 +
  180 +static void setup_iomux_fec(void)
  181 +{
  182 + if (0 == CONFIG_FEC_ENET_DEV)
  183 + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
  184 + else
  185 + imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1));
  186 +}
  187 +
  188 +static void enet_device_phy_reset(void)
  189 +{
  190 + struct gpio_desc desc_enet0;
  191 + struct gpio_desc desc_enet1;
  192 + int ret;
  193 +
  194 + ret = dm_gpio_lookup_name("gpio@18_1", &desc_enet0);
  195 + if (ret)
  196 + return;
  197 +
  198 + ret = dm_gpio_request(&desc_enet0, "enet0_reset");
  199 + if (ret)
  200 + return;
  201 +
  202 + ret = dm_gpio_lookup_name("gpio@18_4", &desc_enet1);
  203 + if (ret)
  204 + return;
  205 +
  206 + ret = dm_gpio_request(&desc_enet1, "enet1_reset");
  207 + if (ret)
  208 + return;
  209 +
  210 + dm_gpio_set_dir_flags(&desc_enet0, GPIOD_IS_OUT);
  211 + dm_gpio_set_value(&desc_enet0, 0);
  212 + udelay(50);
  213 + dm_gpio_set_value(&desc_enet0, 1);
  214 +
  215 + dm_gpio_set_dir_flags(&desc_enet1, GPIOD_IS_OUT);
  216 + dm_gpio_set_value(&desc_enet1, 0);
  217 + udelay(50);
  218 + dm_gpio_set_value(&desc_enet1, 1);
  219 +
  220 + /* The board has a long delay for this reset to become stable */
  221 + mdelay(200);
  222 +}
  223 +
  224 +int board_eth_init(bd_t *bis)
  225 +{
  226 + int ret;
  227 + struct power_domain pd;
  228 +
  229 + printf("[%s] %d\n", __func__, __LINE__);
  230 +
  231 + /* Reset ENET PHY */
  232 + enet_device_phy_reset();
  233 +
  234 + if (CONFIG_FEC_ENET_DEV) {
  235 + if (!power_domain_lookup_name("conn_enet1", &pd))
  236 + power_domain_on(&pd);
  237 + } else {
  238 + if (!power_domain_lookup_name("conn_enet0", &pd))
  239 + power_domain_on(&pd);
  240 + }
  241 +
  242 + setup_iomux_fec();
  243 +
  244 + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
  245 + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  246 + if (ret)
  247 + printf("FEC1 MXC: %s:failed\n", __func__);
  248 +
  249 + return ret;
  250 +}
  251 +#endif
  252 +
  253 +#define MAX7322_I2C_ADDR 0x68
  254 +#define MAX7322_I2C_BUS 0 /* I2C1 */
  255 +int board_phy_config(struct phy_device *phydev)
  256 +{
  257 + if (phydev->addr == 1) {
  258 + /* This is needed to drive the pads to 1.8V instead of 1.5V */
  259 + uint8_t value;
  260 + struct udevice *bus;
  261 + struct udevice *i2c_dev = NULL;
  262 + int ret;
  263 +
  264 + ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS, &bus);
  265 + if (ret) {
  266 + printf("%s: Can't find bus\n", __func__);
  267 + return -EINVAL;
  268 + }
  269 +
  270 + ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &i2c_dev);
  271 + if (ret) {
  272 + printf("%s: Can't find device id=0x%x\n",
  273 + __func__, MAX7322_I2C_ADDR);
  274 + return -ENODEV;
  275 + }
  276 +
  277 + i2c_set_chip_offset_len(i2c_dev, 0);
  278 +
  279 + value = 0x1;
  280 +
  281 + ret = dm_i2c_write(i2c_dev, 0x0, (const uint8_t *)&value, 1);
  282 + if (ret) {
  283 + printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
  284 + return -EIO;
  285 + }
  286 +
  287 + mdelay(1);
  288 + }
  289 +
  290 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  291 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  292 +
  293 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
  294 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
  295 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  296 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  297 +
  298 + if (phydev->drv->config)
  299 + phydev->drv->config(phydev);
  300 +
  301 + return 0;
  302 +}
  303 +#endif
  304 +
  305 +#define DEBUG_LED IMX_GPIO_NR(3, 23)
  306 +#define IOEXP_RESET IMX_GPIO_NR(0, 19)
  307 +#define BB_PWR_EN IMX_GPIO_NR(5, 9)
  308 +
  309 +static iomux_cfg_t board_gpios[] = {
  310 + SC_P_QSPI0B_SS0_B | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  311 + SC_P_MCLK_IN0 | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  312 + SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  313 +};
  314 +
  315 +static void board_gpio_init(void)
  316 +{
  317 + int ret;
  318 + struct gpio_desc desc;
  319 + struct udevice *dev;
  320 +
  321 + imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
  322 +
  323 + /* enable i2c port expander assert reset line first */
  324 + /* we can't use dm_gpio_lookup_name for GPIO1_12, because the func will probe the
  325 + * uclass list until find the device. The expander device is at begin of the list due to
  326 + * I2c nodes is prior than gpio in the DTS. So if the func goes through the uclass list,
  327 + * probe to expander will fail, and exit the dm_gpio_lookup_name func. Thus, we always
  328 + * fail to get the device
  329 + */
  330 + ret = uclass_get_device_by_seq(UCLASS_GPIO, 0, &dev);
  331 + if (ret) {
  332 + printf("%s failed to find GPIO1 device, ret = %d\n", __func__, ret);
  333 + return;
  334 + }
  335 +
  336 + desc.dev = dev;
  337 + desc.offset = 19;
  338 +
  339 + ret = dm_gpio_request(&desc, "ioexp_rst");
  340 + if (ret) {
  341 + printf("%s request ioexp_rst failed ret = %d\n", __func__, ret);
  342 + return;
  343 + }
  344 +
  345 + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  346 +
  347 + ret = dm_gpio_lookup_name("GPIO3_23", &desc);
  348 + if (ret) {
  349 + printf("%s lookup GPIO@3_23 failed ret = %d\n", __func__, ret);
  350 + return;
  351 + }
  352 +
  353 + ret = dm_gpio_request(&desc, "debug_led");
  354 + if (ret) {
  355 + printf("%s request debug_led failed ret = %d\n", __func__, ret);
  356 + return;
  357 + }
  358 +
  359 + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  360 +
  361 + ret = dm_gpio_lookup_name("GPIO5_9", &desc);
  362 + if (ret) {
  363 + printf("%s lookup GPIO@5_9 failed ret = %d\n", __func__, ret);
  364 + return;
  365 + }
  366 +
  367 + ret = dm_gpio_request(&desc, "bb_pwr_en");
  368 + if (ret) {
  369 + printf("%s request bb_pwr_en failed ret = %d\n", __func__, ret);
  370 + return;
  371 + }
  372 +
  373 + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  374 +}
  375 +
  376 +int checkboard(void)
  377 +{
  378 +#if defined(CONFIG_TARGET_IMX8QXP_DDR3_VAL)
  379 + puts("Board: iMX8QXP DDR3 VAL\n");
  380 +#elif defined(CONFIG_TARGET_IMX8X_17X17_VAL)
  381 + puts("Board: iMX8X(QXP/DX) 17x17 Validation Board\n");
  382 +#else
  383 + puts("Board: iMX8QXP LPDDR4 VAL\n");
  384 +#endif
  385 +
  386 + build_info();
  387 + print_bootinfo();
  388 +
  389 + return 0;
  390 +}
  391 +
  392 +#ifdef CONFIG_FSL_HSIO
  393 +
  394 +#define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT))
  395 +static iomux_cfg_t board_pcie_pins[] = {
  396 + SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
  397 + SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
  398 + SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
  399 +};
  400 +
  401 +static void imx8qxp_hsio_initialize(void)
  402 +{
  403 + struct power_domain pd;
  404 + int ret;
  405 +
  406 + if (!power_domain_lookup_name("hsio_pcie1", &pd)) {
  407 + ret = power_domain_on(&pd);
  408 + if (ret)
  409 + printf("hsio_pcie1 Power up failed! (error = %d)\n", ret);
  410 + }
  411 + if (!power_domain_lookup_name("hsio_gpio", &pd)) {
  412 + ret = power_domain_on(&pd);
  413 + if (ret)
  414 + printf("hsio_gpio Power up failed! (error = %d)\n", ret);
  415 + }
  416 +
  417 + lpcg_all_clock_on(HSIO_PCIE_X1_LPCG);
  418 + lpcg_all_clock_on(HSIO_PHY_X1_LPCG);
  419 + lpcg_all_clock_on(HSIO_PHY_X1_CRR1_LPCG);
  420 + lpcg_all_clock_on(HSIO_PCIE_X1_CRR3_LPCG);
  421 + lpcg_all_clock_on(HSIO_MISC_LPCG);
  422 + lpcg_all_clock_on(HSIO_GPIO_LPCG);
  423 +
  424 + imx8_iomux_setup_multiple_pads(board_pcie_pins, ARRAY_SIZE(board_pcie_pins));
  425 +}
  426 +
  427 +void pci_init_board(void)
  428 +{
  429 + imx8qxp_hsio_initialize();
  430 +
  431 + /* test the 1 lane mode of the PCIe A controller */
  432 + mx8qxp_pcie_init();
  433 +}
  434 +
  435 +#endif
  436 +
  437 +int board_usb_init(int index, enum usb_init_type init)
  438 +{
  439 + int ret = 0;
  440 +
  441 + if (index == 0) {
  442 + if (init == USB_INIT_DEVICE) {
  443 +#if !CONFIG_IS_ENABLED(DM_USB_GADGET) && !CONFIG_IS_ENABLED(DM_USB)
  444 + ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0, SC_PM_PW_MODE_ON);
  445 + if (ret != SC_ERR_NONE)
  446 + printf("conn_usb0 Power up failed! (error = %d)\n", ret);
  447 +
  448 + ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0_PHY, SC_PM_PW_MODE_ON);
  449 + if (ret != SC_ERR_NONE)
  450 + printf("conn_usb0_phy Power up failed! (error = %d)\n", ret);
  451 +#endif
  452 + }
  453 + }
  454 + return ret;
  455 +}
  456 +
  457 +int board_usb_cleanup(int index, enum usb_init_type init)
  458 +{
  459 + int ret = 0;
  460 +
  461 + if (index == 0) {
  462 + if (init == USB_INIT_DEVICE) {
  463 +#if !CONFIG_IS_ENABLED(DM_USB_GADGET) && !CONFIG_IS_ENABLED(DM_USB)
  464 + ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0, SC_PM_PW_MODE_OFF);
  465 + if (ret != SC_ERR_NONE)
  466 + printf("conn_usb0 Power down failed! (error = %d)\n", ret);
  467 +
  468 + ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0_PHY, SC_PM_PW_MODE_OFF);
  469 + if (ret != SC_ERR_NONE)
  470 + printf("conn_usb0_phy Power down failed! (error = %d)\n", ret);
  471 +#endif
  472 + }
  473 + }
  474 + return ret;
  475 +}
  476 +
  477 +int board_init(void)
  478 +{
  479 + board_gpio_init();
  480 +
  481 +#ifdef CONFIG_SNVS_SEC_SC_AUTO
  482 + {
  483 + int ret = snvs_security_sc_init();
  484 +
  485 + if (ret)
  486 + return ret;
  487 + }
  488 +#endif
  489 +
  490 + return 0;
  491 +}
  492 +
  493 +void board_quiesce_devices(void)
  494 +{
  495 + const char *power_on_devices[] = {
  496 + "dma_lpuart0",
  497 +
  498 + /* HIFI DSP boot */
  499 + "audio_sai0",
  500 + "audio_ocram",
  501 + };
  502 +
  503 + power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices));
  504 +}
  505 +
  506 +/*
  507 + * Board specific reset that is system reset.
  508 + */
  509 +void reset_cpu(ulong addr)
  510 +{
  511 + /* TODO */
  512 +}
  513 +
  514 +#ifdef CONFIG_OF_BOARD_SETUP
  515 +int ft_board_setup(void *blob, bd_t *bd)
  516 +{
  517 + return 0;
  518 +}
  519 +#endif
  520 +
  521 +
  522 +int board_late_init(void)
  523 +{
  524 +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  525 + env_set("board_name", "VAL");
  526 + env_set("board_rev", "iMX8QXP");
  527 +#endif
  528 +
  529 + env_set("sec_boot", "no");
  530 +#ifdef CONFIG_AHAB_BOOT
  531 + env_set("sec_boot", "yes");
  532 +#endif
  533 +
  534 +#ifdef CONFIG_ENV_IS_IN_MMC
  535 + board_late_mmc_env_init();
  536 +#endif
  537 +
  538 + return 0;
  539 +}
board/freescale/imx8qxp_val/imximage.cfg
Diff comments   View file @ c251cbe
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2018 NXP
  4 + *
  5 + * Refer doc/README.imx8image for more details about how-to configure
  6 + * and create imx8image boot image
  7 + */
  8 +
  9 +#define __ASSEMBLY__
  10 +
  11 +/* Boot from SD, sector size 0x400 */
  12 +BOOT_FROM SD 0x400
  13 +/* SoC type IMX8QX */
  14 +SOC_TYPE IMX8QX
  15 +/* Append seco container image */
  16 +APPEND ahab-container.img
  17 +/* Create the 2nd container */
  18 +CONTAINER
  19 +/* Add scfw image with exec attribute */
  20 +IMAGE SCU mx8qx-mek-scfw-tcm.bin
  21 +/* Add ATF image with exec attribute */
  22 +IMAGE A35 spl/u-boot-spl.bin 0x00100000
board/freescale/imx8qxp_val/spl.c
Diff comments   View file @ c251cbe
  1 +/*
  2 + * Copyright 2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <dm.h>
  9 +#include <spl.h>
  10 +#include <dm/uclass.h>
  11 +#include <dm/device.h>
  12 +#include <dm/uclass-internal.h>
  13 +#include <dm/device-internal.h>
  14 +#include <dm/lists.h>
  15 +#include <bootm.h>
  16 +
  17 +DECLARE_GLOBAL_DATA_PTR;
  18 +
  19 +void spl_board_init(void)
  20 +{
  21 + struct udevice *dev;
  22 +
  23 + uclass_find_first_device(UCLASS_MISC, &dev);
  24 +
  25 + for (; dev; uclass_find_next_device(&dev)) {
  26 + if (device_probe(dev))
  27 + continue;
  28 + }
  29 +
  30 + board_early_init_f();
  31 +
  32 + timer_init();
  33 +
  34 + preloader_console_init();
  35 +
  36 + puts("Normal Boot\n");
  37 +}
  38 +
  39 +void spl_board_prepare_for_boot(void)
  40 +{
  41 + board_quiesce_devices();
  42 +}
  43 +
  44 +#ifdef CONFIG_SPL_LOAD_FIT
  45 +int board_fit_config_name_match(const char *name)
  46 +{
  47 + /* Just empty function now - can't decide what to choose */
  48 + debug("%s: %s\n", __func__, name);
  49 +
  50 + return 0;
  51 +}
  52 +#endif
  53 +
  54 +void board_init_f(ulong dummy)
  55 +{
  56 + /* Clear the BSS. */
  57 + memset(__bss_start, 0, __bss_end - __bss_start);
  58 +
  59 + arch_cpu_init();
  60 +
  61 + board_init_r(NULL, 0);
  62 +}
board/freescale/imx8qxp_val/uboot-container.cfg
Diff comments   View file @ c251cbe
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2019 NXP
  4 + */
  5 +
  6 +#define __ASSEMBLY__
  7 +
  8 +/* This file is to create a container image could be loaded by SPL */
  9 +BOOT_FROM SD 0x400
  10 +SOC_TYPE IMX8QX
  11 +CONTAINER
  12 +IMAGE A35 bl31.bin 0x80000000
  13 +IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE
configs/imx8dx_17x17_val_defconfig
Diff comments   View file @ c251cbe
  1 +CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_ICACHE_OFF=y
  3 +CONFIG_SPL_SYS_DCACHE_OFF=y
  4 +CONFIG_ARCH_IMX8=y
  5 +CONFIG_SYS_TEXT_BASE=0x80020000
  6 +CONFIG_SPL_GPIO_SUPPORT=y
  7 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  8 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  9 +CONFIG_SYS_MALLOC_F_LEN=0x8000
  10 +CONFIG_ENV_SIZE=0x2000
  11 +CONFIG_ENV_OFFSET=0x400000
  12 +CONFIG_DM_GPIO=y
  13 +CONFIG_SPL_LOAD_IMX_CONTAINER=y
  14 +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg"
  15 +CONFIG_TARGET_IMX8X_17X17_VAL=y
  16 +CONFIG_SPL_MMC_SUPPORT=y
  17 +CONFIG_SPL_EFI_PARTITION=n
  18 +CONFIG_SPL_DOS_PARTITION=n
  19 +CONFIG_SPL_DM_SEQ_ALIAS=y
  20 +CONFIG_SPL_SERIAL_SUPPORT=y
  21 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
  22 +CONFIG_USE_TINY_PRINTF=y
  23 +CONFIG_NR_DRAM_BANKS=4
  24 +CONFIG_SPL=y
  25 +CONFIG_PANIC_HANG=y
  26 +CONFIG_SPL_TEXT_BASE=0x100000
  27 +CONFIG_OF_SYSTEM_SETUP=y
  28 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_val/imximage.cfg"
  29 +CONFIG_BOOTDELAY=3
  30 +CONFIG_LOG=y
  31 +CONFIG_SPL_BOARD_INIT=y
  32 +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
  33 +CONFIG_SPL_SEPARATE_BSS=y
  34 +CONFIG_SPL_POWER_SUPPORT=y
  35 +CONFIG_SPL_POWER_DOMAIN=y
  36 +CONFIG_SPL_WATCHDOG_SUPPORT=y
  37 +CONFIG_HUSH_PARSER=y
  38 +CONFIG_CMD_CPU=y
  39 +# CONFIG_BOOTM_NETBSD is not set
  40 +# CONFIG_CMD_IMPORTENV is not set
  41 +CONFIG_CMD_CLK=y
  42 +CONFIG_CMD_DM=y
  43 +CONFIG_CMD_GPIO=y
  44 +CONFIG_CMD_I2C=y
  45 +CONFIG_CMD_MMC=y
  46 +CONFIG_CMD_DHCP=y
  47 +CONFIG_CMD_MII=y
  48 +CONFIG_CMD_PING=y
  49 +CONFIG_CMD_CACHE=y
  50 +CONFIG_CMD_FAT=y
  51 +CONFIG_SPL_OF_CONTROL=y
  52 +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-17x17-val"
  53 +CONFIG_DEFAULT_FDT_FILE="imx8dx-17x17-val.dtb"
  54 +CONFIG_ENV_IS_IN_MMC=y
  55 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  56 +CONFIG_NET_RANDOM_ETHADDR=y
  57 +CONFIG_SPL_DM=y
  58 +CONFIG_SPL_CLK=y
  59 +CONFIG_CLK_IMX8=y
  60 +CONFIG_CPU=y
  61 +CONFIG_MXC_GPIO=y
  62 +CONFIG_DM_PCA953X=y
  63 +CONFIG_DM_I2C=y
  64 +CONFIG_SYS_I2C_IMX_LPI2C=y
  65 +CONFIG_I2C_MUX=y
  66 +CONFIG_I2C_MUX_PCA954x=y
  67 +CONFIG_MISC=y
  68 +CONFIG_DM_MMC=y
  69 +CONFIG_SUPPORT_EMMC_BOOT=y
  70 +CONFIG_FSL_USDHC=y
  71 +CONFIG_MMC_IO_VOLTAGE=y
  72 +CONFIG_MMC_UHS_SUPPORT=y
  73 +CONFIG_MMC_HS400_ES_SUPPORT=y
  74 +CONFIG_EFI_PARTITION=y
  75 +CONFIG_PHYLIB=y
  76 +CONFIG_PHY_ADDR_ENABLE=y
  77 +CONFIG_PHY_ATHEROS=y
  78 +CONFIG_DM_ETH=y
  79 +CONFIG_DM_ETH_PHY=y
  80 +CONFIG_PHY_GIGE=y
  81 +CONFIG_FEC_MXC=y
  82 +CONFIG_MII=y
  83 +CONFIG_PINCTRL=y
  84 +CONFIG_SPL_PINCTRL=y
  85 +CONFIG_PINCTRL_IMX8=y
  86 +CONFIG_POWER_DOMAIN=y
  87 +CONFIG_IMX8_POWER_DOMAIN=y
  88 +CONFIG_DM_REGULATOR=y
  89 +CONFIG_DM_REGULATOR_FIXED=y
  90 +CONFIG_DM_REGULATOR_GPIO=y
  91 +CONFIG_DM_SERIAL=y
  92 +CONFIG_FSL_LPUART=y
  93 +CONFIG_SPL_TINY_MEMSET=y
  94 +# CONFIG_EFI_LOADER is not set
  95 +
  96 +CONFIG_CMD_FUSE=y
  97 +CONFIG_CMD_MEMTEST=y
  98 +
  99 +CONFIG_IMX_BOOTAUX=y
  100 +
  101 +CONFIG_DM_THERMAL=y
  102 +CONFIG_IMX_SCU_THERMAL=y
  103 +
  104 +CONFIG_SPI=y
  105 +CONFIG_FSL_FSPI=y
  106 +CONFIG_DM_SPI=y
  107 +CONFIG_DM_SPI_FLASH=y
  108 +CONFIG_SPI_FLASH=y
  109 +CONFIG_SPI_FLASH_STMICRO=y
  110 +CONFIG_CMD_SF=y
  111 +CONFIG_SF_DEFAULT_BUS=0
  112 +CONFIG_SF_DEFAULT_CS=0
  113 +CONFIG_SF_DEFAULT_SPEED=40000000
  114 +CONFIG_SF_DEFAULT_MODE=0
  115 +
  116 +CONFIG_DM_USB=y
  117 +CONFIG_DM_USB_GADGET=y
  118 +CONFIG_SPL_DM_USB_GADGET=y
  119 +CONFIG_USB=y
  120 +CONFIG_USB_TCPC=y
  121 +CONFIG_USB_GADGET=y
  122 +CONFIG_CI_UDC=y
  123 +CONFIG_USB_GADGET_DOWNLOAD=y
  124 +CONFIG_USB_GADGET_MANUFACTURER="FSL"
  125 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
  126 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
  127 +# CONFIG_USB_CDNS3=y
  128 +# CONFIG_USB_CDNS3_GADGET=y
  129 +# CONFIG_USB_GADGET_DUALSPEED=y
  130 +
  131 +CONFIG_SPL_USB_GADGET=y
  132 +CONFIG_SPL_USB_SDP_SUPPORT=y
  133 +CONFIG_SPL_SDP_USB_DEV=0
  134 +CONFIG_SDP_LOADADDR=0x80400000
  135 +
  136 +CONFIG_FASTBOOT=y
  137 +CONFIG_USB_FUNCTION_FASTBOOT=y
  138 +CONFIG_CMD_FASTBOOT=y
  139 +CONFIG_ANDROID_BOOT_IMAGE=y
  140 +CONFIG_FASTBOOT_UUU_SUPPORT=y
  141 +CONFIG_FASTBOOT_BUF_ADDR=0x82800000
  142 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000
  143 +CONFIG_FASTBOOT_FLASH=y
  144 +CONFIG_FASTBOOT_USB_DEV=0
  145 +
  146 +CONFIG_USB_PORT_AUTO=y
configs/imx8qxp_17x17_val_defconfig
Diff comments   View file @ c251cbe
  1 +CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_ICACHE_OFF=y
  3 +CONFIG_SPL_SYS_DCACHE_OFF=y
  4 +CONFIG_ARCH_IMX8=y
  5 +CONFIG_SYS_TEXT_BASE=0x80020000
  6 +CONFIG_SPL_GPIO_SUPPORT=y
  7 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  8 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  9 +CONFIG_SYS_MALLOC_F_LEN=0x8000
  10 +CONFIG_ENV_SIZE=0x2000
  11 +CONFIG_ENV_OFFSET=0x400000
  12 +CONFIG_DM_GPIO=y
  13 +CONFIG_SPL_LOAD_IMX_CONTAINER=y
  14 +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg"
  15 +CONFIG_TARGET_IMX8X_17X17_VAL=y
  16 +CONFIG_SPL_MMC_SUPPORT=y
  17 +CONFIG_SPL_EFI_PARTITION=n
  18 +CONFIG_SPL_DOS_PARTITION=n
  19 +CONFIG_SPL_DM_SEQ_ALIAS=y
  20 +CONFIG_SPL_SERIAL_SUPPORT=y
  21 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
  22 +CONFIG_USE_TINY_PRINTF=y
  23 +CONFIG_NR_DRAM_BANKS=4
  24 +CONFIG_SPL=y
  25 +CONFIG_PANIC_HANG=y
  26 +CONFIG_SPL_TEXT_BASE=0x100000
  27 +CONFIG_OF_SYSTEM_SETUP=y
  28 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_val/imximage.cfg"
  29 +CONFIG_BOOTDELAY=3
  30 +CONFIG_LOG=y
  31 +CONFIG_SPL_BOARD_INIT=y
  32 +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
  33 +CONFIG_SPL_SEPARATE_BSS=y
  34 +CONFIG_SPL_POWER_SUPPORT=y
  35 +CONFIG_SPL_POWER_DOMAIN=y
  36 +CONFIG_SPL_WATCHDOG_SUPPORT=y
  37 +CONFIG_HUSH_PARSER=y
  38 +CONFIG_CMD_CPU=y
  39 +# CONFIG_BOOTM_NETBSD is not set
  40 +# CONFIG_CMD_IMPORTENV is not set
  41 +CONFIG_CMD_CLK=y
  42 +CONFIG_CMD_DM=y
  43 +CONFIG_CMD_GPIO=y
  44 +CONFIG_CMD_I2C=y
  45 +CONFIG_CMD_MMC=y
  46 +CONFIG_CMD_DHCP=y
  47 +CONFIG_CMD_MII=y
  48 +CONFIG_CMD_PING=y
  49 +CONFIG_CMD_CACHE=y
  50 +CONFIG_CMD_FAT=y
  51 +CONFIG_SPL_OF_CONTROL=y
  52 +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-17x17-val"
  53 +CONFIG_DEFAULT_FDT_FILE="imx8qxp-17x17-val.dtb"
  54 +CONFIG_ENV_IS_IN_MMC=y
  55 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  56 +CONFIG_NET_RANDOM_ETHADDR=y
  57 +CONFIG_SPL_DM=y
  58 +CONFIG_SPL_CLK=y
  59 +CONFIG_CLK_IMX8=y
  60 +CONFIG_CPU=y
  61 +CONFIG_MXC_GPIO=y
  62 +CONFIG_DM_PCA953X=y
  63 +CONFIG_DM_I2C=y
  64 +CONFIG_SYS_I2C_IMX_LPI2C=y
  65 +CONFIG_I2C_MUX=y
  66 +CONFIG_I2C_MUX_PCA954x=y
  67 +CONFIG_MISC=y
  68 +CONFIG_DM_MMC=y
  69 +CONFIG_SUPPORT_EMMC_BOOT=y
  70 +CONFIG_FSL_USDHC=y
  71 +CONFIG_MMC_IO_VOLTAGE=y
  72 +CONFIG_MMC_UHS_SUPPORT=y
  73 +CONFIG_MMC_HS400_ES_SUPPORT=y
  74 +CONFIG_EFI_PARTITION=y
  75 +CONFIG_PHYLIB=y
  76 +CONFIG_PHY_ADDR_ENABLE=y
  77 +CONFIG_PHY_ATHEROS=y
  78 +CONFIG_DM_ETH=y
  79 +CONFIG_DM_ETH_PHY=y
  80 +CONFIG_PHY_GIGE=y
  81 +CONFIG_FEC_MXC=y
  82 +CONFIG_MII=y
  83 +CONFIG_PINCTRL=y
  84 +CONFIG_SPL_PINCTRL=y
  85 +CONFIG_PINCTRL_IMX8=y
  86 +CONFIG_POWER_DOMAIN=y
  87 +CONFIG_IMX8_POWER_DOMAIN=y
  88 +CONFIG_DM_REGULATOR=y
  89 +CONFIG_DM_REGULATOR_FIXED=y
  90 +CONFIG_DM_REGULATOR_GPIO=y
  91 +CONFIG_DM_SERIAL=y
  92 +CONFIG_FSL_LPUART=y
  93 +CONFIG_SPL_TINY_MEMSET=y
  94 +# CONFIG_EFI_LOADER is not set
  95 +
  96 +CONFIG_CMD_FUSE=y
  97 +CONFIG_CMD_MEMTEST=y
  98 +
  99 +CONFIG_IMX_BOOTAUX=y
  100 +
  101 +CONFIG_DM_THERMAL=y
  102 +CONFIG_IMX_SCU_THERMAL=y
  103 +
  104 +CONFIG_SPI=y
  105 +CONFIG_FSL_FSPI=y
  106 +CONFIG_DM_SPI=y
  107 +CONFIG_DM_SPI_FLASH=y
  108 +CONFIG_SPI_FLASH=y
  109 +CONFIG_SPI_FLASH_STMICRO=y
  110 +CONFIG_CMD_SF=y
  111 +CONFIG_SF_DEFAULT_BUS=0
  112 +CONFIG_SF_DEFAULT_CS=0
  113 +CONFIG_SF_DEFAULT_SPEED=40000000
  114 +CONFIG_SF_DEFAULT_MODE=0
  115 +
  116 +CONFIG_DM_USB=y
  117 +CONFIG_DM_USB_GADGET=y
  118 +CONFIG_SPL_DM_USB_GADGET=y
  119 +CONFIG_USB=y
  120 +CONFIG_USB_TCPC=y
  121 +CONFIG_USB_GADGET=y
  122 +CONFIG_CI_UDC=y
  123 +CONFIG_USB_GADGET_DOWNLOAD=y
  124 +CONFIG_USB_GADGET_MANUFACTURER="FSL"
  125 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
  126 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
  127 +# CONFIG_USB_CDNS3=y
  128 +# CONFIG_USB_CDNS3_GADGET=y
  129 +# CONFIG_USB_GADGET_DUALSPEED=y
  130 +
  131 +CONFIG_SPL_USB_GADGET=y
  132 +CONFIG_SPL_USB_SDP_SUPPORT=y
  133 +CONFIG_SPL_SDP_USB_DEV=0
  134 +CONFIG_SDP_LOADADDR=0x80400000
  135 +
  136 +CONFIG_FASTBOOT=y
  137 +CONFIG_USB_FUNCTION_FASTBOOT=y
  138 +CONFIG_CMD_FASTBOOT=y
  139 +CONFIG_ANDROID_BOOT_IMAGE=y
  140 +CONFIG_FASTBOOT_UUU_SUPPORT=y
  141 +CONFIG_FASTBOOT_BUF_ADDR=0x82800000
  142 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000
  143 +CONFIG_FASTBOOT_FLASH=y
  144 +CONFIG_FASTBOOT_USB_DEV=0
  145 +
  146 +CONFIG_USB_PORT_AUTO=y
configs/imx8qxp_ddr3_val_defconfig
Diff comments   View file @ c251cbe
  1 +CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_ICACHE_OFF=y
  3 +CONFIG_SPL_SYS_DCACHE_OFF=y
  4 +CONFIG_ARCH_IMX8=y
  5 +CONFIG_SYS_TEXT_BASE=0x80020000
  6 +CONFIG_SPL_GPIO_SUPPORT=y
  7 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  8 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  9 +CONFIG_SYS_MALLOC_F_LEN=0x8000
  10 +CONFIG_ENV_SIZE=0x2000
  11 +CONFIG_ENV_OFFSET=0x400000
  12 +CONFIG_DM_GPIO=y
  13 +CONFIG_SPL_LOAD_IMX_CONTAINER=y
  14 +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg"
  15 +CONFIG_TARGET_IMX8QXP_DDR3_VAL=y
  16 +CONFIG_SPL_MMC_SUPPORT=y
  17 +CONFIG_SPL_EFI_PARTITION=n
  18 +CONFIG_SPL_DOS_PARTITION=n
  19 +CONFIG_SPL_DM_SEQ_ALIAS=y
  20 +CONFIG_SPL_SERIAL_SUPPORT=y
  21 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
  22 +CONFIG_USE_TINY_PRINTF=y
  23 +CONFIG_NR_DRAM_BANKS=4
  24 +CONFIG_SPL=y
  25 +CONFIG_PANIC_HANG=y
  26 +CONFIG_SPL_TEXT_BASE=0x100000
  27 +CONFIG_OF_SYSTEM_SETUP=y
  28 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_val/imximage.cfg"
  29 +CONFIG_BOOTDELAY=3
  30 +CONFIG_LOG=y
  31 +CONFIG_SPL_BOARD_INIT=y
  32 +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
  33 +CONFIG_SPL_SEPARATE_BSS=y
  34 +CONFIG_SPL_POWER_SUPPORT=y
  35 +CONFIG_SPL_POWER_DOMAIN=y
  36 +CONFIG_SPL_WATCHDOG_SUPPORT=y
  37 +CONFIG_HUSH_PARSER=y
  38 +CONFIG_CMD_CPU=y
  39 +# CONFIG_BOOTM_NETBSD is not set
  40 +# CONFIG_CMD_IMPORTENV is not set
  41 +CONFIG_CMD_CLK=y
  42 +CONFIG_CMD_DM=y
  43 +CONFIG_CMD_GPIO=y
  44 +CONFIG_CMD_I2C=y
  45 +CONFIG_CMD_MMC=y
  46 +CONFIG_CMD_DHCP=y
  47 +CONFIG_CMD_MII=y
  48 +CONFIG_CMD_PING=y
  49 +CONFIG_CMD_CACHE=y
  50 +CONFIG_CMD_FAT=y
  51 +CONFIG_SPL_OF_CONTROL=y
  52 +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-val"
  53 +CONFIG_DEFAULT_FDT_FILE="imx8qxp-ddr3l-val.dtb"
  54 +CONFIG_ENV_IS_IN_MMC=y
  55 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  56 +CONFIG_NET_RANDOM_ETHADDR=y
  57 +CONFIG_SPL_DM=y
  58 +CONFIG_SPL_CLK=y
  59 +CONFIG_CLK_IMX8=y
  60 +CONFIG_CPU=y
  61 +CONFIG_MXC_GPIO=y
  62 +CONFIG_DM_PCA953X=y
  63 +CONFIG_DM_I2C=y
  64 +CONFIG_SYS_I2C_IMX_LPI2C=y
  65 +CONFIG_I2C_MUX=y
  66 +CONFIG_I2C_MUX_PCA954x=y
  67 +CONFIG_MISC=y
  68 +CONFIG_DM_MMC=y
  69 +CONFIG_SUPPORT_EMMC_BOOT=y
  70 +CONFIG_FSL_USDHC=y
  71 +CONFIG_MMC_IO_VOLTAGE=y
  72 +CONFIG_MMC_UHS_SUPPORT=y
  73 +CONFIG_MMC_HS400_ES_SUPPORT=y
  74 +CONFIG_EFI_PARTITION=y
  75 +CONFIG_PHYLIB=y
  76 +CONFIG_PHY_ADDR_ENABLE=y
  77 +CONFIG_PHY_ATHEROS=y
  78 +CONFIG_DM_ETH=y
  79 +CONFIG_DM_ETH_PHY=y
  80 +CONFIG_PHY_GIGE=y
  81 +CONFIG_FEC_MXC=y
  82 +CONFIG_MII=y
  83 +CONFIG_PINCTRL=y
  84 +CONFIG_SPL_PINCTRL=y
  85 +CONFIG_PINCTRL_IMX8=y
  86 +CONFIG_POWER_DOMAIN=y
  87 +CONFIG_IMX8_POWER_DOMAIN=y
  88 +CONFIG_DM_REGULATOR=y
  89 +CONFIG_SPL_DM_REGULATOR=y
  90 +CONFIG_DM_REGULATOR_FIXED=y
  91 +CONFIG_DM_REGULATOR_GPIO=y
  92 +CONFIG_SPL_DM_REGULATOR_FIXED=y
  93 +CONFIG_DM_SERIAL=y
  94 +CONFIG_FSL_LPUART=y
  95 +CONFIG_SPL_TINY_MEMSET=y
  96 +# CONFIG_EFI_LOADER is not set
  97 +
  98 +CONFIG_CMD_FUSE=y
  99 +CONFIG_CMD_MEMTEST=y
  100 +
  101 +CONFIG_IMX_BOOTAUX=y
  102 +
  103 +CONFIG_DM_THERMAL=y
  104 +CONFIG_IMX_SCU_THERMAL=y
  105 +
  106 +CONFIG_SPI=y
  107 +CONFIG_FSL_FSPI=y
  108 +CONFIG_DM_SPI=y
  109 +CONFIG_DM_SPI_FLASH=y
  110 +CONFIG_SPI_FLASH=y
  111 +CONFIG_SPI_FLASH_STMICRO=y
  112 +CONFIG_CMD_SF=y
  113 +CONFIG_SF_DEFAULT_BUS=0
  114 +CONFIG_SF_DEFAULT_CS=0
  115 +CONFIG_SF_DEFAULT_SPEED=40000000
  116 +CONFIG_SF_DEFAULT_MODE=0
  117 +
  118 +CONFIG_USB_XHCI_HCD=y
  119 +CONFIG_USB_XHCI_IMX8=y
  120 +CONFIG_DM_USB=y
  121 +CONFIG_DM_USB_GADGET=y
  122 +CONFIG_SPL_DM_USB_GADGET=y
  123 +CONFIG_USB=y
  124 +CONFIG_USB_TCPC=y
  125 +CONFIG_USB_GADGET=y
  126 +CONFIG_CI_UDC=y
  127 +CONFIG_USB_GADGET_DOWNLOAD=y
  128 +CONFIG_USB_GADGET_MANUFACTURER="FSL"
  129 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
  130 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
  131 +CONFIG_USB_CDNS3=y
  132 +CONFIG_USB_CDNS3_GADGET=y
  133 +CONFIG_USB_GADGET_DUALSPEED=y
  134 +CONFIG_CDNS3_USB_PHY=y
  135 +CONFIG_PHY=y
  136 +CONFIG_SPL_PHY=y
  137 +
  138 +CONFIG_SPL_USB_GADGET=y
  139 +CONFIG_SPL_USB_SDP_SUPPORT=y
  140 +CONFIG_SPL_SDP_USB_DEV=1
  141 +CONFIG_SDP_LOADADDR=0x80400000
  142 +
  143 +CONFIG_FASTBOOT=y
  144 +CONFIG_USB_FUNCTION_FASTBOOT=y
  145 +CONFIG_CMD_FASTBOOT=y
  146 +CONFIG_ANDROID_BOOT_IMAGE=y
  147 +CONFIG_FASTBOOT_UUU_SUPPORT=y
  148 +CONFIG_FASTBOOT_BUF_ADDR=0x82800000
  149 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000
  150 +CONFIG_FASTBOOT_FLASH=y
  151 +CONFIG_FASTBOOT_USB_DEV=1
  152 +
  153 +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
  154 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
  155 +
  156 +CONFIG_USB_PORT_AUTO=y
  157 +
  158 +CONFIG_SNVS_SEC_SC=y
configs/imx8qxp_lpddr4_val_defconfig
Diff comments   View file @ c251cbe
  1 +CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_ICACHE_OFF=y
  3 +CONFIG_SPL_SYS_DCACHE_OFF=y
  4 +CONFIG_ARCH_IMX8=y
  5 +CONFIG_SYS_TEXT_BASE=0x80020000
  6 +CONFIG_SPL_GPIO_SUPPORT=y
  7 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  8 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  9 +CONFIG_SYS_MALLOC_F_LEN=0x8000
  10 +CONFIG_ENV_SIZE=0x2000
  11 +CONFIG_ENV_OFFSET=0x400000
  12 +CONFIG_DM_GPIO=y
  13 +CONFIG_SPL_LOAD_IMX_CONTAINER=y
  14 +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg"
  15 +CONFIG_TARGET_IMX8QXP_LPDDR4_VAL=y
  16 +CONFIG_SPL_MMC_SUPPORT=y
  17 +CONFIG_SPL_EFI_PARTITION=n
  18 +CONFIG_SPL_DOS_PARTITION=n
  19 +CONFIG_SPL_DM_SEQ_ALIAS=y
  20 +CONFIG_SPL_SERIAL_SUPPORT=y
  21 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
  22 +CONFIG_USE_TINY_PRINTF=y
  23 +CONFIG_NR_DRAM_BANKS=4
  24 +CONFIG_SPL=y
  25 +CONFIG_PANIC_HANG=y
  26 +CONFIG_SPL_TEXT_BASE=0x100000
  27 +CONFIG_OF_SYSTEM_SETUP=y
  28 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_val/imximage.cfg"
  29 +CONFIG_BOOTDELAY=3
  30 +CONFIG_LOG=y
  31 +CONFIG_SPL_BOARD_INIT=y
  32 +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
  33 +CONFIG_SPL_SEPARATE_BSS=y
  34 +CONFIG_SPL_POWER_SUPPORT=y
  35 +CONFIG_SPL_POWER_DOMAIN=y
  36 +CONFIG_SPL_WATCHDOG_SUPPORT=y
  37 +CONFIG_HUSH_PARSER=y
  38 +CONFIG_CMD_CPU=y
  39 +# CONFIG_BOOTM_NETBSD is not set
  40 +# CONFIG_CMD_IMPORTENV is not set
  41 +CONFIG_CMD_CLK=y
  42 +CONFIG_CMD_DM=y
  43 +CONFIG_CMD_GPIO=y
  44 +CONFIG_CMD_I2C=y
  45 +CONFIG_CMD_MMC=y
  46 +CONFIG_CMD_DHCP=y
  47 +CONFIG_CMD_MII=y
  48 +CONFIG_CMD_PING=y
  49 +CONFIG_CMD_CACHE=y
  50 +CONFIG_CMD_FAT=y
  51 +CONFIG_SPL_OF_CONTROL=y
  52 +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-val"
  53 +CONFIG_DEFAULT_FDT_FILE="imx8qxp-lpddr4-val.dtb"
  54 +CONFIG_ENV_IS_IN_MMC=y
  55 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  56 +CONFIG_NET_RANDOM_ETHADDR=y
  57 +CONFIG_SPL_DM=y
  58 +CONFIG_SPL_CLK=y
  59 +CONFIG_CLK_IMX8=y
  60 +CONFIG_CPU=y
  61 +CONFIG_MXC_GPIO=y
  62 +CONFIG_DM_PCA953X=y
  63 +CONFIG_DM_I2C=y
  64 +CONFIG_SYS_I2C_IMX_LPI2C=y
  65 +CONFIG_I2C_MUX=y
  66 +CONFIG_I2C_MUX_PCA954x=y
  67 +CONFIG_MISC=y
  68 +CONFIG_DM_MMC=y
  69 +CONFIG_SUPPORT_EMMC_BOOT=y
  70 +CONFIG_FSL_USDHC=y
  71 +CONFIG_MMC_IO_VOLTAGE=y
  72 +CONFIG_MMC_UHS_SUPPORT=y
  73 +CONFIG_MMC_HS400_ES_SUPPORT=y
  74 +CONFIG_EFI_PARTITION=y
  75 +CONFIG_PHYLIB=y
  76 +CONFIG_PHY_ADDR_ENABLE=y
  77 +CONFIG_PHY_ATHEROS=y
  78 +CONFIG_DM_ETH=y
  79 +CONFIG_DM_ETH_PHY=y
  80 +CONFIG_PHY_GIGE=y
  81 +CONFIG_FEC_MXC=y
  82 +CONFIG_MII=y
  83 +CONFIG_PINCTRL=y
  84 +CONFIG_SPL_PINCTRL=y
  85 +CONFIG_PINCTRL_IMX8=y
  86 +CONFIG_POWER_DOMAIN=y
  87 +CONFIG_IMX8_POWER_DOMAIN=y
  88 +CONFIG_DM_REGULATOR=y
  89 +CONFIG_SPL_DM_REGULATOR=y
  90 +CONFIG_DM_REGULATOR_FIXED=y
  91 +CONFIG_DM_REGULATOR_GPIO=y
  92 +CONFIG_SPL_DM_REGULATOR_FIXED=y
  93 +CONFIG_DM_SERIAL=y
  94 +CONFIG_FSL_LPUART=y
  95 +CONFIG_SPL_TINY_MEMSET=y
  96 +# CONFIG_EFI_LOADER is not set
  97 +
  98 +CONFIG_CMD_FUSE=y
  99 +CONFIG_CMD_MEMTEST=y
  100 +
  101 +CONFIG_IMX_BOOTAUX=y
  102 +
  103 +CONFIG_DM_THERMAL=y
  104 +CONFIG_IMX_SCU_THERMAL=y
  105 +
  106 +CONFIG_SPI=y
  107 +CONFIG_FSL_FSPI=y
  108 +CONFIG_DM_SPI=y
  109 +CONFIG_DM_SPI_FLASH=y
  110 +CONFIG_SPI_FLASH=y
  111 +CONFIG_SPI_FLASH_STMICRO=y
  112 +CONFIG_CMD_SF=y
  113 +CONFIG_SF_DEFAULT_BUS=0
  114 +CONFIG_SF_DEFAULT_CS=0
  115 +CONFIG_SF_DEFAULT_SPEED=40000000
  116 +CONFIG_SF_DEFAULT_MODE=0
  117 +
  118 +CONFIG_USB_XHCI_HCD=y
  119 +CONFIG_USB_XHCI_IMX8=y
  120 +CONFIG_DM_USB=y
  121 +CONFIG_DM_USB_GADGET=y
  122 +CONFIG_SPL_DM_USB_GADGET=y
  123 +CONFIG_USB=y
  124 +CONFIG_USB_TCPC=y
  125 +CONFIG_USB_GADGET=y
  126 +CONFIG_CI_UDC=y
  127 +CONFIG_USB_GADGET_DOWNLOAD=y
  128 +CONFIG_USB_GADGET_MANUFACTURER="FSL"
  129 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
  130 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
  131 +CONFIG_USB_CDNS3=y
  132 +CONFIG_USB_CDNS3_GADGET=y
  133 +CONFIG_USB_GADGET_DUALSPEED=y
  134 +CONFIG_CDNS3_USB_PHY=y
  135 +CONFIG_PHY=y
  136 +CONFIG_SPL_PHY=y
  137 +
  138 +CONFIG_SPL_USB_GADGET=y
  139 +CONFIG_SPL_USB_SDP_SUPPORT=y
  140 +CONFIG_SPL_SDP_USB_DEV=1
  141 +CONFIG_SDP_LOADADDR=0x80400000
  142 +
  143 +CONFIG_FASTBOOT=y
  144 +CONFIG_USB_FUNCTION_FASTBOOT=y
  145 +CONFIG_CMD_FASTBOOT=y
  146 +CONFIG_ANDROID_BOOT_IMAGE=y
  147 +CONFIG_FASTBOOT_UUU_SUPPORT=y
  148 +CONFIG_FASTBOOT_BUF_ADDR=0x82800000
  149 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000
  150 +CONFIG_FASTBOOT_FLASH=y
  151 +CONFIG_FASTBOOT_USB_DEV=1
  152 +
  153 +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
  154 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
  155 +
  156 +CONFIG_USB_PORT_AUTO=y
  157 +
  158 +CONFIG_SNVS_SEC_SC=y
configs/imx8qxp_lpddr4_val_fspi_defconfig
Diff comments   View file @ c251cbe
  1 +CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_ICACHE_OFF=y
  3 +CONFIG_SPL_SYS_DCACHE_OFF=y
  4 +CONFIG_ARCH_IMX8=y
  5 +CONFIG_SYS_TEXT_BASE=0x80020000
  6 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  7 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  8 +CONFIG_SYS_MALLOC_F_LEN=0x8000
  9 +CONFIG_ENV_SIZE=0x2000
  10 +CONFIG_ENV_OFFSET=0x400000
  11 +CONFIG_ENV_SECT_SIZE=0x20000
  12 +CONFIG_DM_GPIO=y
  13 +CONFIG_SPL_LOAD_IMX_CONTAINER=y
  14 +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg"
  15 +CONFIG_TARGET_IMX8QXP_LPDDR4_VAL=y
  16 +CONFIG_SPL_SPI_FLASH_SUPPORT=y
  17 +CONFIG_SPL_SPI_SUPPORT=y
  18 +CONFIG_SPL_SPI_LOAD=y
  19 +CONFIG_SPL_SPI_FLASH_TINY=y
  20 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000
  21 +CONFIG_SPL_EFI_PARTITION=n
  22 +CONFIG_SPL_DOS_PARTITION=n
  23 +CONFIG_SPL_DM_SEQ_ALIAS=y
  24 +CONFIG_SPL_SERIAL_SUPPORT=y
  25 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
  26 +CONFIG_USE_TINY_PRINTF=y
  27 +CONFIG_NR_DRAM_BANKS=4
  28 +CONFIG_SPL=y
  29 +CONFIG_PANIC_HANG=y
  30 +CONFIG_SPL_TEXT_BASE=0x100000
  31 +CONFIG_OF_SYSTEM_SETUP=y
  32 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_val/imximage.cfg"
  33 +CONFIG_BOOTDELAY=3
  34 +CONFIG_LOG=y
  35 +CONFIG_SPL_BOARD_INIT=y
  36 +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
  37 +CONFIG_SPL_SEPARATE_BSS=y
  38 +CONFIG_SPL_POWER_SUPPORT=y
  39 +CONFIG_SPL_POWER_DOMAIN=y
  40 +CONFIG_SPL_WATCHDOG_SUPPORT=y
  41 +CONFIG_HUSH_PARSER=y
  42 +CONFIG_CMD_CPU=y
  43 +# CONFIG_BOOTM_NETBSD is not set
  44 +# CONFIG_CMD_IMPORTENV is not set
  45 +CONFIG_CMD_CLK=y
  46 +CONFIG_CMD_DM=y
  47 +CONFIG_CMD_GPIO=y
  48 +CONFIG_CMD_I2C=y
  49 +CONFIG_CMD_MMC=y
  50 +CONFIG_CMD_DHCP=y
  51 +CONFIG_CMD_MII=y
  52 +CONFIG_CMD_PING=y
  53 +CONFIG_CMD_CACHE=y
  54 +CONFIG_CMD_FAT=y
  55 +CONFIG_SPL_OF_CONTROL=y
  56 +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-val"
  57 +CONFIG_DEFAULT_FDT_FILE="imx8qxp-lpddr4-val.dtb"
  58 +CONFIG_ENV_IS_IN_SPI_FLASH=y
  59 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  60 +CONFIG_NET_RANDOM_ETHADDR=y
  61 +CONFIG_SPL_DM=y
  62 +CONFIG_SPL_CLK=y
  63 +CONFIG_CLK_IMX8=y
  64 +CONFIG_CPU=y
  65 +CONFIG_MXC_GPIO=y
  66 +CONFIG_DM_PCA953X=y
  67 +CONFIG_DM_I2C=y
  68 +CONFIG_SYS_I2C_IMX_LPI2C=y
  69 +CONFIG_I2C_MUX=y
  70 +CONFIG_I2C_MUX_PCA954x=y
  71 +CONFIG_MISC=y
  72 +CONFIG_DM_MMC=y
  73 +CONFIG_SUPPORT_EMMC_BOOT=y
  74 +CONFIG_FSL_USDHC=y
  75 +CONFIG_MMC_IO_VOLTAGE=y
  76 +CONFIG_MMC_UHS_SUPPORT=y
  77 +CONFIG_MMC_HS400_ES_SUPPORT=y
  78 +CONFIG_EFI_PARTITION=y
  79 +CONFIG_PHYLIB=y
  80 +CONFIG_PHY_ADDR_ENABLE=y
  81 +CONFIG_PHY_ATHEROS=y
  82 +CONFIG_DM_ETH=y
  83 +CONFIG_DM_ETH_PHY=y
  84 +CONFIG_PHY_GIGE=y
  85 +CONFIG_FEC_MXC=y
  86 +CONFIG_MII=y
  87 +CONFIG_PINCTRL=y
  88 +CONFIG_SPL_PINCTRL=y
  89 +CONFIG_PINCTRL_IMX8=y
  90 +CONFIG_POWER_DOMAIN=y
  91 +CONFIG_IMX8_POWER_DOMAIN=y
  92 +CONFIG_DM_REGULATOR=y
  93 +CONFIG_DM_REGULATOR_FIXED=y
  94 +CONFIG_DM_REGULATOR_GPIO=y
  95 +CONFIG_DM_SERIAL=y
  96 +CONFIG_FSL_LPUART=y
  97 +CONFIG_SPL_TINY_MEMSET=y
  98 +# CONFIG_EFI_LOADER is not set
  99 +
  100 +CONFIG_CMD_FUSE=y
  101 +CONFIG_CMD_MEMTEST=y
  102 +
  103 +CONFIG_IMX_BOOTAUX=y
  104 +
  105 +CONFIG_DM_THERMAL=y
  106 +CONFIG_IMX_SCU_THERMAL=y
  107 +
  108 +CONFIG_QSPI_BOOT=y
  109 +CONFIG_SPI=y
  110 +CONFIG_FSL_FSPI=y
  111 +CONFIG_DM_SPI=y
  112 +CONFIG_DM_SPI_FLASH=y
  113 +CONFIG_SPI_FLASH=y
  114 +CONFIG_SPI_FLASH_STMICRO=y
  115 +CONFIG_CMD_SF=y
  116 +CONFIG_SF_DEFAULT_BUS=0
  117 +CONFIG_SF_DEFAULT_CS=0
  118 +CONFIG_SF_DEFAULT_SPEED=40000000
  119 +CONFIG_SF_DEFAULT_MODE=0
  120 +
  121 +CONFIG_USB_XHCI_HCD=y
  122 +CONFIG_USB_XHCI_IMX8=y
  123 +CONFIG_DM_USB=y
  124 +CONFIG_DM_USB_GADGET=y
  125 +CONFIG_SPL_DM_USB_GADGET=y
  126 +CONFIG_USB=y
  127 +CONFIG_USB_TCPC=y
  128 +CONFIG_USB_GADGET=y
  129 +CONFIG_CI_UDC=y
  130 +CONFIG_USB_GADGET_DOWNLOAD=y
  131 +CONFIG_USB_GADGET_MANUFACTURER="FSL"
  132 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
  133 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
  134 +CONFIG_USB_CDNS3=y
  135 +CONFIG_USB_CDNS3_GADGET=y
  136 +CONFIG_USB_GADGET_DUALSPEED=y
  137 +CONFIG_CDNS3_USB_PHY=y
  138 +CONFIG_PHY=y
  139 +CONFIG_SPL_PHY=y
  140 +
  141 +CONFIG_SPL_USB_GADGET=y
  142 +CONFIG_SPL_USB_SDP_SUPPORT=y
  143 +CONFIG_SPL_SDP_USB_DEV=1
  144 +CONFIG_SDP_LOADADDR=0x80400000
  145 +
  146 +CONFIG_FASTBOOT=y
  147 +CONFIG_USB_FUNCTION_FASTBOOT=y
  148 +CONFIG_CMD_FASTBOOT=y
  149 +CONFIG_ANDROID_BOOT_IMAGE=y
  150 +CONFIG_FASTBOOT_UUU_SUPPORT=y
  151 +CONFIG_FASTBOOT_BUF_ADDR=0x82800000
  152 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000
  153 +CONFIG_FASTBOOT_FLASH=y
  154 +CONFIG_FASTBOOT_USB_DEV=1
  155 +
  156 +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
  157 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
  158 +
  159 +CONFIG_USB_PORT_AUTO=y
  160 +
  161 +CONFIG_SNVS_SEC_SC=y
configs/imx8qxp_lpddr4_val_nand_defconfig
Diff comments   View file @ c251cbe
  1 +CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_ICACHE_OFF=y
  3 +CONFIG_SPL_SYS_DCACHE_OFF=y
  4 +CONFIG_ARCH_IMX8=y
  5 +CONFIG_SYS_TEXT_BASE=0x80020000
  6 +CONFIG_SPL_GPIO_SUPPORT=y
  7 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  8 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  9 +CONFIG_SYS_MALLOC_F_LEN=0x8000
  10 +CONFIG_ENV_SIZE=0x2000
  11 +CONFIG_ENV_OFFSET=0x7800000
  12 +CONFIG_DM_GPIO=y
  13 +CONFIG_SPL_LOAD_IMX_CONTAINER=y
  14 +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg"
  15 +CONFIG_TARGET_IMX8QXP_LPDDR4_VAL=y
  16 +CONFIG_SPL_NAND_SUPPORT=y
  17 +CONFIG_SPL_DMA=y
  18 +CONFIG_SPL_SERIAL_SUPPORT=y
  19 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
  20 +CONFIG_USE_TINY_PRINTF=y
  21 +CONFIG_NR_DRAM_BANKS=4
  22 +CONFIG_SPL=y
  23 +CONFIG_PANIC_HANG=y
  24 +CONFIG_SPL_TEXT_BASE=0x100000
  25 +CONFIG_OF_SYSTEM_SETUP=y
  26 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_val/imximage.cfg"
  27 +CONFIG_BOOTDELAY=3
  28 +CONFIG_LOG=y
  29 +CONFIG_SPL_BOARD_INIT=y
  30 +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
  31 +CONFIG_SPL_SEPARATE_BSS=y
  32 +CONFIG_SPL_POWER_SUPPORT=y
  33 +CONFIG_SPL_POWER_DOMAIN=y
  34 +CONFIG_SPL_WATCHDOG_SUPPORT=y
  35 +CONFIG_HUSH_PARSER=y
  36 +CONFIG_CMD_CPU=y
  37 +# CONFIG_BOOTM_NETBSD is not set
  38 +# CONFIG_CMD_IMPORTENV is not set
  39 +CONFIG_CMD_CLK=y
  40 +CONFIG_CMD_DM=y
  41 +CONFIG_CMD_GPIO=y
  42 +CONFIG_CMD_I2C=y
  43 +CONFIG_CMD_NAND=y
  44 +CONFIG_CMD_DHCP=y
  45 +CONFIG_CMD_MII=y
  46 +CONFIG_CMD_PING=y
  47 +CONFIG_CMD_CACHE=y
  48 +CONFIG_CMD_FAT=y
  49 +CONFIG_SPL_OF_CONTROL=y
  50 +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-val-gpmi-nand"
  51 +CONFIG_DEFAULT_FDT_FILE="imx8qxp-lpddr4-val-gpmi-nand.dtb"
  52 +CONFIG_ENV_IS_IN_NAND=y
  53 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  54 +CONFIG_NET_RANDOM_ETHADDR=y
  55 +CONFIG_SPL_DM=y
  56 +CONFIG_SPL_CLK=y
  57 +CONFIG_CLK_IMX8=y
  58 +CONFIG_CPU=y
  59 +CONFIG_MXC_GPIO=y
  60 +CONFIG_DM_PCA953X=y
  61 +CONFIG_DM_I2C=y
  62 +CONFIG_SYS_I2C_IMX_LPI2C=y
  63 +CONFIG_I2C_MUX=y
  64 +CONFIG_I2C_MUX_PCA954x=y
  65 +CONFIG_MISC=y
  66 +CONFIG_DM_MMC=y
  67 +CONFIG_EFI_PARTITION=y
  68 +CONFIG_PHYLIB=y
  69 +CONFIG_PHY_ADDR_ENABLE=y
  70 +CONFIG_PHY_ATHEROS=y
  71 +CONFIG_DM_ETH=y
  72 +CONFIG_DM_ETH_PHY=y
  73 +CONFIG_PHY_GIGE=y
  74 +CONFIG_FEC_MXC=y
  75 +CONFIG_MII=y
  76 +CONFIG_PINCTRL=y
  77 +CONFIG_SPL_PINCTRL=y
  78 +CONFIG_PINCTRL_IMX8=y
  79 +CONFIG_POWER_DOMAIN=y
  80 +CONFIG_IMX8_POWER_DOMAIN=y
  81 +CONFIG_DM_REGULATOR=y
  82 +CONFIG_DM_REGULATOR_FIXED=y
  83 +CONFIG_DM_REGULATOR_GPIO=y
  84 +CONFIG_DM_SERIAL=y
  85 +CONFIG_FSL_LPUART=y
  86 +CONFIG_SPL_TINY_MEMSET=y
  87 +# CONFIG_EFI_LOADER is not set
  88 +
  89 +CONFIG_CMD_FUSE=y
  90 +CONFIG_CMD_MEMTEST=y
  91 +
  92 +CONFIG_IMX_BOOTAUX=y
  93 +
  94 +CONFIG_DM_THERMAL=y
  95 +CONFIG_IMX_SCU_THERMAL=y
  96 +
  97 +CONFIG_SPI=y
  98 +CONFIG_FSL_FSPI=y
  99 +CONFIG_DM_SPI=y
  100 +CONFIG_DM_SPI_FLASH=y
  101 +CONFIG_SPI_FLASH=y
  102 +CONFIG_SPI_FLASH_STMICRO=y
  103 +CONFIG_CMD_SF=y
  104 +CONFIG_SF_DEFAULT_BUS=0
  105 +CONFIG_SF_DEFAULT_CS=0
  106 +CONFIG_SF_DEFAULT_SPEED=40000000
  107 +CONFIG_SF_DEFAULT_MODE=0
  108 +
  109 +CONFIG_USB_XHCI_HCD=y
  110 +CONFIG_USB_XHCI_IMX8=y
  111 +CONFIG_DM_USB=y
  112 +CONFIG_DM_USB_GADGET=y
  113 +CONFIG_SPL_DM_USB_GADGET=y
  114 +CONFIG_USB=y
  115 +CONFIG_USB_TCPC=y
  116 +CONFIG_USB_GADGET=y
  117 +CONFIG_CI_UDC=y
  118 +CONFIG_USB_GADGET_DOWNLOAD=y
  119 +CONFIG_USB_GADGET_MANUFACTURER="FSL"
  120 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
  121 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
  122 +CONFIG_USB_CDNS3=y
  123 +CONFIG_USB_CDNS3_GADGET=y
  124 +CONFIG_USB_GADGET_DUALSPEED=y
  125 +CONFIG_CDNS3_USB_PHY=y
  126 +CONFIG_PHY=y
  127 +CONFIG_SPL_PHY=y
  128 +
  129 +CONFIG_NAND_BOOT=y
  130 +CONFIG_CMD_UBI=y
  131 +
  132 +CONFIG_MTD=y
  133 +CONFIG_DM_MTD=y
  134 +CONFIG_NAND=y
  135 +CONFIG_NAND_MXS=y
  136 +CONFIG_NAND_MXS_DT=y
  137 +CONFIG_CMD_MTDPARTS=y
  138 +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
  139 +CONFIG_MTDPARTS_SKIP_INVALID=y
  140 +
  141 +CONFIG_SPL_USB_GADGET=y
  142 +CONFIG_SPL_USB_SDP_SUPPORT=y
  143 +CONFIG_SPL_SDP_USB_DEV=1
  144 +CONFIG_SDP_LOADADDR=0x80400000
  145 +
  146 +CONFIG_FASTBOOT=y
  147 +CONFIG_USB_FUNCTION_FASTBOOT=y
  148 +CONFIG_CMD_FASTBOOT=y
  149 +CONFIG_ANDROID_BOOT_IMAGE=y
  150 +CONFIG_FASTBOOT_UUU_SUPPORT=y
  151 +CONFIG_FASTBOOT_BUF_ADDR=0x82800000
  152 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000
  153 +CONFIG_FASTBOOT_FLASH=y
  154 +CONFIG_FASTBOOT_USB_DEV=1
  155 +
  156 +CONFIG_USB_PORT_AUTO=y
  157 +
  158 +CONFIG_SNVS_SEC_SC=y
include/configs/imx8qxp_val.h
Diff comments   View file @ c251cbe
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +#ifndef __IMX8QXP_VAL_H
  7 +#define __IMX8QXP_VAL_H
  8 +
  9 +#include <linux/sizes.h>
  10 +#include <asm/arch/imx-regs.h>
  11 +
  12 +#include "imx_env.h"
  13 +
  14 +#ifdef CONFIG_SPL_BUILD
  15 +#define CONFIG_SPL_MAX_SIZE (192 * 1024)
  16 +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
  17 +
  18 +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0x8000000) /*Put the FIT out of first 128MB boot area */
  19 +#define CONFIG_SPL_NAND_BASE
  20 +#define CONFIG_SPL_NAND_IDENT
  21 +
  22 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  23 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (32K + 2Mb)/sector_size */
  24 +
  25 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
  26 +
  27 +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
  28 +/*
  29 + * The memory layout on stack: DATA section save + gd + early malloc
  30 + * the idea is re-use the early malloc (CONFIG_SYS_MALLOC_F_LEN) with
  31 + * CONFIG_SYS_SPL_MALLOC_START
  32 + */
  33 +#define CONFIG_SPL_STACK 0x013fff0
  34 +#define CONFIG_SPL_BSS_START_ADDR 0x00130000
  35 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
  36 +#define CONFIG_SYS_SPL_MALLOC_START 0x82200000
  37 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
  38 +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
  39 +#define CONFIG_MALLOC_F_ADDR 0x00138000
  40 +
  41 +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
  42 +
  43 +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
  44 +
  45 +#define CONFIG_OF_EMBED
  46 +#endif
  47 +
  48 +#define CONFIG_REMAKE_ELF
  49 +
  50 +#define CONFIG_BOARD_EARLY_INIT_F
  51 +
  52 +#define CONFIG_CMD_READ
  53 +
  54 +/* Flat Device Tree Definitions */
  55 +#define CONFIG_OF_BOARD_SETUP
  56 +
  57 +#undef CONFIG_CMD_EXPORTENV
  58 +#undef CONFIG_CMD_IMPORTENV
  59 +#undef CONFIG_CMD_IMLS
  60 +
  61 +#undef CONFIG_CMD_CRC32
  62 +
  63 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  64 +#define USDHC1_BASE_ADDR 0x5B010000
  65 +#define USDHC2_BASE_ADDR 0x5B020000
  66 +
  67 +#define CONFIG_ENV_OVERWRITE
  68 +
  69 +#define CONFIG_FSL_HSIO
  70 +#ifdef CONFIG_FSL_HSIO
  71 +#define CONFIG_PCIE_IMX8X
  72 +#define CONFIG_CMD_PCI
  73 +#define CONFIG_PCI
  74 +#define CONFIG_PCI_PNP
  75 +#define CONFIG_PCI_SCAN_SHOW
  76 +#endif
  77 +
  78 +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  79 +
  80 +#define CONFIG_FEC_XCV_TYPE RGMII
  81 +#define FEC_QUIRK_ENET_MAC
  82 +
  83 +/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */
  84 +#define CONFIG_ETHPRIME "eth0"
  85 +
  86 +#ifdef CONFIG_AHAB_BOOT
  87 +#define AHAB_ENV "sec_boot=yes\0"
  88 +#else
  89 +#define AHAB_ENV "sec_boot=no\0"
  90 +#endif
  91 +
  92 +/* Boot M4 */
  93 +#define M4_BOOT_ENV \
  94 + "m4_0_image=m4_0.bin\0" \
  95 + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
  96 + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
  97 +
  98 +#ifdef CONFIG_NAND_BOOT
  99 +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
  100 +#endif
  101 +
  102 +#define CONFIG_MFG_ENV_SETTINGS \
  103 + CONFIG_MFG_ENV_SETTINGS_DEFAULT \
  104 + "clk_ignore_unused "\
  105 + "\0" \
  106 + "initrd_addr=0x83100000\0" \
  107 + "initrd_high=0xffffffffffffffff\0" \
  108 + "emmc_dev=0\0" \
  109 + "sd_dev=1\0" \
  110 +
  111 +/* Initial environment variables */
  112 +#ifdef CONFIG_NAND_BOOT
  113 +#define CONFIG_EXTRA_ENV_SETTINGS \
  114 + CONFIG_MFG_ENV_SETTINGS \
  115 + "bootargs=console=ttyLP0,115200 ubi.mtd=nandrootfs " \
  116 + "root=ubi0:nandrootfs rootfstype=ubifs " \
  117 + MFG_NAND_PARTITION \
  118 + "\0"\
  119 + "console=ttyLP0,115200 earlycon\0" \
  120 + "mtdparts=" MFG_NAND_PARTITION "\0" \
  121 + "fdt_addr=0x83000000\0"
  122 +#else
  123 +#define CONFIG_EXTRA_ENV_SETTINGS \
  124 + CONFIG_MFG_ENV_SETTINGS \
  125 + M4_BOOT_ENV \
  126 + AHAB_ENV \
  127 + "script=boot.scr\0" \
  128 + "image=Image\0" \
  129 + "panel=NULL\0" \
  130 + "console=ttyLP0\0" \
  131 + "fdt_addr=0x83000000\0" \
  132 + "fdt_high=0xffffffffffffffff\0" \
  133 + "cntr_addr=0x98000000\0" \
  134 + "cntr_file=os_cntr_signed.bin\0" \
  135 + "boot_fdt=try\0" \
  136 + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
  137 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  138 + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  139 + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  140 + "mmcautodetect=yes\0" \
  141 + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \
  142 + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  143 + "bootscript=echo Running bootscript from mmc ...; " \
  144 + "source\0" \
  145 + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  146 + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  147 + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
  148 + "auth_os=auth_cntr ${cntr_addr}\0" \
  149 + "mmcboot=echo Booting from mmc ...; " \
  150 + "run mmcargs; " \
  151 + "if test ${sec_boot} = yes; then " \
  152 + "if run auth_os; then " \
  153 + "booti ${loadaddr} - ${fdt_addr}; " \
  154 + "else " \
  155 + "echo ERR: failed to authenticate; " \
  156 + "fi; " \
  157 + "else " \
  158 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  159 + "if run loadfdt; then " \
  160 + "booti ${loadaddr} - ${fdt_addr}; " \
  161 + "else " \
  162 + "echo WARN: Cannot load the DT; " \
  163 + "fi; " \
  164 + "else " \
  165 + "echo wait for boot; " \
  166 + "fi;" \
  167 + "fi;\0" \
  168 + "netargs=setenv bootargs console=${console},${baudrate} earlycon " \
  169 + "root=/dev/nfs " \
  170 + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  171 + "netboot=echo Booting from net ...; " \
  172 + "run netargs; " \
  173 + "if test ${ip_dyn} = yes; then " \
  174 + "setenv get_cmd dhcp; " \
  175 + "else " \
  176 + "setenv get_cmd tftp; " \
  177 + "fi; " \
  178 + "if test ${sec_boot} = yes; then " \
  179 + "${get_cmd} ${cntr_addr} ${cntr_file}; " \
  180 + "if run auth_os; then " \
  181 + "booti ${loadaddr} - ${fdt_addr}; " \
  182 + "else " \
  183 + "echo ERR: failed to authenticate; " \
  184 + "fi; " \
  185 + "else " \
  186 + "${get_cmd} ${loadaddr} ${image}; " \
  187 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  188 + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  189 + "booti ${loadaddr} - ${fdt_addr}; " \
  190 + "else " \
  191 + "echo WARN: Cannot load the DT; " \
  192 + "fi; " \
  193 + "else " \
  194 + "booti; " \
  195 + "fi;" \
  196 + "fi;\0"
  197 +#endif
  198 +
  199 +#ifdef CONFIG_NAND_BOOT
  200 +#define CONFIG_BOOTCOMMAND \
  201 + "nand read ${loadaddr} 0x9000000 0x2000000;"\
  202 + "nand read ${fdt_addr} 0xB000000 0x100000;"\
  203 + "booti ${loadaddr} - ${fdt_addr}"
  204 +#else
  205 +#define CONFIG_BOOTCOMMAND \
  206 + "mmc dev ${mmcdev}; if mmc rescan; then " \
  207 + "if run loadbootscript; then " \
  208 + "run bootscript; " \
  209 + "else " \
  210 + "if test ${sec_boot} = yes; then " \
  211 + "if run loadcntr; then " \
  212 + "run mmcboot; " \
  213 + "else run netboot; " \
  214 + "fi; " \
  215 + "else " \
  216 + "if run loadimage; then " \
  217 + "run mmcboot; " \
  218 + "else run netboot; " \
  219 + "fi; " \
  220 + "fi; " \
  221 + "fi; " \
  222 + "else booti ${loadaddr} - ${fdt_addr}; fi"
  223 +#endif
  224 +
  225 +/* Link Definitions */
  226 +#define CONFIG_LOADADDR 0x80280000
  227 +
  228 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  229 +
  230 +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
  231 +
  232 +
  233 +#ifdef CONFIG_QSPI_BOOT
  234 +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
  235 +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  236 +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
  237 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  238 +#else
  239 +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
  240 +#endif
  241 +
  242 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  243 +
  244 +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board
  245 + */
  246 +#ifdef CONFIG_TARGET_IMX8X_17X17_VAL
  247 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
  248 +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
  249 +#define CONFIG_SYS_FSL_USDHC_NUM 1
  250 +#else
  251 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
  252 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  253 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  254 +#endif
  255 +
  256 +/* Size of malloc() pool */
  257 +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024)
  258 +
  259 +#define CONFIG_SYS_SDRAM_BASE 0x80000000
  260 +#define PHYS_SDRAM_1 0x80000000
  261 +#define PHYS_SDRAM_2 0x880000000
  262 +#if defined(CONFIG_TARGET_IMX8QXP_DDR3_VAL) || defined(CONFIG_TARGET_IMX8X_17X17_VAL)
  263 +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB totally */
  264 +#define PHYS_SDRAM_2_SIZE 0x00000000
  265 +#else
  266 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
  267 +/* LPDDR4 board total DDR is 3GB */
  268 +#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
  269 +#endif
  270 +
  271 +#define CONFIG_SYS_MEMTEST_START 0xA0000000
  272 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2))
  273 +
  274 +/* Serial */
  275 +#define CONFIG_BAUDRATE 115200
  276 +
  277 +/* Monitor Command Prompt */
  278 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  279 +#define CONFIG_SYS_CBSIZE 2048
  280 +#define CONFIG_SYS_MAXARGS 64
  281 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  282 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  283 + sizeof(CONFIG_SYS_PROMPT) + 16)
  284 +
  285 +/* Generic Timer Definitions */
  286 +#define COUNTER_FREQUENCY 8000000 /* 8MHz */
  287 +
  288 +#ifndef CONFIG_DM_PCA953X
  289 +#define CONFIG_PCA953X
  290 +#define CONFIG_CMD_PCA953X
  291 +#define CONFIG_CMD_PCA953X_INFO
  292 +#endif
  293 +
  294 +/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */
  295 +#ifdef CONFIG_FSL_FSPI
  296 +#define FSL_FSPI_FLASH_SIZE SZ_64M
  297 +#define FSL_FSPI_FLASH_NUM 1
  298 +#define FSPI0_BASE_ADDR 0x5d120000
  299 +#define FSPI0_AMBA_BASE 0
  300 +#define CONFIG_SYS_FSL_FSPI_AHB
  301 +#endif
  302 +
  303 +#define CONFIG_SERIAL_TAG
  304 +
  305 +#ifdef CONFIG_NAND_MXS
  306 +#define CONFIG_CMD_NAND_TRIMFFS
  307 +
  308 +/* NAND stuff */
  309 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  310 +#define CONFIG_SYS_NAND_BASE 0x40000000
  311 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  312 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  313 +#define CONFIG_SYS_NAND_USE_FLASH_BBT
  314 +
  315 +#endif
  316 +
  317 +/* USB Config */
  318 +#ifndef CONFIG_SPL_BUILD
  319 +#define CONFIG_CMD_USB
  320 +#define CONFIG_USB_STORAGE
  321 +#define CONFIG_USBD_HS
  322 +
  323 +#define CONFIG_CMD_USB_MASS_STORAGE
  324 +#define CONFIG_USB_GADGET_MASS_STORAGE
  325 +#define CONFIG_USB_FUNCTION_MASS_STORAGE
  326 +#endif
  327 +
  328 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  329 +
  330 +/* USB OTG controller configs */
  331 +#ifdef CONFIG_USB_EHCI_HCD
  332 +#define CONFIG_USB_HOST_ETHER
  333 +#define CONFIG_USB_ETHER_ASIX
  334 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  335 +#endif
  336 +
  337 +#endif /* __IMX8QXP_VAL_H */