mx6: titanium: Move BSP code to barco board directory

Since the titanium board is not a Freescale board, move its BSP code from the freescale board directory to the newly created barco board directory. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Korsgaard <peter.korsgaard@barco.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Peter Korsgaard <peter.korsgaard@barco.com>

mx6: titanium: Move BSP code to barco board directory
Since the titanium board is not a Freescale board, move its BSP code from the freescale board directory to the newly created barco board directory. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Korsgaard <peter.korsgaard@barco.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Peter Korsgaard <peter.korsgaard@barco.com>
Stefan Roese · Stefano Babic
1 parent 90fb985863
Showing 7 changed files with 500 additions and 500 deletions Side-by-side Diff
board/barco/titanium/Makefile
board/barco/titanium/imximage.cfg
board/barco/titanium/titanium.c
board/freescale/titanium/Makefile
board/freescale/titanium/imximage.cfg
board/freescale/titanium/titanium.c
boards.cfg
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := titanium.o
+/*
+ * Projectiondesign AS
+ * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * sd, nand
+ */
+BOOT_FROM      nand
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+
+/* (differential input) */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* disable ddr pullups */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+/* (differential input) */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
+
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+/*
+ * Copyright (C) 2013 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6q_pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/boot_mode.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
+			PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	\
+			PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |	\
+			PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
+			 PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
+			 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart4_pads[] = {
+	MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+struct i2c_pads_info i2c_pad_info0 = {
+	.scl = {
+		.i2c_mode  = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC,
+		.gp = IMX_GPIO_NR(5, 27)
+	},
+	.sda = {
+		 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
+		 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC,
+		 .gp = IMX_GPIO_NR(5, 26)
+	 }
+};
+
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
+		 .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
+		 .gp = IMX_GPIO_NR(7, 11)
+	 }
+};
+
+iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t const enet_pads1[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/* pin 35 - 1 (PHY_AD2) on reset */
+	MX6_PAD_RGMII_RXC__GPIO_6_30		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 32 - 1 - (MODE0) all */
+	MX6_PAD_RGMII_RD0__GPIO_6_25		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 31 - 1 - (MODE1) all */
+	MX6_PAD_RGMII_RD1__GPIO_6_27		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 28 - 1 - (MODE2) all */
+	MX6_PAD_RGMII_RD2__GPIO_6_28		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 27 - 1 - (MODE3) all */
+	MX6_PAD_RGMII_RD3__GPIO_6_29		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+	MX6_PAD_RGMII_RX_CTL__GPIO_6_24		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 42 PHY nRST */
+	MX6_PAD_EIM_D23__GPIO_3_23		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads2[] = {
+	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+iomux_v3_cfg_t nfc_pads[] = {
+	MX6_PAD_NANDF_CLE__RAWNAND_CLE		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_ALE__RAWNAND_ALE		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_WP_B__RAWNAND_RESETN	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_RB0__RAWNAND_READY0	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS0__RAWNAND_CE0N		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS1__RAWNAND_CE1N		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS2__RAWNAND_CE2N		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS3__RAWNAND_CE3N		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_CMD__RAWNAND_RDN		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_CLK__RAWNAND_WRN		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D0__RAWNAND_D0		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D1__RAWNAND_D1		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D2__RAWNAND_D2		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D3__RAWNAND_D3		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D4__RAWNAND_D4		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D5__RAWNAND_D5		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D6__RAWNAND_D6		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D7__RAWNAND_D7		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__RAWNAND_DQS		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	imx_iomux_v3_setup_multiple_pads(nfc_pads,
+					 ARRAY_SIZE(nfc_pads));
+
+	/* config gpmi and bch clock to 100 MHz */
+	clrsetbits_le32(&mxc_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+	/* enable gpmi and bch clock gating */
+	setbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+
+static void setup_iomux_enet(void)
+{
+	gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+	gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+
+	/* Need delay 10ms according to KSZ9021 spec */
+	udelay(1000 * 10);
+	gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+
+	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+}
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{ USDHC3_BASE_ADDR },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
+		gpio_direction_input(IMX_GPIO_NR(7, 0));
+		return !gpio_get_value(IMX_GPIO_NR(7, 0));
+	}
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	/*
+	 * Only one USDHC controller on titianium
+	 */
+	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* min rx data delay */
+	ksz9021_phy_extended_write(phydev,
+				   MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
+	/* min tx data delay */
+	ksz9021_phy_extended_write(phydev,
+				   MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
+	/* max rx/tx clock delay, min rx/tx control */
+	ksz9021_phy_extended_write(phydev,
+				   MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+
+	setup_iomux_enet();
+
+	ret = cpu_eth_init(bis);
+	if (ret)
+		printf("FEC MXC: %s:failed\n", __func__);
+
+	return ret;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+	setup_gpmi_nand();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Titanium\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* NAND */
+	{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
+	/* 4 bit bus width */
+	{ "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
+	{ "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
+	{ NULL, 0 },
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	return 0;
+}
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y  := titanium.o
-/*
- * Projectiondesign AS
- * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg
- *
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- * Jason Liu <r64343@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Refer docs/README.imxmage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * sd, nand
- */
-BOOT_FROM      nand
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-
-#define __ASSEMBLY__
-#include <config.h>
-#include "asm/arch/mx6-ddr.h"
-#include "asm/arch/iomux.h"
-#include "asm/arch/crm_regs.h"
-
-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
-
-DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
-DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
-
-DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
-DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
-
-DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
-
-DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
-DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
-
-DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
-DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
-DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
-
-/* (differential input) */
-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-/* disable ddr pullups */
-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-/* (differential input) */
-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
-
-/* Read data DQ Byte0-3 delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
-
-/*
- * MDMISC	mirroring	interleaved (row/bank/col)
- */
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
-
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
-DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21
-DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
-DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
-DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
-DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
-DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
-DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-/*
- * Copyright (C) 2013 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6q_pins.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/boot_mode.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <micrel.h>
-#include <miiphy.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
-			PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	\
-			PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |	\
-			PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
-			 PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
-			 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
-	return 0;
-}
-
-iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart2_pads[] = {
-	MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart4_pads[] = {
-	MX6_PAD_CSI0_DAT12__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT13__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-struct i2c_pads_info i2c_pad_info0 = {
-	.scl = {
-		.i2c_mode  = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
-		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 | PC,
-		.gp = IMX_GPIO_NR(5, 27)
-	},
-	.sda = {
-		 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
-		 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 | PC,
-		 .gp = IMX_GPIO_NR(5, 26)
-	 }
-};
-
-struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 | PC,
-		.gp = IMX_GPIO_NR(1, 3)
-	},
-	.sda = {
-		 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
-		 .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
-		 .gp = IMX_GPIO_NR(7, 11)
-	 }
-};
-
-iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
-
-iomux_v3_cfg_t const enet_pads1[] = {
-	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	/* pin 35 - 1 (PHY_AD2) on reset */
-	MX6_PAD_RGMII_RXC__GPIO_6_30		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 32 - 1 - (MODE0) all */
-	MX6_PAD_RGMII_RD0__GPIO_6_25		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 31 - 1 - (MODE1) all */
-	MX6_PAD_RGMII_RD1__GPIO_6_27		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 28 - 1 - (MODE2) all */
-	MX6_PAD_RGMII_RD2__GPIO_6_28		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 27 - 1 - (MODE3) all */
-	MX6_PAD_RGMII_RD3__GPIO_6_29		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
-	MX6_PAD_RGMII_RX_CTL__GPIO_6_24		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 42 PHY nRST */
-	MX6_PAD_EIM_D23__GPIO_3_23		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const enet_pads2[] = {
-	MX6_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-iomux_v3_cfg_t nfc_pads[] = {
-	MX6_PAD_NANDF_CLE__RAWNAND_CLE		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_ALE__RAWNAND_ALE		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_WP_B__RAWNAND_RESETN	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_RB0__RAWNAND_READY0	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS0__RAWNAND_CE0N		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS1__RAWNAND_CE1N		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS2__RAWNAND_CE2N		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_CS3__RAWNAND_CE3N		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_CMD__RAWNAND_RDN		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_CLK__RAWNAND_WRN		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D0__RAWNAND_D0		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D1__RAWNAND_D1		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D2__RAWNAND_D2		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D3__RAWNAND_D3		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D4__RAWNAND_D4		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D5__RAWNAND_D5		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D6__RAWNAND_D6		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_NANDF_D7__RAWNAND_D7		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__RAWNAND_DQS		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_gpmi_nand(void)
-{
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	/* config gpmi nand iomux */
-	imx_iomux_v3_setup_multiple_pads(nfc_pads,
-					 ARRAY_SIZE(nfc_pads));
-
-	/* config gpmi and bch clock to 100 MHz */
-	clrsetbits_le32(&mxc_ccm->cs2cdr,
-			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
-			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
-			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
-			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
-			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
-			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
-
-	/* enable gpmi and bch clock gating */
-	setbits_le32(&mxc_ccm->CCGR4,
-		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
-		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
-
-	/* enable apbh clock gating */
-	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-
-static void setup_iomux_enet(void)
-{
-	gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
-	gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
-	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
-	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
-	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
-	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
-	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
-	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
-
-	/* Need delay 10ms according to KSZ9021 spec */
-	udelay(1000 * 10);
-	gpio_set_value(IMX_GPIO_NR(3, 23), 1);
-
-	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
-}
-
-static void setup_iomux_uart(void)
-{
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
-	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
-}
-
-#ifdef CONFIG_USB_EHCI_MX6
-int board_ehci_hcd_init(int port)
-{
-	return 0;
-}
-
-#endif
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
-	{ USDHC3_BASE_ADDR },
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-
-	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
-		gpio_direction_input(IMX_GPIO_NR(7, 0));
-		return !gpio_get_value(IMX_GPIO_NR(7, 0));
-	}
-
-	return 0;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	/*
-	 * Only one USDHC controller on titianium
-	 */
-	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-
-	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-#endif
-
-int board_phy_config(struct phy_device *phydev)
-{
-	/* min rx data delay */
-	ksz9021_phy_extended_write(phydev,
-				   MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
-	/* min tx data delay */
-	ksz9021_phy_extended_write(phydev,
-				   MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
-	/* max rx/tx clock delay, min rx/tx control */
-	ksz9021_phy_extended_write(phydev,
-				   MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int ret;
-
-	setup_iomux_enet();
-
-	ret = cpu_eth_init(bis);
-	if (ret)
-		printf("FEC MXC: %s:failed\n", __func__);
-
-	return ret;
-}
-
-int board_early_init_f(void)
-{
-	setup_iomux_uart();
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-
-	setup_gpmi_nand();
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: Titanium\n");
-
-	return 0;
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
-	/* NAND */
-	{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
-	/* 4 bit bus width */
-	{ "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
-	{ "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
-	{ NULL, 0 },
-};
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_CMD_BMODE
-	add_board_boot_modes(board_boot_modes);
-#endif
-
-	return 0;
-}
@@ -302,7 +302,7 @@
 Active  arm         armv7          mx6         freescale       mx6sabresd          mx6dlsabresd                         mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL                                                             Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         freescale       mx6sabresd          mx6qsabresd                          mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q                                                           Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         armv7          mx6         freescale       mx6slevk            mx6slevk                             mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL                                                                   Fabio Estevam <fabio.estevam@freescale.com>
-Active  arm         armv7          mx6         freescale       titanium            titanium                             titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg                                                                         Stefan Roese <sr@denx.de>
+Active  arm         armv7          mx6         barco           titanium            titanium                             titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg                                                                         Stefan Roese <sr@denx.de>
 Active  arm         armv7          omap3       -               overo               omap3_overo                          -                                                                                                                                 Steve Sakoman <sakoman@gmail.com>
 Active  arm         armv7          omap3       -               pandora             omap3_pandora                        -                                                                                                                                 Grazvydas Ignotas <notasas@gmail.com>
 Active  arm         armv7          omap3       8dtech          eco5pk              eco5pk                               -                                                                                                                                 Raphael Assenat <raph@8d.com>
	1	+#
	2	+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
	3	+#
	4	+# (C) Copyright 2011 Freescale Semiconductor, Inc.
	5	+#
	6	+# SPDX-License-Identifier: GPL-2.0+
	7	+#
	8	+
	9	+obj-y := titanium.o
	1	+/*
	2	+ * Projectiondesign AS
	3	+ * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg
	4	+ *
	5	+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
	6	+ * Jason Liu <r64343@freescale.com>
	7	+ *
	8	+ * SPDX-License-Identifier: GPL-2.0+
	9	+ *
	10	+ * Refer docs/README.imxmage for more details about how-to configure
	11	+ * and create imximage boot image
	12	+ *
	13	+ * The syntax is taken as close as possible with the kwbimage
	14	+ */
	15	+
	16	+/* image version */
	17	+
	18	+IMAGE_VERSION 2
	19	+
	20	+/*
	21	+ * Boot Device : one of
	22	+ * sd, nand
	23	+ */
	24	+BOOT_FROM nand
	25	+
	26	+/*
	27	+ * Device Configuration Data (DCD)
	28	+ *
	29	+ * Each entry must have the format:
	30	+ * Addr-type Address Value
	31	+ *
	32	+ * where:
	33	+ * Addr-type register length (1,2 or 4 bytes)
	34	+ * Address absolute address of the register
	35	+ * value value to be stored in the register
	36	+ */
	37	+
	38	+#define __ASSEMBLY__
	39	+#include <config.h>
	40	+#include "asm/arch/mx6-ddr.h"
	41	+#include "asm/arch/iomux.h"
	42	+#include "asm/arch/crm_regs.h"
	43	+
	44	+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
	45	+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
	46	+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
	47	+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
	48	+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
	49	+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
	50	+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
	51	+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
	52	+
	53	+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
	54	+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
	55	+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
	56	+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
	57	+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
	58	+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
	59	+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
	60	+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
	61	+
	62	+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
	63	+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
	64	+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
	65	+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
	66	+
	67	+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
	68	+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
	69	+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
	70	+
	71	+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
	72	+
	73	+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
	74	+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
	75	+
	76	+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
	77	+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
	78	+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
	79	+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
	80	+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
	81	+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
	82	+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
	83	+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
	84	+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
	85	+
	86	+/* (differential input) */
	87	+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
	88	+/* disable ddr pullups */
	89	+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
	90	+/* (differential input) */
	91	+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
	92	+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
	93	+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
	94	+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
	95	+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
	96	+
	97	+/* Read data DQ Byte0-3 delay */
	98	+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
	99	+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
	100	+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
	101	+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
	102	+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
	103	+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
	104	+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
	105	+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
	106	+
	107	+/*
	108	+ * MDMISC mirroring interleaved (row/bank/col)
	109	+ */
	110	+DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
	111	+
	112	+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
	113	+DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975
	114	+DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64
	115	+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
	116	+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
	117	+DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21
	118	+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
	119	+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
	120	+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
	121	+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
	122	+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
	123	+DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A
	124	+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
	125	+DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B
	126	+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
	127	+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
	128	+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
	129	+DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
	130	+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
	131	+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
	132	+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
	133	+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
	134	+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
	135	+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
	136	+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
	137	+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350
	138	+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359
	139	+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350
	140	+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348
	141	+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B
	142	+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341
	143	+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933
	144	+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36
	145	+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
	146	+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
	147	+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044
	148	+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044
	149	+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
	150	+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
	151	+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
	152	+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
	153	+
	154	+/* set the default clock gate to save power */
	155	+DATA 4, CCM_CCGR0, 0x00C03F3F
	156	+DATA 4, CCM_CCGR1, 0x0030FC03
	157	+DATA 4, CCM_CCGR2, 0x0FFFC000
	158	+DATA 4, CCM_CCGR3, 0x3FF00000
	159	+DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
	160	+DATA 4, CCM_CCGR5, 0x0F0000C3
	161	+DATA 4, CCM_CCGR6, 0x000003FF
	162	+
	163	+/* enable AXI cache for VDOA/VPU/IPU */
	164	+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
	165	+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	166	+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
	167	+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
	1	+/*
	2	+ * Copyright (C) 2013 Stefan Roese <sr@denx.de>
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <common.h>
	8	+#include <asm/io.h>
	9	+#include <asm/arch/clock.h>
	10	+#include <asm/arch/imx-regs.h>
	11	+#include <asm/arch/iomux.h>
	12	+#include <asm/arch/mx6q_pins.h>
	13	+#include <asm/arch/crm_regs.h>
	14	+#include <asm/arch/sys_proto.h>
	15	+#include <asm/gpio.h>
	16	+#include <asm/imx-common/iomux-v3.h>
	17	+#include <asm/imx-common/mxc_i2c.h>
	18	+#include <asm/imx-common/boot_mode.h>
	19	+#include <mmc.h>
	20	+#include <fsl_esdhc.h>
	21	+#include <micrel.h>
	22	+#include <miiphy.h>
	23	+#include <netdev.h>
	24	+
	25	+DECLARE_GLOBAL_DATA_PTR;
	26	+
	27	+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	28	+ PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	29	+
	30	+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \| \
	31	+ PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	32	+
	33	+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	34	+ PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
	35	+
	36	+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	37	+ PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
	38	+ PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
	39	+
	40	+int dram_init(void)
	41	+{
	42	+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
	43	+
	44	+ return 0;
	45	+}
	46	+
	47	+iomux_v3_cfg_t const uart1_pads[] = {
	48	+ MX6_PAD_SD3_DAT6__UART1_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	49	+ MX6_PAD_SD3_DAT7__UART1_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	50	+};
	51	+
	52	+iomux_v3_cfg_t const uart2_pads[] = {
	53	+ MX6_PAD_EIM_D26__UART2_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	54	+ MX6_PAD_EIM_D27__UART2_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	55	+};
	56	+
	57	+iomux_v3_cfg_t const uart4_pads[] = {
	58	+ MX6_PAD_CSI0_DAT12__UART4_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	59	+ MX6_PAD_CSI0_DAT13__UART4_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
	60	+};
	61	+
	62	+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
	63	+
	64	+struct i2c_pads_info i2c_pad_info0 = {
	65	+ .scl = {
	66	+ .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL \| PC,
	67	+ .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 \| PC,
	68	+ .gp = IMX_GPIO_NR(5, 27)
	69	+ },
	70	+ .sda = {
	71	+ .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA \| PC,
	72	+ .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 \| PC,
	73	+ .gp = IMX_GPIO_NR(5, 26)
	74	+ }
	75	+};
	76	+
	77	+struct i2c_pads_info i2c_pad_info2 = {
	78	+ .scl = {
	79	+ .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL \| PC,
	80	+ .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 \| PC,
	81	+ .gp = IMX_GPIO_NR(1, 3)
	82	+ },
	83	+ .sda = {
	84	+ .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA \| PC,
	85	+ .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 \| PC,
	86	+ .gp = IMX_GPIO_NR(7, 11)
	87	+ }
	88	+};
	89	+
	90	+iomux_v3_cfg_t const usdhc3_pads[] = {
	91	+ MX6_PAD_SD3_CLK__USDHC3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	92	+ MX6_PAD_SD3_CMD__USDHC3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	93	+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	94	+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	95	+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	96	+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	97	+ MX6_PAD_SD3_DAT5__GPIO_7_0 \| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
	98	+};
	99	+
	100	+iomux_v3_cfg_t const enet_pads1[] = {
	101	+ MX6_PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	102	+ MX6_PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	103	+ MX6_PAD_RGMII_TXC__ENET_RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	104	+ MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	105	+ MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	106	+ MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	107	+ MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	108	+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	109	+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	110	+ /* pin 35 - 1 (PHY_AD2) on reset */
	111	+ MX6_PAD_RGMII_RXC__GPIO_6_30 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	112	+ /* pin 32 - 1 - (MODE0) all */
	113	+ MX6_PAD_RGMII_RD0__GPIO_6_25 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	114	+ /* pin 31 - 1 - (MODE1) all */
	115	+ MX6_PAD_RGMII_RD1__GPIO_6_27 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	116	+ /* pin 28 - 1 - (MODE2) all */
	117	+ MX6_PAD_RGMII_RD2__GPIO_6_28 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	118	+ /* pin 27 - 1 - (MODE3) all */
	119	+ MX6_PAD_RGMII_RD3__GPIO_6_29 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	120	+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
	121	+ MX6_PAD_RGMII_RX_CTL__GPIO_6_24 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	122	+ /* pin 42 PHY nRST */
	123	+ MX6_PAD_EIM_D23__GPIO_3_23 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	124	+};
	125	+
	126	+iomux_v3_cfg_t const enet_pads2[] = {
	127	+ MX6_PAD_RGMII_RXC__ENET_RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	128	+ MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	129	+ MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	130	+ MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	131	+ MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	132	+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	133	+};
	134	+
	135	+iomux_v3_cfg_t nfc_pads[] = {
	136	+ MX6_PAD_NANDF_CLE__RAWNAND_CLE \| MUX_PAD_CTRL(NO_PAD_CTRL),
	137	+ MX6_PAD_NANDF_ALE__RAWNAND_ALE \| MUX_PAD_CTRL(NO_PAD_CTRL),
	138	+ MX6_PAD_NANDF_WP_B__RAWNAND_RESETN \| MUX_PAD_CTRL(NO_PAD_CTRL),
	139	+ MX6_PAD_NANDF_RB0__RAWNAND_READY0 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	140	+ MX6_PAD_NANDF_CS0__RAWNAND_CE0N \| MUX_PAD_CTRL(NO_PAD_CTRL),
	141	+ MX6_PAD_NANDF_CS1__RAWNAND_CE1N \| MUX_PAD_CTRL(NO_PAD_CTRL),
	142	+ MX6_PAD_NANDF_CS2__RAWNAND_CE2N \| MUX_PAD_CTRL(NO_PAD_CTRL),
	143	+ MX6_PAD_NANDF_CS3__RAWNAND_CE3N \| MUX_PAD_CTRL(NO_PAD_CTRL),
	144	+ MX6_PAD_SD4_CMD__RAWNAND_RDN \| MUX_PAD_CTRL(NO_PAD_CTRL),
	145	+ MX6_PAD_SD4_CLK__RAWNAND_WRN \| MUX_PAD_CTRL(NO_PAD_CTRL),
	146	+ MX6_PAD_NANDF_D0__RAWNAND_D0 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	147	+ MX6_PAD_NANDF_D1__RAWNAND_D1 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	148	+ MX6_PAD_NANDF_D2__RAWNAND_D2 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	149	+ MX6_PAD_NANDF_D3__RAWNAND_D3 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	150	+ MX6_PAD_NANDF_D4__RAWNAND_D4 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	151	+ MX6_PAD_NANDF_D5__RAWNAND_D5 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	152	+ MX6_PAD_NANDF_D6__RAWNAND_D6 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	153	+ MX6_PAD_NANDF_D7__RAWNAND_D7 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	154	+ MX6_PAD_SD4_DAT0__RAWNAND_DQS \| MUX_PAD_CTRL(NO_PAD_CTRL),
	155	+};
	156	+
	157	+static void setup_gpmi_nand(void)
	158	+{
	159	+ struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	160	+
	161	+ /* config gpmi nand iomux */
	162	+ imx_iomux_v3_setup_multiple_pads(nfc_pads,
	163	+ ARRAY_SIZE(nfc_pads));
	164	+
	165	+ /* config gpmi and bch clock to 100 MHz */
	166	+ clrsetbits_le32(&mxc_ccm->cs2cdr,
	167	+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK \|
	168	+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK \|
	169	+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
	170	+ MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) \|
	171	+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) \|
	172	+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
	173	+
	174	+ /* enable gpmi and bch clock gating */
	175	+ setbits_le32(&mxc_ccm->CCGR4,
	176	+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK \|
	177	+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK \|
	178	+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK \|
	179	+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK \|
	180	+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
	181	+
	182	+ /* enable apbh clock gating */
	183	+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
	184	+}
	185	+
	186	+static void setup_iomux_enet(void)
	187	+{
	188	+ gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
	189	+ gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
	190	+ gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
	191	+ gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
	192	+ gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
	193	+ gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
	194	+ imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
	195	+ gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
	196	+
	197	+ /* Need delay 10ms according to KSZ9021 spec */
	198	+ udelay(1000 * 10);
	199	+ gpio_set_value(IMX_GPIO_NR(3, 23), 1);
	200	+
	201	+ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
	202	+}
	203	+
	204	+static void setup_iomux_uart(void)
	205	+{
	206	+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
	207	+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
	208	+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
	209	+}
	210	+
	211	+#ifdef CONFIG_USB_EHCI_MX6
	212	+int board_ehci_hcd_init(int port)
	213	+{
	214	+ return 0;
	215	+}
	216	+
	217	+#endif
	218	+
	219	+#ifdef CONFIG_FSL_ESDHC
	220	+struct fsl_esdhc_cfg usdhc_cfg[1] = {
	221	+ { USDHC3_BASE_ADDR },
	222	+};
	223	+
	224	+int board_mmc_getcd(struct mmc *mmc)
	225	+{
	226	+ struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	227	+
	228	+ if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
	229	+ gpio_direction_input(IMX_GPIO_NR(7, 0));
	230	+ return !gpio_get_value(IMX_GPIO_NR(7, 0));
	231	+ }
	232	+
	233	+ return 0;
	234	+}
	235	+
	236	+int board_mmc_init(bd_t *bis)
	237	+{
	238	+ /*
	239	+ * Only one USDHC controller on titianium
	240	+ */
	241	+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
	242	+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	243	+
	244	+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
	245	+}
	246	+#endif
	247	+
	248	+int board_phy_config(struct phy_device *phydev)
	249	+{
	250	+ /* min rx data delay */
	251	+ ksz9021_phy_extended_write(phydev,
	252	+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
	253	+ /* min tx data delay */
	254	+ ksz9021_phy_extended_write(phydev,
	255	+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
	256	+ /* max rx/tx clock delay, min rx/tx control */
	257	+ ksz9021_phy_extended_write(phydev,
	258	+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
	259	+ if (phydev->drv->config)
	260	+ phydev->drv->config(phydev);
	261	+
	262	+ return 0;
	263	+}
	264	+
	265	+int board_eth_init(bd_t *bis)
	266	+{
	267	+ int ret;
	268	+
	269	+ setup_iomux_enet();
	270	+
	271	+ ret = cpu_eth_init(bis);
	272	+ if (ret)
	273	+ printf("FEC MXC: %s:failed\n", __func__);
	274	+
	275	+ return ret;
	276	+}
	277	+
	278	+int board_early_init_f(void)
	279	+{
	280	+ setup_iomux_uart();
	281	+
	282	+ return 0;
	283	+}
	284	+
	285	+int board_init(void)
	286	+{
	287	+ /* address of boot parameters */
	288	+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	289	+
	290	+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
	291	+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
	292	+
	293	+ setup_gpmi_nand();
	294	+
	295	+ return 0;
	296	+}
	297	+
	298	+int checkboard(void)
	299	+{
	300	+ puts("Board: Titanium\n");
	301	+
	302	+ return 0;
	303	+}
	304	+
	305	+#ifdef CONFIG_CMD_BMODE
	306	+static const struct boot_mode board_boot_modes[] = {
	307	+ /* NAND */
	308	+ { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
	309	+ /* 4 bit bus width */
	310	+ { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
	311	+ { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
	312	+ { NULL, 0 },
	313	+};
	314	+#endif
	315	+
	316	+int misc_init_r(void)
	317	+{
	318	+#ifdef CONFIG_CMD_BMODE
	319	+ add_board_boot_modes(board_boot_modes);
	320	+#endif
	321	+
	322	+ return 0;
	323	+}
1		-#
2		-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
3		-#
4		-# (C) Copyright 2011 Freescale Semiconductor, Inc.
5		-#
6		-# SPDX-License-Identifier: GPL-2.0+
7		-#
8		-
9		-obj-y := titanium.o
1		-/*
2		- * Projectiondesign AS
3		- * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg
4		- *
5		- * Copyright (C) 2011 Freescale Semiconductor, Inc.
6		- * Jason Liu <r64343@freescale.com>
7		- *
8		- * SPDX-License-Identifier: GPL-2.0+
9		- *
10		- * Refer docs/README.imxmage for more details about how-to configure
11		- * and create imximage boot image
12		- *
13		- * The syntax is taken as close as possible with the kwbimage
14		- */
15		-
16		-/* image version */
17		-
18		-IMAGE_VERSION 2
19		-
20		-/*
21		- * Boot Device : one of
22		- * sd, nand
23		- */
24		-BOOT_FROM nand
25		-
26		-/*
27		- * Device Configuration Data (DCD)
28		- *
29		- * Each entry must have the format:
30		- * Addr-type Address Value
31		- *
32		- * where:
33		- * Addr-type register length (1,2 or 4 bytes)
34		- * Address absolute address of the register
35		- * value value to be stored in the register
36		- */
37		-
38		-#define __ASSEMBLY__
39		-#include <config.h>
40		-#include "asm/arch/mx6-ddr.h"
41		-#include "asm/arch/iomux.h"
42		-#include "asm/arch/crm_regs.h"
43		-
44		-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
45		-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
46		-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
47		-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
48		-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
49		-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
50		-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
51		-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
52		-
53		-DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
54		-DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
55		-DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
56		-DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
57		-DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
58		-DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
59		-DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
60		-DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
61		-
62		-DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
63		-DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
64		-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
65		-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
66		-
67		-DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
68		-DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
69		-DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
70		-
71		-DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
72		-
73		-DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
74		-DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
75		-
76		-DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
77		-DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
78		-DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
79		-DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
80		-DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
81		-DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
82		-DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
83		-DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
84		-DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
85		-
86		-/* (differential input) */
87		-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
88		-/* disable ddr pullups */
89		-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
90		-/* (differential input) */
91		-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
92		-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
93		-DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
94		-/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
95		-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
96		-
97		-/* Read data DQ Byte0-3 delay */
98		-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
99		-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
100		-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
101		-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
102		-DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
103		-DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
104		-DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
105		-DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
106		-
107		-/*
108		- * MDMISC mirroring interleaved (row/bank/col)
109		- */
110		-DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
111		-
112		-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
113		-DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975
114		-DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64
115		-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
116		-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
117		-DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21
118		-DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
119		-DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
120		-DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
121		-DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
122		-DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
123		-DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A
124		-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
125		-DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B
126		-DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
127		-DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
128		-DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
129		-DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
130		-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
131		-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
132		-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
133		-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
134		-DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
135		-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
136		-DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
137		-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350
138		-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359
139		-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350
140		-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348
141		-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B
142		-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341
143		-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933
144		-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36
145		-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
146		-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
147		-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044
148		-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044
149		-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
150		-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
151		-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
152		-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
153		-
154		-/* set the default clock gate to save power */
155		-DATA 4, CCM_CCGR0, 0x00C03F3F
156		-DATA 4, CCM_CCGR1, 0x0030FC03
157		-DATA 4, CCM_CCGR2, 0x0FFFC000
158		-DATA 4, CCM_CCGR3, 0x3FF00000
159		-DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
160		-DATA 4, CCM_CCGR5, 0x0F0000C3
161		-DATA 4, CCM_CCGR6, 0x000003FF
162		-
163		-/* enable AXI cache for VDOA/VPU/IPU */
164		-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
165		-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
166		-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
167		-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
1		-/*
2		- * Copyright (C) 2013 Stefan Roese <sr@denx.de>
3		- *
4		- * SPDX-License-Identifier: GPL-2.0+
5		- */
6		-
7		-#include <common.h>
8		-#include <asm/io.h>
9		-#include <asm/arch/clock.h>
10		-#include <asm/arch/imx-regs.h>
11		-#include <asm/arch/iomux.h>
12		-#include <asm/arch/mx6q_pins.h>
13		-#include <asm/arch/crm_regs.h>
14		-#include <asm/arch/sys_proto.h>
15		-#include <asm/gpio.h>
16		-#include <asm/imx-common/iomux-v3.h>
17		-#include <asm/imx-common/mxc_i2c.h>
18		-#include <asm/imx-common/boot_mode.h>
19		-#include <mmc.h>
20		-#include <fsl_esdhc.h>
21		-#include <micrel.h>
22		-#include <miiphy.h>
23		-#include <netdev.h>
24		-
25		-DECLARE_GLOBAL_DATA_PTR;
26		-
27		-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
28		- PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
29		-
30		-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \| \
31		- PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
32		-
33		-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
34		- PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
35		-
36		-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
37		- PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
38		- PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
39		-
40		-int dram_init(void)
41		-{
42		- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
43		-
44		- return 0;
45		-}
46		-
47		-iomux_v3_cfg_t const uart1_pads[] = {
48		- MX6_PAD_SD3_DAT6__UART1_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
49		- MX6_PAD_SD3_DAT7__UART1_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
50		-};
51		-
52		-iomux_v3_cfg_t const uart2_pads[] = {
53		- MX6_PAD_EIM_D26__UART2_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
54		- MX6_PAD_EIM_D27__UART2_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
55		-};
56		-
57		-iomux_v3_cfg_t const uart4_pads[] = {
58		- MX6_PAD_CSI0_DAT12__UART4_TXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
59		- MX6_PAD_CSI0_DAT13__UART4_RXD \| MUX_PAD_CTRL(UART_PAD_CTRL),
60		-};
61		-
62		-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
63		-
64		-struct i2c_pads_info i2c_pad_info0 = {
65		- .scl = {
66		- .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL \| PC,
67		- .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO_5_27 \| PC,
68		- .gp = IMX_GPIO_NR(5, 27)
69		- },
70		- .sda = {
71		- .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA \| PC,
72		- .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO_5_26 \| PC,
73		- .gp = IMX_GPIO_NR(5, 26)
74		- }
75		-};
76		-
77		-struct i2c_pads_info i2c_pad_info2 = {
78		- .scl = {
79		- .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL \| PC,
80		- .gpio_mode = MX6_PAD_GPIO_3__GPIO_1_3 \| PC,
81		- .gp = IMX_GPIO_NR(1, 3)
82		- },
83		- .sda = {
84		- .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA \| PC,
85		- .gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 \| PC,
86		- .gp = IMX_GPIO_NR(7, 11)
87		- }
88		-};
89		-
90		-iomux_v3_cfg_t const usdhc3_pads[] = {
91		- MX6_PAD_SD3_CLK__USDHC3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
92		- MX6_PAD_SD3_CMD__USDHC3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
93		- MX6_PAD_SD3_DAT0__USDHC3_DAT0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
94		- MX6_PAD_SD3_DAT1__USDHC3_DAT1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
95		- MX6_PAD_SD3_DAT2__USDHC3_DAT2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
96		- MX6_PAD_SD3_DAT3__USDHC3_DAT3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
97		- MX6_PAD_SD3_DAT5__GPIO_7_0 \| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
98		-};
99		-
100		-iomux_v3_cfg_t const enet_pads1[] = {
101		- MX6_PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
102		- MX6_PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
103		- MX6_PAD_RGMII_TXC__ENET_RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
104		- MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
105		- MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
106		- MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
107		- MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
108		- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
109		- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL),
110		- /* pin 35 - 1 (PHY_AD2) on reset */
111		- MX6_PAD_RGMII_RXC__GPIO_6_30 \| MUX_PAD_CTRL(NO_PAD_CTRL),
112		- /* pin 32 - 1 - (MODE0) all */
113		- MX6_PAD_RGMII_RD0__GPIO_6_25 \| MUX_PAD_CTRL(NO_PAD_CTRL),
114		- /* pin 31 - 1 - (MODE1) all */
115		- MX6_PAD_RGMII_RD1__GPIO_6_27 \| MUX_PAD_CTRL(NO_PAD_CTRL),
116		- /* pin 28 - 1 - (MODE2) all */
117		- MX6_PAD_RGMII_RD2__GPIO_6_28 \| MUX_PAD_CTRL(NO_PAD_CTRL),
118		- /* pin 27 - 1 - (MODE3) all */
119		- MX6_PAD_RGMII_RD3__GPIO_6_29 \| MUX_PAD_CTRL(NO_PAD_CTRL),
120		- /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
121		- MX6_PAD_RGMII_RX_CTL__GPIO_6_24 \| MUX_PAD_CTRL(NO_PAD_CTRL),
122		- /* pin 42 PHY nRST */
123		- MX6_PAD_EIM_D23__GPIO_3_23 \| MUX_PAD_CTRL(NO_PAD_CTRL),
124		-};
125		-
126		-iomux_v3_cfg_t const enet_pads2[] = {
127		- MX6_PAD_RGMII_RXC__ENET_RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
128		- MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
129		- MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
130		- MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
131		- MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
132		- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
133		-};
134		-
135		-iomux_v3_cfg_t nfc_pads[] = {
136		- MX6_PAD_NANDF_CLE__RAWNAND_CLE \| MUX_PAD_CTRL(NO_PAD_CTRL),
137		- MX6_PAD_NANDF_ALE__RAWNAND_ALE \| MUX_PAD_CTRL(NO_PAD_CTRL),
138		- MX6_PAD_NANDF_WP_B__RAWNAND_RESETN \| MUX_PAD_CTRL(NO_PAD_CTRL),
139		- MX6_PAD_NANDF_RB0__RAWNAND_READY0 \| MUX_PAD_CTRL(NO_PAD_CTRL),
140		- MX6_PAD_NANDF_CS0__RAWNAND_CE0N \| MUX_PAD_CTRL(NO_PAD_CTRL),
141		- MX6_PAD_NANDF_CS1__RAWNAND_CE1N \| MUX_PAD_CTRL(NO_PAD_CTRL),
142		- MX6_PAD_NANDF_CS2__RAWNAND_CE2N \| MUX_PAD_CTRL(NO_PAD_CTRL),
143		- MX6_PAD_NANDF_CS3__RAWNAND_CE3N \| MUX_PAD_CTRL(NO_PAD_CTRL),
144		- MX6_PAD_SD4_CMD__RAWNAND_RDN \| MUX_PAD_CTRL(NO_PAD_CTRL),
145		- MX6_PAD_SD4_CLK__RAWNAND_WRN \| MUX_PAD_CTRL(NO_PAD_CTRL),
146		- MX6_PAD_NANDF_D0__RAWNAND_D0 \| MUX_PAD_CTRL(NO_PAD_CTRL),
147		- MX6_PAD_NANDF_D1__RAWNAND_D1 \| MUX_PAD_CTRL(NO_PAD_CTRL),
148		- MX6_PAD_NANDF_D2__RAWNAND_D2 \| MUX_PAD_CTRL(NO_PAD_CTRL),
149		- MX6_PAD_NANDF_D3__RAWNAND_D3 \| MUX_PAD_CTRL(NO_PAD_CTRL),
150		- MX6_PAD_NANDF_D4__RAWNAND_D4 \| MUX_PAD_CTRL(NO_PAD_CTRL),
151		- MX6_PAD_NANDF_D5__RAWNAND_D5 \| MUX_PAD_CTRL(NO_PAD_CTRL),
152		- MX6_PAD_NANDF_D6__RAWNAND_D6 \| MUX_PAD_CTRL(NO_PAD_CTRL),
153		- MX6_PAD_NANDF_D7__RAWNAND_D7 \| MUX_PAD_CTRL(NO_PAD_CTRL),
154		- MX6_PAD_SD4_DAT0__RAWNAND_DQS \| MUX_PAD_CTRL(NO_PAD_CTRL),
155		-};
156		-
157		-static void setup_gpmi_nand(void)
158		-{
159		- struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
160		-
161		- /* config gpmi nand iomux */
162		- imx_iomux_v3_setup_multiple_pads(nfc_pads,
163		- ARRAY_SIZE(nfc_pads));
164		-
165		- /* config gpmi and bch clock to 100 MHz */
166		- clrsetbits_le32(&mxc_ccm->cs2cdr,
167		- MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK \|
168		- MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK \|
169		- MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
170		- MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) \|
171		- MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) \|
172		- MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
173		-
174		- /* enable gpmi and bch clock gating */
175		- setbits_le32(&mxc_ccm->CCGR4,
176		- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK \|
177		- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK \|
178		- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK \|
179		- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK \|
180		- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
181		-
182		- /* enable apbh clock gating */
183		- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
184		-}
185		-
186		-static void setup_iomux_enet(void)
187		-{
188		- gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
189		- gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
190		- gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
191		- gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
192		- gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
193		- gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
194		- imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
195		- gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
196		-
197		- /* Need delay 10ms according to KSZ9021 spec */
198		- udelay(1000 * 10);
199		- gpio_set_value(IMX_GPIO_NR(3, 23), 1);
200		-
201		- imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
202		-}
203		-
204		-static void setup_iomux_uart(void)
205		-{
206		- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
207		- imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
208		- imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
209		-}
210		-
211		-#ifdef CONFIG_USB_EHCI_MX6
212		-int board_ehci_hcd_init(int port)
213		-{
214		- return 0;
215		-}
216		-
217		-#endif
218		-
219		-#ifdef CONFIG_FSL_ESDHC
220		-struct fsl_esdhc_cfg usdhc_cfg[1] = {
221		- { USDHC3_BASE_ADDR },
222		-};
223		-
224		-int board_mmc_getcd(struct mmc *mmc)
225		-{
226		- struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
227		-
228		- if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
229		- gpio_direction_input(IMX_GPIO_NR(7, 0));
230		- return !gpio_get_value(IMX_GPIO_NR(7, 0));
231		- }
232		-
233		- return 0;
234		-}
235		-
236		-int board_mmc_init(bd_t *bis)
237		-{
238		- /*
239		- * Only one USDHC controller on titianium
240		- */
241		- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
242		- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
243		-
244		- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
245		-}
246		-#endif
247		-
248		-int board_phy_config(struct phy_device *phydev)
249		-{
250		- /* min rx data delay */
251		- ksz9021_phy_extended_write(phydev,
252		- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
253		- /* min tx data delay */
254		- ksz9021_phy_extended_write(phydev,
255		- MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
256		- /* max rx/tx clock delay, min rx/tx control */
257		- ksz9021_phy_extended_write(phydev,
258		- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
259		- if (phydev->drv->config)
260		- phydev->drv->config(phydev);
261		-
262		- return 0;
263		-}
264		-
265		-int board_eth_init(bd_t *bis)
266		-{
267		- int ret;
268		-
269		- setup_iomux_enet();
270		-
271		- ret = cpu_eth_init(bis);
272		- if (ret)
273		- printf("FEC MXC: %s:failed\n", __func__);
274		-
275		- return ret;
276		-}
277		-
278		-int board_early_init_f(void)
279		-{
280		- setup_iomux_uart();
281		-
282		- return 0;
283		-}
284		-
285		-int board_init(void)
286		-{
287		- /* address of boot parameters */
288		- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
289		-
290		- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
291		- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
292		-
293		- setup_gpmi_nand();
294		-
295		- return 0;
296		-}
297		-
298		-int checkboard(void)
299		-{
300		- puts("Board: Titanium\n");
301		-
302		- return 0;
303		-}
304		-
305		-#ifdef CONFIG_CMD_BMODE
306		-static const struct boot_mode board_boot_modes[] = {
307		- /* NAND */
308		- { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
309		- /* 4 bit bus width */
310		- { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
311		- { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
312		- { NULL, 0 },
313		-};
314		-#endif
315		-
316		-int misc_init_r(void)
317		-{
318		-#ifdef CONFIG_CMD_BMODE
319		- add_board_boot_modes(board_boot_modes);
320		-#endif
321		-
322		- return 0;
323		-}
...	...	@@ -302,7 +302,7 @@
302	302	Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
303	303	Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
304	304	Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
305		-Active arm armv7 mx6 freescale titanium titanium titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg Stefan Roese <sr@denx.de>
	305	+Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr@denx.de>
306	306	Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
307	307	Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
308	308	Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph@8d.com>