Eric Lee / smarc-uboot

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Commit c2fa5dc82da47fef4f49dd505aa52f088e5feb11

Authored by Patrick Delaunay
Committed by Tom Rini
1 parent 8a07d5bfe1
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro 

This patch define RCC_PLLNCFGR2_SHIFT to reuse it in
the pll function for set rate.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>

Showing 1 changed file with 6 additions and 9 deletions Side-by-side Diff

drivers/clk/clk_stm32mp1.c
Diff comments   View file @ c2fa5dc
... ... @@ -175,13 +175,14 @@
175 175 #define RCC_PLLNCFGR1_IFRGE_SHIFT 24
176 176 #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
177 177  
178   -/* used for ALL PLLNCFGR2 registers */
  178 +/* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
  179 +#define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
179 180 #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
180   -#define RCC_PLLNCFGR2_DIVP_SHIFT 0
  181 +#define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
181 182 #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
182   -#define RCC_PLLNCFGR2_DIVQ_SHIFT 8
  183 +#define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
183 184 #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
184   -#define RCC_PLLNCFGR2_DIVR_SHIFT 16
  185 +#define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
185 186 #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
186 187  
187 188 /* used for ALL PLLNFRACR registers */
... ... @@ -814,10 +815,6 @@
814 815 int divm, divn, divy, src;
815 816 ulong refclk, dfout;
816 817 u32 selr, cfgr1, cfgr2, fracr;
817   - const u8 shift[_DIV_NB] = {
818   - [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT,
819   - [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT,
820   - [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT };
821 818  
822 819 debug("%s(%d, %d)\n", __func__, pll_id, div_id);
823 820 if (div_id > _DIV_NB)
... ... @@ -833,7 +830,7 @@
833 830  
834 831 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
835 832 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
836   - divy = (cfgr2 >> shift[div_id]) & RCC_PLLNCFGR2_DIVX_MASK;
  833 + divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
837 834  
838 835 debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy);
839 836