arm: pxa: Add support for ICP DAS LP-8x4x

LP-8x4x is a programmable automation controller by ICP DAS. It is shipped with outdated U-Boot v1.3.0 This patch adds enough supports to boot the board: - 128M of 128M SDRAM - 32M of 48M NOR Flash memory - 1 of 4 Serial consoles (PXA FFUART) - 2 of 2 Ethernet controllers (DM9000) Signed-off-by: Sergey Yanovich <ynvich@gmail.com> Series-to: u-boot Series-cc: marex

arm: pxa: Add support for ICP DAS LP-8x4x
LP-8x4x is a programmable automation controller by ICP DAS. It is shipped with outdated U-Boot v1.3.0 This patch adds enough supports to boot the board: - 128M of 128M SDRAM - 32M of 48M NOR Flash memory - 1 of 4 Serial consoles (PXA FFUART) - 2 of 2 Ethernet controllers (DM9000) Signed-off-by: Sergey Yanovich <ynvich@gmail.com> Series-to: u-boot Series-cc: marex
Sergey Yanovich · Marek Vasut
1 parent 58bb8f5f61
Showing 5 changed files with 455 additions and 0 deletions Side-by-side Diff
MAINTAINERS
board/icpdas/lp8x4x/Makefile
board/icpdas/lp8x4x/lp8x4x.c
boards.cfg
include/configs/lp8x4x.h
@@ -1074,6 +1074,10 @@
  
 	vf610twr	VF610
  
+Sergey Yanovich <ynvich@gmail.com>
+
+	lp8x4x		xscale/pxa
+
 -------------------------------------------------------------------------
  
 Unknown / orphaned boards:
+#
+# ICPDAS LP-8x4x Support
+#
+# Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= lp8x4x.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+/*
+ * ICP DAS LP-8x4x Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * adapted from Voipac PXA270 Support by
+ * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/regs-mmc.h>
+#include <asm/arch/pxa.h>
+#include <netdev.h>
+#include <serial.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	/* We have RAM, disable cache */
+	dcache_disable();
+	icache_disable();
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	pxa2xx_dram_init();
+	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
+#ifdef	CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+	pxa_mmc_register(0);
+	return 0;
+}
+#endif
+
+#ifdef	CONFIG_CMD_USB
+int usb_board_init(void)
+{
+	writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+		UHCHR);
+
+	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+	while (readl(UHCHR) & UHCHR_FSBIR)
+		continue; /* required by checkpath.pl */
+
+	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+	/* Clear any OTG Pin Hold */
+	if (readl(PSSR) & PSSR_OTGPH)
+		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+	writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+	/* Set port power control mask bits, only 3 ports. */
+	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+	/* enable port 2 */
+	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+	return 0;
+}
+
+void usb_board_init_fail(void)
+{
+	return;
+}
+
+void usb_board_stop(void)
+{
+	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+	udelay(11);
+	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+	writel(readl(UHCCOMS) | 1, UHCCOMS);
+	udelay(10);
+
+	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+	return;
+}
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+void lp8x4x_eth1_mac_init(void)
+{
+	u8 eth1addr[8];
+	int i;
+	u8 reg;
+
+	eth_getenv_enetaddr_by_index("eth", 1, eth1addr);
+	if (!is_valid_ether_addr(eth1addr))
+		return;
+
+	for (i = 0, reg = 0x10; i < 6; i++, reg++) {
+		writeb(reg, (u8 *)(DM9000_IO_2));
+		writeb(eth1addr[i], (u8 *)(DM9000_DATA_2));
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+	lp8x4x_eth1_mac_init();
+	return dm9000_initialize(bis);
+}
+#endif
@@ -348,6 +348,7 @@
 scpu                         arm         ixp         pdnb3               prodrive       -           pdnb3:SCPU
 balloon3                     arm         pxa
 h2200                        arm         pxa
+lp8x4x                       arm         pxa         lp8x4x              icpdas
 lubbock                      arm         pxa
 palmld                       arm         pxa
 palmtc                       arm         pxa
+/*
+ * ICP DAS LP-8x4x configuration file
+ *
+ * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__CONFIG_H
+#define	__CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define	CONFIG_CPU_PXA27X			/* Marvell PXA270 CPU */
+#define	MACH_TYPE_LP8X4X		4539	/* ICP DAS LP-8x4x */
+#define	CONFIG_MACH_TYPE		MACH_TYPE_LP8X4X
+#define	CONFIG_SYS_TEXT_BASE		0x00000000
+
+#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
+#define	CONFIG_ARCH_CPU_INIT
+#define	CONFIG_BOOTCOMMAND		\
+	"bootm 80000;"
+
+#define	CONFIG_BOOTARGS			\
+	"console=ttySA0,115200 mem=128M root=/dev/mmcblk0p1 rw" \
+	"init=/sbin/init rootfstype=ext3"
+
+#define	CONFIG_TIMESTAMP
+#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_LZMA			/* LZMA compression support */
+#undef	CONFIG_OF_LIBFDT
+
+/*
+ * Serial Console Configuration
+ */
+#define	CONFIG_PXA_SERIAL
+#define	CONFIG_FFUART			1
+#define	CONFIG_CONS_INDEX		3
+#define	CONFIG_BAUDRATE			115200
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#define	CONFIG_CMD_NET
+#define	CONFIG_CMD_ENV
+#undef	CONFIG_CMD_IMLS
+#define	CONFIG_CMD_MMC
+#define	CONFIG_CMD_USB
+#undef	CONFIG_LCD
+#undef	CONFIG_CMD_IDE
+
+/*
+ * Networking Configuration
+ * chip on the ICPDAS LINPAC board
+ */
+#ifdef	CONFIG_CMD_NET
+#define	CONFIG_CMD_PING
+#define	CONFIG_CMD_DHCP
+
+#define	CONFIG_DRIVER_DM9000		1
+#define	CONFIG_DM9000_BASE		0x0C000000
+#define	DM9000_IO			0x0C000000
+#define	DM9000_DATA			0x0C004000
+#define	DM9000_IO_2			0x0D000000
+#define	DM9000_DATA_2			0x0D004000
+#define	CONFIG_NET_RETRY_COUNT		10
+
+#define	CONFIG_BOOTP_BOOTFILESIZE
+#define	CONFIG_BOOTP_BOOTPATH
+#define	CONFIG_BOOTP_GATEWAY
+#define	CONFIG_BOOTP_HOSTNAME
+#endif
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef	CONFIG_CMD_MMC
+#define	CONFIG_MMC
+#define	CONFIG_GENERIC_MMC
+#define	CONFIG_PXA_MMC_GENERIC
+#define	CONFIG_CMD_FAT
+#define	CONFIG_CMD_EXT2
+#define	CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef	CONFIG_CMD_KGDB
+#define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
+#define	CONFIG_KGDB_SER_INDEX		2	/* which serial port to use */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define	CONFIG_SYS_HUSH_PARSER		1
+
+#undef	CONFIG_SYS_LONGHELP
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT		"$ "
+#else
+#define	CONFIG_SYS_PROMPT		"=> "
+#endif
+#define	CONFIG_SYS_CBSIZE		256
+#define	CONFIG_SYS_PBSIZE		\
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define	CONFIG_SYS_MAXARGS		16
+#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define	CONFIG_SYS_DEVICE_NULLDEV	1
+#define	CONFIG_CMDLINE_EDITING		1
+#define	CONFIG_AUTO_COMPLETE		1
+
+/*
+ * Clock Configuration
+ */
+#define	CONFIG_SYS_HZ			1000		/* Timer @ 3250000 Hz */
+
+/*
+ * DRAM Map
+ */
+#define	CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
+#define	PHYS_SDRAM_1_SIZE		0x08000000	/* 128 MB */
+
+#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
+#define	CONFIG_SYS_DRAM_SIZE		0x08000000	/* 128 MB DRAM */
+
+#define	CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
+#define	CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */
+
+#define	CONFIG_SYS_LOAD_ADDR		0xa0008000
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+/* Use first 64kb bank of the internal SRAM */
+#define	CONFIG_SYS_INIT_SP_ADDR		0x5c010000
+
+/*
+ * NOR FLASH
+ */
+#define	CONFIG_SYS_MONITOR_BASE		0x0
+#define	CONFIG_SYS_MONITOR_LEN		0x40000
+#define	CONFIG_ENV_ADDR			\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define	CONFIG_ENV_SIZE			0x40000
+#define	CONFIG_ENV_SECT_SIZE		0x40000
+
+#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
+#define	PHYS_FLASH_2			0x02000000	/* Flash Bank #2 */
+
+#define	CONFIG_SYS_FLASH_CFI
+#define	CONFIG_FLASH_CFI_DRIVER		1
+
+#define	CONFIG_SYS_MAX_FLASH_SECT	(4 + 255)
+#define	CONFIG_SYS_MAX_FLASH_BANKS	2
+#define	CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, PHYS_FLASH_2 }
+
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ)
+#define	CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ)
+
+#define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define	CONFIG_SYS_FLASH_PROTECTION		1
+
+#define	CONFIG_ENV_IS_IN_FLASH		1
+
+/*
+ * GPIO settings
+ */
+#define	CONFIG_SYS_GPSR0_VAL	0x0808c014
+#define	CONFIG_SYS_GPSR1_VAL	0x00cf0002
+#define	CONFIG_SYS_GPSR2_VAL	0x0221c000
+#define	CONFIG_SYS_GPSR3_VAL	0x00020000
+
+#define	CONFIG_SYS_GPCR0_VAL	0x00000000
+#define	CONFIG_SYS_GPCR1_VAL	0x0000ab80
+#define	CONFIG_SYS_GPCR2_VAL	0x00100000
+#define	CONFIG_SYS_GPCR3_VAL	0x0
+
+#define	CONFIG_SYS_GPDR0_VAL	0xc0e9ddf4
+#define	CONFIG_SYS_GPDR1_VAL	0xfcffab83
+#define	CONFIG_SYS_GPDR2_VAL	0x02f1ffff
+#define	CONFIG_SYS_GPDR3_VAL	0x00021b81
+
+#define	CONFIG_SYS_GAFR0_L_VAL	0x80000000
+#define	CONFIG_SYS_GAFR0_U_VAL	0xa5e54018
+#define	CONFIG_SYS_GAFR1_L_VAL	0x999a955a
+#define	CONFIG_SYS_GAFR1_U_VAL	0xaaa5a00a
+#define	CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
+#define	CONFIG_SYS_GAFR2_U_VAL	0x55f0a402
+#define	CONFIG_SYS_GAFR3_L_VAL	0x540a950c
+#define	CONFIG_SYS_GAFR3_U_VAL	0x00001599
+
+#define	CONFIG_SYS_PSSR_VAL	0x32
+
+/*
+ * Clock settings
+ */
+#define	CONFIG_SYS_CKEN		0x005002c0
+#define	CONFIG_SYS_CCCR		0x02000290
+#define	CONFIG_SYS_CLKCFG	0x0000000b
+
+/*
+ * Memory settings
+ */
+#define	CONFIG_SYS_MSC0_VAL	0x2bd8aad2
+#define	CONFIG_SYS_MSC1_VAL	0xb8c9b8dc
+#define	CONFIG_SYS_MSC2_VAL	0xfff9b8c9
+#define	CONFIG_SYS_FLYCNFG_VAL	0x00010001
+#define	CONFIG_SYS_MDREFR_VAL	0x2093e018
+#define	CONFIG_SYS_MDCNFG_VAL	0x890009d1
+#define	CONFIG_SYS_MDMRS_VAL	0x00220022
+#define	CONFIG_SYS_SXCNFG_VAL	0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define	CONFIG_SYS_MECR_VAL	0x00000001
+#define	CONFIG_SYS_MCMEM0_VAL	0x0000c497
+#define	CONFIG_SYS_MCMEM1_VAL	0x0000c497
+#define	CONFIG_SYS_MCATT0_VAL	0x0000c497
+#define	CONFIG_SYS_MCATT1_VAL	0x0000c497
+#define	CONFIG_SYS_MCIO0_VAL	0x00008407
+#define	CONFIG_SYS_MCIO1_VAL	0x00008407
+
+/*
+ * LCD
+ */
+#ifdef	CONFIG_LCD
+#define	CONFIG_VOIPAC_LCD
+#endif
+
+/*
+ * USB
+ */
+#ifdef	CONFIG_CMD_USB
+#define	CONFIG_USB_OHCI_NEW
+#define	CONFIG_SYS_USB_OHCI_CPU_INIT
+#define	CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define	CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define	CONFIG_SYS_USB_OHCI_REGS_BASE	0x4C000000
+#define	CONFIG_SYS_USB_OHCI_SLOT_NAME	"lp8x4x"
+#define	CONFIG_USB_STORAGE
+#endif
+
+#endif	/* __CONFIG_H */
...	...	@@ -1074,6 +1074,10 @@
1074	1074
1075	1075	vf610twr VF610
1076	1076
	1077	+Sergey Yanovich <ynvich@gmail.com>
	1078	+
	1079	+ lp8x4x xscale/pxa
	1080	+
1077	1081	-------------------------------------------------------------------------
1078	1082
1079	1083	Unknown / orphaned boards:
	1	+#
	2	+# ICPDAS LP-8x4x Support
	3	+#
	4	+# Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
	5	+#
	6	+# This program is free software; you can redistribute it and/or
	7	+# modify it under the terms of the GNU General Public License as
	8	+# published by the Free Software Foundation; either version 2 of
	9	+# the License, or (at your option) any later version.
	10	+#
	11	+# This program is distributed in the hope that it will be useful,
	12	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	+# GNU General Public License for more details.
	15	+#
	16	+# You should have received a copy of the GNU General Public License
	17	+# along with this program; if not, write to the Free Software
	18	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	+# MA 02111-1307 USA
	20	+#
	21	+
	22	+include $(TOPDIR)/config.mk
	23	+
	24	+LIB = $(obj)lib$(BOARD).o
	25	+
	26	+COBJS := lp8x4x.o
	27	+
	28	+SRCS := $(COBJS:.o=.c)
	29	+OBJS := $(addprefix $(obj),$(COBJS))
	30	+
	31	+$(LIB): $(obj).depend $(OBJS)
	32	+ $(call cmd_link_o_target, $(OBJS))
	33	+
	34	+#########################################################################
	35	+
	36	+# defines $(obj).depend target
	37	+include $(SRCTREE)/rules.mk
	38	+
	39	+sinclude $(obj).depend
	40	+
	41	+#########################################################################
	1	+/*
	2	+ * ICP DAS LP-8x4x Support
	3	+ *
	4	+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
	5	+ * adapted from Voipac PXA270 Support by
	6	+ * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+#include <asm/arch/hardware.h>
	26	+#include <asm/arch/regs-mmc.h>
	27	+#include <asm/arch/pxa.h>
	28	+#include <netdev.h>
	29	+#include <serial.h>
	30	+#include <asm/io.h>
	31	+
	32	+DECLARE_GLOBAL_DATA_PTR;
	33	+
	34	+/*
	35	+ * Miscelaneous platform dependent initialisations
	36	+ */
	37	+int board_init(void)
	38	+{
	39	+ /* We have RAM, disable cache */
	40	+ dcache_disable();
	41	+ icache_disable();
	42	+
	43	+ /* memory and cpu-speed are setup before relocation */
	44	+ /* so we do _nothing_ here */
	45	+
	46	+ /* adress of boot parameters */
	47	+ gd->bd->bi_boot_params = 0xa0000100;
	48	+
	49	+ return 0;
	50	+}
	51	+
	52	+int dram_init(void)
	53	+{
	54	+ pxa2xx_dram_init();
	55	+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
	56	+ return 0;
	57	+}
	58	+
	59	+void dram_init_banksize(void)
	60	+{
	61	+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	62	+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
	63	+}
	64	+
	65	+#ifdef CONFIG_CMD_MMC
	66	+int board_mmc_init(bd_t *bis)
	67	+{
	68	+ pxa_mmc_register(0);
	69	+ return 0;
	70	+}
	71	+#endif
	72	+
	73	+#ifdef CONFIG_CMD_USB
	74	+int usb_board_init(void)
	75	+{
	76	+ writel((UHCHR \| UHCHR_PCPL \| UHCHR_PSPL) &
	77	+ ~(UHCHR_SSEP0 \| UHCHR_SSEP1 \| UHCHR_SSEP2 \| UHCHR_SSE),
	78	+ UHCHR);
	79	+
	80	+ writel(readl(UHCHR) \| UHCHR_FSBIR, UHCHR);
	81	+
	82	+ while (readl(UHCHR) & UHCHR_FSBIR)
	83	+ continue; /* required by checkpath.pl */
	84	+
	85	+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
	86	+ writel((UHCHIE_UPRIE \| UHCHIE_RWIE), UHCHIE);
	87	+
	88	+ /* Clear any OTG Pin Hold */
	89	+ if (readl(PSSR) & PSSR_OTGPH)
	90	+ writel(readl(PSSR) \| PSSR_OTGPH, PSSR);
	91	+
	92	+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
	93	+ writel(readl(UHCRHDA) \| 0x100, UHCRHDA);
	94	+
	95	+ /* Set port power control mask bits, only 3 ports. */
	96	+ writel(readl(UHCRHDB) \| (0x7<<17), UHCRHDB);
	97	+
	98	+ /* enable port 2 */
	99	+ writel(readl(UP2OCR) \| UP2OCR_HXOE \| UP2OCR_HXS \|
	100	+ UP2OCR_DMPDE \| UP2OCR_DPPDE, UP2OCR);
	101	+
	102	+ return 0;
	103	+}
	104	+
	105	+void usb_board_init_fail(void)
	106	+{
	107	+ return;
	108	+}
	109	+
	110	+void usb_board_stop(void)
	111	+{
	112	+ writel(readl(UHCHR) \| UHCHR_FHR, UHCHR);
	113	+ udelay(11);
	114	+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
	115	+
	116	+ writel(readl(UHCCOMS) \| 1, UHCCOMS);
	117	+ udelay(10);
	118	+
	119	+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
	120	+
	121	+ return;
	122	+}
	123	+#endif
	124	+
	125	+#ifdef CONFIG_DRIVER_DM9000
	126	+void lp8x4x_eth1_mac_init(void)
	127	+{
	128	+ u8 eth1addr[8];
	129	+ int i;
	130	+ u8 reg;
	131	+
	132	+ eth_getenv_enetaddr_by_index("eth", 1, eth1addr);
	133	+ if (!is_valid_ether_addr(eth1addr))
	134	+ return;
	135	+
	136	+ for (i = 0, reg = 0x10; i < 6; i++, reg++) {
	137	+ writeb(reg, (u8 *)(DM9000_IO_2));
	138	+ writeb(eth1addr[i], (u8 *)(DM9000_DATA_2));
	139	+ }
	140	+}
	141	+
	142	+int board_eth_init(bd_t *bis)
	143	+{
	144	+ lp8x4x_eth1_mac_init();
	145	+ return dm9000_initialize(bis);
	146	+}
	147	+#endif
...	...	@@ -348,6 +348,7 @@
348	348	scpu arm ixp pdnb3 prodrive - pdnb3:SCPU
349	349	balloon3 arm pxa
350	350	h2200 arm pxa
	351	+lp8x4x arm pxa lp8x4x icpdas
351	352	lubbock arm pxa
352	353	palmld arm pxa
353	354	palmtc arm pxa
	1	+/*
	2	+ * ICP DAS LP-8x4x configuration file
	3	+ *
	4	+ * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or
	7	+ * modify it under the terms of the GNU General Public License as
	8	+ * published by the Free Software Foundation; either version 2 of
	9	+ * the License, or (at your option) any later version.
	10	+ *
	11	+ * This program is distributed in the hope that it will be useful,
	12	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	+ * GNU General Public License for more details.
	15	+ *
	16	+ * You should have received a copy of the GNU General Public License
	17	+ * along with this program; if not, write to the Free Software
	18	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	+ * MA 02111-1307 USA
	20	+ */
	21	+
	22	+#ifndef __CONFIG_H
	23	+#define __CONFIG_H
	24	+
	25	+/*
	26	+ * High Level Board Configuration Options
	27	+ */
	28	+#define CONFIG_CPU_PXA27X /* Marvell PXA270 CPU */
	29	+#define MACH_TYPE_LP8X4X 4539 /* ICP DAS LP-8x4x */
	30	+#define CONFIG_MACH_TYPE MACH_TYPE_LP8X4X
	31	+#define CONFIG_SYS_TEXT_BASE 0x00000000
	32	+
	33	+#define CONFIG_SYS_MALLOC_LEN (128*1024)
	34	+#define CONFIG_ARCH_CPU_INIT
	35	+#define CONFIG_BOOTCOMMAND \
	36	+ "bootm 80000;"
	37	+
	38	+#define CONFIG_BOOTARGS \
	39	+ "console=ttySA0,115200 mem=128M root=/dev/mmcblk0p1 rw" \
	40	+ "init=/sbin/init rootfstype=ext3"
	41	+
	42	+#define CONFIG_TIMESTAMP
	43	+#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
	44	+#define CONFIG_CMDLINE_TAG
	45	+#define CONFIG_SETUP_MEMORY_TAGS
	46	+#define CONFIG_LZMA /* LZMA compression support */
	47	+#undef CONFIG_OF_LIBFDT
	48	+
	49	+/*
	50	+ * Serial Console Configuration
	51	+ */
	52	+#define CONFIG_PXA_SERIAL
	53	+#define CONFIG_FFUART 1
	54	+#define CONFIG_CONS_INDEX 3
	55	+#define CONFIG_BAUDRATE 115200
	56	+
	57	+/*
	58	+ * Bootloader Components Configuration
	59	+ */
	60	+#include <config_cmd_default.h>
	61	+
	62	+#define CONFIG_CMD_NET
	63	+#define CONFIG_CMD_ENV
	64	+#undef CONFIG_CMD_IMLS
	65	+#define CONFIG_CMD_MMC
	66	+#define CONFIG_CMD_USB
	67	+#undef CONFIG_LCD
	68	+#undef CONFIG_CMD_IDE
	69	+
	70	+/*
	71	+ * Networking Configuration
	72	+ * chip on the ICPDAS LINPAC board
	73	+ */
	74	+#ifdef CONFIG_CMD_NET
	75	+#define CONFIG_CMD_PING
	76	+#define CONFIG_CMD_DHCP
	77	+
	78	+#define CONFIG_DRIVER_DM9000 1
	79	+#define CONFIG_DM9000_BASE 0x0C000000
	80	+#define DM9000_IO 0x0C000000
	81	+#define DM9000_DATA 0x0C004000
	82	+#define DM9000_IO_2 0x0D000000
	83	+#define DM9000_DATA_2 0x0D004000
	84	+#define CONFIG_NET_RETRY_COUNT 10
	85	+
	86	+#define CONFIG_BOOTP_BOOTFILESIZE
	87	+#define CONFIG_BOOTP_BOOTPATH
	88	+#define CONFIG_BOOTP_GATEWAY
	89	+#define CONFIG_BOOTP_HOSTNAME
	90	+#endif
	91	+
	92	+/*
	93	+ * MMC Card Configuration
	94	+ */
	95	+#ifdef CONFIG_CMD_MMC
	96	+#define CONFIG_MMC
	97	+#define CONFIG_GENERIC_MMC
	98	+#define CONFIG_PXA_MMC_GENERIC
	99	+#define CONFIG_CMD_FAT
	100	+#define CONFIG_CMD_EXT2
	101	+#define CONFIG_DOS_PARTITION
	102	+#endif
	103	+
	104	+/*
	105	+ * KGDB
	106	+ */
	107	+#ifdef CONFIG_CMD_KGDB
	108	+#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
	109	+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	110	+#endif
	111	+
	112	+/*
	113	+ * HUSH Shell Configuration
	114	+ */
	115	+#define CONFIG_SYS_HUSH_PARSER 1
	116	+
	117	+#undef CONFIG_SYS_LONGHELP
	118	+#ifdef CONFIG_SYS_HUSH_PARSER
	119	+#define CONFIG_SYS_PROMPT "$ "
	120	+#else
	121	+#define CONFIG_SYS_PROMPT "=> "
	122	+#endif
	123	+#define CONFIG_SYS_CBSIZE 256
	124	+#define CONFIG_SYS_PBSIZE \
	125	+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	126	+#define CONFIG_SYS_MAXARGS 16
	127	+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	128	+#define CONFIG_SYS_DEVICE_NULLDEV 1
	129	+#define CONFIG_CMDLINE_EDITING 1
	130	+#define CONFIG_AUTO_COMPLETE 1
	131	+
	132	+/*
	133	+ * Clock Configuration
	134	+ */
	135	+#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */
	136	+
	137	+/*
	138	+ * DRAM Map
	139	+ */
	140	+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
	141	+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	142	+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
	143	+
	144	+#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
	145	+#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */
	146	+
	147	+#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
	148	+#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
	149	+
	150	+#define CONFIG_SYS_LOAD_ADDR 0xa0008000
	151	+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	152	+/* Use first 64kb bank of the internal SRAM */
	153	+#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
	154	+
	155	+/*
	156	+ * NOR FLASH
	157	+ */
	158	+#define CONFIG_SYS_MONITOR_BASE 0x0
	159	+#define CONFIG_SYS_MONITOR_LEN 0x40000
	160	+#define CONFIG_ENV_ADDR \
	161	+ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	162	+#define CONFIG_ENV_SIZE 0x40000
	163	+#define CONFIG_ENV_SECT_SIZE 0x40000
	164	+
	165	+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	166	+#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
	167	+
	168	+#define CONFIG_SYS_FLASH_CFI
	169	+#define CONFIG_FLASH_CFI_DRIVER 1
	170	+
	171	+#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
	172	+#define CONFIG_SYS_MAX_FLASH_BANKS 2
	173	+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
	174	+
	175	+#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
	176	+#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
	177	+
	178	+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	179	+#define CONFIG_SYS_FLASH_PROTECTION 1
	180	+
	181	+#define CONFIG_ENV_IS_IN_FLASH 1
	182	+
	183	+/*
	184	+ * GPIO settings
	185	+ */
	186	+#define CONFIG_SYS_GPSR0_VAL 0x0808c014
	187	+#define CONFIG_SYS_GPSR1_VAL 0x00cf0002
	188	+#define CONFIG_SYS_GPSR2_VAL 0x0221c000
	189	+#define CONFIG_SYS_GPSR3_VAL 0x00020000
	190	+
	191	+#define CONFIG_SYS_GPCR0_VAL 0x00000000
	192	+#define CONFIG_SYS_GPCR1_VAL 0x0000ab80
	193	+#define CONFIG_SYS_GPCR2_VAL 0x00100000
	194	+#define CONFIG_SYS_GPCR3_VAL 0x0
	195	+
	196	+#define CONFIG_SYS_GPDR0_VAL 0xc0e9ddf4
	197	+#define CONFIG_SYS_GPDR1_VAL 0xfcffab83
	198	+#define CONFIG_SYS_GPDR2_VAL 0x02f1ffff
	199	+#define CONFIG_SYS_GPDR3_VAL 0x00021b81
	200	+
	201	+#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
	202	+#define CONFIG_SYS_GAFR0_U_VAL 0xa5e54018
	203	+#define CONFIG_SYS_GAFR1_L_VAL 0x999a955a
	204	+#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a
	205	+#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
	206	+#define CONFIG_SYS_GAFR2_U_VAL 0x55f0a402
	207	+#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c
	208	+#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
	209	+
	210	+#define CONFIG_SYS_PSSR_VAL 0x32
	211	+
	212	+/*
	213	+ * Clock settings
	214	+ */
	215	+#define CONFIG_SYS_CKEN 0x005002c0
	216	+#define CONFIG_SYS_CCCR 0x02000290
	217	+#define CONFIG_SYS_CLKCFG 0x0000000b
	218	+
	219	+/*
	220	+ * Memory settings
	221	+ */
	222	+#define CONFIG_SYS_MSC0_VAL 0x2bd8aad2
	223	+#define CONFIG_SYS_MSC1_VAL 0xb8c9b8dc
	224	+#define CONFIG_SYS_MSC2_VAL 0xfff9b8c9
	225	+#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
	226	+#define CONFIG_SYS_MDREFR_VAL 0x2093e018
	227	+#define CONFIG_SYS_MDCNFG_VAL 0x890009d1
	228	+#define CONFIG_SYS_MDMRS_VAL 0x00220022
	229	+#define CONFIG_SYS_SXCNFG_VAL 0x40044004
	230	+
	231	+/*
	232	+ * PCMCIA and CF Interfaces
	233	+ */
	234	+#define CONFIG_SYS_MECR_VAL 0x00000001
	235	+#define CONFIG_SYS_MCMEM0_VAL 0x0000c497
	236	+#define CONFIG_SYS_MCMEM1_VAL 0x0000c497
	237	+#define CONFIG_SYS_MCATT0_VAL 0x0000c497
	238	+#define CONFIG_SYS_MCATT1_VAL 0x0000c497
	239	+#define CONFIG_SYS_MCIO0_VAL 0x00008407
	240	+#define CONFIG_SYS_MCIO1_VAL 0x00008407
	241	+
	242	+/*
	243	+ * LCD
	244	+ */
	245	+#ifdef CONFIG_LCD
	246	+#define CONFIG_VOIPAC_LCD
	247	+#endif
	248	+
	249	+/*
	250	+ * USB
	251	+ */
	252	+#ifdef CONFIG_CMD_USB
	253	+#define CONFIG_USB_OHCI_NEW
	254	+#define CONFIG_SYS_USB_OHCI_CPU_INIT
	255	+#define CONFIG_SYS_USB_OHCI_BOARD_INIT
	256	+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
	257	+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
	258	+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lp8x4x"
	259	+#define CONFIG_USB_STORAGE
	260	+#endif
	261	+
	262	+#endif /* __CONFIG_H */