Eric Lee / smarc-uboot

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Commit c40b29568232761e33400e58be86b15a167d3422

Authored by wdenk
1 parent 6629d2f22b
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

* Patch by Rune Torgersen, 27 Feb 2004: 

- Added LBA48 support (CONFIG_LBA48 & CFG_64BIT_LBA)
  - Added support for 64bit printing in vsprintf (CFG_64BIT_VSPRINTF)
  - Added support for 64bit strtoul (CFG_64BIT_STRTOUL)

* Patch by Masami Komiya, 27 Feb 2004:
  Fix rarpboot: add autoload by NFS

* Patch by Dan Eisenhut, 26 Feb 2004:
  fix flash_write return value in saveenv

* Patch by Stephan Linz, 11 Dec 2003
  expand config.mk to avoid trigraph warnings on NIOS

* Rename "BMS2003" board into "HMI10"

Showing 17 changed files with 849 additions and 637 deletions Side-by-side Diff

... ... @@ -2,6 +2,22 @@
2 2 Changes for U-Boot 1.0.2:
3 3 ======================================================================
4 4  
  5 +* Patch by Rune Torgersen, 27 Feb 2004:
  6 + - Added LBA48 support (CONFIG_LBA48 & CFG_64BIT_LBA)
  7 + - Added support for 64bit printing in vsprintf (CFG_64BIT_VSPRINTF)
  8 + - Added support for 64bit strtoul (CFG_64BIT_STRTOUL)
  9 +
  10 +* Patch by Masami Komiya, 27 Feb 2004:
  11 + Fix rarpboot: add autoload by NFS
  12 +
  13 +* Patch by Dan Eisenhut, 26 Feb 2004:
  14 + fix flash_write return value in saveenv
  15 +
  16 +* Patch by Stephan Linz, 11 Dec 2003
  17 + expand config.mk to avoid trigraph warnings on NIOS
  18 +
  19 +* Rename "BMS2003" board into "HMI10"
  20 +
5 21 * SX1 patches: use "serial#" for USB serial #; use redundand environment
6 22 storage; auto-set console on USB port (using preboot command)
7 23  
... ... @@ -261,9 +261,6 @@
261 261 AMX860_config : unconfig
262 262 @./mkconfig $(@:_config=) ppc mpc8xx amx860 westel
263 263  
264   -bms2003_config : unconfig
265   - @./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
266   -
267 264 c2mon_config: unconfig
268 265 @./mkconfig $(@:_config=) ppc mpc8xx c2mon
269 266  
... ... @@ -304,6 +301,9 @@
304 301  
305 302 hermes_config : unconfig
306 303 @./mkconfig $(@:_config=) ppc mpc8xx hermes
  304 +
  305 +HMI10_config : unconfig
  306 + @./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
307 307  
308 308 IAD210_config: unconfig
309 309 @./mkconfig $(@:_config=) ppc mpc8xx IAD210 siemens
... ... @@ -670,6 +670,18 @@
670 670  
671 671 Set this to enable ATAPI support.
672 672  
  673 +- LBA48 Support
  674 + CONFIG_LBA48
  675 +
  676 + Set this to enable support for disks larger than 137GB
  677 + Also look at CFG_64BIT_LBA ,CFG_64BIT_VSPRINTF and CFG_64BIT_STRTOUL
  678 + Whithout these , LBA48 support uses 32bit variables and will 'only'
  679 + support disks up to 2.1TB.
  680 +
  681 + CFG_64BIT_LBA:
  682 + When enabled, makes the IDE subsystem use 64bit sector addresses.
  683 + Default is 32bit.
  684 +
673 685 - SCSI Support:
674 686 At the moment only there is only support for the
675 687 SYM53C8XX SCSI controller; define
... ... @@ -1712,6 +1724,13 @@
1712 1724  
1713 1725 - CFG_FAULT_MII_ADDR:
1714 1726 MII address of the PHY to check for the Ethernet link state.
  1727 +
  1728 +- CFG_64BIT_VSPRINTF:
  1729 + Makes vsprintf (and all *printf functions) support printing
  1730 + of 64bit values by using the L quantifier
  1731 +
  1732 +- CFG_64BIT_STRTOUL:
  1733 + Adds simple_strtoull that returns a 64bit value
1715 1734  
1716 1735 Low Level (hardware related) configuration options:
1717 1736 ---------------------------------------------------
board/tqm8xx/tqm8xx.c
Diff comments   View file @ c40b295
... ... @@ -425,7 +425,7 @@
425 425  
426 426 #ifdef CONFIG_PS2MULT
427 427  
428   -#ifdef CONFIG_BMS2003
  428 +#ifdef CONFIG_HMI10
429 429 #define BASE_BAUD ( 1843200 / 16 )
430 430 struct serial_state rs_table[] = {
431 431 { BASE_BAUD, 4, (void*)0xec140000 },
432 432  
... ... @@ -441,12 +441,12 @@
441 441 return (0);
442 442 }
443 443 #endif
444   -#endif /* CONFIG_BMS2003 */
  444 +#endif /* CONFIG_HMI10 */
445 445  
446 446 #endif /* CONFIG_PS2MULT */
447 447  
448 448 /* ------------------------------------------------------------------------- */
449   -#ifdef CONFIG_BMS2003
  449 +#ifdef CONFIG_HMI10
450 450  
451 451 int misc_init_r (void)
452 452 {
... ... @@ -476,6 +476,6 @@
476 476 }
477 477 #endif
478 478  
479   -#endif /* CONFIG_BMS2003 */
  479 +#endif /* CONFIG_HMI10 */
480 480 /* ------------------------------------------------------------------------- */
... ... @@ -139,7 +139,7 @@
139 139 /* ------------------------------------------------------------------------- */
140 140  
141 141 #ifdef CONFIG_IDE_LED
142   -#if !defined(CONFIG_KUP4K) && !defined(CONFIG_BMS2003)
  142 +#if !defined(CONFIG_KUP4K) && !defined(CONFIG_HMI10)
143 143 static void ide_led (uchar led, uchar status);
144 144 #else
145 145 extern void ide_led (uchar led, uchar status);
... ... @@ -180,7 +180,7 @@
180 180  
181 181 #ifdef CONFIG_ATAPI
182 182 static void atapi_inquiry(block_dev_desc_t *dev_desc);
183   -ulong atapi_read (int device, ulong blknr, ulong blkcnt, ulong *buffer);
  183 +ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer);
184 184 #endif
185 185  
186 186  
187 187  
... ... @@ -303,11 +303,15 @@
303 303  
304 304 if (strcmp(argv[1],"read") == 0) {
305 305 ulong addr = simple_strtoul(argv[2], NULL, 16);
306   - ulong blk = simple_strtoul(argv[3], NULL, 16);
  306 +#if CFG_64BIT_STRTOUL
  307 + lbaint_t blk = simple_strtoull(argv[3], NULL, 16);
  308 +#else
  309 + lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
  310 +#endif
307 311 ulong cnt = simple_strtoul(argv[4], NULL, 16);
308 312 ulong n;
309 313  
310   - printf ("\nIDE read: device %d block # %ld, count %ld ... ",
  314 + printf ("\nIDE read: device %d block # %qd, count %ld ... ",
311 315 curr_device, blk, cnt);
312 316  
313 317 n = ide_dev_desc[curr_device].block_read (curr_device,
314 318  
... ... @@ -325,11 +329,15 @@
325 329 }
326 330 } else if (strcmp(argv[1],"write") == 0) {
327 331 ulong addr = simple_strtoul(argv[2], NULL, 16);
328   - ulong blk = simple_strtoul(argv[3], NULL, 16);
  332 +#if CFG_64BIT_STRTOUL
  333 + lbaint_t blk = simple_strtoull(argv[3], NULL, 16);
  334 +#else
  335 + lbaint_t blk = simple_strtoul(argv[3], NULL, 16);
  336 +#endif
329 337 ulong cnt = simple_strtoul(argv[4], NULL, 16);
330 338 ulong n;
331 339  
332   - printf ("\nIDE write: device %d block # %ld, count %ld ... ",
  340 + printf ("\nIDE write: device %d block # %qd, count %ld ... ",
333 341 curr_device, blk, cnt);
334 342  
335 343 n = ide_write (curr_device, blk, cnt, (ulong *)addr);
... ... @@ -607,8 +615,7 @@
607 615 ide_led ((LED_IDE1 | LED_IDE2), 0); /* LED's off */
608 616 #ifdef CONFIG_AMIGAONEG3SE
609 617 /* If this is the second bus, the first one was OK */
610   - if (bus != 0)
611   - {
  618 + if (bus != 0) {
612 619 ide_bus_ok[bus] = 0;
613 620 goto skip_bus;
614 621 }
... ... @@ -838,7 +845,7 @@
838 845 static void
839 846 input_swap_data(int dev, ulong *sect_buf, int words)
840 847 {
841   -#ifndef CONFIG_BMS2003
  848 +#ifndef CONFIG_HMI10
842 849 volatile ushort *pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG);
843 850 ushort *dbuf = (ushort *)sect_buf;
844 851  
... ... @@ -846,7 +853,7 @@
846 853 *dbuf++ = ld_le16(pbuf);
847 854 *dbuf++ = ld_le16(pbuf);
848 855 }
849   -#else /* CONFIG_BMS2003 */
  856 +#else /* CONFIG_HMI10 */
850 857 uchar i;
851 858 volatile uchar *pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN);
852 859 volatile uchar *pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD);
... ... @@ -859,7 +866,7 @@
859 866 dbuf+=1;
860 867 }
861 868 }
862   -#endif /* CONFIG_BMS2003 */
  869 +#endif /* CONFIG_HMI10 */
863 870 }
864 871 #endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */
865 872  
... ... @@ -868,7 +875,7 @@
868 875 static void
869 876 output_data(int dev, ulong *sect_buf, int words)
870 877 {
871   -#ifndef CONFIG_BMS2003
  878 +#ifndef CONFIG_HMI10
872 879 ushort *dbuf;
873 880 volatile ushort *pbuf;
874 881  
... ... @@ -880,7 +887,7 @@
880 887 __asm__ volatile ("eieio");
881 888 *pbuf = *dbuf++;
882 889 }
883   -#else /* CONFIG_BMS2003 */
  890 +#else /* CONFIG_HMI10 */
884 891 uchar *dbuf;
885 892 volatile uchar *pbuf_even;
886 893 volatile uchar *pbuf_odd;
... ... @@ -898,7 +905,7 @@
898 905 __asm__ volatile ("eieio");
899 906 *pbuf_odd = *dbuf++;
900 907 }
901   -#endif /* CONFIG_BMS2003 */
  908 +#endif /* CONFIG_HMI10 */
902 909 }
903 910 #else /* ! __PPC__ */
904 911 static void
... ... @@ -912,7 +919,7 @@
912 919 static void
913 920 input_data(int dev, ulong *sect_buf, int words)
914 921 {
915   -#ifndef CONFIG_BMS2003
  922 +#ifndef CONFIG_HMI10
916 923 ushort *dbuf;
917 924 volatile ushort *pbuf;
918 925  
... ... @@ -924,7 +931,7 @@
924 931 __asm__ volatile ("eieio");
925 932 *dbuf++ = *pbuf;
926 933 }
927   -#else /* CONFIG_BMS2003 */
  934 +#else /* CONFIG_HMI10 */
928 935 uchar *dbuf;
929 936 volatile uchar *pbuf_even;
930 937 volatile uchar *pbuf_odd;
... ... @@ -942,7 +949,7 @@
942 949 __asm__ volatile ("eieio");
943 950 *dbuf++ = *pbuf_odd;
944 951 }
945   -#endif /* CONFIG_BMS2003 */
  952 +#endif /* CONFIG_HMI10 */
946 953 }
947 954 #else /* ! __PPC__ */
948 955 static void
... ... @@ -968,8 +975,7 @@
968 975 __asm__ volatile ("eieio");
969 976 }
970 977  
971   - if (words&1)
972   - {
  978 + if (words&1) {
973 979 ushort dummy;
974 980 dummy = *pbuf;
975 981 }
... ... @@ -1023,8 +1029,7 @@
1023 1029 retries = 0;
1024 1030  
1025 1031 /* Warning: This will be tricky to read */
1026   - while (retries <= 1)
1027   - {
  1032 + while (retries <= 1) {
1028 1033 #endif /* CONFIG_AMIGAONEG3SE */
1029 1034  
1030 1035 /* check signature */
... ... @@ -1042,8 +1047,7 @@
1042 1047 * to become ready
1043 1048 */
1044 1049 c = ide_wait (device, ATAPI_TIME_OUT);
1045   - }
1046   - else
  1050 + } else
1047 1051 #endif
1048 1052 {
1049 1053 /* Start Ident Command
... ... @@ -1133,6 +1137,19 @@
1133 1137  
1134 1138 /* swap shorts */
1135 1139 dev_desc->lba = (iop->lba_capacity << 16) | (iop->lba_capacity >> 16);
  1140 +
  1141 +#if CONFIG_LBA48
  1142 + if (iop->command_set_2 & 0x0400) { /* LBA 48 support */
  1143 + dev_desc->lba48support = 1;
  1144 + dev_desc->lba48 = (unsigned long long)iop->lba48_capacity[0] |
  1145 + ((unsigned long long)iop->lba48_capacity[1] << 16) |
  1146 + ((unsigned long long)iop->lba48_capacity[2] << 32) |
  1147 + ((unsigned long long)iop->lba48_capacity[3] << 48);
  1148 + } else {
  1149 + dev_desc->lba48support = 0;
  1150 + dev_desc->lba48 = 0;
  1151 + }
  1152 +#endif /* CONFIG_LBA48 */
1136 1153 /* assuming HD */
1137 1154 dev_desc->type=DEV_TYPE_HARDDISK;
1138 1155 dev_desc->blksz=ATA_BLOCKSIZE;
1139 1156  
1140 1157  
... ... @@ -1158,13 +1175,20 @@
1158 1175  
1159 1176 /* ------------------------------------------------------------------------- */
1160 1177  
1161   -ulong ide_read (int device, ulong blknr, ulong blkcnt, ulong *buffer)
  1178 +ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer)
1162 1179 {
1163 1180 ulong n = 0;
1164 1181 unsigned char c;
1165 1182 unsigned char pwrsave=0; /* power save */
  1183 +#if CONFIG_LBA48
  1184 + unsigned char lba48 = 0;
1166 1185  
1167   - PRINTF ("ide_read dev %d start %lX, blocks %lX buffer at %lX\n",
  1186 + if (blknr & 0x0000fffff0000000) {
  1187 + /* more than 28 bits used, use 48bit mode */
  1188 + lba48 = 1;
  1189 + }
  1190 +#endif
  1191 + PRINTF ("ide_read dev %d start %qX, blocks %lX buffer at %lX\n",
1168 1192 device, blknr, blkcnt, (ulong)buffer);
1169 1193  
1170 1194 ide_led (DEVICE_LED(device), 1); /* LED on */
1171 1195  
1172 1196  
... ... @@ -1208,16 +1232,34 @@
1208 1232 printf ("IDE read: device %d not ready\n", device);
1209 1233 break;
1210 1234 }
1211   -
  1235 +#if CONFIG_LBA48
  1236 + if (lba48) {
  1237 + /* write high bits */
  1238 + ide_outb (device, ATA_SECT_CNT, 0);
  1239 + ide_outb (device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
  1240 + ide_outb (device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
  1241 + ide_outb (device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
  1242 + }
  1243 +#endif
1212 1244 ide_outb (device, ATA_SECT_CNT, 1);
1213 1245 ide_outb (device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
1214 1246 ide_outb (device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
1215 1247 ide_outb (device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
1216   - ide_outb (device, ATA_DEV_HD, ATA_LBA |
1217   - ATA_DEVICE(device) |
1218   - ((blknr >> 24) & 0xF) );
1219   - ide_outb (device, ATA_COMMAND, ATA_CMD_READ);
1220 1248  
  1249 +#if CONFIG_LBA48
  1250 + if (lba48) {
  1251 + ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device) );
  1252 + ide_outb (device, ATA_COMMAND, ATA_CMD_READ_EXT);
  1253 +
  1254 + } else
  1255 +#endif
  1256 + {
  1257 + ide_outb (device, ATA_DEV_HD, ATA_LBA |
  1258 + ATA_DEVICE(device) |
  1259 + ((blknr >> 24) & 0xF) );
  1260 + ide_outb (device, ATA_COMMAND, ATA_CMD_READ);
  1261 + }
  1262 +
1221 1263 udelay (50);
1222 1264  
1223 1265 if(pwrsave) {
1224 1266  
... ... @@ -1228,8 +1270,13 @@
1228 1270 }
1229 1271  
1230 1272 if ((c&(ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR)) != ATA_STAT_DRQ) {
1231   - printf ("Error (no IRQ) dev %d blk %ld: status 0x%02x\n",
  1273 +#if CFG_64BIT_LBA && CFG_64BIT_VSPRINTF
  1274 + printf ("Error (no IRQ) dev %d blk %qd: status 0x%02x\n",
1232 1275 device, blknr, c);
  1276 +#else
  1277 + printf ("Error (no IRQ) dev %d blk %ld: status 0x%02x\n",
  1278 + device, (ulong)blknr, c);
  1279 +#endif
1233 1280 break;
1234 1281 }
1235 1282  
1236 1283  
1237 1284  
... ... @@ -1248,11 +1295,19 @@
1248 1295 /* ------------------------------------------------------------------------- */
1249 1296  
1250 1297  
1251   -ulong ide_write (int device, ulong blknr, ulong blkcnt, ulong *buffer)
  1298 +ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer)
1252 1299 {
1253 1300 ulong n = 0;
1254 1301 unsigned char c;
  1302 +#if CONFIG_LBA48
  1303 + unsigned char lba48 = 0;
1255 1304  
  1305 + if (blknr & 0x0000fffff0000000) {
  1306 + /* more than 28 bits used, use 48bit mode */
  1307 + lba48 = 1;
  1308 + }
  1309 +#endif
  1310 +
1256 1311 ide_led (DEVICE_LED(device), 1); /* LED on */
1257 1312  
1258 1313 /* Select device
1259 1314  
1260 1315  
1261 1316  
1262 1317  
... ... @@ -1267,23 +1322,46 @@
1267 1322 printf ("IDE read: device %d not ready\n", device);
1268 1323 goto WR_OUT;
1269 1324 }
1270   -
  1325 +#if CONFIG_LBA48
  1326 + if (lba48) {
  1327 + /* write high bits */
  1328 + ide_outb (device, ATA_SECT_CNT, 0);
  1329 + ide_outb (device, ATA_LBA_LOW, (blknr >> 24) & 0xFF);
  1330 + ide_outb (device, ATA_LBA_MID, (blknr >> 32) & 0xFF);
  1331 + ide_outb (device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF);
  1332 + }
  1333 +#endif
1271 1334 ide_outb (device, ATA_SECT_CNT, 1);
1272 1335 ide_outb (device, ATA_LBA_LOW, (blknr >> 0) & 0xFF);
1273 1336 ide_outb (device, ATA_LBA_MID, (blknr >> 8) & 0xFF);
1274 1337 ide_outb (device, ATA_LBA_HIGH, (blknr >> 16) & 0xFF);
1275   - ide_outb (device, ATA_DEV_HD, ATA_LBA |
1276   - ATA_DEVICE(device) |
1277   - ((blknr >> 24) & 0xF) );
1278   - ide_outb (device, ATA_COMMAND, ATA_CMD_WRITE);
1279 1338  
  1339 +#if CONFIG_LBA48
  1340 + if (lba48) {
  1341 + ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device) );
  1342 + ide_outb (device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
  1343 +
  1344 + } else
  1345 +#endif
  1346 + {
  1347 + ide_outb (device, ATA_DEV_HD, ATA_LBA |
  1348 + ATA_DEVICE(device) |
  1349 + ((blknr >> 24) & 0xF) );
  1350 + ide_outb (device, ATA_COMMAND, ATA_CMD_WRITE);
  1351 + }
  1352 +
1280 1353 udelay (50);
1281 1354  
1282 1355 c = ide_wait (device, IDE_TIME_OUT); /* can't take over 500 ms */
1283 1356  
1284 1357 if ((c&(ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR)) != ATA_STAT_DRQ) {
1285   - printf ("Error (no IRQ) dev %d blk %ld: status 0x%02x\n",
  1358 +#if CFG_64BIT_LBA && CFG_64BIT_VSPRINTF
  1359 + printf ("Error (no IRQ) dev %d blk %qd: status 0x%02x\n",
1286 1360 device, blknr, c);
  1361 +#else
  1362 + printf ("Error (no IRQ) dev %d blk %ld: status 0x%02x\n",
  1363 + device, (ulong)blknr, c);
  1364 +#endif
1287 1365 goto WR_OUT;
1288 1366 }
1289 1367  
... ... @@ -1426,7 +1504,7 @@
1426 1504  
1427 1505 /* ------------------------------------------------------------------------- */
1428 1506  
1429   -#if defined(CONFIG_IDE_LED) && !defined(CONFIG_AMIGAONEG3SE) && !defined(CONFIG_KUP4K) && !defined(CONFIG_BMS2003)
  1507 +#if defined(CONFIG_IDE_LED) && !defined(CONFIG_AMIGAONEG3SE) && !defined(CONFIG_KUP4K) && !defined(CONFIG_HMI10)
1430 1508  
1431 1509 static uchar led_buffer = 0; /* Buffer for current LED status */
1432 1510  
... ... @@ -1467,7 +1545,7 @@
1467 1545 static void
1468 1546 output_data_shorts(int dev, ushort *sect_buf, int shorts)
1469 1547 {
1470   -#ifndef CONFIG_BMS2003
  1548 +#ifndef CONFIG_HMI10
1471 1549 ushort *dbuf;
1472 1550 volatile ushort *pbuf;
1473 1551  
... ... @@ -1477,7 +1555,7 @@
1477 1555 __asm__ volatile ("eieio");
1478 1556 *pbuf = *dbuf++;
1479 1557 }
1480   -#else /* CONFIG_BMS2003 */
  1558 +#else /* CONFIG_HMI10 */
1481 1559 uchar *dbuf;
1482 1560 volatile uchar *pbuf_even;
1483 1561 volatile uchar *pbuf_odd;
1484 1562  
... ... @@ -1490,13 +1568,13 @@
1490 1568 __asm__ volatile ("eieio");
1491 1569 *pbuf_odd = *dbuf++;
1492 1570 }
1493   -#endif /* CONFIG_BMS2003 */
  1571 +#endif /* CONFIG_HMI10 */
1494 1572 }
1495 1573  
1496 1574 static void
1497 1575 input_data_shorts(int dev, ushort *sect_buf, int shorts)
1498 1576 {
1499   -#ifndef CONFIG_BMS2003
  1577 +#ifndef CONFIG_HMI10
1500 1578 ushort *dbuf;
1501 1579 volatile ushort *pbuf;
1502 1580  
... ... @@ -1506,7 +1584,7 @@
1506 1584 __asm__ volatile ("eieio");
1507 1585 *dbuf++ = *pbuf;
1508 1586 }
1509   -#else /* CONFIG_BMS2003 */
  1587 +#else /* CONFIG_HMI10 */
1510 1588 uchar *dbuf;
1511 1589 volatile uchar *pbuf_even;
1512 1590 volatile uchar *pbuf_odd;
... ... @@ -1519,7 +1597,7 @@
1519 1597 __asm__ volatile ("eieio");
1520 1598 *dbuf++ = *pbuf_odd;
1521 1599 }
1522   -#endif /* CONFIG_BMS2003 */
  1600 +#endif /* CONFIG_HMI10 */
1523 1601 }
1524 1602  
1525 1603 #else /* ! __PPC__ */
... ... @@ -1858,6 +1936,7 @@
1858 1936 ((unsigned long)iobuf[5]<<16) +
1859 1937 ((unsigned long)iobuf[6]<< 8) +
1860 1938 ((unsigned long)iobuf[7]);
  1939 + dev_desc->lba48 = 0; /* ATAPI devices cannot use 48bit addressing (ATA/ATAPI v7) */
1861 1940 return;
1862 1941 }
1863 1942  
... ... @@ -1871,7 +1950,7 @@
1871 1950 #define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */
1872 1951 #define ATAPI_READ_MAX_BLOCK ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE /* max blocks */
1873 1952  
1874   -ulong atapi_read (int device, ulong blknr, ulong blkcnt, ulong *buffer)
  1953 +ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer)
1875 1954 {
1876 1955 ulong n = 0;
1877 1956 unsigned char ccb[12]; /* Command descriptor block */
... ... @@ -160,8 +160,8 @@
160 160 }
161 161 #else
162 162  
163   -#ifdef CONFIG_BMS2003
164   -# define BMS2003_FRAM_TIMING (PCMCIA_SHT(2) | PCMCIA_SST(2) | PCMCIA_SL(4))
  163 +#ifdef CONFIG_HMI10
  164 +# define HMI10_FRAM_TIMING (PCMCIA_SHT(2) | PCMCIA_SST(2) | PCMCIA_SL(4))
165 165 #endif
166 166 #if defined(CONFIG_LWMON) || defined(CONFIG_NSCU)
167 167 # define CFG_PCMCIA_TIMING (PCMCIA_SHT(9) | PCMCIA_SST(3) | PCMCIA_SL(12))
168 168  
... ... @@ -200,14 +200,14 @@
200 200 switch (i) {
201 201 #ifdef CONFIG_IDE_8xx_PCCARD
202 202 case 4:
203   -#ifdef CONFIG_BMS2003
  203 +#ifdef CONFIG_HMI10
204 204 { /* map FRAM area */
205 205 win->or = ( PCMCIA_BSIZE_256K
206 206 | PCMCIA_PPS_8
207 207 | PCMCIA_PRS_ATTR
208 208 | slotbit
209 209 | PCMCIA_PV
210   - | BMS2003_FRAM_TIMING );
  210 + | HMI10_FRAM_TIMING );
211 211 break;
212 212 }
213 213 #endif
... ... @@ -241,7 +241,7 @@
241 241 break;
242 242 }
243 243 #endif /* CONFIG_IDE_8xx_PCCARD */
244   -#ifdef CONFIG_BMS2003
  244 +#ifdef CONFIG_HMI10
245 245 case 3: { /* map I/O window for 4xUART data/ctrl */
246 246 win->br += 0x40000;
247 247 win->or = ( PCMCIA_BSIZE_256K
... ... @@ -252,7 +252,7 @@
252 252 | CFG_PCMCIA_TIMING );
253 253 break;
254 254 }
255   -#endif /* CONFIG_BMS2003 */
  255 +#endif /* CONFIG_HMI10 */
256 256 default: /* set to not valid */
257 257 win->or = 0;
258 258 break;
... ... @@ -636,7 +636,7 @@
636 636 PCMCIA_PGCRX(slot) = reg;
637 637 udelay(500);
638 638  
639   -#ifndef CONFIG_BMS2003
  639 +#ifndef CONFIG_HMI10
640 640 #ifndef CONFIG_NSCU
641 641 /*
642 642 * Configure Port C pins for
... ... @@ -648,7 +648,7 @@
648 648  
649 649 immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
650 650 #endif
651   -#else /* CONFIG_BMS2003 */
  651 +#else /* CONFIG_HMI10 */
652 652 /*
653 653 * Configure Port B pins for
654 654 * 5 Volts Enable and 3 Volts enable
... ... @@ -657,7 +657,7 @@
657 657  
658 658 /* remove all power */
659 659 immap->im_cpm.cp_pbdat |= 0x00000300;
660   -#endif /* CONFIG_BMS2003 */
  660 +#endif /* CONFIG_HMI10 */
661 661  
662 662 /*
663 663 * Make sure there is a card in the slot, then configure the interface.
664 664  
... ... @@ -666,11 +666,11 @@
666 666 debug ("[%d] %s: PIPR(%p)=0x%x\n",
667 667 __LINE__,__FUNCTION__,
668 668 &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
669   -#ifndef CONFIG_BMS2003
  669 +#ifndef CONFIG_HMI10
670 670 if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
671 671 #else
672 672 if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) {
673   -#endif /* CONFIG_BMS2003 */
  673 +#endif /* CONFIG_HMI10 */
674 674 printf (" No Card found\n");
675 675 return (1);
676 676 }
677 677  
678 678  
679 679  
680 680  
681 681  
... ... @@ -686,25 +686,25 @@
686 686 (reg&PCMCIA_VS2(slot))?"n":"ff");
687 687 #ifndef CONFIG_NSCU
688 688 if ((reg & mask) == mask) {
689   -#ifndef CONFIG_BMS2003
  689 +#ifndef CONFIG_HMI10
690 690 immap->im_ioport.iop_pcdat |= 0x0004;
691 691 #else
692 692 immap->im_cpm.cp_pbdat &= ~(0x0000100);
693   -#endif /* CONFIG_BMS2003 */
  693 +#endif /* CONFIG_HMI10 */
694 694 puts (" 5.0V card found: ");
695 695 } else {
696   -#ifndef CONFIG_BMS2003
  696 +#ifndef CONFIG_HMI10
697 697 immap->im_ioport.iop_pcdat |= 0x0002;
698 698 #else
699 699 immap->im_cpm.cp_pbdat &= ~(0x0000200);
700   -#endif /* CONFIG_BMS2003 */
  700 +#endif /* CONFIG_HMI10 */
701 701 puts (" 3.3V card found: ");
702 702 }
703   -#ifndef CONFIG_BMS2003
  703 +#ifndef CONFIG_HMI10
704 704 immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004);
705 705 #else
706 706 immap->im_cpm.cp_pbdir |= 0x00000300;
707   -#endif /* CONFIG_BMS2003 */
  707 +#endif /* CONFIG_HMI10 */
708 708 #else
709 709 if ((reg & mask) == mask) {
710 710 puts (" 5.0V card found: ");
711 711  
712 712  
... ... @@ -749,14 +749,14 @@
749 749 immap = (immap_t *)CFG_IMMR;
750 750 pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
751 751  
752   -#ifndef CONFIG_BMS2003
  752 +#ifndef CONFIG_HMI10
753 753 #ifndef CONFIG_NSCU
754 754 /* remove all power */
755 755 immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004);
756 756 #endif
757   -#else /* CONFIG_BMS2003 */
  757 +#else /* CONFIG_HMI10 */
758 758 immap->im_cpm.cp_pbdat |= 0x00000300;
759   -#endif /* CONFIG_BMS2003 */
  759 +#endif /* CONFIG_HMI10 */
760 760  
761 761 debug ("Disable PCMCIA buffers and assert RESET\n");
762 762 reg = 0;
... ... @@ -806,7 +806,7 @@
806 806 PCMCIA_PGCRX(slot) = reg;
807 807 udelay(500);
808 808  
809   -#ifndef CONFIG_BMS2003
  809 +#ifndef CONFIG_HMI10
810 810 /*
811 811 * Configure Port C pins for
812 812 * 5 Volts Enable and 3 Volts enable,
... ... @@ -824,7 +824,7 @@
824 824 case 50: reg |= 0x0004; break;
825 825 default: goto done;
826 826 }
827   -#else /* CONFIG_BMS2003 */
  827 +#else /* CONFIG_HMI10 */
828 828 /*
829 829 * Configure Port B pins for
830 830 * 5 Volts Enable and 3 Volts enable,
... ... @@ -843,7 +843,7 @@
843 843 case 50: reg |= 0x00000100; break;
844 844 default: goto done;
845 845 }
846   -#endif /* CONFIG_BMS2003 */
  846 +#endif /* CONFIG_HMI10 */
847 847  
848 848 /* Checking supported voltages */
849 849  
850 850  
851 851  
852 852  
... ... @@ -851,21 +851,21 @@
851 851 pcmp->pcmc_pipr,
852 852 (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
853 853  
854   -#ifndef CONFIG_BMS2003
  854 +#ifndef CONFIG_HMI10
855 855 immap->im_ioport.iop_pcdat |= reg;
856 856 immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004);
857 857 #else
858 858 immap->im_cpm.cp_pbdat &= !reg;
859 859 immap->im_cpm.cp_pbdir |= 0x00000300;
860   -#endif /* CONFIG_BMS2003 */
  860 +#endif /* CONFIG_HMI10 */
861 861 if (reg) {
862   -#ifndef CONFIG_BMS2003
  862 +#ifndef CONFIG_HMI10
863 863 debug ("PCMCIA powered at %sV\n",
864 864 (reg&0x0004) ? "5.0" : "3.3");
865 865 #else
866 866 debug ("PCMCIA powered at %sV\n",
867 867 (reg&0x00000200) ? "5.0" : "3.3");
868   -#endif /* CONFIG_BMS2003 */
  868 +#endif /* CONFIG_HMI10 */
869 869 } else {
870 870 debug ("PCMCIA powered down\n");
871 871 }
872 872  
... ... @@ -1850,11 +1850,11 @@
1850 1850 debug ("[%d] %s: PIPR(%p)=0x%x\n",
1851 1851 __LINE__,__FUNCTION__,
1852 1852 &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
1853   -#ifndef CONFIG_BMS2003
  1853 +#ifndef CONFIG_HMI10
1854 1854 if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
1855 1855 #else
1856 1856 if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) {
1857   -#endif /* CONFIG_BMS2003 */
  1857 +#endif /* CONFIG_HMI10 */
1858 1858 printf (" No Card found\n");
1859 1859 return (1);
1860 1860 }
... ... @@ -207,21 +207,21 @@
207 207 debug (" %08lX ... %08lX ...",
208 208 (ulong)&(flash_addr_new->data),
209 209 sizeof(env_ptr->data)+(ulong)&(flash_addr_new->data));
210   - if (flash_write(env_ptr->data,
  210 + if ((rc = flash_write(env_ptr->data,
211 211 (ulong)&(flash_addr_new->data),
212   - sizeof(env_ptr->data)) ||
  212 + sizeof(env_ptr->data))) ||
213 213  
214   - flash_write((char *)&(env_ptr->crc),
  214 + (rc = flash_write((char *)&(env_ptr->crc),
215 215 (ulong)&(flash_addr_new->crc),
216   - sizeof(env_ptr->crc)) ||
  216 + sizeof(env_ptr->crc))) ||
217 217  
218   - flash_write((char *)&obsolete_flag,
  218 + (rc = flash_write((char *)&obsolete_flag,
219 219 (ulong)&(flash_addr->flags),
220   - sizeof(flash_addr->flags)) ||
  220 + sizeof(flash_addr->flags))) ||
221 221  
222   - flash_write((char *)&active_flag,
  222 + (rc = flash_write((char *)&active_flag,
223 223 (ulong)&(flash_addr_new->flags),
224   - sizeof(flash_addr_new->flags)))
  224 + sizeof(flash_addr_new->flags))))
225 225 {
226 226 flash_perror (rc);
227 227 goto Done;
... ... @@ -122,6 +122,14 @@
122 122 CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes
123 123 endif
124 124  
  125 +# avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9)
  126 +# this option have to be placed behind -Wall -- that's why it is here
  127 +ifeq ($(ARCH),nios)
  128 +ifeq ($(findstring 2.9,$(shell $(CC) --version)),2.9)
  129 +CFLAGS := $(CPPFLAGS) -Wno-trigraphs
  130 +endif
  131 +endif
  132 +
125 133 AFLAGS_DEBUG := -Wa,-gstabs
126 134 AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS)
127 135  
... ... @@ -44,7 +44,11 @@
44 44 */
45 45 void dev_print (block_dev_desc_t *dev_desc)
46 46 {
47   - ulong lba512; /* number of blocks if 512bytes block size */
  47 +#if CONFIG_LBA48
  48 + uint64_t lba512; /* number of blocks if 512bytes block size */
  49 +#else
  50 + lbaint_t lba512;
  51 +#endif
48 52  
49 53 if (dev_desc->type==DEV_TYPE_UNKNOWN) {
50 54 puts ("not available\n");
51 55  
... ... @@ -82,9 +86,15 @@
82 86 puts ("\n");
83 87 if ((dev_desc->lba * dev_desc->blksz)>0L) {
84 88 ulong mb, mb_quot, mb_rem, gb, gb_quot, gb_rem;
  89 + lbaint_t lba;
  90 +#if CONFIG_LBA48
  91 + if (dev_desc->lba48support)
  92 + lba = dev_desc->lba48;
  93 + else
  94 +#endif
  95 + lba = dev_desc->lba;
85 96  
86   - lba512 = (dev_desc->lba * (dev_desc->blksz/512));
87   -
  97 + lba512 = (lba * (dev_desc->blksz/512));
88 98 mb = (10 * lba512) / 2048; /* 2048 = (1024 * 1024) / 512 MB */
89 99 /* round to 1 digit */
90 100 mb_quot = mb / 10;
91 101  
92 102  
... ... @@ -93,12 +103,23 @@
93 103 gb = mb / 1024;
94 104 gb_quot = gb / 10;
95 105 gb_rem = gb - (10 * gb_quot);
96   -
  106 +#if CONFIG_LBA48
  107 + if (dev_desc->lba48support)
  108 + printf (" Supports 48-bit addressing\n");
  109 +#endif
  110 +#if CFG_64BIT_LBA && CFG_64BIT_VSPRINTF
  111 + printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%qd x %ld)\n",
  112 + mb_quot, mb_rem,
  113 + gb_quot, gb_rem,
  114 + lba,
  115 + dev_desc->blksz);
  116 +#else
97 117 printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\n",
98 118 mb_quot, mb_rem,
99 119 gb_quot, gb_rem,
100   - dev_desc->lba,
  120 + (ulong)lba,
101 121 dev_desc->blksz);
  122 +#endif
102 123 } else {
103 124 puts (" Capacity: not available\n");
104 125 }
... ... @@ -106,6 +106,10 @@
106 106 #define ATA_CMD_SETF 0xEF /* Set Features */
107 107 #define ATA_CMD_CHK_PWR 0xE5 /* Check Power Mode */
108 108  
  109 +#define ATA_CMD_READ_EXT 0x24 /* Read Sectors (with retries) with 48bit addressing */
  110 +#define ATA_CMD_WRITE_EXT 0x34 /* Write Sectores (with retries) with 48bit addressing */
  111 +#define ATA_CMD_VRFY_EXT 0x42 /* Read Verify (with retries) with 48bit addressing */
  112 +
109 113 /*
110 114 * ATAPI Commands
111 115 */
... ... @@ -192,7 +196,7 @@
192 196 unsigned short major_rev_num; /* */
193 197 unsigned short minor_rev_num; /* */
194 198 unsigned short command_set_1; /* bits 0:Smart 1:Security 2:Removable 3:PM */
195   - unsigned short command_set_2; /* bits 14:Smart Enabled 13:0 zero */
  199 + unsigned short command_set_2; /* bits 14:Smart Enabled 13:0 zero 10:lba48 support*/
196 200 unsigned short cfsse; /* command set-feature supported extensions */
197 201 unsigned short cfs_enable_1; /* command set-feature enabled */
198 202 unsigned short cfs_enable_2; /* command set-feature enabled */
... ... @@ -203,7 +207,10 @@
203 207 unsigned short CurAPMvalues; /* current APM values */
204 208 unsigned short word92; /* reserved (word 92) */
205 209 unsigned short hw_config; /* hardware config */
206   - unsigned short words94_125[32];/* reserved words 94-125 */
  210 + unsigned short words94_99[6];/* reserved words 94-99 */
  211 + //unsigned long long lba48_capacity; /* 4 16bit values containing lba 48 total number of sectors */
  212 + unsigned short lba48_capacity[4]; /* 4 16bit values containing lba 48 total number of sectors */
  213 + unsigned short words104_125[22];/* reserved words 104-125 */
207 214 unsigned short last_lun; /* reserved (word 126) */
208 215 unsigned short word127; /* reserved (word 127) */
209 216 unsigned short dlf; /* device lock function
... ... @@ -459,6 +459,9 @@
459 459  
460 460 /* lib_generic/vsprintf.c */
461 461 ulong simple_strtoul(const char *cp,char **endp,unsigned int base);
  462 +#if CFG_64BIT_VSPRINTF
  463 +unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base);
  464 +#endif
462 465 long simple_strtol(const char *cp,char **endp,unsigned int base);
463 466 void panic(const char *fmt, ...);
464 467 int sprintf(char * buf, const char *fmt, ...);
include/configs/HMI10.h
Diff comments   View file @ c40b295
  1 +/*
  2 + * (C) Copyright 2000-2003
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * board/config.h - configuration options, board specific
  26 + */
  27 +
  28 +#ifndef __CONFIG_H
  29 +#define __CONFIG_H
  30 +
  31 +/*
  32 + * High Level Configuration Options
  33 + * (easy to change)
  34 + */
  35 +
  36 +#define CONFIG_HMI10
  37 +#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
  38 +#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
  39 +
  40 +#define CONFIG_LCD
  41 +#define CONFIG_NEC_NL6448BC33_54 /* NEC NL6448BC33_54 display */
  42 +
  43 +#ifdef CONFIG_LCD /* with LCD controller ? */
  44 +#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
  45 +#endif
  46 +
  47 +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
  48 +#undef CONFIG_8xx_CONS_SMC2
  49 +#undef CONFIG_8xx_CONS_NONE
  50 +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
  51 +
  52 +#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
  53 +#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
  54 +#define CONFIG_PS2SERIAL 2 /* .. on COM3 */
  55 +#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
  56 +
  57 +#define CONFIG_BOOTCOUNT_LIMIT
  58 +
  59 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  60 +
  61 +#define CONFIG_BOARD_TYPES 1 /* support board types */
  62 +
  63 +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
  64 +
  65 +#undef CONFIG_BOOTARGS
  66 +
  67 +#define CONFIG_EXTRA_ENV_SETTINGS \
  68 + "netdev=eth0\0" \
  69 + "nfsargs=setenv bootargs root=/dev/nfs rw " \
  70 + "nfsroot=$(serverip):$(rootpath)\0" \
  71 + "ramargs=setenv bootargs root=/dev/ram rw\0" \
  72 + "addip=setenv bootargs $(bootargs) " \
  73 + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
  74 + ":$(hostname):$(netdev):off panic=1\0" \
  75 + "flash_nfs=run nfsargs addip;" \
  76 + "bootm $(kernel_addr)\0" \
  77 + "flash_self=run ramargs addip;" \
  78 + "bootm $(kernel_addr) $(ramdisk_addr)\0" \
  79 + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
  80 + "rootpath=/opt/eldk/ppc_8xx\0" \
  81 + "bootfile=/tftpboot/HMI10/uImage\0" \
  82 + "kernel_addr=40040000\0" \
  83 + "ramdisk_addr=40100000\0" \
  84 + ""
  85 +#define CONFIG_BOOTCOMMAND "run flash_self"
  86 +
  87 +#define CONFIG_BOARD_EARLY_INIT_R 1
  88 +#define CONFIG_MISC_INIT_R 1
  89 +
  90 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  91 +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  92 +
  93 +/* enable I2C and select the hardware/software driver */
  94 +#undef CONFIG_HARD_I2C /* I2C with hardware support */
  95 +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
  96 +
  97 +#define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */
  98 +#define CFG_I2C_SLAVE 0xFE
  99 +
  100 +/* Software (bit-bang) I2C driver configuration */
  101 +#define PB_SCL 0x00000020 /* PB 26 */
  102 +#define PB_SDA 0x00000010 /* PB 27 */
  103 +
  104 +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
  105 +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
  106 +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
  107 +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
  108 +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
  109 + else immr->im_cpm.cp_pbdat &= ~PB_SDA
  110 +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
  111 + else immr->im_cpm.cp_pbdat &= ~PB_SCL
  112 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
  113 +
  114 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  115 +
  116 +#define CONFIG_STATUS_LED 1 /* Status LED enabled */
  117 +
  118 +#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
  119 +
  120 +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  121 +
  122 +#define CONFIG_MAC_PARTITION
  123 +#define CONFIG_DOS_PARTITION
  124 +
  125 +#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
  126 +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  127 +
  128 +#ifdef CONFIG_SPLASH_SCREEN
  129 +# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
  130 + CFG_CMD_ASKENV | \
  131 + CFG_CMD_BMP | \
  132 + CFG_CMD_DATE | \
  133 + CFG_CMD_DHCP | \
  134 + CFG_CMD_I2C | \
  135 + CFG_CMD_IDE )
  136 +#else
  137 +# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
  138 + CFG_CMD_ASKENV | \
  139 + CFG_CMD_DATE | \
  140 + CFG_CMD_DHCP | \
  141 + CFG_CMD_I2C | \
  142 + CFG_CMD_IDE )
  143 +#endif
  144 +
  145 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  146 +#include <cmd_confdefs.h>
  147 +
  148 +/*
  149 + * Miscellaneous configurable options
  150 + */
  151 +#define CFG_LONGHELP /* undef to save memory */
  152 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  153 +
  154 +#if 0
  155 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
  156 +#endif
  157 +#ifdef CFG_HUSH_PARSER
  158 +#define CFG_PROMPT_HUSH_PS2 "> "
  159 +#endif
  160 +
  161 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  162 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  163 +#else
  164 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  165 +#endif
  166 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  167 +#define CFG_MAXARGS 16 /* max number of command args */
  168 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  169 +
  170 +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  171 +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  172 +
  173 +#define CFG_LOAD_ADDR 0x100000 /* default load address */
  174 +
  175 +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  176 +
  177 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  178 +
  179 +/*
  180 + * Low Level Configuration Settings
  181 + * (address mappings, register initial values, etc.)
  182 + * You should know what you are doing if you make changes here.
  183 + */
  184 +/*-----------------------------------------------------------------------
  185 + * Internal Memory Mapped Register
  186 + */
  187 +#define CFG_IMMR 0xFFF00000
  188 +
  189 +/*-----------------------------------------------------------------------
  190 + * Definitions for initial stack pointer and data area (in DPRAM)
  191 + */
  192 +#define CFG_INIT_RAM_ADDR CFG_IMMR
  193 +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  194 +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  195 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  196 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  197 +
  198 +/*-----------------------------------------------------------------------
  199 + * Start addresses for the final memory configuration
  200 + * (Set up by the startup code)
  201 + * Please note that CFG_SDRAM_BASE _must_ start at 0
  202 + */
  203 +#define CFG_SDRAM_BASE 0x00000000
  204 +#define CFG_FLASH_BASE 0x40000000
  205 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  206 +#define CFG_MONITOR_BASE CFG_FLASH_BASE
  207 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  208 +
  209 +/*
  210 + * For booting Linux, the board info and command line data
  211 + * have to be in the first 8 MB of memory, since this is
  212 + * the maximum mapped by the Linux kernel during initialization.
  213 + */
  214 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  215 +
  216 +/*-----------------------------------------------------------------------
  217 + * FLASH organization
  218 + */
  219 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
  220 +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
  221 +
  222 +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  223 +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  224 +
  225 +#define CFG_ENV_IS_IN_FLASH 1
  226 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
  227 +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  228 +
  229 +/* Address and size of Redundant Environment Sector */
  230 +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
  231 +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
  232 +
  233 +/*-----------------------------------------------------------------------
  234 + * Hardware Information Block
  235 + */
  236 +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
  237 +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
  238 +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
  239 +
  240 +/*-----------------------------------------------------------------------
  241 + * Cache Configuration
  242 + */
  243 +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  244 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  245 +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  246 +#endif
  247 +
  248 +/*-----------------------------------------------------------------------
  249 + * SYPCR - System Protection Control 11-9
  250 + * SYPCR can only be written once after reset!
  251 + *-----------------------------------------------------------------------
  252 + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  253 + */
  254 +#if defined(CONFIG_WATCHDOG)
  255 +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  256 + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  257 +#else
  258 +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  259 +#endif
  260 +
  261 +/*-----------------------------------------------------------------------
  262 + * SIUMCR - SIU Module Configuration 11-6
  263 + *-----------------------------------------------------------------------
  264 + * PCMCIA config., multi-function pin tri-state
  265 + */
  266 +#ifndef CONFIG_CAN_DRIVER
  267 +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  268 +#else /* we must activate GPL5 in the SIUMCR for CAN */
  269 +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  270 +#endif /* CONFIG_CAN_DRIVER */
  271 +
  272 +/*-----------------------------------------------------------------------
  273 + * TBSCR - Time Base Status and Control 11-26
  274 + *-----------------------------------------------------------------------
  275 + * Clear Reference Interrupt Status, Timebase freezing enabled
  276 + */
  277 +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  278 +
  279 +/*-----------------------------------------------------------------------
  280 + * RTCSC - Real-Time Clock Status and Control Register 11-27
  281 + *-----------------------------------------------------------------------
  282 + */
  283 +#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  284 +
  285 +/*-----------------------------------------------------------------------
  286 + * PISCR - Periodic Interrupt Status and Control 11-31
  287 + *-----------------------------------------------------------------------
  288 + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  289 + */
  290 +#define CFG_PISCR (PISCR_PS | PISCR_PITF)
  291 +
  292 +/*-----------------------------------------------------------------------
  293 + * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  294 + *-----------------------------------------------------------------------
  295 + * Reset PLL lock status sticky bit, timer expired status bit and timer
  296 + * interrupt status bit
  297 + *
  298 + * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
  299 + */
  300 +#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
  301 +#define CFG_PLPRCR \
  302 + ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
  303 +#else /* up to 66 MHz we use a 1:1 clock */
  304 +#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
  305 +#endif /* CONFIG_80MHz */
  306 +
  307 +/*-----------------------------------------------------------------------
  308 + * SCCR - System Clock and reset Control Register 15-27
  309 + *-----------------------------------------------------------------------
  310 + * Set clock output, timebase and RTC source and divider,
  311 + * power management and some other internal clocks
  312 + */
  313 +#define SCCR_MASK SCCR_EBDF11
  314 +#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
  315 +#define CFG_SCCR (/* SCCR_TBS | */ \
  316 + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  317 + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  318 + SCCR_DFALCD00)
  319 +#else /* up to 66 MHz we use a 1:1 clock */
  320 +#define CFG_SCCR (SCCR_TBS | \
  321 + SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  322 + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  323 + SCCR_DFALCD00)
  324 +#endif /* CONFIG_80MHz */
  325 +
  326 +/*-----------------------------------------------------------------------
  327 + * PCMCIA stuff
  328 + *-----------------------------------------------------------------------
  329 + *
  330 + */
  331 +#ifndef CONFIG_HMI10
  332 +#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
  333 +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
  334 +#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
  335 +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
  336 +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
  337 +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  338 +#define CFG_PCMCIA_IO_ADDR (0xEC000000)
  339 +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
  340 +#else /* CONFIG_HMI10 */
  341 +#define CFG_PCMCIA_MEM_ADDR (0xE0100000)
  342 +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
  343 +#define CFG_PCMCIA_DMA_ADDR (0xE4100000)
  344 +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
  345 +#define CFG_PCMCIA_ATTRB_ADDR (0xE8100000)
  346 +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  347 +#define CFG_PCMCIA_IO_ADDR (0xEC100000)
  348 +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
  349 +#define PCMCIA_MEM_WIN_NO 5
  350 +#define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */
  351 +#endif
  352 +
  353 +/*-----------------------------------------------------------------------
  354 + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
  355 + *-----------------------------------------------------------------------
  356 + */
  357 +
  358 +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
  359 +
  360 +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  361 +#undef CONFIG_IDE_RESET /* reset for ide not supported */
  362 +#ifndef CONFIG_STATUS_LED /* Status and IDE LED's are mutually exclusive */
  363 +#define CONFIG_IDE_LED 1 /* LED for ide supported */
  364 +#endif
  365 +
  366 +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
  367 +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  368 +
  369 +#define CFG_ATA_IDE0_OFFSET 0x0000
  370 +
  371 +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
  372 +
  373 +/* Offset for data I/O */
  374 +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
  375 +
  376 +/* Offset for normal register accesses */
  377 +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
  378 +
  379 +/* Offset for alternate registers */
  380 +#define CFG_ATA_ALT_OFFSET 0x0100
  381 +
  382 +/*-----------------------------------------------------------------------
  383 + *
  384 + *-----------------------------------------------------------------------
  385 + *
  386 + */
  387 +#define CFG_DER 0
  388 +
  389 +/*
  390 + * Init Memory Controller:
  391 + *
  392 + * BR0/1 and OR0/1 (FLASH)
  393 + */
  394 +
  395 +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
  396 +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
  397 +
  398 +/* used to re-map FLASH both when starting from SRAM or FLASH:
  399 + * restrict access enough to keep SRAM working (if any)
  400 + * but not too much to meddle with FLASH accesses
  401 + */
  402 +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
  403 +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
  404 +
  405 +/*
  406 + * FLASH timing:
  407 + */
  408 +#if defined(CONFIG_80MHz)
  409 +/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
  410 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
  411 + OR_SCY_3_CLK | OR_EHTR | OR_BI)
  412 +#elif defined(CONFIG_66MHz)
  413 +/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
  414 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
  415 + OR_SCY_3_CLK | OR_EHTR | OR_BI)
  416 +#else /* 50 MHz */
  417 +/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
  418 +#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
  419 + OR_SCY_2_CLK | OR_EHTR | OR_BI)
  420 +#endif /*CONFIG_??MHz */
  421 +
  422 +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
  423 +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
  424 +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
  425 +
  426 +#define CFG_OR1_REMAP CFG_OR0_REMAP
  427 +#define CFG_OR1_PRELIM CFG_OR0_PRELIM
  428 +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
  429 +
  430 +/*
  431 + * BR2/3 and OR2/3 (SDRAM)
  432 + *
  433 + */
  434 +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
  435 +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
  436 +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
  437 +
  438 +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
  439 +#define CFG_OR_TIMING_SDRAM 0x00000A00
  440 +
  441 +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
  442 +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  443 +
  444 +#ifndef CONFIG_CAN_DRIVER
  445 +#define CFG_OR3_PRELIM CFG_OR2_PRELIM
  446 +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  447 +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
  448 +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
  449 +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
  450 +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
  451 +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
  452 + BR_PS_8 | BR_MS_UPMB | BR_V )
  453 +#endif /* CONFIG_CAN_DRIVER */
  454 +
  455 +/*
  456 + * Memory Periodic Timer Prescaler
  457 + *
  458 + * The Divider for PTA (refresh timer) configuration is based on an
  459 + * example SDRAM configuration (64 MBit, one bank). The adjustment to
  460 + * the number of chip selects (NCS) and the actually needed refresh
  461 + * rate is done by setting MPTPR.
  462 + *
  463 + * PTA is calculated from
  464 + * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
  465 + *
  466 + * gclk CPU clock (not bus clock!)
  467 + * Trefresh Refresh cycle * 4 (four word bursts used)
  468 + *
  469 + * 4096 Rows from SDRAM example configuration
  470 + * 1000 factor s -> ms
  471 + * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
  472 + * 4 Number of refresh cycles per period
  473 + * 64 Refresh cycle in ms per number of rows
  474 + * --------------------------------------------
  475 + * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
  476 + *
  477 + * 50 MHz => 50.000.000 / Divider = 98
  478 + * 66 Mhz => 66.000.000 / Divider = 129
  479 + * 80 Mhz => 80.000.000 / Divider = 156
  480 + */
  481 +#if defined(CONFIG_80MHz)
  482 +#define CFG_MAMR_PTA 156
  483 +#elif defined(CONFIG_66MHz)
  484 +#define CFG_MAMR_PTA 129
  485 +#else /* 50 MHz */
  486 +#define CFG_MAMR_PTA 98
  487 +#endif /*CONFIG_??MHz */
  488 +
  489 +/*
  490 + * For 16 MBit, refresh rates could be 31.3 us
  491 + * (= 64 ms / 2K = 125 / quad bursts).
  492 + * For a simpler initialization, 15.6 us is used instead.
  493 + *
  494 + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
  495 + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
  496 + */
  497 +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
  498 +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
  499 +
  500 +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
  501 +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
  502 +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
  503 +
  504 +/*
  505 + * MAMR settings for SDRAM
  506 + */
  507 +
  508 +/* 8 column SDRAM */
  509 +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  510 + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
  511 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  512 +/* 9 column SDRAM */
  513 +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  514 + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
  515 + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  516 +
  517 +
  518 +/*
  519 + * Internal Definitions
  520 + *
  521 + * Boot Flags
  522 + */
  523 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  524 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  525 +
  526 +#endif /* __CONFIG_H */
include/configs/bms2003.h
View file @ c40b295
1   -/*
2   - * (C) Copyright 2000-2003
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -/*
25   - * board/config.h - configuration options, board specific
26   - */
27   -
28   -#ifndef __CONFIG_H
29   -#define __CONFIG_H
30   -
31   -/*
32   - * High Level Configuration Options
33   - * (easy to change)
34   - */
35   -
36   -#define CONFIG_BMS2003
37   -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
38   -#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
39   -
40   -#define CONFIG_LCD
41   -#define CONFIG_NEC_NL6448BC33_54 /* NEC NL6448BC33_54 display */
42   -
43   -#ifdef CONFIG_LCD /* with LCD controller ? */
44   -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
45   -#endif
46   -
47   -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
48   -#undef CONFIG_8xx_CONS_SMC2
49   -#undef CONFIG_8xx_CONS_NONE
50   -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
51   -
52   -#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
53   -#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
54   -#define CONFIG_PS2SERIAL 2 /* .. on COM3 */
55   -#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
56   -
57   -#define CONFIG_BOOTCOUNT_LIMIT
58   -
59   -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60   -
61   -#define CONFIG_BOARD_TYPES 1 /* support board types */
62   -
63   -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
64   -
65   -#undef CONFIG_BOOTARGS
66   -
67   -#define CONFIG_EXTRA_ENV_SETTINGS \
68   - "netdev=eth0\0" \
69   - "nfsargs=setenv bootargs root=/dev/nfs rw " \
70   - "nfsroot=$(serverip):$(rootpath)\0" \
71   - "ramargs=setenv bootargs root=/dev/ram rw\0" \
72   - "addip=setenv bootargs $(bootargs) " \
73   - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
74   - ":$(hostname):$(netdev):off panic=1\0" \
75   - "flash_nfs=run nfsargs addip;" \
76   - "bootm $(kernel_addr)\0" \
77   - "flash_self=run ramargs addip;" \
78   - "bootm $(kernel_addr) $(ramdisk_addr)\0" \
79   - "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
80   - "rootpath=/opt/eldk/ppc_8xx\0" \
81   - "bootfile=/tftpboot/BMS/uImage\0" \
82   - "kernel_addr=40040000\0" \
83   - "ramdisk_addr=40100000\0" \
84   - ""
85   -#define CONFIG_BOOTCOMMAND "run flash_self"
86   -
87   -#define CONFIG_BOARD_EARLY_INIT_R 1
88   -#define CONFIG_MISC_INIT_R 1
89   -
90   -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
91   -#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
92   -
93   -/* enable I2C and select the hardware/software driver */
94   -#undef CONFIG_HARD_I2C /* I2C with hardware support */
95   -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
96   -
97   -#define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */
98   -#define CFG_I2C_SLAVE 0xFE
99   -
100   -/* Software (bit-bang) I2C driver configuration */
101   -#define PB_SCL 0x00000020 /* PB 26 */
102   -#define PB_SDA 0x00000010 /* PB 27 */
103   -
104   -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
105   -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
106   -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
107   -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
108   -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
109   - else immr->im_cpm.cp_pbdat &= ~PB_SDA
110   -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
111   - else immr->im_cpm.cp_pbdat &= ~PB_SCL
112   -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
113   -
114   -#undef CONFIG_WATCHDOG /* watchdog disabled */
115   -
116   -#define CONFIG_STATUS_LED 1 /* Status LED enabled */
117   -
118   -#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
119   -
120   -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
121   -
122   -#define CONFIG_MAC_PARTITION
123   -#define CONFIG_DOS_PARTITION
124   -
125   -#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
126   -#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
127   -
128   -#ifdef CONFIG_SPLASH_SCREEN
129   -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
130   - CFG_CMD_ASKENV | \
131   - CFG_CMD_BMP | \
132   - CFG_CMD_DATE | \
133   - CFG_CMD_DHCP | \
134   - CFG_CMD_I2C | \
135   - CFG_CMD_IDE )
136   -#else
137   -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
138   - CFG_CMD_ASKENV | \
139   - CFG_CMD_DATE | \
140   - CFG_CMD_DHCP | \
141   - CFG_CMD_I2C | \
142   - CFG_CMD_IDE )
143   -#endif
144   -
145   -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
146   -#include <cmd_confdefs.h>
147   -
148   -/*
149   - * Miscellaneous configurable options
150   - */
151   -#define CFG_LONGHELP /* undef to save memory */
152   -#define CFG_PROMPT "=> " /* Monitor Command Prompt */
153   -
154   -#if 0
155   -#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
156   -#endif
157   -#ifdef CFG_HUSH_PARSER
158   -#define CFG_PROMPT_HUSH_PS2 "> "
159   -#endif
160   -
161   -#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
162   -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
163   -#else
164   -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
165   -#endif
166   -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
167   -#define CFG_MAXARGS 16 /* max number of command args */
168   -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
169   -
170   -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
171   -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
172   -
173   -#define CFG_LOAD_ADDR 0x100000 /* default load address */
174   -
175   -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
176   -
177   -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
178   -
179   -/*
180   - * Low Level Configuration Settings
181   - * (address mappings, register initial values, etc.)
182   - * You should know what you are doing if you make changes here.
183   - */
184   -/*-----------------------------------------------------------------------
185   - * Internal Memory Mapped Register
186   - */
187   -#define CFG_IMMR 0xFFF00000
188   -
189   -/*-----------------------------------------------------------------------
190   - * Definitions for initial stack pointer and data area (in DPRAM)
191   - */
192   -#define CFG_INIT_RAM_ADDR CFG_IMMR
193   -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
194   -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
195   -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
196   -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
197   -
198   -/*-----------------------------------------------------------------------
199   - * Start addresses for the final memory configuration
200   - * (Set up by the startup code)
201   - * Please note that CFG_SDRAM_BASE _must_ start at 0
202   - */
203   -#define CFG_SDRAM_BASE 0x00000000
204   -#define CFG_FLASH_BASE 0x40000000
205   -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
206   -#define CFG_MONITOR_BASE CFG_FLASH_BASE
207   -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
208   -
209   -/*
210   - * For booting Linux, the board info and command line data
211   - * have to be in the first 8 MB of memory, since this is
212   - * the maximum mapped by the Linux kernel during initialization.
213   - */
214   -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
215   -
216   -/*-----------------------------------------------------------------------
217   - * FLASH organization
218   - */
219   -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
220   -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
221   -
222   -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
223   -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
224   -
225   -#define CFG_ENV_IS_IN_FLASH 1
226   -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
227   -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
228   -
229   -/* Address and size of Redundant Environment Sector */
230   -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
231   -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
232   -
233   -/*-----------------------------------------------------------------------
234   - * Hardware Information Block
235   - */
236   -#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
237   -#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
238   -#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
239   -
240   -/*-----------------------------------------------------------------------
241   - * Cache Configuration
242   - */
243   -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
244   -#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
245   -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
246   -#endif
247   -
248   -/*-----------------------------------------------------------------------
249   - * SYPCR - System Protection Control 11-9
250   - * SYPCR can only be written once after reset!
251   - *-----------------------------------------------------------------------
252   - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
253   - */
254   -#if defined(CONFIG_WATCHDOG)
255   -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
256   - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
257   -#else
258   -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
259   -#endif
260   -
261   -/*-----------------------------------------------------------------------
262   - * SIUMCR - SIU Module Configuration 11-6
263   - *-----------------------------------------------------------------------
264   - * PCMCIA config., multi-function pin tri-state
265   - */
266   -#ifndef CONFIG_CAN_DRIVER
267   -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
268   -#else /* we must activate GPL5 in the SIUMCR for CAN */
269   -#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
270   -#endif /* CONFIG_CAN_DRIVER */
271   -
272   -/*-----------------------------------------------------------------------
273   - * TBSCR - Time Base Status and Control 11-26
274   - *-----------------------------------------------------------------------
275   - * Clear Reference Interrupt Status, Timebase freezing enabled
276   - */
277   -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
278   -
279   -/*-----------------------------------------------------------------------
280   - * RTCSC - Real-Time Clock Status and Control Register 11-27
281   - *-----------------------------------------------------------------------
282   - */
283   -#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
284   -
285   -/*-----------------------------------------------------------------------
286   - * PISCR - Periodic Interrupt Status and Control 11-31
287   - *-----------------------------------------------------------------------
288   - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
289   - */
290   -#define CFG_PISCR (PISCR_PS | PISCR_PITF)
291   -
292   -/*-----------------------------------------------------------------------
293   - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
294   - *-----------------------------------------------------------------------
295   - * Reset PLL lock status sticky bit, timer expired status bit and timer
296   - * interrupt status bit
297   - *
298   - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
299   - */
300   -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
301   -#define CFG_PLPRCR \
302   - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
303   -#else /* up to 66 MHz we use a 1:1 clock */
304   -#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
305   -#endif /* CONFIG_80MHz */
306   -
307   -/*-----------------------------------------------------------------------
308   - * SCCR - System Clock and reset Control Register 15-27
309   - *-----------------------------------------------------------------------
310   - * Set clock output, timebase and RTC source and divider,
311   - * power management and some other internal clocks
312   - */
313   -#define SCCR_MASK SCCR_EBDF11
314   -#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
315   -#define CFG_SCCR (/* SCCR_TBS | */ \
316   - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
317   - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
318   - SCCR_DFALCD00)
319   -#else /* up to 66 MHz we use a 1:1 clock */
320   -#define CFG_SCCR (SCCR_TBS | \
321   - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
322   - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
323   - SCCR_DFALCD00)
324   -#endif /* CONFIG_80MHz */
325   -
326   -/*-----------------------------------------------------------------------
327   - * PCMCIA stuff
328   - *-----------------------------------------------------------------------
329   - *
330   - */
331   -#ifndef CONFIG_BMS2003
332   -#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
333   -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
334   -#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
335   -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
336   -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
337   -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
338   -#define CFG_PCMCIA_IO_ADDR (0xEC000000)
339   -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
340   -#else /* CONFIG_BMS2003 */
341   -#define CFG_PCMCIA_MEM_ADDR (0xE0100000)
342   -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
343   -#define CFG_PCMCIA_DMA_ADDR (0xE4100000)
344   -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
345   -#define CFG_PCMCIA_ATTRB_ADDR (0xE8100000)
346   -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
347   -#define CFG_PCMCIA_IO_ADDR (0xEC100000)
348   -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
349   -#define PCMCIA_MEM_WIN_NO 5
350   -#define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */
351   -#endif
352   -
353   -/*-----------------------------------------------------------------------
354   - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
355   - *-----------------------------------------------------------------------
356   - */
357   -
358   -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
359   -
360   -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
361   -#undef CONFIG_IDE_RESET /* reset for ide not supported */
362   -#ifndef CONFIG_STATUS_LED /* Status and IDE LED's are mutually exclusive */
363   -#define CONFIG_IDE_LED 1 /* LED for ide supported */
364   -#endif
365   -
366   -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
367   -#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
368   -
369   -#define CFG_ATA_IDE0_OFFSET 0x0000
370   -
371   -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
372   -
373   -/* Offset for data I/O */
374   -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
375   -
376   -/* Offset for normal register accesses */
377   -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
378   -
379   -/* Offset for alternate registers */
380   -#define CFG_ATA_ALT_OFFSET 0x0100
381   -
382   -/*-----------------------------------------------------------------------
383   - *
384   - *-----------------------------------------------------------------------
385   - *
386   - */
387   -#define CFG_DER 0
388   -
389   -/*
390   - * Init Memory Controller:
391   - *
392   - * BR0/1 and OR0/1 (FLASH)
393   - */
394   -
395   -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
396   -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
397   -
398   -/* used to re-map FLASH both when starting from SRAM or FLASH:
399   - * restrict access enough to keep SRAM working (if any)
400   - * but not too much to meddle with FLASH accesses
401   - */
402   -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
403   -#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
404   -
405   -/*
406   - * FLASH timing:
407   - */
408   -#if defined(CONFIG_80MHz)
409   -/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
410   -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
411   - OR_SCY_3_CLK | OR_EHTR | OR_BI)
412   -#elif defined(CONFIG_66MHz)
413   -/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
414   -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
415   - OR_SCY_3_CLK | OR_EHTR | OR_BI)
416   -#else /* 50 MHz */
417   -/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
418   -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
419   - OR_SCY_2_CLK | OR_EHTR | OR_BI)
420   -#endif /*CONFIG_??MHz */
421   -
422   -#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
423   -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
424   -#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
425   -
426   -#define CFG_OR1_REMAP CFG_OR0_REMAP
427   -#define CFG_OR1_PRELIM CFG_OR0_PRELIM
428   -#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
429   -
430   -/*
431   - * BR2/3 and OR2/3 (SDRAM)
432   - *
433   - */
434   -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
435   -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
436   -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
437   -
438   -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
439   -#define CFG_OR_TIMING_SDRAM 0x00000A00
440   -
441   -#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
442   -#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
443   -
444   -#ifndef CONFIG_CAN_DRIVER
445   -#define CFG_OR3_PRELIM CFG_OR2_PRELIM
446   -#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
447   -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
448   -#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
449   -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
450   -#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
451   -#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
452   - BR_PS_8 | BR_MS_UPMB | BR_V )
453   -#endif /* CONFIG_CAN_DRIVER */
454   -
455   -/*
456   - * Memory Periodic Timer Prescaler
457   - *
458   - * The Divider for PTA (refresh timer) configuration is based on an
459   - * example SDRAM configuration (64 MBit, one bank). The adjustment to
460   - * the number of chip selects (NCS) and the actually needed refresh
461   - * rate is done by setting MPTPR.
462   - *
463   - * PTA is calculated from
464   - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
465   - *
466   - * gclk CPU clock (not bus clock!)
467   - * Trefresh Refresh cycle * 4 (four word bursts used)
468   - *
469   - * 4096 Rows from SDRAM example configuration
470   - * 1000 factor s -> ms
471   - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
472   - * 4 Number of refresh cycles per period
473   - * 64 Refresh cycle in ms per number of rows
474   - * --------------------------------------------
475   - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
476   - *
477   - * 50 MHz => 50.000.000 / Divider = 98
478   - * 66 Mhz => 66.000.000 / Divider = 129
479   - * 80 Mhz => 80.000.000 / Divider = 156
480   - */
481   -#if defined(CONFIG_80MHz)
482   -#define CFG_MAMR_PTA 156
483   -#elif defined(CONFIG_66MHz)
484   -#define CFG_MAMR_PTA 129
485   -#else /* 50 MHz */
486   -#define CFG_MAMR_PTA 98
487   -#endif /*CONFIG_??MHz */
488   -
489   -/*
490   - * For 16 MBit, refresh rates could be 31.3 us
491   - * (= 64 ms / 2K = 125 / quad bursts).
492   - * For a simpler initialization, 15.6 us is used instead.
493   - *
494   - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
495   - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
496   - */
497   -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
498   -#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
499   -
500   -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
501   -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
502   -#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
503   -
504   -/*
505   - * MAMR settings for SDRAM
506   - */
507   -
508   -/* 8 column SDRAM */
509   -#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
510   - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
511   - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
512   -/* 9 column SDRAM */
513   -#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
514   - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
515   - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
516   -
517   -
518   -/*
519   - * Internal Definitions
520   - *
521   - * Boot Flags
522   - */
523   -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
524   -#define BOOTFLAG_WARM 0x02 /* Software reboot */
525   -
526   -#endif /* __CONFIG_H */
... ... @@ -38,13 +38,19 @@
38 38  
39 39 #endif /* CONFIG_IDE_LED */
40 40  
  41 +#if CFG_64BIT_LBA
  42 +typedef uint64_t lbaint_t;
  43 +#else
  44 +typedef ulong lbaint_t;
  45 +#endif
  46 +
41 47 /*
42 48 * Function Prototypes
43 49 */
44 50  
45 51 void ide_init (void);
46   -ulong ide_read (int device, ulong blknr, ulong blkcnt, ulong *buffer);
47   -ulong ide_write (int device, ulong blknr, ulong blkcnt, ulong *buffer);
  52 +ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer);
  53 +ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer);
48 54  
49 55 #endif /* _IDE_H */
include/status_led.h
Diff comments   View file @ c40b295
... ... @@ -43,7 +43,7 @@
43 43 void status_led_set (int led, int state);
44 44  
45 45 /***** TQM8xxL ********************************************************/
46   -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_BMS2003)
  46 +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_HMI10)
47 47 # define STATUS_LED_PAR im_cpm.cp_pbpar
48 48 # define STATUS_LED_DIR im_cpm.cp_pbdir
49 49 # define STATUS_LED_ODR im_cpm.cp_pbodr
... ... @@ -318,8 +318,8 @@
318 318  
319 319 # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
320 320  
321   -/***** BMS2003 ********************************************************/
322   -#elif defined(CONFIG_BMS2003)
  321 +/***** HMI10 **********************************************************/
  322 +#elif defined(CONFIG_HMI10)
323 323 # define STATUS_LED_PAR im_ioport.iop_papar
324 324 # define STATUS_LED_DIR im_ioport.iop_padir
325 325 # define STATUS_LED_ODR im_ioport.iop_paodr
lib_generic/vsprintf.c
Diff comments   View file @ c40b295
... ... @@ -55,6 +55,36 @@
55 55 return simple_strtoul(cp,endp,base);
56 56 }
57 57  
  58 +#if CFG_64BIT_STRTOUL
  59 +unsigned long long simple_strtoull (const char *cp, char **endp, unsigned int base)
  60 +{
  61 + unsigned long long result = 0, value;
  62 +
  63 + if (*cp == '0') {
  64 + cp++;
  65 + if ((*cp == 'x') && isxdigit (cp[1])) {
  66 + base = 16;
  67 + cp++;
  68 + }
  69 + if (!base) {
  70 + base = 8;
  71 + }
  72 + }
  73 + if (!base) {
  74 + base = 10;
  75 + }
  76 + while (isxdigit (*cp) && (value = isdigit (*cp)
  77 + ? *cp - '0'
  78 + : (islower (*cp) ? toupper (*cp) : *cp) - 'A' + 10) < base) {
  79 + result = result * base + value;
  80 + cp++;
  81 + }
  82 + if (endp)
  83 + *endp = (char *) cp;
  84 + return result;
  85 +}
  86 +#endif /* CFG_64BIT_STRTOUL */
  87 +
58 88 /* we use this so that we can do without the ctype library */
59 89 #define is_digit(c) ((c) >= '0' && (c) <= '9')
60 90  
61 91  
... ... @@ -76,13 +106,17 @@
76 106 #define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */
77 107  
78 108 #define do_div(n,base) ({ \
79   -int __res; \
80   -__res = ((unsigned long) n) % (unsigned) base; \
81   -n = ((unsigned long) n) / (unsigned) base; \
82   -__res; })
  109 + int __res; \
  110 + __res = ((unsigned long) n) % (unsigned) base; \
  111 + n = ((unsigned long) n) / (unsigned) base; \
  112 + __res; \
  113 +})
83 114  
84   -static char * number(char * str, long num, int base, int size, int precision
85   - ,int type)
  115 +#if CFG_64BIT_VSPRINTF
  116 +static char * number(char * str, long long num, int base, int size, int precision ,int type)
  117 +#else
  118 +static char * number(char * str, long num, int base, int size, int precision ,int type)
  119 +#endif
86 120 {
87 121 char c,sign,tmp[66];
88 122 const char *digits="0123456789abcdefghijklmnopqrstuvwxyz";
89 123  
... ... @@ -154,7 +188,11 @@
154 188 int vsprintf(char *buf, const char *fmt, va_list args)
155 189 {
156 190 int len;
  191 +#if CFG_64BIT_VSPRINTF
  192 + unsigned long long num;
  193 +#else
157 194 unsigned long num;
  195 +#endif
158 196 int i, base;
159 197 char * str;
160 198 const char *s;
... ... @@ -164,7 +202,7 @@
164 202 int field_width; /* width of output field */
165 203 int precision; /* min. # of digits for integers; max
166 204 number of chars for from string */
167   - int qualifier; /* 'h', 'l', or 'L' for integer fields */
  205 + int qualifier; /* 'h', 'l', or 'q' for integer fields */
168 206  
169 207 for (str=buf ; *fmt ; ++fmt) {
170 208 if (*fmt != '%') {
... ... @@ -215,7 +253,7 @@
215 253  
216 254 /* get the conversion qualifier */
217 255 qualifier = -1;
218   - if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') {
  256 + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'q') {
219 257 qualifier = *fmt;
220 258 ++fmt;
221 259 }
... ... @@ -299,6 +337,11 @@
299 337 --fmt;
300 338 continue;
301 339 }
  340 +#if CFG_64BIT_VSPRINTF
  341 + if (qualifier == 'q') /* "quad" for 64 bit variables */
  342 + num = va_arg(args, unsigned long long);
  343 + else
  344 +#endif
302 345 if (qualifier == 'l')
303 346 num = va_arg(args, unsigned long);
304 347 else if (qualifier == 'h') {
... ... @@ -24,6 +24,7 @@
24 24 #include <common.h>
25 25 #include <command.h>
26 26 #include <net.h>
  27 +#include "nfs.h"
27 28 #include "bootp.h"
28 29 #include "rarp.h"
29 30 #include "tftp.h"
30 31  
... ... @@ -46,9 +47,18 @@
46 47 static void
47 48 RarpHandler(uchar * dummi0, unsigned dummi1, unsigned dummi2, unsigned dummi3)
48 49 {
  50 + char *s;
49 51 #ifdef DEBUG
50 52 printf("Got good RARP\n");
51 53 #endif
  54 + if (((s = getenv("autoload")) != NULL) && (*s == 'n')) {
  55 + NetState = NETLOOP_SUCCESS;
  56 + return;
  57 + }
  58 + else if ((s != NULL) && !strcmp(s, "NFS")) {
  59 + NfsStart();
  60 + return;
  61 + }
52 62 TftpStart ();
53 63 }
54 64