MLK-14375-1 mx6ullevk: Update board codes to align with v2016.03

Update mx6ull evk to add features from v2016.03. 1. Add support for NAND flash. 2. Add support for QSPI DM driver. 3. Add USB DM driver support. 4. Add two FEC support by using DM FEC driver 5. Update environments for various boot devices support: SD/NAND/eMMC/QSPI 6. Add MFGtool environments. 7. Add board codes for 9x9 EVK board For the DTS file, some changes are needed for using QSPI DM driver 1. Add spi0 alias for qspi node. Which is used for bus number 0. 2. Modify the n25q256a@0 compatible property to "spi-flash". 3. Modify spi4 (gpio_spi) node to spi5 Signed-off-by: Ye Li <ye.li@nxp.com>

MLK-14375-1 mx6ullevk: Update board codes to align with v2016.03
Update mx6ull evk to add features from v2016.03. 1. Add support for NAND flash. 2. Add support for QSPI DM driver. 3. Add USB DM driver support. 4. Add two FEC support by using DM FEC driver 5. Update environments for various boot devices support: SD/NAND/eMMC/QSPI 6. Add MFGtool environments. 7. Add board codes for 9x9 EVK board For the DTS file, some changes are needed for using QSPI DM driver 1. Add spi0 alias for qspi node. Which is used for bus number 0. 2. Modify the n25q256a@0 compatible property to "spi-flash". 3. Modify spi4 (gpio_spi) node to spi5 Signed-off-by: Ye Li <ye.li@nxp.com>
Ye Li
1 parent 7901123eb0
Showing 8 changed files with 683 additions and 32 deletions Side-by-side Diff
arch/arm/cpu/armv7/mx6/Kconfig
arch/arm/dts/imx6ull-14x14-evk.dts
arch/arm/dts/imx6ull.dtsi
board/freescale/mx6ullevk/Kconfig
board/freescale/mx6ullevk/mx6ullevk.c
configs/mx6ull_14x14_evk_defconfig
configs/mx6ull_14x14_evk_plugin_defconfig
include/configs/mx6ullevk.h
@@ -278,6 +278,13 @@
 	select DM
 	select DM_THERMAL
  
+config TARGET_MX6ULL_9X9_EVK
+	bool "Support mx6ull_9x9_evk"
+	select BOARD_LATE_INIT
+	select MX6ULL
+	select DM
+	select DM_THERMAL
+
 config TARGET_NITROGEN6X
 	bool "nitrogen6x"
  
@@ -23,6 +23,19 @@
 		reg = <0x80000000 0x20000000>;
 	};
  
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x14000000>;
+			linux,cma-default;
+		};
+	};
+
 	backlight {
 		compatible = "pwm-backlight";
 		pwms = <&pwm1 0 5000000>;
@@ -31,6 +44,11 @@
 		status = "okay";
 	};
  
+	pxp_v4l2 {
+		compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
+		status = "okay";
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
  
@@ -67,10 +85,48 @@
 		};
 	};
  
-	spi4 {
+	sound {
+		compatible = "fsl,imx6ul-evk-wm8960",
+			   "fsl,imx-audio-wm8960";
+		model = "wm8960-audio";
+		cpu-dai = <&sai2>;
+		audio-codec = <&codec>;
+		asrc-controller = <&asrc>;
+		codec-master;
+		gpr = <&gpr 4 0x100000 0x100000>;
+		/*
+                 * hp-det = <hp-det-pin hp-det-polarity>;
+		 * hp-det-pin: JD1 JD2  or JD3
+		 * hp-det-polarity = 0: hp detect high for headphone
+		 * hp-det-polarity = 1: hp detect high for speaker
+		 */
+		hp-det = <3 0>;
+		hp-det-gpios = <&gpio5 4 0>;
+		mic-det-gpios = <&gpio5 4 0>;
+		audio-routing =
+			"Headphone Jack", "HP_L",
+			"Headphone Jack", "HP_R",
+			"Ext Spk", "SPK_LP",
+			"Ext Spk", "SPK_LN",
+			"Ext Spk", "SPK_RP",
+			"Ext Spk", "SPK_RN",
+			"LINPUT2", "Mic Jack",
+			"LINPUT3", "Mic Jack",
+			"RINPUT1", "Main MIC",
+			"RINPUT2", "Main MIC",
+			"Mic Jack", "MICB",
+			"Main MIC", "MICB",
+			"CPU-Playback", "ASRC-Playback",
+			"Playback", "CPU-Playback",
+			"ASRC-Capture", "CPU-Capture",
+			"CPU-Capture", "Capture";
+	};
+
+	spi5 {
 		compatible = "spi-gpio";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_spi4>;
+		pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
 		status = "okay";
 		gpio-sck = <&gpio5 11 0>;
 		gpio-mosi = <&gpio5 10 0>;
@@ -82,7 +138,6 @@
 		gpio_spi: gpio_spi@0 {
 			compatible = "fairchild,74hc595";
 			gpio-controller;
-			oe-gpios = <&gpio5 8 0>;
 			#gpio-cells = <2>;
 			reg = <0>;
 			registers-number = <1>;
@@ -103,6 +158,16 @@
 	assigned-clock-rates = <786432000>;
 };
  
+&csi {
+	status = "okay";
+
+	port {
+		csi1_ep: endpoint {
+			remote-endpoint = <&ov5640_ep>;
+		};
+	};
+};
+
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet1>;
@@ -134,6 +199,20 @@
 	};
 };
  
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_can_3v3>;
+	status = "okay";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can_3v3>;
+	status = "okay";
+};
+
 &gpc {
 	fsl,cpu_pupscr_sw2iso = <0x1>;
 	fsl,cpu_pupscr_sw = <0x0>;
@@ -168,6 +247,34 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_i2c2>;
 	status = "okay";
+
+	codec: wm8960@1a {
+		compatible = "wlf,wm8960";
+		reg = <0x1a>;
+		clocks = <&clks IMX6UL_CLK_SAI2>;
+		clock-names = "mclk";
+		wlf,shared-lrclk;
+	};
+
+	ov5640: ov5640@3c {
+		compatible = "ovti,ov5640";
+		reg = <0x3c>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_csi1>;
+		clocks = <&clks IMX6UL_CLK_CSI>;
+		clock-names = "csi_mclk";
+		pwn-gpios = <&gpio_spi 6 1>;
+		rst-gpios = <&gpio_spi 5 0>;
+		csi_id = <0>;
+		mclk = <24000000>;
+		mclk_source = <0>;
+		status = "okay";
+		port {
+			ov5640_ep: endpoint {
+				remote-endpoint = <&csi1_ep>;
+			};
+		};
+	};
 };
  
 &iomuxc {
@@ -310,6 +417,25 @@
 			>;
 		};
  
+		pinctrl_sai2: sai2grp {
+			fsl,pins = <
+				MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
+				MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
+				MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x11088
+				MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x11088
+				MX6UL_PAD_JTAG_TMS__SAI2_MCLK		0x17088
+			>;
+		};
+
+		pinctrl_tsc: tscgrp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
+				MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
+				MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
+				MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0xb0
+			>;
+		};
+
 		pinctrl_uart1: uart1grp {
 			fsl,pins = <
 				MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
@@ -346,6 +472,28 @@
 			>;
 		};
  
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+			>;
+		};
+
 		pinctrl_usdhc2: usdhc2grp {
 			fsl,pins = <
 				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
@@ -357,6 +505,51 @@
 			>;
 		};
  
+		pinctrl_usdhc2_8bit: usdhc2grp_8bit {
+			fsl,pins = <
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+				MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+				MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+				MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+			>;
+		};
+
+		pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
+			fsl,pins = <
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+				MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
+				MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
+				MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
+				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
+			>;
+		};
+
+		pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
+			fsl,pins = <
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+				MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+				MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+				MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+			>;
+		};
+
 		pinctrl_wdog: wdoggrp {
 			fsl,pins = <
 				MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
@@ -380,7 +573,7 @@
                                 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x79
                         >;
                 };
-
+		
 		pinctrl_lcdif_reset: lcdifresetgrp {
                         fsl,pins = <
                                 /* used for lcd reset */
@@ -446,6 +639,10 @@
 	status = "okay";
 };
  
+&pxp {
+	status = "okay";
+};
+
 &qspi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_qspi>;
  
@@ -455,13 +652,35 @@
 	flash0: n25q256a@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "micron,n25q256a";
+		compatible = "spi-flash";
 		spi-max-frequency = <29000000>;
 		spi-nor,ddr-quad-read-dummy = <6>;
 		reg = <0>;
 	};
 };
  
+&sai2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2
+		     &pinctrl_sai2_hp_det_b>;
+
+	assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
+			  <&clks IMX6UL_CLK_SAI2>;
+	assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <0>, <12288000>;
+
+	status = "okay";
+};
+
+&tsc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_tsc>;
+	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+	measure-delay-time = <0xffff>;
+	pre-charge-time = <0xfff>;
+	status = "okay";
+};
+
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1>;
  
@@ -501,8 +720,10 @@
 };
  
 &usdhc1 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 	keep-power-in-suspend;
 	enable-sdio-wakeup;
  
@@ -513,10 +734,7 @@
 &usdhc2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc2>;
-	no-1-8-v;
 	non-removable;
-	keep-power-in-suspend;
-	enable-sdio-wakeup;
 	status = "okay";
 };
  
@@ -38,10 +38,11 @@
 		serial5 = &uart6;
 		serial6 = &uart7;
 		serial7 = &uart8;
-		spi0 = &ecspi1;
-		spi1 = &ecspi2;
-		spi2 = &ecspi3;
-		spi3 = &ecspi4;
+		spi0 = &qspi;
+		spi1 = &ecspi1;
+		spi2 = &ecspi2;
+		spi3 = &ecspi3;
+		spi4 = &ecspi4;
 		usbphy0 = &usbphy1;
 		usbphy1 = &usbphy2;
 	};
-if TARGET_MX6ULL_14X14_EVK
+if TARGET_MX6ULL_14X14_EVK || TARGET_MX6ULL_9X9_EVK
  
 config SYS_BOARD
 	default "mx6ullevk"
@@ -13,13 +13,19 @@
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
 #include <asm/io.h>
 #include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
 #include <fsl_esdhc.h>
 #include <linux/sizes.h>
 #include <mmc.h>
 #include <mxsfb.h>
 #include <asm/imx-common/video.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../common/pfuze.h"
  
 DECLARE_GLOBAL_DATA_PTR;
  
  
@@ -27,9 +33,118 @@
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
 	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+#ifdef CONFIG_SYS_I2C
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC and EEPROM */
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode =  MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC,
+		.gp = IMX_GPIO_NR(1, 28),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC,
+		.gp = IMX_GPIO_NR(1, 29),
+	},
+};
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC       0
+int power_init_board(void)
+{
+	if (is_mx6ull_9x9_evk()) {
+		struct pmic *pfuze;
+		int ret;
+		unsigned int reg, rev_id;
+
+		ret = power_pfuze3000_init(I2C_PMIC);
+		if (ret)
+			return ret;
+
+		pfuze = pmic_get("PFUZE3000");
+		ret = pmic_probe(pfuze);
+		if (ret)
+			return ret;
+
+		pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
+		pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
+		printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
+		       reg, rev_id);
+
+		/* disable Low Power Mode during standby mode */
+		pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
+		reg |= 0x1;
+		pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
+
+		/* SW1B step ramp up time from 2us to 4us/25mV */
+		reg = 0x40;
+		pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
+
+		/* SW1B mode to APS/PFM */
+		reg = 0xc;
+		pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
+
+		/* SW1B standby voltage set to 0.975V */
+		reg = 0xb;
+		pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	unsigned int value;
+	u32 vddarm;
+
+	struct pmic *p = pmic_get("PFUZE3000");
+
+	if (!p) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+		/* decrease VDDARM to 1.275V */
+		pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value);
+		value &= ~0x1f;
+		value |= PFUZE3000_SW1AB_SETP(1275);
+		pmic_reg_write(p, PFUZE3000_SW1BVOLT, value);
+
+		set_anatop_bypass(1);
+		vddarm = PFUZE3000_SW1AB_SETP(1175);
+
+		pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value);
+		value &= ~0x1f;
+		value |= vddarm;
+		pmic_reg_write(p, PFUZE3000_SW1BVOLT, value);
+
+		finish_anatop_bypass();
+
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
+#endif
+#endif
+
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -47,6 +162,115 @@
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
  
+#ifdef CONFIG_FSL_QSPI
+
+#ifndef CONFIG_DM_SPI
+#define QSPI_PAD_CTRL1	\
+	(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+	 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+	MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+#endif
+
+static int board_qspi_init(void)
+{
+#ifndef CONFIG_DM_SPI
+	/* Set the iomux */
+	imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+					 ARRAY_SIZE(quadspi_pads));
+#endif
+	/* Set the clock */
+	enable_qspi_clk(0);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const nand_pads[] = {
+	MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+
+	setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
+			  (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(int fec_id)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	if (fec_id == 0) {
+		/*
+		 * Use 50M anatop loopback REF_CLK1 for ENET1,
+		 * clear gpr1[13], set gpr1[17].
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+	} else {
+		/*
+		 * Use 50M anatop loopback REF_CLK2 for ENET2,
+		 * clear gpr1[14], set gpr1[18].
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+	}
+
+	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
 int board_mmc_get_env_dev(int devno)
 {
 	return devno;
@@ -147,6 +371,22 @@
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  
+#ifdef CONFIG_SYS_I2C
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+#ifdef	CONFIG_FEC_MXC
+	setup_fec(CONFIG_FEC_ENET_DEV);
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
 	return 0;
 }
  
  
  
@@ -168,15 +408,28 @@
  
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	setenv("board_name", "EVK");
-	setenv("board_rev", "14X14");
+
+	if (is_mx6ull_9x9_evk())
+		setenv("board_rev", "9X9");
+	else
+		setenv("board_rev", "14X14");
 #endif
  
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
 	return 0;
 }
  
 int checkboard(void)
 {
-	puts("Board: MX6ULL 14x14 EVK\n");
+	if (is_mx6ull_9x9_evk())
+		puts("Board: MX6ULL 9x9 EVK\n");
+	else
+		puts("Board: MX6ULL 14x14 EVK\n");
  
 	return 0;
 }
@@ -11,11 +11,14 @@
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
  
@@ -27,9 +30,21 @@
 CONFIG_DM_74X164=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_REGULATOR=y
-CONFIG_DM_SPI=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_FSL_QSPI=y
+CONFIG_DM_ETH=y
@@ -12,11 +12,14 @@
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
  
@@ -28,9 +31,21 @@
 CONFIG_DM_74X164=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_DM_MMC_OPS is not set
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_REGULATOR=y
-CONFIG_DM_SPI=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_FSL_QSPI=y
+CONFIG_DM_ETH=y
@@ -14,21 +14,24 @@
 #include "mx6_common.h"
 #include <asm/imx-common/gpio.h>
  
-#ifdef CONFIG_SECURE_BOOT
-#ifndef CONFIG_CSF_SIZE
-#define CONFIG_CSF_SIZE 0x4000
-#endif
-#endif
  
-#define PHYS_SDRAM_SIZE	SZ_512M
+#define is_mx6ull_9x9_evk()	CONFIG_IS_ENABLED(TARGET_MX6ULL_9X9_EVK)
  
+#ifdef CONFIG_TARGET_MX6ULL_9X9_EVK
+#define PHYS_SDRAM_SIZE		SZ_256M
+#define BOOTARGS_CMA_SIZE   "cma=96M "
+#else
+#define PHYS_SDRAM_SIZE		SZ_512M
+#define BOOTARGS_CMA_SIZE   ""
+/* DCDC used on 14x14 EVK, no PMIC */
+#undef CONFIG_LDO_BYPASS_CHECK
+#endif
+
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
  
-#define CONFIG_MXC_GPIO
-
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE		UART1_BASE
  
@@ -37,7 +40,7 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
  
 /* NAND pin conflicts with usdhc2 */
-#ifdef CONFIG_SYS_USE_NAND
+#ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_FSL_USDHC_NUM	1
 #else
 #define CONFIG_SYS_FSL_USDHC_NUM	2
  
  
  
  
  
@@ -52,24 +55,74 @@
 #define CONFIG_SYS_I2C_SPEED		100000
 #endif
  
+/* Only use DM I2C driver for 14x14 EVK. Because the PFUZE3000 driver does not support DM */
+#ifndef CONFIG_DM_I2C
+#define CONFIG_SYS_I2C
+
+/* PMIC only for 9X9 EVK */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE3000
+#define CONFIG_POWER_PFUZE3000_I2C_ADDR  0x08
+#endif
+
 #define CONFIG_SYS_MMC_IMG_LOAD_PART	1
  
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) "
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+	    BOOTARGS_CMA_SIZE \
+		"rdinit=/linuxrc " \
+		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+		"g_mass_storage.file=/fat g_mass_storage.ro=1 " \
+		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+		"g_mass_storage.iSerialNumber=\"\" "\
+		MFG_NAND_PARTITION \
+		"clk_ignore_unused "\
+		"\0" \
+	"initrd_addr=0x83800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+
+#if defined(CONFIG_NAND_BOOT)
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"panel=TFT43AB\0" \
+	"fdt_addr=0x83000000\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"console=ttymxc0\0" \
+	"bootargs=console=ttymxc0,115200 ubi.mtd=4 "  \
+		"root=ubi0:rootfs rootfstype=ubifs "		     \
+		BOOTARGS_CMA_SIZE \
+		"mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\
+	"bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
+		"nand read ${fdt_addr} 0x5000000 0x100000;"\
+		"bootz ${loadaddr} - ${fdt_addr}\0"
+
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
 	"console=ttymxc0\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
-	"fdt_file=imx6ull-14x14-evk.dtb\0" \" \
+	"fdt_file=undefined\0" \" \
 	"fdt_addr=0x83000000\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
-	"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \" \
+	"panel=TFT43AB\0" \" \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
 	"mmcautodetect=yes\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		BOOTARGS_CMA_SIZE \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
@@ -93,6 +146,7 @@
 			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
+		BOOTARGS_CMA_SIZE \
 		"root=/dev/nfs " \
 	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
 		"netboot=echo Booting from net ...; " \
  
@@ -116,8 +170,18 @@
 		"else " \
 			"bootz; " \
 		"fi;\0" \
+		"findfdt="\
+			"if test $fdt_file = undefined; then " \
+				"if test $board_name = EVK && test $board_rev = 9X9; then " \
+					"setenv fdt_file imx6ull-9x9-evk.dtb; fi; " \
+				"if test $board_name = EVK && test $board_rev = 14X14; then " \
+					"setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \
+				"if test $fdt_file = undefined; then " \
+					"echo WARNING: Could not determine dtb to use; fi; " \
+			"fi;\0" \
  
 #define CONFIG_BOOTCOMMAND \
+	   "run findfdt;" \
 	   "mmc dev ${mmcdev};" \
 	   "mmc dev ${mmcdev}; if mmc rescan; then " \
 		   "if run loadbootscript; then " \
@@ -129,6 +193,7 @@
 			   "fi; " \
 		   "fi; " \
 	   "else run netboot; fi"
+#endif
  
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_MEMTEST_START	0x80000000
  
@@ -152,15 +217,20 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#elif defined CONFIG_NAND_BOOT
+#define CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#else
+#define CONFIG_ENV_IS_IN_MMC
+#endif
+
 /* environment organization */
 #define CONFIG_SYS_MMC_ENV_DEV		1	/* USDHC2 */
 #define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
  
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_ENV_SIZE			SZ_8K
-#define CONFIG_ENV_OFFSET		(12 * SZ_64K)
-
 #define CONFIG_CMD_BMODE
  
 #define CONFIG_IMX_THERMAL
@@ -168,6 +238,78 @@
 #define CONFIG_IOMUX_LPSR
  
 #define CONFIG_SOFT_SPI
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_FSL_QSPI_AHB
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED	40000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define FSL_QSPI_FLASH_NUM		1
+#define FSL_QSPI_FLASH_SIZE		SZ_32M
+#endif
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#endif
+
+#define CONFIG_ENV_SIZE			SZ_8K
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(13 * SZ_64K)
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET		(864 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET		(60 << 20)
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#endif
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define CONFIG_FEC_ENET_DEV		1
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x2
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME			"FEC0"
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE			ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x1
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"FEC1"
+#endif
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR
+#endif
  
 #ifdef CONFIG_VIDEO
 #define CONFIG_VIDEO_MXS
...	...	@@ -278,6 +278,13 @@
278	278	select DM
279	279	select DM_THERMAL
280	280
	281	+config TARGET_MX6ULL_9X9_EVK
	282	+ bool "Support mx6ull_9x9_evk"
	283	+ select BOARD_LATE_INIT
	284	+ select MX6ULL
	285	+ select DM
	286	+ select DM_THERMAL
	287	+
281	288	config TARGET_NITROGEN6X
282	289	bool "nitrogen6x"
283	290
...	...	@@ -23,6 +23,19 @@
23	23	reg = <0x80000000 0x20000000>;
24	24	};
25	25
	26	+ reserved-memory {
	27	+ #address-cells = <1>;
	28	+ #size-cells = <1>;
	29	+ ranges;
	30	+
	31	+ linux,cma {
	32	+ compatible = "shared-dma-pool";
	33	+ reusable;
	34	+ size = <0x14000000>;
	35	+ linux,cma-default;
	36	+ };
	37	+ };
	38	+
26	39	backlight {
27	40	compatible = "pwm-backlight";
28	41	pwms = <&pwm1 0 5000000>;
...	...	@@ -31,6 +44,11 @@
31	44	status = "okay";
32	45	};
33	46
	47	+ pxp_v4l2 {
	48	+ compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
	49	+ status = "okay";
	50	+ };
	51	+
34	52	regulators {
35	53	compatible = "simple-bus";
36	54	#address-cells = <1>;
37	55
...	...	@@ -67,10 +85,48 @@
67	85	};
68	86	};
69	87
70		- spi4 {
	88	+ sound {
	89	+ compatible = "fsl,imx6ul-evk-wm8960",
	90	+ "fsl,imx-audio-wm8960";
	91	+ model = "wm8960-audio";
	92	+ cpu-dai = <&sai2>;
	93	+ audio-codec = <&codec>;
	94	+ asrc-controller = <&asrc>;
	95	+ codec-master;
	96	+ gpr = <&gpr 4 0x100000 0x100000>;
	97	+ /*
	98	+ * hp-det = <hp-det-pin hp-det-polarity>;
	99	+ * hp-det-pin: JD1 JD2 or JD3
	100	+ * hp-det-polarity = 0: hp detect high for headphone
	101	+ * hp-det-polarity = 1: hp detect high for speaker
	102	+ */
	103	+ hp-det = <3 0>;
	104	+ hp-det-gpios = <&gpio5 4 0>;
	105	+ mic-det-gpios = <&gpio5 4 0>;
	106	+ audio-routing =
	107	+ "Headphone Jack", "HP_L",
	108	+ "Headphone Jack", "HP_R",
	109	+ "Ext Spk", "SPK_LP",
	110	+ "Ext Spk", "SPK_LN",
	111	+ "Ext Spk", "SPK_RP",
	112	+ "Ext Spk", "SPK_RN",
	113	+ "LINPUT2", "Mic Jack",
	114	+ "LINPUT3", "Mic Jack",
	115	+ "RINPUT1", "Main MIC",
	116	+ "RINPUT2", "Main MIC",
	117	+ "Mic Jack", "MICB",
	118	+ "Main MIC", "MICB",
	119	+ "CPU-Playback", "ASRC-Playback",
	120	+ "Playback", "CPU-Playback",
	121	+ "ASRC-Capture", "CPU-Capture",
	122	+ "CPU-Capture", "Capture";
	123	+ };
	124	+
	125	+ spi5 {
71	126	compatible = "spi-gpio";
72	127	pinctrl-names = "default";
73	128	pinctrl-0 = <&pinctrl_spi4>;
	129	+ pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
74	130	status = "okay";
75	131	gpio-sck = <&gpio5 11 0>;
76	132	gpio-mosi = <&gpio5 10 0>;
...	...	@@ -82,7 +138,6 @@
82	138	gpio_spi: gpio_spi@0 {
83	139	compatible = "fairchild,74hc595";
84	140	gpio-controller;
85		- oe-gpios = <&gpio5 8 0>;
86	141	#gpio-cells = <2>;
87	142	reg = <0>;
88	143	registers-number = <1>;
...	...	@@ -103,6 +158,16 @@
103	158	assigned-clock-rates = <786432000>;
104	159	};
105	160
	161	+&csi {
	162	+ status = "okay";
	163	+
	164	+ port {
	165	+ csi1_ep: endpoint {
	166	+ remote-endpoint = <&ov5640_ep>;
	167	+ };
	168	+ };
	169	+};
	170	+
106	171	&fec1 {
107	172	pinctrl-names = "default";
108	173	pinctrl-0 = <&pinctrl_enet1>;
...	...	@@ -134,6 +199,20 @@
134	199	};
135	200	};
136	201
	202	+&flexcan1 {
	203	+ pinctrl-names = "default";
	204	+ pinctrl-0 = <&pinctrl_flexcan1>;
	205	+ xceiver-supply = <&reg_can_3v3>;
	206	+ status = "okay";
	207	+};
	208	+
	209	+&flexcan2 {
	210	+ pinctrl-names = "default";
	211	+ pinctrl-0 = <&pinctrl_flexcan2>;
	212	+ xceiver-supply = <&reg_can_3v3>;
	213	+ status = "okay";
	214	+};
	215	+
137	216	&gpc {
138	217	fsl,cpu_pupscr_sw2iso = <0x1>;
139	218	fsl,cpu_pupscr_sw = <0x0>;
...	...	@@ -168,6 +247,34 @@
168	247	pinctrl-names = "default";
169	248	pinctrl-0 = <&pinctrl_i2c2>;
170	249	status = "okay";
	250	+
	251	+ codec: wm8960@1a {
	252	+ compatible = "wlf,wm8960";
	253	+ reg = <0x1a>;
	254	+ clocks = <&clks IMX6UL_CLK_SAI2>;
	255	+ clock-names = "mclk";
	256	+ wlf,shared-lrclk;
	257	+ };
	258	+
	259	+ ov5640: ov5640@3c {
	260	+ compatible = "ovti,ov5640";
	261	+ reg = <0x3c>;
	262	+ pinctrl-names = "default";
	263	+ pinctrl-0 = <&pinctrl_csi1>;
	264	+ clocks = <&clks IMX6UL_CLK_CSI>;
	265	+ clock-names = "csi_mclk";
	266	+ pwn-gpios = <&gpio_spi 6 1>;
	267	+ rst-gpios = <&gpio_spi 5 0>;
	268	+ csi_id = <0>;
	269	+ mclk = <24000000>;
	270	+ mclk_source = <0>;
	271	+ status = "okay";
	272	+ port {
	273	+ ov5640_ep: endpoint {
	274	+ remote-endpoint = <&csi1_ep>;
	275	+ };
	276	+ };
	277	+ };
171	278	};
172	279
173	280	&iomuxc {
...	...	@@ -310,6 +417,25 @@
310	417	>;
311	418	};
312	419
	420	+ pinctrl_sai2: sai2grp {
	421	+ fsl,pins = <
	422	+ MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
	423	+ MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
	424	+ MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
	425	+ MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
	426	+ MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
	427	+ >;
	428	+ };
	429	+
	430	+ pinctrl_tsc: tscgrp {
	431	+ fsl,pins = <
	432	+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
	433	+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
	434	+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
	435	+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
	436	+ >;
	437	+ };
	438	+
313	439	pinctrl_uart1: uart1grp {
314	440	fsl,pins = <
315	441	MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
...	...	@@ -346,6 +472,28 @@
346	472	>;
347	473	};
348	474
	475	+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
	476	+ fsl,pins = <
	477	+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
	478	+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
	479	+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
	480	+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
	481	+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
	482	+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
	483	+ >;
	484	+ };
	485	+
	486	+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
	487	+ fsl,pins = <
	488	+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
	489	+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
	490	+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
	491	+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
	492	+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
	493	+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
	494	+ >;
	495	+ };
	496	+
349	497	pinctrl_usdhc2: usdhc2grp {
350	498	fsl,pins = <
351	499	MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
...	...	@@ -357,6 +505,51 @@
357	505	>;
358	506	};
359	507
	508	+ pinctrl_usdhc2_8bit: usdhc2grp_8bit {
	509	+ fsl,pins = <
	510	+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
	511	+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
	512	+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
	513	+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
	514	+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
	515	+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
	516	+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
	517	+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
	518	+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
	519	+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
	520	+ >;
	521	+ };
	522	+
	523	+ pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
	524	+ fsl,pins = <
	525	+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
	526	+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
	527	+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
	528	+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
	529	+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
	530	+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
	531	+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
	532	+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
	533	+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
	534	+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
	535	+ >;
	536	+ };
	537	+
	538	+ pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
	539	+ fsl,pins = <
	540	+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
	541	+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
	542	+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
	543	+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
	544	+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
	545	+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
	546	+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
	547	+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
	548	+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
	549	+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
	550	+ >;
	551	+ };
	552	+
360	553	pinctrl_wdog: wdoggrp {
361	554	fsl,pins = <
362	555	MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
...	...	@@ -380,7 +573,7 @@
380	573	MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
381	574	>;
382	575	};
383		-
	576	+
384	577	pinctrl_lcdif_reset: lcdifresetgrp {
385	578	fsl,pins = <
386	579	/* used for lcd reset */
...	...	@@ -446,6 +639,10 @@
446	639	status = "okay";
447	640	};
448	641
	642	+&pxp {
	643	+ status = "okay";
	644	+};
	645	+
449	646	&qspi {
450	647	pinctrl-names = "default";
451	648	pinctrl-0 = <&pinctrl_qspi>;
452	649
...	...	@@ -455,13 +652,35 @@
455	652	flash0: n25q256a@0 {
456	653	#address-cells = <1>;
457	654	#size-cells = <1>;
458		- compatible = "micron,n25q256a";
	655	+ compatible = "spi-flash";
459	656	spi-max-frequency = <29000000>;
460	657	spi-nor,ddr-quad-read-dummy = <6>;
461	658	reg = <0>;
462	659	};
463	660	};
464	661
	662	+&sai2 {
	663	+ pinctrl-names = "default";
	664	+ pinctrl-0 = <&pinctrl_sai2
	665	+ &pinctrl_sai2_hp_det_b>;
	666	+
	667	+ assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
	668	+ <&clks IMX6UL_CLK_SAI2>;
	669	+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	670	+ assigned-clock-rates = <0>, <12288000>;
	671	+
	672	+ status = "okay";
	673	+};
	674	+
	675	+&tsc {
	676	+ pinctrl-names = "default";
	677	+ pinctrl-0 = <&pinctrl_tsc>;
	678	+ xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
	679	+ measure-delay-time = <0xffff>;
	680	+ pre-charge-time = <0xfff>;
	681	+ status = "okay";
	682	+};
	683	+
465	684	&uart1 {
466	685	pinctrl-names = "default";
467	686	pinctrl-0 = <&pinctrl_uart1>;
468	687
...	...	@@ -501,8 +720,10 @@
501	720	};
502	721
503	722	&usdhc1 {
504		- pinctrl-names = "default";
	723	+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
505	724	pinctrl-0 = <&pinctrl_usdhc1>;
	725	+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	726	+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
506	727	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
507	728	keep-power-in-suspend;
508	729	enable-sdio-wakeup;
509	730
...	...	@@ -513,10 +734,7 @@
513	734	&usdhc2 {
514	735	pinctrl-names = "default";
515	736	pinctrl-0 = <&pinctrl_usdhc2>;
516		- no-1-8-v;
517	737	non-removable;
518		- keep-power-in-suspend;
519		- enable-sdio-wakeup;
520	738	status = "okay";
521	739	};
522	740
...	...	@@ -38,10 +38,11 @@
38	38	serial5 = &uart6;
39	39	serial6 = &uart7;
40	40	serial7 = &uart8;
41		- spi0 = &ecspi1;
42		- spi1 = &ecspi2;
43		- spi2 = &ecspi3;
44		- spi3 = &ecspi4;
	41	+ spi0 = &qspi;
	42	+ spi1 = &ecspi1;
	43	+ spi2 = &ecspi2;
	44	+ spi3 = &ecspi3;
	45	+ spi4 = &ecspi4;
45	46	usbphy0 = &usbphy1;
46	47	usbphy1 = &usbphy2;
47	48	};
1		-if TARGET_MX6ULL_14X14_EVK
	1	+if TARGET_MX6ULL_14X14_EVK \|\| TARGET_MX6ULL_9X9_EVK
2	2
3	3	config SYS_BOARD
4	4	default "mx6ullevk"
...	...	@@ -13,13 +13,19 @@
13	13	#include <asm/gpio.h>
14	14	#include <asm/imx-common/iomux-v3.h>
15	15	#include <asm/imx-common/boot_mode.h>
	16	+#include <asm/imx-common/mxc_i2c.h>
16	17	#include <asm/io.h>
17	18	#include <common.h>
	19	+#include <i2c.h>
	20	+#include <miiphy.h>
18	21	#include <fsl_esdhc.h>
19	22	#include <linux/sizes.h>
20	23	#include <mmc.h>
21	24	#include <mxsfb.h>
22	25	#include <asm/imx-common/video.h>
	26	+#include <power/pmic.h>
	27	+#include <power/pfuze3000_pmic.h>
	28	+#include "../common/pfuze.h"
23	29
24	30	DECLARE_GLOBAL_DATA_PTR;
25	31
26	32
...	...	@@ -27,9 +33,118 @@
27	33	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
28	34	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
29	35
	36	+#define I2C_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	37	+ PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	38	+ PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
	39	+ PAD_CTL_ODE)
	40	+
30	41	#define LCD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_100K_UP \| PAD_CTL_PUE \| \
31	42	PAD_CTL_PKE \| PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm)
32	43
	44	+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE \| PAD_CTL_PUE \| PAD_CTL_PUS_100K_UP)
	45	+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm \| PAD_CTL_SPEED_MED \| \
	46	+ PAD_CTL_SRE_FAST)
	47	+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 \| GPMI_PAD_CTRL1)
	48	+
	49	+#ifdef CONFIG_SYS_I2C
	50	+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
	51	+/* I2C1 for PMIC and EEPROM */
	52	+static struct i2c_pads_info i2c_pad_info1 = {
	53	+ .scl = {
	54	+ .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL \| PC,
	55	+ .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 \| PC,
	56	+ .gp = IMX_GPIO_NR(1, 28),
	57	+ },
	58	+ .sda = {
	59	+ .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA \| PC,
	60	+ .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 \| PC,
	61	+ .gp = IMX_GPIO_NR(1, 29),
	62	+ },
	63	+};
	64	+
	65	+#ifdef CONFIG_POWER
	66	+#define I2C_PMIC 0
	67	+int power_init_board(void)
	68	+{
	69	+ if (is_mx6ull_9x9_evk()) {
	70	+ struct pmic *pfuze;
	71	+ int ret;
	72	+ unsigned int reg, rev_id;
	73	+
	74	+ ret = power_pfuze3000_init(I2C_PMIC);
	75	+ if (ret)
	76	+ return ret;
	77	+
	78	+ pfuze = pmic_get("PFUZE3000");
	79	+ ret = pmic_probe(pfuze);
	80	+ if (ret)
	81	+ return ret;
	82	+
	83	+ pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
	84	+ pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
	85	+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
	86	+ reg, rev_id);
	87	+
	88	+ /* disable Low Power Mode during standby mode */
	89	+ pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
	90	+ reg \|= 0x1;
	91	+ pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
	92	+
	93	+ /* SW1B step ramp up time from 2us to 4us/25mV */
	94	+ reg = 0x40;
	95	+ pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
	96	+
	97	+ /* SW1B mode to APS/PFM */
	98	+ reg = 0xc;
	99	+ pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
	100	+
	101	+ /* SW1B standby voltage set to 0.975V */
	102	+ reg = 0xb;
	103	+ pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
	104	+ }
	105	+
	106	+ return 0;
	107	+}
	108	+
	109	+#ifdef CONFIG_LDO_BYPASS_CHECK
	110	+void ldo_mode_set(int ldo_bypass)
	111	+{
	112	+ unsigned int value;
	113	+ u32 vddarm;
	114	+
	115	+ struct pmic *p = pmic_get("PFUZE3000");
	116	+
	117	+ if (!p) {
	118	+ printf("No PMIC found!\n");
	119	+ return;
	120	+ }
	121	+
	122	+ /* switch to ldo_bypass mode */
	123	+ if (ldo_bypass) {
	124	+ prep_anatop_bypass();
	125	+ /* decrease VDDARM to 1.275V */
	126	+ pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value);
	127	+ value &= ~0x1f;
	128	+ value \|= PFUZE3000_SW1AB_SETP(1275);
	129	+ pmic_reg_write(p, PFUZE3000_SW1BVOLT, value);
	130	+
	131	+ set_anatop_bypass(1);
	132	+ vddarm = PFUZE3000_SW1AB_SETP(1175);
	133	+
	134	+ pmic_reg_read(p, PFUZE3000_SW1BVOLT, &value);
	135	+ value &= ~0x1f;
	136	+ value \|= vddarm;
	137	+ pmic_reg_write(p, PFUZE3000_SW1BVOLT, value);
	138	+
	139	+ finish_anatop_bypass();
	140	+
	141	+ printf("switch to ldo_bypass mode!\n");
	142	+ }
	143	+}
	144	+#endif
	145	+#endif
	146	+#endif
	147	+
33	148	int dram_init(void)
34	149	{
35	150	gd->ram_size = imx_ddr_size();
...	...	@@ -47,6 +162,115 @@
47	162	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
48	163	}
49	164
	165	+#ifdef CONFIG_FSL_QSPI
	166	+
	167	+#ifndef CONFIG_DM_SPI
	168	+#define QSPI_PAD_CTRL1 \
	169	+ (PAD_CTL_SRE_FAST \| PAD_CTL_SPEED_MED \| \
	170	+ PAD_CTL_PKE \| PAD_CTL_PUE \| PAD_CTL_PUS_47K_UP \| PAD_CTL_DSE_120ohm)
	171	+
	172	+static iomux_v3_cfg_t const quadspi_pads[] = {
	173	+ MX6_PAD_NAND_WP_B__QSPI_A_SCLK \| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	174	+ MX6_PAD_NAND_READY_B__QSPI_A_DATA00 \| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	175	+ MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 \| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	176	+ MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 \| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	177	+ MX6_PAD_NAND_CLE__QSPI_A_DATA03 \| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	178	+ MX6_PAD_NAND_DQS__QSPI_A_SS0_B \| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	179	+};
	180	+#endif
	181	+
	182	+static int board_qspi_init(void)
	183	+{
	184	+#ifndef CONFIG_DM_SPI
	185	+ /* Set the iomux */
	186	+ imx_iomux_v3_setup_multiple_pads(quadspi_pads,
	187	+ ARRAY_SIZE(quadspi_pads));
	188	+#endif
	189	+ /* Set the clock */
	190	+ enable_qspi_clk(0);
	191	+
	192	+ return 0;
	193	+}
	194	+#endif
	195	+
	196	+#ifdef CONFIG_NAND_MXS
	197	+static iomux_v3_cfg_t const nand_pads[] = {
	198	+ MX6_PAD_NAND_DATA00__RAWNAND_DATA00 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	199	+ MX6_PAD_NAND_DATA01__RAWNAND_DATA01 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	200	+ MX6_PAD_NAND_DATA02__RAWNAND_DATA02 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	201	+ MX6_PAD_NAND_DATA03__RAWNAND_DATA03 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	202	+ MX6_PAD_NAND_DATA04__RAWNAND_DATA04 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	203	+ MX6_PAD_NAND_DATA05__RAWNAND_DATA05 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	204	+ MX6_PAD_NAND_DATA06__RAWNAND_DATA06 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	205	+ MX6_PAD_NAND_DATA07__RAWNAND_DATA07 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	206	+ MX6_PAD_NAND_CLE__RAWNAND_CLE \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	207	+ MX6_PAD_NAND_ALE__RAWNAND_ALE \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	208	+ MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	209	+ MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	210	+ MX6_PAD_NAND_RE_B__RAWNAND_RE_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	211	+ MX6_PAD_NAND_WE_B__RAWNAND_WE_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	212	+ MX6_PAD_NAND_WP_B__RAWNAND_WP_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	213	+ MX6_PAD_NAND_READY_B__RAWNAND_READY_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	214	+ MX6_PAD_NAND_DQS__RAWNAND_DQS \| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
	215	+};
	216	+
	217	+static void setup_gpmi_nand(void)
	218	+{
	219	+ struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	220	+
	221	+ /* config gpmi nand iomux */
	222	+ imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
	223	+
	224	+ setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) \|
	225	+ (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
	226	+
	227	+ /* enable apbh clock gating */
	228	+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
	229	+}
	230	+#endif
	231	+
	232	+#ifdef CONFIG_FEC_MXC
	233	+static int setup_fec(int fec_id)
	234	+{
	235	+ struct iomuxc const iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	236	+ int ret;
	237	+
	238	+ if (fec_id == 0) {
	239	+ /*
	240	+ * Use 50M anatop loopback REF_CLK1 for ENET1,
	241	+ * clear gpr1[13], set gpr1[17].
	242	+ */
	243	+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
	244	+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
	245	+ } else {
	246	+ /*
	247	+ * Use 50M anatop loopback REF_CLK2 for ENET2,
	248	+ * clear gpr1[14], set gpr1[18].
	249	+ */
	250	+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
	251	+ IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
	252	+ }
	253	+
	254	+ ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
	255	+ if (ret)
	256	+ return ret;
	257	+
	258	+ enable_enet_clk(1);
	259	+
	260	+ return 0;
	261	+}
	262	+
	263	+int board_phy_config(struct phy_device *phydev)
	264	+{
	265	+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
	266	+
	267	+ if (phydev->drv->config)
	268	+ phydev->drv->config(phydev);
	269	+
	270	+ return 0;
	271	+}
	272	+#endif
	273	+
50	274	int board_mmc_get_env_dev(int devno)
51	275	{
52	276	return devno;
...	...	@@ -147,6 +371,22 @@
147	371	/* Address of boot parameters */
148	372	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
149	373
	374	+#ifdef CONFIG_SYS_I2C
	375	+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	376	+#endif
	377	+
	378	+#ifdef CONFIG_FEC_MXC
	379	+ setup_fec(CONFIG_FEC_ENET_DEV);
	380	+#endif
	381	+
	382	+#ifdef CONFIG_FSL_QSPI
	383	+ board_qspi_init();
	384	+#endif
	385	+
	386	+#ifdef CONFIG_NAND_MXS
	387	+ setup_gpmi_nand();
	388	+#endif
	389	+
150	390	return 0;
151	391	}
152	392
153	393
154	394
...	...	@@ -168,15 +408,28 @@
168	408
169	409	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
170	410	setenv("board_name", "EVK");
171		- setenv("board_rev", "14X14");
	411	+
	412	+ if (is_mx6ull_9x9_evk())
	413	+ setenv("board_rev", "9X9");
	414	+ else
	415	+ setenv("board_rev", "14X14");
172	416	#endif
173	417
	418	+#ifdef CONFIG_ENV_IS_IN_MMC
	419	+ board_late_mmc_env_init();
	420	+#endif
	421	+
	422	+ set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
	423	+
174	424	return 0;
175	425	}
176	426
177	427	int checkboard(void)
178	428	{
179		- puts("Board: MX6ULL 14x14 EVK\n");
	429	+ if (is_mx6ull_9x9_evk())
	430	+ puts("Board: MX6ULL 9x9 EVK\n");
	431	+ else
	432	+ puts("Board: MX6ULL 14x14 EVK\n");
180	433
181	434	return 0;
182	435	}
...	...	@@ -11,11 +11,14 @@
11	11	# CONFIG_CMD_IMLS is not set
12	12	CONFIG_CMD_MEMTEST=y
13	13	CONFIG_CMD_MMC=y
	14	+CONFIG_CMD_SF=y
	15	+CONFIG_CMD_USB=y
14	16	CONFIG_CMD_I2C=y
15	17	CONFIG_CMD_GPIO=y
16	18	CONFIG_CMD_DHCP=y
17	19	CONFIG_CMD_PING=y
18	20	CONFIG_CMD_CACHE=y
	21	+CONFIG_CMD_NET=y
19	22	CONFIG_CMD_EXT2=y
20	23	CONFIG_CMD_EXT4=y
21	24	CONFIG_CMD_EXT4_WRITE=y
22	25
...	...	@@ -27,9 +30,21 @@
27	30	CONFIG_DM_74X164=y
28	31	CONFIG_DM_I2C=y
29	32	CONFIG_DM_MMC=y
	33	+CONFIG_DM_SPI=y
	34	+CONFIG_DM_SPI_FLASH=y
	35	+CONFIG_SPI_FLASH=y
	36	+CONFIG_SPI_FLASH_BAR=y
	37	+CONFIG_SPI_FLASH_STMICRO=y
30	38	# CONFIG_DM_MMC_OPS is not set
31	39	CONFIG_PINCTRL=y
32	40	CONFIG_PINCTRL_IMX6=y
33	41	CONFIG_DM_REGULATOR=y
34		-CONFIG_DM_SPI=y
	42	+CONFIG_DM_REGULATOR_FIXED=y
	43	+CONFIG_DM_REGULATOR_GPIO=y
	44	+CONFIG_USB=y
	45	+CONFIG_DM_USB=y
	46	+CONFIG_USB_EHCI_HCD=y
	47	+CONFIG_USB_STORAGE=y
	48	+CONFIG_FSL_QSPI=y
	49	+CONFIG_DM_ETH=y
...	...	@@ -12,11 +12,14 @@
12	12	# CONFIG_CMD_IMLS is not set
13	13	CONFIG_CMD_MEMTEST=y
14	14	CONFIG_CMD_MMC=y
	15	+CONFIG_CMD_SF=y
	16	+CONFIG_CMD_USB=y
15	17	CONFIG_CMD_I2C=y
16	18	CONFIG_CMD_GPIO=y
17	19	CONFIG_CMD_DHCP=y
18	20	CONFIG_CMD_PING=y
19	21	CONFIG_CMD_CACHE=y
	22	+CONFIG_CMD_NET=y
20	23	CONFIG_CMD_EXT2=y
21	24	CONFIG_CMD_EXT4=y
22	25	CONFIG_CMD_EXT4_WRITE=y
23	26
...	...	@@ -28,9 +31,21 @@
28	31	CONFIG_DM_74X164=y
29	32	CONFIG_DM_I2C=y
30	33	CONFIG_DM_MMC=y
	34	+CONFIG_DM_SPI=y
	35	+CONFIG_DM_SPI_FLASH=y
	36	+CONFIG_SPI_FLASH=y
	37	+CONFIG_SPI_FLASH_BAR=y
	38	+CONFIG_SPI_FLASH_STMICRO=y
31	39	# CONFIG_DM_MMC_OPS is not set
32	40	CONFIG_PINCTRL=y
33	41	CONFIG_PINCTRL_IMX6=y
34	42	CONFIG_DM_REGULATOR=y
35		-CONFIG_DM_SPI=y
	43	+CONFIG_DM_REGULATOR_FIXED=y
	44	+CONFIG_DM_REGULATOR_GPIO=y
	45	+CONFIG_USB=y
	46	+CONFIG_DM_USB=y
	47	+CONFIG_USB_EHCI_HCD=y
	48	+CONFIG_USB_STORAGE=y
	49	+CONFIG_FSL_QSPI=y
	50	+CONFIG_DM_ETH=y
...	...	@@ -14,21 +14,24 @@
14	14	#include "mx6_common.h"
15	15	#include <asm/imx-common/gpio.h>
16	16
17		-#ifdef CONFIG_SECURE_BOOT
18		-#ifndef CONFIG_CSF_SIZE
19		-#define CONFIG_CSF_SIZE 0x4000
20		-#endif
21		-#endif
22	17
23		-#define PHYS_SDRAM_SIZE SZ_512M
	18	+#define is_mx6ull_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6ULL_9X9_EVK)
24	19
	20	+#ifdef CONFIG_TARGET_MX6ULL_9X9_EVK
	21	+#define PHYS_SDRAM_SIZE SZ_256M
	22	+#define BOOTARGS_CMA_SIZE "cma=96M "
	23	+#else
	24	+#define PHYS_SDRAM_SIZE SZ_512M
	25	+#define BOOTARGS_CMA_SIZE ""
	26	+/* DCDC used on 14x14 EVK, no PMIC */
	27	+#undef CONFIG_LDO_BYPASS_CHECK
	28	+#endif
	29	+
25	30	#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
26	31
27	32	/* Size of malloc() pool */
28	33	#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
29	34
30		-#define CONFIG_MXC_GPIO
31		-
32	35	#define CONFIG_MXC_UART
33	36	#define CONFIG_MXC_UART_BASE UART1_BASE
34	37
...	...	@@ -37,7 +40,7 @@
37	40	#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
38	41
39	42	/* NAND pin conflicts with usdhc2 */
40		-#ifdef CONFIG_SYS_USE_NAND
	43	+#ifdef CONFIG_CMD_NAND
41	44	#define CONFIG_SYS_FSL_USDHC_NUM 1
42	45	#else
43	46	#define CONFIG_SYS_FSL_USDHC_NUM 2
44	47
45	48
46	49
47	50
48	51
...	...	@@ -52,24 +55,74 @@
52	55	#define CONFIG_SYS_I2C_SPEED 100000
53	56	#endif
54	57
	58	+/* Only use DM I2C driver for 14x14 EVK. Because the PFUZE3000 driver does not support DM */
	59	+#ifndef CONFIG_DM_I2C
	60	+#define CONFIG_SYS_I2C
	61	+
	62	+/* PMIC only for 9X9 EVK */
	63	+#define CONFIG_POWER
	64	+#define CONFIG_POWER_I2C
	65	+#define CONFIG_POWER_PFUZE3000
	66	+#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
	67	+#endif
	68	+
55	69	#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
56	70
	71	+#ifdef CONFIG_NAND_BOOT
	72	+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) "
	73	+#else
	74	+#define MFG_NAND_PARTITION ""
	75	+#endif
	76	+
	77	+#define CONFIG_MFG_ENV_SETTINGS \
	78	+ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
	79	+ BOOTARGS_CMA_SIZE \
	80	+ "rdinit=/linuxrc " \
	81	+ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
	82	+ "g_mass_storage.file=/fat g_mass_storage.ro=1 " \
	83	+ "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
	84	+ "g_mass_storage.iSerialNumber=\"\" "\
	85	+ MFG_NAND_PARTITION \
	86	+ "clk_ignore_unused "\
	87	+ "\0" \
	88	+ "initrd_addr=0x83800000\0" \
	89	+ "initrd_high=0xffffffff\0" \
	90	+ "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
	91	+
	92	+#if defined(CONFIG_NAND_BOOT)
57	93	#define CONFIG_EXTRA_ENV_SETTINGS \
	94	+ CONFIG_MFG_ENV_SETTINGS \
	95	+ "panel=TFT43AB\0" \
	96	+ "fdt_addr=0x83000000\0" \
	97	+ "fdt_high=0xffffffff\0" \
	98	+ "console=ttymxc0\0" \
	99	+ "bootargs=console=ttymxc0,115200 ubi.mtd=4 " \
	100	+ "root=ubi0:rootfs rootfstype=ubifs " \
	101	+ BOOTARGS_CMA_SIZE \
	102	+ "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\
	103	+ "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
	104	+ "nand read ${fdt_addr} 0x5000000 0x100000;"\
	105	+ "bootz ${loadaddr} - ${fdt_addr}\0"
	106	+
	107	+#else
	108	+#define CONFIG_EXTRA_ENV_SETTINGS \
	109	+ CONFIG_MFG_ENV_SETTINGS \
58	110	"script=boot.scr\0" \
59	111	"image=zImage\0" \
60	112	"console=ttymxc0\0" \
61	113	"fdt_high=0xffffffff\0" \
62	114	"initrd_high=0xffffffff\0" \
63		- "fdt_file=imx6ull-14x14-evk.dtb\0" \" \
	115	+ "fdt_file=undefined\0" \" \
64	116	"fdt_addr=0x83000000\0" \
65	117	"boot_fdt=try\0" \
66	118	"ip_dyn=yes\0" \
67		- "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \" \
	119	+ "panel=TFT43AB\0" \" \
68	120	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
69	121	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
70	122	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
71	123	"mmcautodetect=yes\0" \
72	124	"mmcargs=setenv bootargs console=${console},${baudrate} " \
	125	+ BOOTARGS_CMA_SIZE \
73	126	"root=${mmcroot}\0" \
74	127	"loadbootscript=" \
75	128	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
...	...	@@ -93,6 +146,7 @@
93	146	"bootz; " \
94	147	"fi;\0" \
95	148	"netargs=setenv bootargs console=${console},${baudrate} " \
	149	+ BOOTARGS_CMA_SIZE \
96	150	"root=/dev/nfs " \
97	151	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
98	152	"netboot=echo Booting from net ...; " \
99	153
...	...	@@ -116,8 +170,18 @@
116	170	"else " \
117	171	"bootz; " \
118	172	"fi;\0" \
	173	+ "findfdt="\
	174	+ "if test $fdt_file = undefined; then " \
	175	+ "if test $board_name = EVK && test $board_rev = 9X9; then " \
	176	+ "setenv fdt_file imx6ull-9x9-evk.dtb; fi; " \
	177	+ "if test $board_name = EVK && test $board_rev = 14X14; then " \
	178	+ "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \
	179	+ "if test $fdt_file = undefined; then " \
	180	+ "echo WARNING: Could not determine dtb to use; fi; " \
	181	+ "fi;\0" \
119	182
120	183	#define CONFIG_BOOTCOMMAND \
	184	+ "run findfdt;" \
121	185	"mmc dev ${mmcdev};" \
122	186	"mmc dev ${mmcdev}; if mmc rescan; then " \
123	187	"if run loadbootscript; then " \
...	...	@@ -129,6 +193,7 @@
129	193	"fi; " \
130	194	"fi; " \
131	195	"else run netboot; fi"
	196	+#endif
132	197
133	198	/* Miscellaneous configurable options */
134	199	#define CONFIG_SYS_MEMTEST_START 0x80000000
135	200
...	...	@@ -152,15 +217,20 @@
152	217	#define CONFIG_SYS_INIT_SP_ADDR \
153	218	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
154	219
	220	+#ifdef CONFIG_QSPI_BOOT
	221	+#define CONFIG_ENV_IS_IN_SPI_FLASH
	222	+#elif defined CONFIG_NAND_BOOT
	223	+#define CONFIG_CMD_NAND
	224	+#define CONFIG_ENV_IS_IN_NAND
	225	+#else
	226	+#define CONFIG_ENV_IS_IN_MMC
	227	+#endif
	228	+
155	229	/* environment organization */
156	230	#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
157	231	#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
158	232	#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
159	233
160		-#define CONFIG_ENV_IS_IN_MMC
161		-#define CONFIG_ENV_SIZE SZ_8K
162		-#define CONFIG_ENV_OFFSET (12 * SZ_64K)
163		-
164	234	#define CONFIG_CMD_BMODE
165	235
166	236	#define CONFIG_IMX_THERMAL
...	...	@@ -168,6 +238,78 @@
168	238	#define CONFIG_IOMUX_LPSR
169	239
170	240	#define CONFIG_SOFT_SPI
	241	+
	242	+#ifdef CONFIG_FSL_QSPI
	243	+#define CONFIG_SYS_FSL_QSPI_AHB
	244	+#define CONFIG_SF_DEFAULT_BUS 0
	245	+#define CONFIG_SF_DEFAULT_CS 0
	246	+#define CONFIG_SF_DEFAULT_SPEED 40000000
	247	+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
	248	+#define FSL_QSPI_FLASH_NUM 1
	249	+#define FSL_QSPI_FLASH_SIZE SZ_32M
	250	+#endif
	251	+
	252	+#ifdef CONFIG_CMD_NAND
	253	+#define CONFIG_CMD_NAND_TRIMFFS
	254	+
	255	+#define CONFIG_NAND_MXS
	256	+#define CONFIG_SYS_MAX_NAND_DEVICE 1
	257	+#define CONFIG_SYS_NAND_BASE 0x40000000
	258	+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	259	+#define CONFIG_SYS_NAND_ONFI_DETECTION
	260	+
	261	+/* DMA stuff, needed for GPMI/MXS NAND support */
	262	+#define CONFIG_APBH_DMA
	263	+#define CONFIG_APBH_DMA_BURST
	264	+#define CONFIG_APBH_DMA_BURST8
	265	+#endif
	266	+
	267	+#define CONFIG_ENV_SIZE SZ_8K
	268	+#if defined(CONFIG_ENV_IS_IN_MMC)
	269	+#define CONFIG_ENV_OFFSET (13 * SZ_64K)
	270	+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
	271	+#define CONFIG_ENV_OFFSET (864 * 1024)
	272	+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	273	+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
	274	+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	275	+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
	276	+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	277	+#elif defined(CONFIG_ENV_IS_IN_NAND)
	278	+#undef CONFIG_ENV_SIZE
	279	+#define CONFIG_ENV_OFFSET (60 << 20)
	280	+#define CONFIG_ENV_SECT_SIZE (128 << 10)
	281	+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	282	+#endif
	283	+
	284	+/* USB Configs */
	285	+#ifdef CONFIG_CMD_USB
	286	+#define CONFIG_USB_HOST_ETHER
	287	+#define CONFIG_USB_ETHER_ASIX
	288	+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	289	+#endif
	290	+
	291	+#ifdef CONFIG_CMD_NET
	292	+#define CONFIG_CMD_MII
	293	+#define CONFIG_FEC_MXC
	294	+#define CONFIG_MII
	295	+#define CONFIG_FEC_ENET_DEV 1
	296	+
	297	+#if (CONFIG_FEC_ENET_DEV == 0)
	298	+#define IMX_FEC_BASE ENET_BASE_ADDR
	299	+#define CONFIG_FEC_MXC_PHYADDR 0x2
	300	+#define CONFIG_FEC_XCV_TYPE RMII
	301	+#define CONFIG_ETHPRIME "FEC0"
	302	+#elif (CONFIG_FEC_ENET_DEV == 1)
	303	+#define IMX_FEC_BASE ENET2_BASE_ADDR
	304	+#define CONFIG_FEC_MXC_PHYADDR 0x1
	305	+#define CONFIG_FEC_XCV_TYPE RMII
	306	+#define CONFIG_ETHPRIME "FEC1"
	307	+#endif
	308	+
	309	+#define CONFIG_PHYLIB
	310	+#define CONFIG_PHY_MICREL
	311	+#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR
	312	+#endif
171	313
172	314	#ifdef CONFIG_VIDEO
173	315	#define CONFIG_VIDEO_MXS