Commit c416eeb2084d6f47919e52b90d2f5fc69c756624
Committed by
guoyin.chen
1 parent
907059ee67
Exists in
smarc-imx_v2015.04_4.1.15_1.0.0_ga
and in
1 other branch
MLK-12017 imx: mx6ulevk: Update DDR script for new DDR MT41K256M16TW-107
Current Micron DDR MT41K256M16HA-125 on i.MX6UL will be EOL. Plan is i.MX6UL will use the new 20nm litho 4Gb DDR3L MT41K256M16TW-107. Update DDR script of mx6ul evk board for this new DDR, and use it as default. http://compass.freescale.net/livelink/livelink?func=ll&objId=234910940&objAction=browse&viewType=1 Test result: Stress test passed. Meanwhile add build targets below for old DDR support: mx6ul_14x14_evk_ddr_eol_android_defconfig mx6ul_14x14_evk_ddr_eol_brillo_defconfig mx6ul_14x14_evk_ddr_eol_defconfig mx6ul_14x14_evk_ddr_eol_qspi1_defconfig Signed-off-by: Ye.Li <B37916@freescale.com>
Showing 6 changed files with 203 additions and 0 deletions Side-by-side Diff
board/freescale/mx6ul_14x14_evk/imximage.cfg
... | ... | @@ -50,6 +50,10 @@ |
50 | 50 | * value value to be stored in the register |
51 | 51 | */ |
52 | 52 | |
53 | +#ifdef CONFIG_DDR3L_MT41K256M16HA | |
54 | + | |
55 | +/* DDR type MT41K256M16HA-125 which is EOL */ | |
56 | + | |
53 | 57 | /* Enable all clocks */ |
54 | 58 | DATA 4 0x020c4068 0xffffffff |
55 | 59 | DATA 4 0x020c406c 0xffffffff |
... | ... | @@ -111,5 +115,74 @@ |
111 | 115 | DATA 4 0x021B0004 0x0002552D |
112 | 116 | DATA 4 0x021B0404 0x00011006 |
113 | 117 | DATA 4 0x021B001C 0x00000000 |
118 | + | |
119 | +#else | |
120 | + | |
121 | +/* New DDR type MT41K256M16TW-107 */ | |
122 | + | |
123 | +/* Enable all clocks */ | |
124 | +DATA 4 0x020c4068 0xffffffff | |
125 | +DATA 4 0x020c406c 0xffffffff | |
126 | +DATA 4 0x020c4070 0xffffffff | |
127 | +DATA 4 0x020c4074 0xffffffff | |
128 | +DATA 4 0x020c4078 0xffffffff | |
129 | +DATA 4 0x020c407c 0xffffffff | |
130 | +DATA 4 0x020c4080 0xffffffff | |
131 | + | |
132 | +DATA 4 0x020E04B4 0x000C0000 | |
133 | +DATA 4 0x020E04AC 0x00000000 | |
134 | +DATA 4 0x020E027C 0x00000030 | |
135 | +DATA 4 0x020E0250 0x00000030 | |
136 | +DATA 4 0x020E024C 0x00000030 | |
137 | +DATA 4 0x020E0490 0x00000030 | |
138 | +DATA 4 0x020E0288 0x00000030 | |
139 | +DATA 4 0x020E0270 0x00000000 | |
140 | +DATA 4 0x020E0260 0x00000030 | |
141 | +DATA 4 0x020E0264 0x00000030 | |
142 | +DATA 4 0x020E04A0 0x00000030 | |
143 | +DATA 4 0x020E0494 0x00020000 | |
144 | +DATA 4 0x020E0280 0x00000030 | |
145 | +DATA 4 0x020E0284 0x00000030 | |
146 | +DATA 4 0x020E04B0 0x00020000 | |
147 | +DATA 4 0x020E0498 0x00000030 | |
148 | +DATA 4 0x020E04A4 0x00000030 | |
149 | +DATA 4 0x020E0244 0x00000030 | |
150 | +DATA 4 0x020E0248 0x00000030 | |
151 | +DATA 4 0x021B001C 0x00008000 | |
152 | +DATA 4 0x021B0800 0xA1390003 | |
153 | +DATA 4 0x021B080C 0x00000000 | |
154 | +DATA 4 0x021B083C 0x41570155 | |
155 | +DATA 4 0x021B0848 0x4040474A | |
156 | +DATA 4 0x021B0850 0x40405550 | |
157 | +DATA 4 0x021B081C 0x33333333 | |
158 | +DATA 4 0x021B0820 0x33333333 | |
159 | +DATA 4 0x021B082C 0xf3333333 | |
160 | +DATA 4 0x021B0830 0xf3333333 | |
161 | +DATA 4 0x021B08C0 0x00921012 | |
162 | +DATA 4 0x021B08b8 0x00000800 | |
163 | +DATA 4 0x021B0004 0x0002002D | |
164 | +DATA 4 0x021B0008 0x1B333030 | |
165 | +DATA 4 0x021B000C 0x676B52F3 | |
166 | +DATA 4 0x021B0010 0xB66D0B63 | |
167 | +DATA 4 0x021B0014 0x01FF00DB | |
168 | +DATA 4 0x021B0018 0x00201740 | |
169 | +DATA 4 0x021B001C 0x00008000 | |
170 | +DATA 4 0x021B002C 0x000026D2 | |
171 | +DATA 4 0x021B0030 0x006B1023 | |
172 | +DATA 4 0x021B0040 0x0000004F | |
173 | +DATA 4 0x021B0000 0x84180000 | |
174 | +DATA 4 0x021B0890 0x23400A38 | |
175 | +DATA 4 0x021B001C 0x02008032 | |
176 | +DATA 4 0x021B001C 0x00008033 | |
177 | +DATA 4 0x021B001C 0x00048031 | |
178 | +DATA 4 0x021B001C 0x15208030 | |
179 | +DATA 4 0x021B001C 0x04008040 | |
180 | +DATA 4 0x021B0020 0x00000800 | |
181 | +DATA 4 0x021B0818 0x00000227 | |
182 | +DATA 4 0x021B0004 0x0002552D | |
183 | +DATA 4 0x021B0404 0x00011006 | |
184 | +DATA 4 0x021B001C 0x00000000 | |
185 | +#endif | |
186 | + | |
114 | 187 | #endif |
board/freescale/mx6ul_14x14_evk/plugin.S
... | ... | @@ -53,6 +53,114 @@ |
53 | 53 | str r1, [r0, #0x800] |
54 | 54 | ldr r1, =0x00000000 |
55 | 55 | str r1, [r0, #0x80C] |
56 | + ldr r1, =0x41570155 | |
57 | + str r1, [r0, #0x83C] | |
58 | + ldr r1, =0x4040474A | |
59 | + str r1, [r0, #0x848] | |
60 | + ldr r1, =0x40405550 | |
61 | + str r1, [r0, #0x850] | |
62 | + ldr r1, =0x33333333 | |
63 | + str r1, [r0, #0x81C] | |
64 | + str r1, [r0, #0x820] | |
65 | + ldr r1, =0xF3333333 | |
66 | + str r1, [r0, #0x82C] | |
67 | + str r1, [r0, #0x830] | |
68 | + ldr r1, =0x00921012 | |
69 | + str r1, [r0, #0x8C0] | |
70 | + ldr r1, =0x00000800 | |
71 | + str r1, [r0, #0x8B8] | |
72 | + ldr r1, =0x0002002D | |
73 | + str r1, [r0, #0x004] | |
74 | + ldr r1, =0x1B333030 | |
75 | + str r1, [r0, #0x008] | |
76 | + ldr r1, =0x676B52F3 | |
77 | + str r1, [r0, #0x00C] | |
78 | + ldr r1, =0xB66D0B63 | |
79 | + str r1, [r0, #0x010] | |
80 | + ldr r1, =0x01FF00DB | |
81 | + str r1, [r0, #0x014] | |
82 | + ldr r1, =0x00201740 | |
83 | + str r1, [r0, #0x018] | |
84 | + ldr r1, =0x00008000 | |
85 | + str r1, [r0, #0x01C] | |
86 | + ldr r1, =0x000026D2 | |
87 | + str r1, [r0, #0x02C] | |
88 | + ldr r1, =0x006B1023 | |
89 | + str r1, [r0, #0x030] | |
90 | + ldr r1, =0x0000004F | |
91 | + str r1, [r0, #0x040] | |
92 | + ldr r1, =0x84180000 | |
93 | + str r1, [r0, #0x000] | |
94 | + ldr r1, =0x23400A38 | |
95 | + str r1, [r0, #0x890] | |
96 | + ldr r1, =0x02008032 | |
97 | + str r1, [r0, #0x01C] | |
98 | + ldr r1, =0x00008033 | |
99 | + str r1, [r0, #0x01C] | |
100 | + ldr r1, =0x00048031 | |
101 | + str r1, [r0, #0x01C] | |
102 | + ldr r1, =0x15208030 | |
103 | + str r1, [r0, #0x01C] | |
104 | + ldr r1, =0x04008040 | |
105 | + str r1, [r0, #0x01C] | |
106 | + ldr r1, =0x00000800 | |
107 | + str r1, [r0, #0x020] | |
108 | + ldr r1, =0x00000227 | |
109 | + str r1, [r0, #0x818] | |
110 | + ldr r1, =0x0002552D | |
111 | + str r1, [r0, #0x004] | |
112 | + ldr r1, =0x00011006 | |
113 | + str r1, [r0, #0x404] | |
114 | + ldr r1, =0x00000000 | |
115 | + str r1, [r0, #0x01C] | |
116 | +.endm | |
117 | + | |
118 | +.macro imx6ul_ddr3_eol_evk_setting | |
119 | + ldr r0, =IOMUXC_BASE_ADDR | |
120 | + ldr r1, =0x000C0000 | |
121 | + str r1, [r0, #0x4B4] | |
122 | + ldr r1, =0x00000000 | |
123 | + str r1, [r0, #0x4AC] | |
124 | + ldr r1, =0x00000030 | |
125 | + str r1, [r0, #0x27C] | |
126 | + ldr r1, =0x00000030 | |
127 | + str r1, [r0, #0x250] | |
128 | + str r1, [r0, #0x24C] | |
129 | + str r1, [r0, #0x490] | |
130 | + str r1, [r0, #0x288] | |
131 | + | |
132 | + ldr r1, =0x00000000 | |
133 | + str r1, [r0, #0x270] | |
134 | + | |
135 | + ldr r1, =0x00000030 | |
136 | + str r1, [r0, #0x260] | |
137 | + str r1, [r0, #0x264] | |
138 | + str r1, [r0, #0x4A0] | |
139 | + | |
140 | + ldr r1, =0x00020000 | |
141 | + str r1, [r0, #0x494] | |
142 | + | |
143 | + ldr r1, =0x00000030 | |
144 | + str r1, [r0, #0x280] | |
145 | + ldr r1, =0x00000030 | |
146 | + str r1, [r0, #0x284] | |
147 | + | |
148 | + ldr r1, =0x00020000 | |
149 | + str r1, [r0, #0x4B0] | |
150 | + | |
151 | + ldr r1, =0x00000030 | |
152 | + str r1, [r0, #0x498] | |
153 | + str r1, [r0, #0x4A4] | |
154 | + str r1, [r0, #0x244] | |
155 | + str r1, [r0, #0x248] | |
156 | + | |
157 | + ldr r0, =MMDC_P0_BASE_ADDR | |
158 | + ldr r1, =0x00008000 | |
159 | + str r1, [r0, #0x1C] | |
160 | + ldr r1, =0xA1390003 | |
161 | + str r1, [r0, #0x800] | |
162 | + ldr r1, =0x00000000 | |
163 | + str r1, [r0, #0x80C] | |
56 | 164 | ldr r1, =0x41490145 |
57 | 165 | str r1, [r0, #0x83C] |
58 | 166 | ldr r1, =0x40404546 |
... | ... | @@ -245,6 +353,8 @@ |
245 | 353 | .macro imx6_ddr_setting |
246 | 354 | #if defined (CONFIG_MX6UL_9X9_LPDDR2) |
247 | 355 | imx6ul_lpddr2_evk_setting |
356 | +#elif defined(CONFIG_DDR3L_MT41K256M16HA) | |
357 | + imx6ul_ddr3_eol_evk_setting | |
248 | 358 | #else |
249 | 359 | imx6ul_ddr3_evk_setting |
250 | 360 | #endif |
configs/mx6ul_14x14_evk_ddr_eol_android_defconfig
configs/mx6ul_14x14_evk_ddr_eol_brillo_defconfig
configs/mx6ul_14x14_evk_ddr_eol_defconfig
configs/mx6ul_14x14_evk_ddr_eol_qspi1_defconfig