Eric Lee / smarc-uboot

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Commit c4217568797456bf2db2131a91c565596e88d588

Authored by Marek Vasut
Committed by Haibo Chen
1 parent 4c95f33890
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 4 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

mmc: Do not poll using CMD13 when changing timing 

When using CMD6 to switch eMMC card timing from HS200/HS400 to HS/legacy,
do not poll for the completion status using CMD13, but rather wait 50mS.

Once the card receives the CMD6 and starts executing it, the bus is in
undefined state until both the card finishes executing the command and
until the controller switches the bus to matching timing configuration.
During this time, it is not possible to transport any commands or data
across the bus, which includes the CMD13.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
(cherry picked from commit 5dbade95cb7ebc1f3a309b00430ebf2b466d7aba)
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

Showing 1 changed file with 20 additions and 8 deletions Inline Diff

1 /* 1 /*
2 * Copyright 2008, Freescale Semiconductor, Inc 2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming 3 * Andy Fleming
4 * 4 *
5 * Based vaguely on the Linux code 5 * Based vaguely on the Linux code
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #include <config.h> 10 #include <config.h>
11 #include <common.h> 11 #include <common.h>
12 #include <command.h> 12 #include <command.h>
13 #include <dm.h> 13 #include <dm.h>
14 #include <dm/device-internal.h> 14 #include <dm/device-internal.h>
15 #include <errno.h> 15 #include <errno.h>
16 #include <mmc.h> 16 #include <mmc.h>
17 #include <part.h> 17 #include <part.h>
18 #include <power/regulator.h> 18 #include <power/regulator.h>
19 #include <malloc.h> 19 #include <malloc.h>
20 #include <memalign.h> 20 #include <memalign.h>
21 #include <linux/list.h> 21 #include <linux/list.h>
22 #include <div64.h> 22 #include <div64.h>
23 #include "mmc_private.h" 23 #include "mmc_private.h"
24 24
25 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage); 25 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
26 static int mmc_power_cycle(struct mmc *mmc); 26 static int mmc_power_cycle(struct mmc *mmc);
27 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps); 27 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
28 28
29 #if CONFIG_IS_ENABLED(MMC_TINY) 29 #if CONFIG_IS_ENABLED(MMC_TINY)
30 static struct mmc mmc_static; 30 static struct mmc mmc_static;
31 struct mmc *find_mmc_device(int dev_num) 31 struct mmc *find_mmc_device(int dev_num)
32 { 32 {
33 return &mmc_static; 33 return &mmc_static;
34 } 34 }
35 35
36 void mmc_do_preinit(void) 36 void mmc_do_preinit(void)
37 { 37 {
38 struct mmc *m = &mmc_static; 38 struct mmc *m = &mmc_static;
39 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 39 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
40 mmc_set_preinit(m, 1); 40 mmc_set_preinit(m, 1);
41 #endif 41 #endif
42 if (m->preinit) 42 if (m->preinit)
43 mmc_start_init(m); 43 mmc_start_init(m);
44 } 44 }
45 45
46 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) 46 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
47 { 47 {
48 return &mmc->block_dev; 48 return &mmc->block_dev;
49 } 49 }
50 #endif 50 #endif
51 51
52 #if !CONFIG_IS_ENABLED(DM_MMC) 52 #if !CONFIG_IS_ENABLED(DM_MMC)
53 53
54 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 54 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
55 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout) 55 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
56 { 56 {
57 return -ENOSYS; 57 return -ENOSYS;
58 } 58 }
59 #endif 59 #endif
60 60
61 __weak int board_mmc_getwp(struct mmc *mmc) 61 __weak int board_mmc_getwp(struct mmc *mmc)
62 { 62 {
63 return -1; 63 return -1;
64 } 64 }
65 65
66 int mmc_getwp(struct mmc *mmc) 66 int mmc_getwp(struct mmc *mmc)
67 { 67 {
68 int wp; 68 int wp;
69 69
70 wp = board_mmc_getwp(mmc); 70 wp = board_mmc_getwp(mmc);
71 71
72 if (wp < 0) { 72 if (wp < 0) {
73 if (mmc->cfg->ops->getwp) 73 if (mmc->cfg->ops->getwp)
74 wp = mmc->cfg->ops->getwp(mmc); 74 wp = mmc->cfg->ops->getwp(mmc);
75 else 75 else
76 wp = 0; 76 wp = 0;
77 } 77 }
78 78
79 return wp; 79 return wp;
80 } 80 }
81 81
82 __weak int board_mmc_getcd(struct mmc *mmc) 82 __weak int board_mmc_getcd(struct mmc *mmc)
83 { 83 {
84 return -1; 84 return -1;
85 } 85 }
86 #endif 86 #endif
87 87
88 #ifdef CONFIG_MMC_TRACE 88 #ifdef CONFIG_MMC_TRACE
89 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd) 89 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
90 { 90 {
91 printf("CMD_SEND:%d\n", cmd->cmdidx); 91 printf("CMD_SEND:%d\n", cmd->cmdidx);
92 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); 92 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
93 } 93 }
94 94
95 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret) 95 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
96 { 96 {
97 int i; 97 int i;
98 u8 *ptr; 98 u8 *ptr;
99 99
100 if (ret) { 100 if (ret) {
101 printf("\t\tRET\t\t\t %d\n", ret); 101 printf("\t\tRET\t\t\t %d\n", ret);
102 } else { 102 } else {
103 switch (cmd->resp_type) { 103 switch (cmd->resp_type) {
104 case MMC_RSP_NONE: 104 case MMC_RSP_NONE:
105 printf("\t\tMMC_RSP_NONE\n"); 105 printf("\t\tMMC_RSP_NONE\n");
106 break; 106 break;
107 case MMC_RSP_R1: 107 case MMC_RSP_R1:
108 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", 108 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
109 cmd->response[0]); 109 cmd->response[0]);
110 break; 110 break;
111 case MMC_RSP_R1b: 111 case MMC_RSP_R1b:
112 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", 112 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
113 cmd->response[0]); 113 cmd->response[0]);
114 break; 114 break;
115 case MMC_RSP_R2: 115 case MMC_RSP_R2:
116 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", 116 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
117 cmd->response[0]); 117 cmd->response[0]);
118 printf("\t\t \t\t 0x%08X \n", 118 printf("\t\t \t\t 0x%08X \n",
119 cmd->response[1]); 119 cmd->response[1]);
120 printf("\t\t \t\t 0x%08X \n", 120 printf("\t\t \t\t 0x%08X \n",
121 cmd->response[2]); 121 cmd->response[2]);
122 printf("\t\t \t\t 0x%08X \n", 122 printf("\t\t \t\t 0x%08X \n",
123 cmd->response[3]); 123 cmd->response[3]);
124 printf("\n"); 124 printf("\n");
125 printf("\t\t\t\t\tDUMPING DATA\n"); 125 printf("\t\t\t\t\tDUMPING DATA\n");
126 for (i = 0; i < 4; i++) { 126 for (i = 0; i < 4; i++) {
127 int j; 127 int j;
128 printf("\t\t\t\t\t%03d - ", i*4); 128 printf("\t\t\t\t\t%03d - ", i*4);
129 ptr = (u8 *)&cmd->response[i]; 129 ptr = (u8 *)&cmd->response[i];
130 ptr += 3; 130 ptr += 3;
131 for (j = 0; j < 4; j++) 131 for (j = 0; j < 4; j++)
132 printf("%02X ", *ptr--); 132 printf("%02X ", *ptr--);
133 printf("\n"); 133 printf("\n");
134 } 134 }
135 break; 135 break;
136 case MMC_RSP_R3: 136 case MMC_RSP_R3:
137 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", 137 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
138 cmd->response[0]); 138 cmd->response[0]);
139 break; 139 break;
140 default: 140 default:
141 printf("\t\tERROR MMC rsp not supported\n"); 141 printf("\t\tERROR MMC rsp not supported\n");
142 break; 142 break;
143 } 143 }
144 } 144 }
145 } 145 }
146 146
147 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd) 147 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
148 { 148 {
149 int status; 149 int status;
150 150
151 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9; 151 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
152 printf("CURR STATE:%d\n", status); 152 printf("CURR STATE:%d\n", status);
153 } 153 }
154 #endif 154 #endif
155 155
156 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) 156 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
157 const char *mmc_mode_name(enum bus_mode mode) 157 const char *mmc_mode_name(enum bus_mode mode)
158 { 158 {
159 static const char *const names[] = { 159 static const char *const names[] = {
160 [MMC_LEGACY] = "MMC legacy", 160 [MMC_LEGACY] = "MMC legacy",
161 [SD_LEGACY] = "SD Legacy", 161 [SD_LEGACY] = "SD Legacy",
162 [MMC_HS] = "MMC High Speed (26MHz)", 162 [MMC_HS] = "MMC High Speed (26MHz)",
163 [SD_HS] = "SD High Speed (50MHz)", 163 [SD_HS] = "SD High Speed (50MHz)",
164 [UHS_SDR12] = "UHS SDR12 (25MHz)", 164 [UHS_SDR12] = "UHS SDR12 (25MHz)",
165 [UHS_SDR25] = "UHS SDR25 (50MHz)", 165 [UHS_SDR25] = "UHS SDR25 (50MHz)",
166 [UHS_SDR50] = "UHS SDR50 (100MHz)", 166 [UHS_SDR50] = "UHS SDR50 (100MHz)",
167 [UHS_SDR104] = "UHS SDR104 (208MHz)", 167 [UHS_SDR104] = "UHS SDR104 (208MHz)",
168 [UHS_DDR50] = "UHS DDR50 (50MHz)", 168 [UHS_DDR50] = "UHS DDR50 (50MHz)",
169 [MMC_HS_52] = "MMC High Speed (52MHz)", 169 [MMC_HS_52] = "MMC High Speed (52MHz)",
170 [MMC_DDR_52] = "MMC DDR52 (52MHz)", 170 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
171 [MMC_HS_200] = "HS200 (200MHz)", 171 [MMC_HS_200] = "HS200 (200MHz)",
172 [MMC_HS_400] = "HS400 (200MHz)", 172 [MMC_HS_400] = "HS400 (200MHz)",
173 [MMC_HS_400_ES] = "HS400ES (200MHz)", 173 [MMC_HS_400_ES] = "HS400ES (200MHz)",
174 }; 174 };
175 175
176 if (mode >= MMC_MODES_END) 176 if (mode >= MMC_MODES_END)
177 return "Unknown mode"; 177 return "Unknown mode";
178 else 178 else
179 return names[mode]; 179 return names[mode];
180 } 180 }
181 #endif 181 #endif
182 182
183 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode) 183 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
184 { 184 {
185 static const int freqs[] = { 185 static const int freqs[] = {
186 [MMC_LEGACY] = 25000000, 186 [MMC_LEGACY] = 25000000,
187 [SD_LEGACY] = 25000000, 187 [SD_LEGACY] = 25000000,
188 [MMC_HS] = 26000000, 188 [MMC_HS] = 26000000,
189 [SD_HS] = 50000000, 189 [SD_HS] = 50000000,
190 [MMC_HS_52] = 52000000, 190 [MMC_HS_52] = 52000000,
191 [MMC_DDR_52] = 52000000, 191 [MMC_DDR_52] = 52000000,
192 [UHS_SDR12] = 25000000, 192 [UHS_SDR12] = 25000000,
193 [UHS_SDR25] = 50000000, 193 [UHS_SDR25] = 50000000,
194 [UHS_SDR50] = 100000000, 194 [UHS_SDR50] = 100000000,
195 [UHS_DDR50] = 50000000, 195 [UHS_DDR50] = 50000000,
196 [UHS_SDR104] = 208000000, 196 [UHS_SDR104] = 208000000,
197 [MMC_HS_200] = 200000000, 197 [MMC_HS_200] = 200000000,
198 [MMC_HS_400] = 200000000, 198 [MMC_HS_400] = 200000000,
199 [MMC_HS_400_ES] = 200000000, 199 [MMC_HS_400_ES] = 200000000,
200 }; 200 };
201 201
202 if (mode == MMC_LEGACY) 202 if (mode == MMC_LEGACY)
203 return mmc->legacy_speed; 203 return mmc->legacy_speed;
204 else if (mode >= MMC_MODES_END) 204 else if (mode >= MMC_MODES_END)
205 return 0; 205 return 0;
206 else 206 else
207 return freqs[mode]; 207 return freqs[mode];
208 } 208 }
209 209
210 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode) 210 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
211 { 211 {
212 mmc->selected_mode = mode; 212 mmc->selected_mode = mode;
213 mmc->tran_speed = mmc_mode2freq(mmc, mode); 213 mmc->tran_speed = mmc_mode2freq(mmc, mode);
214 mmc->ddr_mode = mmc_is_mode_ddr(mode); 214 mmc->ddr_mode = mmc_is_mode_ddr(mode);
215 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode), 215 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
216 mmc->tran_speed / 1000000); 216 mmc->tran_speed / 1000000);
217 return 0; 217 return 0;
218 } 218 }
219 219
220 #if !CONFIG_IS_ENABLED(DM_MMC) 220 #if !CONFIG_IS_ENABLED(DM_MMC)
221 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 221 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
222 { 222 {
223 int ret; 223 int ret;
224 224
225 mmmc_trace_before_send(mmc, cmd); 225 mmmc_trace_before_send(mmc, cmd);
226 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 226 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
227 mmmc_trace_after_send(mmc, cmd, ret); 227 mmmc_trace_after_send(mmc, cmd, ret);
228 228
229 return ret; 229 return ret;
230 } 230 }
231 #endif 231 #endif
232 232
233 int mmc_send_status(struct mmc *mmc, int timeout) 233 int mmc_send_status(struct mmc *mmc, int timeout)
234 { 234 {
235 struct mmc_cmd cmd; 235 struct mmc_cmd cmd;
236 int err, retries = 5; 236 int err, retries = 5;
237 237
238 cmd.cmdidx = MMC_CMD_SEND_STATUS; 238 cmd.cmdidx = MMC_CMD_SEND_STATUS;
239 cmd.resp_type = MMC_RSP_R1; 239 cmd.resp_type = MMC_RSP_R1;
240 if (!mmc_host_is_spi(mmc)) 240 if (!mmc_host_is_spi(mmc))
241 cmd.cmdarg = mmc->rca << 16; 241 cmd.cmdarg = mmc->rca << 16;
242 242
243 while (1) { 243 while (1) {
244 err = mmc_send_cmd(mmc, &cmd, NULL); 244 err = mmc_send_cmd(mmc, &cmd, NULL);
245 if (!err) { 245 if (!err) {
246 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && 246 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
247 (cmd.response[0] & MMC_STATUS_CURR_STATE) != 247 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
248 MMC_STATE_PRG) 248 MMC_STATE_PRG)
249 break; 249 break;
250 250
251 if (cmd.response[0] & MMC_STATUS_MASK) { 251 if (cmd.response[0] & MMC_STATUS_MASK) {
252 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 252 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
253 pr_err("Status Error: 0x%08X\n", 253 pr_err("Status Error: 0x%08X\n",
254 cmd.response[0]); 254 cmd.response[0]);
255 #endif 255 #endif
256 return -ECOMM; 256 return -ECOMM;
257 } 257 }
258 } else if (--retries < 0) 258 } else if (--retries < 0)
259 return err; 259 return err;
260 260
261 if (timeout-- <= 0) 261 if (timeout-- <= 0)
262 break; 262 break;
263 263
264 udelay(1000); 264 udelay(1000);
265 } 265 }
266 266
267 mmc_trace_state(mmc, &cmd); 267 mmc_trace_state(mmc, &cmd);
268 if (timeout <= 0) { 268 if (timeout <= 0) {
269 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 269 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
270 pr_err("Timeout waiting card ready\n"); 270 pr_err("Timeout waiting card ready\n");
271 #endif 271 #endif
272 return -ETIMEDOUT; 272 return -ETIMEDOUT;
273 } 273 }
274 274
275 return 0; 275 return 0;
276 } 276 }
277 277
278 int mmc_set_blocklen(struct mmc *mmc, int len) 278 int mmc_set_blocklen(struct mmc *mmc, int len)
279 { 279 {
280 struct mmc_cmd cmd; 280 struct mmc_cmd cmd;
281 int err; 281 int err;
282 282
283 if (mmc->ddr_mode) 283 if (mmc->ddr_mode)
284 return 0; 284 return 0;
285 285
286 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; 286 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
287 cmd.resp_type = MMC_RSP_R1; 287 cmd.resp_type = MMC_RSP_R1;
288 cmd.cmdarg = len; 288 cmd.cmdarg = len;
289 289
290 err = mmc_send_cmd(mmc, &cmd, NULL); 290 err = mmc_send_cmd(mmc, &cmd, NULL);
291 291
292 #ifdef CONFIG_MMC_QUIRKS 292 #ifdef CONFIG_MMC_QUIRKS
293 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) { 293 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
294 int retries = 4; 294 int retries = 4;
295 /* 295 /*
296 * It has been seen that SET_BLOCKLEN may fail on the first 296 * It has been seen that SET_BLOCKLEN may fail on the first
297 * attempt, let's try a few more time 297 * attempt, let's try a few more time
298 */ 298 */
299 do { 299 do {
300 err = mmc_send_cmd(mmc, &cmd, NULL); 300 err = mmc_send_cmd(mmc, &cmd, NULL);
301 if (!err) 301 if (!err)
302 break; 302 break;
303 } while (retries--); 303 } while (retries--);
304 } 304 }
305 #endif 305 #endif
306 306
307 return err; 307 return err;
308 } 308 }
309 309
310 #ifdef MMC_SUPPORTS_TUNING 310 #ifdef MMC_SUPPORTS_TUNING
311 static const u8 tuning_blk_pattern_4bit[] = { 311 static const u8 tuning_blk_pattern_4bit[] = {
312 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc, 312 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
313 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef, 313 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
314 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb, 314 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
315 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef, 315 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
316 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c, 316 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
317 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee, 317 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
318 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff, 318 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
319 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde, 319 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
320 }; 320 };
321 321
322 static const u8 tuning_blk_pattern_8bit[] = { 322 static const u8 tuning_blk_pattern_8bit[] = {
323 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00, 323 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
324 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc, 324 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
325 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff, 325 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
326 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff, 326 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
327 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd, 327 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
328 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb, 328 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
329 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff, 329 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
330 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff, 330 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
331 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 331 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
332 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 332 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
333 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 333 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
334 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 334 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
335 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 335 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
336 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 336 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
337 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 337 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
338 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 338 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
339 }; 339 };
340 340
341 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error) 341 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
342 { 342 {
343 struct mmc_cmd cmd; 343 struct mmc_cmd cmd;
344 struct mmc_data data; 344 struct mmc_data data;
345 const u8 *tuning_block_pattern; 345 const u8 *tuning_block_pattern;
346 int size, err; 346 int size, err;
347 347
348 if (mmc->bus_width == 8) { 348 if (mmc->bus_width == 8) {
349 tuning_block_pattern = tuning_blk_pattern_8bit; 349 tuning_block_pattern = tuning_blk_pattern_8bit;
350 size = sizeof(tuning_blk_pattern_8bit); 350 size = sizeof(tuning_blk_pattern_8bit);
351 } else if (mmc->bus_width == 4) { 351 } else if (mmc->bus_width == 4) {
352 tuning_block_pattern = tuning_blk_pattern_4bit; 352 tuning_block_pattern = tuning_blk_pattern_4bit;
353 size = sizeof(tuning_blk_pattern_4bit); 353 size = sizeof(tuning_blk_pattern_4bit);
354 } else { 354 } else {
355 return -EINVAL; 355 return -EINVAL;
356 } 356 }
357 357
358 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size); 358 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
359 359
360 cmd.cmdidx = opcode; 360 cmd.cmdidx = opcode;
361 cmd.cmdarg = 0; 361 cmd.cmdarg = 0;
362 cmd.resp_type = MMC_RSP_R1; 362 cmd.resp_type = MMC_RSP_R1;
363 363
364 data.dest = (void *)data_buf; 364 data.dest = (void *)data_buf;
365 data.blocks = 1; 365 data.blocks = 1;
366 data.blocksize = size; 366 data.blocksize = size;
367 data.flags = MMC_DATA_READ; 367 data.flags = MMC_DATA_READ;
368 368
369 err = mmc_send_cmd(mmc, &cmd, &data); 369 err = mmc_send_cmd(mmc, &cmd, &data);
370 if (err) 370 if (err)
371 return err; 371 return err;
372 372
373 if (memcmp(data_buf, tuning_block_pattern, size)) 373 if (memcmp(data_buf, tuning_block_pattern, size))
374 return -EIO; 374 return -EIO;
375 375
376 return 0; 376 return 0;
377 } 377 }
378 #endif 378 #endif
379 379
380 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, 380 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
381 lbaint_t blkcnt) 381 lbaint_t blkcnt)
382 { 382 {
383 struct mmc_cmd cmd; 383 struct mmc_cmd cmd;
384 struct mmc_data data; 384 struct mmc_data data;
385 385
386 if (blkcnt > 1) 386 if (blkcnt > 1)
387 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 387 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
388 else 388 else
389 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; 389 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
390 390
391 if (mmc->high_capacity) 391 if (mmc->high_capacity)
392 cmd.cmdarg = start; 392 cmd.cmdarg = start;
393 else 393 else
394 cmd.cmdarg = start * mmc->read_bl_len; 394 cmd.cmdarg = start * mmc->read_bl_len;
395 395
396 cmd.resp_type = MMC_RSP_R1; 396 cmd.resp_type = MMC_RSP_R1;
397 397
398 data.dest = dst; 398 data.dest = dst;
399 data.blocks = blkcnt; 399 data.blocks = blkcnt;
400 data.blocksize = mmc->read_bl_len; 400 data.blocksize = mmc->read_bl_len;
401 data.flags = MMC_DATA_READ; 401 data.flags = MMC_DATA_READ;
402 402
403 if (mmc_send_cmd(mmc, &cmd, &data)) 403 if (mmc_send_cmd(mmc, &cmd, &data))
404 return 0; 404 return 0;
405 405
406 if (blkcnt > 1) { 406 if (blkcnt > 1) {
407 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 407 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
408 cmd.cmdarg = 0; 408 cmd.cmdarg = 0;
409 cmd.resp_type = MMC_RSP_R1b; 409 cmd.resp_type = MMC_RSP_R1b;
410 if (mmc_send_cmd(mmc, &cmd, NULL)) { 410 if (mmc_send_cmd(mmc, &cmd, NULL)) {
411 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 411 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
412 pr_err("mmc fail to send stop cmd\n"); 412 pr_err("mmc fail to send stop cmd\n");
413 #endif 413 #endif
414 return 0; 414 return 0;
415 } 415 }
416 } 416 }
417 417
418 return blkcnt; 418 return blkcnt;
419 } 419 }
420 420
421 #if CONFIG_IS_ENABLED(BLK) 421 #if CONFIG_IS_ENABLED(BLK)
422 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst) 422 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
423 #else 423 #else
424 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, 424 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
425 void *dst) 425 void *dst)
426 #endif 426 #endif
427 { 427 {
428 #if CONFIG_IS_ENABLED(BLK) 428 #if CONFIG_IS_ENABLED(BLK)
429 struct blk_desc *block_dev = dev_get_uclass_platdata(dev); 429 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
430 #endif 430 #endif
431 int dev_num = block_dev->devnum; 431 int dev_num = block_dev->devnum;
432 int err; 432 int err;
433 lbaint_t cur, blocks_todo = blkcnt; 433 lbaint_t cur, blocks_todo = blkcnt;
434 434
435 if (blkcnt == 0) 435 if (blkcnt == 0)
436 return 0; 436 return 0;
437 437
438 struct mmc *mmc = find_mmc_device(dev_num); 438 struct mmc *mmc = find_mmc_device(dev_num);
439 if (!mmc) 439 if (!mmc)
440 return 0; 440 return 0;
441 441
442 if (CONFIG_IS_ENABLED(MMC_TINY)) 442 if (CONFIG_IS_ENABLED(MMC_TINY))
443 err = mmc_switch_part(mmc, block_dev->hwpart); 443 err = mmc_switch_part(mmc, block_dev->hwpart);
444 else 444 else
445 err = blk_dselect_hwpart(block_dev, block_dev->hwpart); 445 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
446 446
447 if (err < 0) 447 if (err < 0)
448 return 0; 448 return 0;
449 449
450 if ((start + blkcnt) > block_dev->lba) { 450 if ((start + blkcnt) > block_dev->lba) {
451 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 451 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
452 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", 452 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
453 start + blkcnt, block_dev->lba); 453 start + blkcnt, block_dev->lba);
454 #endif 454 #endif
455 return 0; 455 return 0;
456 } 456 }
457 457
458 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { 458 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
459 pr_debug("%s: Failed to set blocklen\n", __func__); 459 pr_debug("%s: Failed to set blocklen\n", __func__);
460 return 0; 460 return 0;
461 } 461 }
462 462
463 do { 463 do {
464 cur = (blocks_todo > mmc->cfg->b_max) ? 464 cur = (blocks_todo > mmc->cfg->b_max) ?
465 mmc->cfg->b_max : blocks_todo; 465 mmc->cfg->b_max : blocks_todo;
466 if (mmc_read_blocks(mmc, dst, start, cur) != cur) { 466 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
467 pr_debug("%s: Failed to read blocks\n", __func__); 467 pr_debug("%s: Failed to read blocks\n", __func__);
468 return 0; 468 return 0;
469 } 469 }
470 blocks_todo -= cur; 470 blocks_todo -= cur;
471 start += cur; 471 start += cur;
472 dst += cur * mmc->read_bl_len; 472 dst += cur * mmc->read_bl_len;
473 } while (blocks_todo > 0); 473 } while (blocks_todo > 0);
474 474
475 return blkcnt; 475 return blkcnt;
476 } 476 }
477 477
478 static int mmc_go_idle(struct mmc *mmc) 478 static int mmc_go_idle(struct mmc *mmc)
479 { 479 {
480 struct mmc_cmd cmd; 480 struct mmc_cmd cmd;
481 int err; 481 int err;
482 482
483 udelay(1000); 483 udelay(1000);
484 484
485 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; 485 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
486 cmd.cmdarg = 0; 486 cmd.cmdarg = 0;
487 cmd.resp_type = MMC_RSP_NONE; 487 cmd.resp_type = MMC_RSP_NONE;
488 488
489 err = mmc_send_cmd(mmc, &cmd, NULL); 489 err = mmc_send_cmd(mmc, &cmd, NULL);
490 490
491 if (err) 491 if (err)
492 return err; 492 return err;
493 493
494 udelay(2000); 494 udelay(2000);
495 495
496 return 0; 496 return 0;
497 } 497 }
498 498
499 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 499 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
500 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage) 500 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
501 { 501 {
502 struct mmc_cmd cmd; 502 struct mmc_cmd cmd;
503 int err = 0; 503 int err = 0;
504 504
505 /* 505 /*
506 * Send CMD11 only if the request is to switch the card to 506 * Send CMD11 only if the request is to switch the card to
507 * 1.8V signalling. 507 * 1.8V signalling.
508 */ 508 */
509 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) 509 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
510 return mmc_set_signal_voltage(mmc, signal_voltage); 510 return mmc_set_signal_voltage(mmc, signal_voltage);
511 511
512 cmd.cmdidx = SD_CMD_SWITCH_UHS18V; 512 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
513 cmd.cmdarg = 0; 513 cmd.cmdarg = 0;
514 cmd.resp_type = MMC_RSP_R1; 514 cmd.resp_type = MMC_RSP_R1;
515 515
516 err = mmc_send_cmd(mmc, &cmd, NULL); 516 err = mmc_send_cmd(mmc, &cmd, NULL);
517 if (err) 517 if (err)
518 return err; 518 return err;
519 519
520 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR)) 520 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
521 return -EIO; 521 return -EIO;
522 522
523 /* 523 /*
524 * The card should drive cmd and dat[0:3] low immediately 524 * The card should drive cmd and dat[0:3] low immediately
525 * after the response of cmd11, but wait 100 us to be sure 525 * after the response of cmd11, but wait 100 us to be sure
526 */ 526 */
527 err = mmc_wait_dat0(mmc, 0, 100); 527 err = mmc_wait_dat0(mmc, 0, 100);
528 if (err == -ENOSYS) 528 if (err == -ENOSYS)
529 udelay(100); 529 udelay(100);
530 else if (err) 530 else if (err)
531 return -ETIMEDOUT; 531 return -ETIMEDOUT;
532 532
533 /* 533 /*
534 * During a signal voltage level switch, the clock must be gated 534 * During a signal voltage level switch, the clock must be gated
535 * for 5 ms according to the SD spec 535 * for 5 ms according to the SD spec
536 */ 536 */
537 mmc_set_clock(mmc, mmc->clock, true); 537 mmc_set_clock(mmc, mmc->clock, true);
538 538
539 err = mmc_set_signal_voltage(mmc, signal_voltage); 539 err = mmc_set_signal_voltage(mmc, signal_voltage);
540 if (err) 540 if (err)
541 return err; 541 return err;
542 542
543 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */ 543 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
544 mdelay(10); 544 mdelay(10);
545 mmc_set_clock(mmc, mmc->clock, false); 545 mmc_set_clock(mmc, mmc->clock, false);
546 546
547 /* 547 /*
548 * Failure to switch is indicated by the card holding 548 * Failure to switch is indicated by the card holding
549 * dat[0:3] low. Wait for at least 1 ms according to spec 549 * dat[0:3] low. Wait for at least 1 ms according to spec
550 */ 550 */
551 err = mmc_wait_dat0(mmc, 1, 1000); 551 err = mmc_wait_dat0(mmc, 1, 1000);
552 if (err == -ENOSYS) 552 if (err == -ENOSYS)
553 udelay(1000); 553 udelay(1000);
554 else if (err) 554 else if (err)
555 return -ETIMEDOUT; 555 return -ETIMEDOUT;
556 556
557 return 0; 557 return 0;
558 } 558 }
559 #endif 559 #endif
560 560
561 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en) 561 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
562 { 562 {
563 int timeout = 1000; 563 int timeout = 1000;
564 int err; 564 int err;
565 struct mmc_cmd cmd; 565 struct mmc_cmd cmd;
566 566
567 while (1) { 567 while (1) {
568 cmd.cmdidx = MMC_CMD_APP_CMD; 568 cmd.cmdidx = MMC_CMD_APP_CMD;
569 cmd.resp_type = MMC_RSP_R1; 569 cmd.resp_type = MMC_RSP_R1;
570 cmd.cmdarg = 0; 570 cmd.cmdarg = 0;
571 571
572 err = mmc_send_cmd(mmc, &cmd, NULL); 572 err = mmc_send_cmd(mmc, &cmd, NULL);
573 573
574 if (err) 574 if (err)
575 return err; 575 return err;
576 576
577 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; 577 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
578 cmd.resp_type = MMC_RSP_R3; 578 cmd.resp_type = MMC_RSP_R3;
579 579
580 /* 580 /*
581 * Most cards do not answer if some reserved bits 581 * Most cards do not answer if some reserved bits
582 * in the ocr are set. However, Some controller 582 * in the ocr are set. However, Some controller
583 * can set bit 7 (reserved for low voltages), but 583 * can set bit 7 (reserved for low voltages), but
584 * how to manage low voltages SD card is not yet 584 * how to manage low voltages SD card is not yet
585 * specified. 585 * specified.
586 */ 586 */
587 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : 587 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
588 (mmc->cfg->voltages & 0xff8000); 588 (mmc->cfg->voltages & 0xff8000);
589 589
590 if (mmc->version == SD_VERSION_2) 590 if (mmc->version == SD_VERSION_2)
591 cmd.cmdarg |= OCR_HCS; 591 cmd.cmdarg |= OCR_HCS;
592 592
593 if (uhs_en) 593 if (uhs_en)
594 cmd.cmdarg |= OCR_S18R; 594 cmd.cmdarg |= OCR_S18R;
595 595
596 err = mmc_send_cmd(mmc, &cmd, NULL); 596 err = mmc_send_cmd(mmc, &cmd, NULL);
597 597
598 if (err) 598 if (err)
599 return err; 599 return err;
600 600
601 if (cmd.response[0] & OCR_BUSY) 601 if (cmd.response[0] & OCR_BUSY)
602 break; 602 break;
603 603
604 if (timeout-- <= 0) 604 if (timeout-- <= 0)
605 return -EOPNOTSUPP; 605 return -EOPNOTSUPP;
606 606
607 udelay(1000); 607 udelay(1000);
608 } 608 }
609 609
610 if (mmc->version != SD_VERSION_2) 610 if (mmc->version != SD_VERSION_2)
611 mmc->version = SD_VERSION_1_0; 611 mmc->version = SD_VERSION_1_0;
612 612
613 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 613 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
614 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 614 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
615 cmd.resp_type = MMC_RSP_R3; 615 cmd.resp_type = MMC_RSP_R3;
616 cmd.cmdarg = 0; 616 cmd.cmdarg = 0;
617 617
618 err = mmc_send_cmd(mmc, &cmd, NULL); 618 err = mmc_send_cmd(mmc, &cmd, NULL);
619 619
620 if (err) 620 if (err)
621 return err; 621 return err;
622 } 622 }
623 623
624 mmc->ocr = cmd.response[0]; 624 mmc->ocr = cmd.response[0];
625 625
626 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 626 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
627 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000) 627 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
628 == 0x41000000) { 628 == 0x41000000) {
629 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180); 629 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
630 if (err) 630 if (err)
631 return err; 631 return err;
632 } 632 }
633 #endif 633 #endif
634 634
635 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 635 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
636 mmc->rca = 0; 636 mmc->rca = 0;
637 637
638 return 0; 638 return 0;
639 } 639 }
640 640
641 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) 641 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
642 { 642 {
643 struct mmc_cmd cmd; 643 struct mmc_cmd cmd;
644 int err; 644 int err;
645 645
646 cmd.cmdidx = MMC_CMD_SEND_OP_COND; 646 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
647 cmd.resp_type = MMC_RSP_R3; 647 cmd.resp_type = MMC_RSP_R3;
648 cmd.cmdarg = 0; 648 cmd.cmdarg = 0;
649 if (use_arg && !mmc_host_is_spi(mmc)) 649 if (use_arg && !mmc_host_is_spi(mmc))
650 cmd.cmdarg = OCR_HCS | 650 cmd.cmdarg = OCR_HCS |
651 (mmc->cfg->voltages & 651 (mmc->cfg->voltages &
652 (mmc->ocr & OCR_VOLTAGE_MASK)) | 652 (mmc->ocr & OCR_VOLTAGE_MASK)) |
653 (mmc->ocr & OCR_ACCESS_MODE); 653 (mmc->ocr & OCR_ACCESS_MODE);
654 654
655 err = mmc_send_cmd(mmc, &cmd, NULL); 655 err = mmc_send_cmd(mmc, &cmd, NULL);
656 if (err) 656 if (err)
657 return err; 657 return err;
658 mmc->ocr = cmd.response[0]; 658 mmc->ocr = cmd.response[0];
659 return 0; 659 return 0;
660 } 660 }
661 661
662 static int mmc_send_op_cond(struct mmc *mmc) 662 static int mmc_send_op_cond(struct mmc *mmc)
663 { 663 {
664 int err, i; 664 int err, i;
665 665
666 /* Some cards seem to need this */ 666 /* Some cards seem to need this */
667 mmc_go_idle(mmc); 667 mmc_go_idle(mmc);
668 668
669 /* Asking to the card its capabilities */ 669 /* Asking to the card its capabilities */
670 for (i = 0; i < 2; i++) { 670 for (i = 0; i < 2; i++) {
671 err = mmc_send_op_cond_iter(mmc, i != 0); 671 err = mmc_send_op_cond_iter(mmc, i != 0);
672 if (err) 672 if (err)
673 return err; 673 return err;
674 674
675 /* exit if not busy (flag seems to be inverted) */ 675 /* exit if not busy (flag seems to be inverted) */
676 if (mmc->ocr & OCR_BUSY) 676 if (mmc->ocr & OCR_BUSY)
677 break; 677 break;
678 } 678 }
679 mmc->op_cond_pending = 1; 679 mmc->op_cond_pending = 1;
680 return 0; 680 return 0;
681 } 681 }
682 682
683 static int mmc_complete_op_cond(struct mmc *mmc) 683 static int mmc_complete_op_cond(struct mmc *mmc)
684 { 684 {
685 struct mmc_cmd cmd; 685 struct mmc_cmd cmd;
686 int timeout = 1000; 686 int timeout = 1000;
687 uint start; 687 uint start;
688 int err; 688 int err;
689 689
690 mmc->op_cond_pending = 0; 690 mmc->op_cond_pending = 0;
691 if (!(mmc->ocr & OCR_BUSY)) { 691 if (!(mmc->ocr & OCR_BUSY)) {
692 /* Some cards seem to need this */ 692 /* Some cards seem to need this */
693 mmc_go_idle(mmc); 693 mmc_go_idle(mmc);
694 694
695 start = get_timer(0); 695 start = get_timer(0);
696 while (1) { 696 while (1) {
697 err = mmc_send_op_cond_iter(mmc, 1); 697 err = mmc_send_op_cond_iter(mmc, 1);
698 if (err) 698 if (err)
699 return err; 699 return err;
700 if (mmc->ocr & OCR_BUSY) 700 if (mmc->ocr & OCR_BUSY)
701 break; 701 break;
702 if (get_timer(start) > timeout) 702 if (get_timer(start) > timeout)
703 return -EOPNOTSUPP; 703 return -EOPNOTSUPP;
704 udelay(100); 704 udelay(100);
705 } 705 }
706 } 706 }
707 707
708 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 708 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
709 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 709 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
710 cmd.resp_type = MMC_RSP_R3; 710 cmd.resp_type = MMC_RSP_R3;
711 cmd.cmdarg = 0; 711 cmd.cmdarg = 0;
712 712
713 err = mmc_send_cmd(mmc, &cmd, NULL); 713 err = mmc_send_cmd(mmc, &cmd, NULL);
714 714
715 if (err) 715 if (err)
716 return err; 716 return err;
717 717
718 mmc->ocr = cmd.response[0]; 718 mmc->ocr = cmd.response[0];
719 } 719 }
720 720
721 mmc->version = MMC_VERSION_UNKNOWN; 721 mmc->version = MMC_VERSION_UNKNOWN;
722 722
723 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 723 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
724 mmc->rca = 1; 724 mmc->rca = 1;
725 725
726 return 0; 726 return 0;
727 } 727 }
728 728
729 729
730 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) 730 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
731 { 731 {
732 struct mmc_cmd cmd; 732 struct mmc_cmd cmd;
733 struct mmc_data data; 733 struct mmc_data data;
734 int err; 734 int err;
735 735
736 /* Get the Card Status Register */ 736 /* Get the Card Status Register */
737 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; 737 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
738 cmd.resp_type = MMC_RSP_R1; 738 cmd.resp_type = MMC_RSP_R1;
739 cmd.cmdarg = 0; 739 cmd.cmdarg = 0;
740 740
741 data.dest = (char *)ext_csd; 741 data.dest = (char *)ext_csd;
742 data.blocks = 1; 742 data.blocks = 1;
743 data.blocksize = MMC_MAX_BLOCK_LEN; 743 data.blocksize = MMC_MAX_BLOCK_LEN;
744 data.flags = MMC_DATA_READ; 744 data.flags = MMC_DATA_READ;
745 745
746 err = mmc_send_cmd(mmc, &cmd, &data); 746 err = mmc_send_cmd(mmc, &cmd, &data);
747 747
748 return err; 748 return err;
749 } 749 }
750 750
751 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) 751 static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
752 bool send_status)
752 { 753 {
753 struct mmc_cmd cmd; 754 struct mmc_cmd cmd;
754 int timeout = 1000; 755 int timeout = 1000;
755 int retries = 3; 756 int retries = 3;
756 int ret; 757 int ret;
757 758
758 cmd.cmdidx = MMC_CMD_SWITCH; 759 cmd.cmdidx = MMC_CMD_SWITCH;
759 cmd.resp_type = MMC_RSP_R1b; 760 cmd.resp_type = MMC_RSP_R1b;
760 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 761 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
761 (index << 16) | 762 (index << 16) |
762 (value << 8); 763 (value << 8);
763 764
764 while (retries > 0) { 765 while (retries > 0) {
765 ret = mmc_send_cmd(mmc, &cmd, NULL); 766 ret = mmc_send_cmd(mmc, &cmd, NULL);
766 767
767 /* Waiting for the ready status */ 768 if (ret) {
768 if (!ret) { 769 retries--;
769 ret = mmc_send_status(mmc, timeout); 770 continue;
770 return ret;
771 } 771 }
772 772
773 retries--; 773 if (!send_status) {
774 mdelay(50);
775 return 0;
776 }
777
778 /* Waiting for the ready status */
779 return mmc_send_status(mmc, timeout);
774 } 780 }
775 781
776 return ret; 782 return ret;
777 783
778 } 784 }
779 785
786 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
787 {
788 return __mmc_switch(mmc, set, index, value, true);
789 }
790
780 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode, 791 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
781 bool hsdowngrade) 792 bool hsdowngrade)
782 { 793 {
783 int err; 794 int err;
784 int speed_bits; 795 int speed_bits;
785 796
786 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 797 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
787 798
788 switch (mode) { 799 switch (mode) {
789 case MMC_HS: 800 case MMC_HS:
790 case MMC_HS_52: 801 case MMC_HS_52:
791 case MMC_DDR_52: 802 case MMC_DDR_52:
792 speed_bits = EXT_CSD_TIMING_HS; 803 speed_bits = EXT_CSD_TIMING_HS;
793 break; 804 break;
794 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) 805 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
795 case MMC_HS_200: 806 case MMC_HS_200:
796 speed_bits = EXT_CSD_TIMING_HS200; 807 speed_bits = EXT_CSD_TIMING_HS200;
797 break; 808 break;
798 #endif 809 #endif
799 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) 810 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
800 case MMC_HS_400: 811 case MMC_HS_400:
801 speed_bits = EXT_CSD_TIMING_HS400; 812 speed_bits = EXT_CSD_TIMING_HS400;
802 break; 813 break;
803 #endif 814 #endif
804 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) 815 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
805 case MMC_HS_400_ES: 816 case MMC_HS_400_ES:
806 speed_bits = EXT_CSD_TIMING_HS400; 817 speed_bits = EXT_CSD_TIMING_HS400;
807 break; 818 break;
808 #endif 819 #endif
809 case MMC_LEGACY: 820 case MMC_LEGACY:
810 speed_bits = EXT_CSD_TIMING_LEGACY; 821 speed_bits = EXT_CSD_TIMING_LEGACY;
811 break; 822 break;
812 default: 823 default:
813 return -EINVAL; 824 return -EINVAL;
814 } 825 }
815 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 826
816 speed_bits); 827 err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
828 speed_bits, !hsdowngrade);
817 if (err) 829 if (err)
818 return err; 830 return err;
819 831
820 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ 832 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
821 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) 833 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
822 /* 834 /*
823 * In case the eMMC is in HS200/HS400 mode and we are downgrading 835 * In case the eMMC is in HS200/HS400 mode and we are downgrading
824 * to HS mode, the card clock are still running much faster than 836 * to HS mode, the card clock are still running much faster than
825 * the supported HS mode clock, so we can not reliably read out 837 * the supported HS mode clock, so we can not reliably read out
826 * Extended CSD. Reconfigure the controller to run at HS mode. 838 * Extended CSD. Reconfigure the controller to run at HS mode.
827 */ 839 */
828 if (hsdowngrade) { 840 if (hsdowngrade) {
829 mmc_select_mode(mmc, MMC_HS); 841 mmc_select_mode(mmc, MMC_HS);
830 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false); 842 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
831 } 843 }
832 #endif 844 #endif
833 845
834 if ((mode == MMC_HS) || (mode == MMC_HS_52)) { 846 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
835 /* Now check to see that it worked */ 847 /* Now check to see that it worked */
836 err = mmc_send_ext_csd(mmc, test_csd); 848 err = mmc_send_ext_csd(mmc, test_csd);
837 if (err) 849 if (err)
838 return err; 850 return err;
839 851
840 /* No high-speed support */ 852 /* No high-speed support */
841 if (!test_csd[EXT_CSD_HS_TIMING]) 853 if (!test_csd[EXT_CSD_HS_TIMING])
842 return -ENOTSUPP; 854 return -ENOTSUPP;
843 } 855 }
844 856
845 return 0; 857 return 0;
846 } 858 }
847 859
848 static int mmc_get_capabilities(struct mmc *mmc) 860 static int mmc_get_capabilities(struct mmc *mmc)
849 { 861 {
850 u8 *ext_csd = mmc->ext_csd; 862 u8 *ext_csd = mmc->ext_csd;
851 char cardtype; 863 char cardtype;
852 864
853 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY); 865 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
854 866
855 if (mmc_host_is_spi(mmc)) 867 if (mmc_host_is_spi(mmc))
856 return 0; 868 return 0;
857 869
858 /* Only version 4 supports high-speed */ 870 /* Only version 4 supports high-speed */
859 if (mmc->version < MMC_VERSION_4) 871 if (mmc->version < MMC_VERSION_4)
860 return 0; 872 return 0;
861 873
862 if (!ext_csd) { 874 if (!ext_csd) {
863 pr_err("No ext_csd found!\n"); /* this should enver happen */ 875 pr_err("No ext_csd found!\n"); /* this should enver happen */
864 return -ENOTSUPP; 876 return -ENOTSUPP;
865 } 877 }
866 878
867 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; 879 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
868 880
869 cardtype = ext_csd[EXT_CSD_CARD_TYPE]; 881 cardtype = ext_csd[EXT_CSD_CARD_TYPE];
870 mmc->cardtype = cardtype; 882 mmc->cardtype = cardtype;
871 883
872 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) 884 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
873 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V | 885 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
874 EXT_CSD_CARD_TYPE_HS200_1_8V)) { 886 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
875 mmc->card_caps |= MMC_MODE_HS200; 887 mmc->card_caps |= MMC_MODE_HS200;
876 } 888 }
877 #endif 889 #endif
878 #if (CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)) 890 #if (CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT))
879 if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V | 891 if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
880 EXT_CSD_CARD_TYPE_HS400_1_8V)) { 892 EXT_CSD_CARD_TYPE_HS400_1_8V)) {
881 mmc->card_caps |= MMC_MODE_HS400; 893 mmc->card_caps |= MMC_MODE_HS400;
882 } 894 }
883 #endif 895 #endif
884 if (cardtype & EXT_CSD_CARD_TYPE_52) { 896 if (cardtype & EXT_CSD_CARD_TYPE_52) {
885 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52) 897 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
886 mmc->card_caps |= MMC_MODE_DDR_52MHz; 898 mmc->card_caps |= MMC_MODE_DDR_52MHz;
887 mmc->card_caps |= MMC_MODE_HS_52MHz; 899 mmc->card_caps |= MMC_MODE_HS_52MHz;
888 } 900 }
889 if (cardtype & EXT_CSD_CARD_TYPE_26) 901 if (cardtype & EXT_CSD_CARD_TYPE_26)
890 mmc->card_caps |= MMC_MODE_HS; 902 mmc->card_caps |= MMC_MODE_HS;
891 903
892 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) 904 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
893 if (ext_csd[EXT_CSD_STROBE_SUPPORT] && (mmc->card_caps & MMC_MODE_HS400)) 905 if (ext_csd[EXT_CSD_STROBE_SUPPORT] && (mmc->card_caps & MMC_MODE_HS400))
894 mmc->card_caps |= MMC_MODE_HS400_ES; 906 mmc->card_caps |= MMC_MODE_HS400_ES;
895 #endif 907 #endif
896 908
897 return 0; 909 return 0;
898 } 910 }
899 911
900 static int mmc_set_capacity(struct mmc *mmc, int part_num) 912 static int mmc_set_capacity(struct mmc *mmc, int part_num)
901 { 913 {
902 switch (part_num) { 914 switch (part_num) {
903 case 0: 915 case 0:
904 mmc->capacity = mmc->capacity_user; 916 mmc->capacity = mmc->capacity_user;
905 break; 917 break;
906 case 1: 918 case 1:
907 case 2: 919 case 2:
908 mmc->capacity = mmc->capacity_boot; 920 mmc->capacity = mmc->capacity_boot;
909 break; 921 break;
910 case 3: 922 case 3:
911 mmc->capacity = mmc->capacity_rpmb; 923 mmc->capacity = mmc->capacity_rpmb;
912 break; 924 break;
913 case 4: 925 case 4:
914 case 5: 926 case 5:
915 case 6: 927 case 6:
916 case 7: 928 case 7:
917 mmc->capacity = mmc->capacity_gp[part_num - 4]; 929 mmc->capacity = mmc->capacity_gp[part_num - 4];
918 break; 930 break;
919 default: 931 default:
920 return -1; 932 return -1;
921 } 933 }
922 934
923 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len); 935 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
924 936
925 return 0; 937 return 0;
926 } 938 }
927 939
928 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) 940 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
929 static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num) 941 static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
930 { 942 {
931 int forbidden = 0; 943 int forbidden = 0;
932 bool change = false; 944 bool change = false;
933 945
934 if (part_num & PART_ACCESS_MASK) 946 if (part_num & PART_ACCESS_MASK)
935 forbidden = MMC_CAP(MMC_HS_200); 947 forbidden = MMC_CAP(MMC_HS_200);
936 948
937 if (MMC_CAP(mmc->selected_mode) & forbidden) { 949 if (MMC_CAP(mmc->selected_mode) & forbidden) {
938 pr_debug("selected mode (%s) is forbidden for part %d\n", 950 pr_debug("selected mode (%s) is forbidden for part %d\n",
939 mmc_mode_name(mmc->selected_mode), part_num); 951 mmc_mode_name(mmc->selected_mode), part_num);
940 change = true; 952 change = true;
941 } else if (mmc->selected_mode != mmc->best_mode) { 953 } else if (mmc->selected_mode != mmc->best_mode) {
942 pr_debug("selected mode is not optimal\n"); 954 pr_debug("selected mode is not optimal\n");
943 change = true; 955 change = true;
944 } 956 }
945 957
946 if (change) 958 if (change)
947 return mmc_select_mode_and_width(mmc, 959 return mmc_select_mode_and_width(mmc,
948 mmc->card_caps & ~forbidden); 960 mmc->card_caps & ~forbidden);
949 961
950 return 0; 962 return 0;
951 } 963 }
952 #else 964 #else
953 static inline int mmc_boot_part_access_chk(struct mmc *mmc, 965 static inline int mmc_boot_part_access_chk(struct mmc *mmc,
954 unsigned int part_num) 966 unsigned int part_num)
955 { 967 {
956 return 0; 968 return 0;
957 } 969 }
958 #endif 970 #endif
959 971
960 int mmc_switch_part(struct mmc *mmc, unsigned int part_num) 972 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
961 { 973 {
962 int ret; 974 int ret;
963 975
964 ret = mmc_boot_part_access_chk(mmc, part_num); 976 ret = mmc_boot_part_access_chk(mmc, part_num);
965 if (ret) 977 if (ret)
966 return ret; 978 return ret;
967 979
968 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 980 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
969 (mmc->part_config & ~PART_ACCESS_MASK) 981 (mmc->part_config & ~PART_ACCESS_MASK)
970 | (part_num & PART_ACCESS_MASK)); 982 | (part_num & PART_ACCESS_MASK));
971 983
972 /* 984 /*
973 * Set the capacity if the switch succeeded or was intended 985 * Set the capacity if the switch succeeded or was intended
974 * to return to representing the raw device. 986 * to return to representing the raw device.
975 */ 987 */
976 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { 988 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
977 ret = mmc_set_capacity(mmc, part_num); 989 ret = mmc_set_capacity(mmc, part_num);
978 mmc_get_blk_desc(mmc)->hwpart = part_num; 990 mmc_get_blk_desc(mmc)->hwpart = part_num;
979 } 991 }
980 992
981 return ret; 993 return ret;
982 } 994 }
983 995
984 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) 996 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
985 int mmc_hwpart_config(struct mmc *mmc, 997 int mmc_hwpart_config(struct mmc *mmc,
986 const struct mmc_hwpart_conf *conf, 998 const struct mmc_hwpart_conf *conf,
987 enum mmc_hwpart_conf_mode mode) 999 enum mmc_hwpart_conf_mode mode)
988 { 1000 {
989 u8 part_attrs = 0; 1001 u8 part_attrs = 0;
990 u32 enh_size_mult; 1002 u32 enh_size_mult;
991 u32 enh_start_addr; 1003 u32 enh_start_addr;
992 u32 gp_size_mult[4]; 1004 u32 gp_size_mult[4];
993 u32 max_enh_size_mult; 1005 u32 max_enh_size_mult;
994 u32 tot_enh_size_mult = 0; 1006 u32 tot_enh_size_mult = 0;
995 u8 wr_rel_set; 1007 u8 wr_rel_set;
996 int i, pidx, err; 1008 int i, pidx, err;
997 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 1009 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
998 1010
999 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) 1011 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
1000 return -EINVAL; 1012 return -EINVAL;
1001 1013
1002 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { 1014 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
1003 pr_err("eMMC >= 4.4 required for enhanced user data area\n"); 1015 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
1004 return -EMEDIUMTYPE; 1016 return -EMEDIUMTYPE;
1005 } 1017 }
1006 1018
1007 if (!(mmc->part_support & PART_SUPPORT)) { 1019 if (!(mmc->part_support & PART_SUPPORT)) {
1008 pr_err("Card does not support partitioning\n"); 1020 pr_err("Card does not support partitioning\n");
1009 return -EMEDIUMTYPE; 1021 return -EMEDIUMTYPE;
1010 } 1022 }
1011 1023
1012 if (!mmc->hc_wp_grp_size) { 1024 if (!mmc->hc_wp_grp_size) {
1013 pr_err("Card does not define HC WP group size\n"); 1025 pr_err("Card does not define HC WP group size\n");
1014 return -EMEDIUMTYPE; 1026 return -EMEDIUMTYPE;
1015 } 1027 }
1016 1028
1017 /* check partition alignment and total enhanced size */ 1029 /* check partition alignment and total enhanced size */
1018 if (conf->user.enh_size) { 1030 if (conf->user.enh_size) {
1019 if (conf->user.enh_size % mmc->hc_wp_grp_size || 1031 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1020 conf->user.enh_start % mmc->hc_wp_grp_size) { 1032 conf->user.enh_start % mmc->hc_wp_grp_size) {
1021 pr_err("User data enhanced area not HC WP group " 1033 pr_err("User data enhanced area not HC WP group "
1022 "size aligned\n"); 1034 "size aligned\n");
1023 return -EINVAL; 1035 return -EINVAL;
1024 } 1036 }
1025 part_attrs |= EXT_CSD_ENH_USR; 1037 part_attrs |= EXT_CSD_ENH_USR;
1026 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; 1038 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1027 if (mmc->high_capacity) { 1039 if (mmc->high_capacity) {
1028 enh_start_addr = conf->user.enh_start; 1040 enh_start_addr = conf->user.enh_start;
1029 } else { 1041 } else {
1030 enh_start_addr = (conf->user.enh_start << 9); 1042 enh_start_addr = (conf->user.enh_start << 9);
1031 } 1043 }
1032 } else { 1044 } else {
1033 enh_size_mult = 0; 1045 enh_size_mult = 0;
1034 enh_start_addr = 0; 1046 enh_start_addr = 0;
1035 } 1047 }
1036 tot_enh_size_mult += enh_size_mult; 1048 tot_enh_size_mult += enh_size_mult;
1037 1049
1038 for (pidx = 0; pidx < 4; pidx++) { 1050 for (pidx = 0; pidx < 4; pidx++) {
1039 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { 1051 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
1040 pr_err("GP%i partition not HC WP group size " 1052 pr_err("GP%i partition not HC WP group size "
1041 "aligned\n", pidx+1); 1053 "aligned\n", pidx+1);
1042 return -EINVAL; 1054 return -EINVAL;
1043 } 1055 }
1044 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; 1056 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1045 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { 1057 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1046 part_attrs |= EXT_CSD_ENH_GP(pidx); 1058 part_attrs |= EXT_CSD_ENH_GP(pidx);
1047 tot_enh_size_mult += gp_size_mult[pidx]; 1059 tot_enh_size_mult += gp_size_mult[pidx];
1048 } 1060 }
1049 } 1061 }
1050 1062
1051 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { 1063 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
1052 pr_err("Card does not support enhanced attribute\n"); 1064 pr_err("Card does not support enhanced attribute\n");
1053 return -EMEDIUMTYPE; 1065 return -EMEDIUMTYPE;
1054 } 1066 }
1055 1067
1056 err = mmc_send_ext_csd(mmc, ext_csd); 1068 err = mmc_send_ext_csd(mmc, ext_csd);
1057 if (err) 1069 if (err)
1058 return err; 1070 return err;
1059 1071
1060 max_enh_size_mult = 1072 max_enh_size_mult =
1061 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + 1073 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1062 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + 1074 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1063 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; 1075 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1064 if (tot_enh_size_mult > max_enh_size_mult) { 1076 if (tot_enh_size_mult > max_enh_size_mult) {
1065 pr_err("Total enhanced size exceeds maximum (%u > %u)\n", 1077 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
1066 tot_enh_size_mult, max_enh_size_mult); 1078 tot_enh_size_mult, max_enh_size_mult);
1067 return -EMEDIUMTYPE; 1079 return -EMEDIUMTYPE;
1068 } 1080 }
1069 1081
1070 /* The default value of EXT_CSD_WR_REL_SET is device 1082 /* The default value of EXT_CSD_WR_REL_SET is device
1071 * dependent, the values can only be changed if the 1083 * dependent, the values can only be changed if the
1072 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 1084 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1073 * changed only once and before partitioning is completed. */ 1085 * changed only once and before partitioning is completed. */
1074 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1086 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1075 if (conf->user.wr_rel_change) { 1087 if (conf->user.wr_rel_change) {
1076 if (conf->user.wr_rel_set) 1088 if (conf->user.wr_rel_set)
1077 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; 1089 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1078 else 1090 else
1079 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; 1091 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1080 } 1092 }
1081 for (pidx = 0; pidx < 4; pidx++) { 1093 for (pidx = 0; pidx < 4; pidx++) {
1082 if (conf->gp_part[pidx].wr_rel_change) { 1094 if (conf->gp_part[pidx].wr_rel_change) {
1083 if (conf->gp_part[pidx].wr_rel_set) 1095 if (conf->gp_part[pidx].wr_rel_set)
1084 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); 1096 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1085 else 1097 else
1086 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); 1098 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1087 } 1099 }
1088 } 1100 }
1089 1101
1090 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && 1102 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1091 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { 1103 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1092 puts("Card does not support host controlled partition write " 1104 puts("Card does not support host controlled partition write "
1093 "reliability settings\n"); 1105 "reliability settings\n");
1094 return -EMEDIUMTYPE; 1106 return -EMEDIUMTYPE;
1095 } 1107 }
1096 1108
1097 if (ext_csd[EXT_CSD_PARTITION_SETTING] & 1109 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1098 EXT_CSD_PARTITION_SETTING_COMPLETED) { 1110 EXT_CSD_PARTITION_SETTING_COMPLETED) {
1099 pr_err("Card already partitioned\n"); 1111 pr_err("Card already partitioned\n");
1100 return -EPERM; 1112 return -EPERM;
1101 } 1113 }
1102 1114
1103 if (mode == MMC_HWPART_CONF_CHECK) 1115 if (mode == MMC_HWPART_CONF_CHECK)
1104 return 0; 1116 return 0;
1105 1117
1106 /* Partitioning requires high-capacity size definitions */ 1118 /* Partitioning requires high-capacity size definitions */
1107 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { 1119 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1108 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1120 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1109 EXT_CSD_ERASE_GROUP_DEF, 1); 1121 EXT_CSD_ERASE_GROUP_DEF, 1);
1110 1122
1111 if (err) 1123 if (err)
1112 return err; 1124 return err;
1113 1125
1114 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1126 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1115 1127
1116 /* update erase group size to be high-capacity */ 1128 /* update erase group size to be high-capacity */
1117 mmc->erase_grp_size = 1129 mmc->erase_grp_size =
1118 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1130 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1119 1131
1120 } 1132 }
1121 1133
1122 /* all OK, write the configuration */ 1134 /* all OK, write the configuration */
1123 for (i = 0; i < 4; i++) { 1135 for (i = 0; i < 4; i++) {
1124 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1136 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1125 EXT_CSD_ENH_START_ADDR+i, 1137 EXT_CSD_ENH_START_ADDR+i,
1126 (enh_start_addr >> (i*8)) & 0xFF); 1138 (enh_start_addr >> (i*8)) & 0xFF);
1127 if (err) 1139 if (err)
1128 return err; 1140 return err;
1129 } 1141 }
1130 for (i = 0; i < 3; i++) { 1142 for (i = 0; i < 3; i++) {
1131 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1143 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1132 EXT_CSD_ENH_SIZE_MULT+i, 1144 EXT_CSD_ENH_SIZE_MULT+i,
1133 (enh_size_mult >> (i*8)) & 0xFF); 1145 (enh_size_mult >> (i*8)) & 0xFF);
1134 if (err) 1146 if (err)
1135 return err; 1147 return err;
1136 } 1148 }
1137 for (pidx = 0; pidx < 4; pidx++) { 1149 for (pidx = 0; pidx < 4; pidx++) {
1138 for (i = 0; i < 3; i++) { 1150 for (i = 0; i < 3; i++) {
1139 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1151 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1140 EXT_CSD_GP_SIZE_MULT+pidx*3+i, 1152 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1141 (gp_size_mult[pidx] >> (i*8)) & 0xFF); 1153 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1142 if (err) 1154 if (err)
1143 return err; 1155 return err;
1144 } 1156 }
1145 } 1157 }
1146 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1158 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1147 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); 1159 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1148 if (err) 1160 if (err)
1149 return err; 1161 return err;
1150 1162
1151 if (mode == MMC_HWPART_CONF_SET) 1163 if (mode == MMC_HWPART_CONF_SET)
1152 return 0; 1164 return 0;
1153 1165
1154 /* The WR_REL_SET is a write-once register but shall be 1166 /* The WR_REL_SET is a write-once register but shall be
1155 * written before setting PART_SETTING_COMPLETED. As it is 1167 * written before setting PART_SETTING_COMPLETED. As it is
1156 * write-once we can only write it when completing the 1168 * write-once we can only write it when completing the
1157 * partitioning. */ 1169 * partitioning. */
1158 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { 1170 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1159 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1171 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1160 EXT_CSD_WR_REL_SET, wr_rel_set); 1172 EXT_CSD_WR_REL_SET, wr_rel_set);
1161 if (err) 1173 if (err)
1162 return err; 1174 return err;
1163 } 1175 }
1164 1176
1165 /* Setting PART_SETTING_COMPLETED confirms the partition 1177 /* Setting PART_SETTING_COMPLETED confirms the partition
1166 * configuration but it only becomes effective after power 1178 * configuration but it only becomes effective after power
1167 * cycle, so we do not adjust the partition related settings 1179 * cycle, so we do not adjust the partition related settings
1168 * in the mmc struct. */ 1180 * in the mmc struct. */
1169 1181
1170 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1182 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1171 EXT_CSD_PARTITION_SETTING, 1183 EXT_CSD_PARTITION_SETTING,
1172 EXT_CSD_PARTITION_SETTING_COMPLETED); 1184 EXT_CSD_PARTITION_SETTING_COMPLETED);
1173 if (err) 1185 if (err)
1174 return err; 1186 return err;
1175 1187
1176 return 0; 1188 return 0;
1177 } 1189 }
1178 #endif 1190 #endif
1179 1191
1180 #if !CONFIG_IS_ENABLED(DM_MMC) 1192 #if !CONFIG_IS_ENABLED(DM_MMC)
1181 int mmc_getcd(struct mmc *mmc) 1193 int mmc_getcd(struct mmc *mmc)
1182 { 1194 {
1183 int cd; 1195 int cd;
1184 1196
1185 cd = board_mmc_getcd(mmc); 1197 cd = board_mmc_getcd(mmc);
1186 1198
1187 if (cd < 0) { 1199 if (cd < 0) {
1188 if (mmc->cfg->ops->getcd) 1200 if (mmc->cfg->ops->getcd)
1189 cd = mmc->cfg->ops->getcd(mmc); 1201 cd = mmc->cfg->ops->getcd(mmc);
1190 else 1202 else
1191 cd = 1; 1203 cd = 1;
1192 } 1204 }
1193 1205
1194 return cd; 1206 return cd;
1195 } 1207 }
1196 #endif 1208 #endif
1197 1209
1198 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) 1210 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1199 { 1211 {
1200 struct mmc_cmd cmd; 1212 struct mmc_cmd cmd;
1201 struct mmc_data data; 1213 struct mmc_data data;
1202 1214
1203 /* Switch the frequency */ 1215 /* Switch the frequency */
1204 cmd.cmdidx = SD_CMD_SWITCH_FUNC; 1216 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1205 cmd.resp_type = MMC_RSP_R1; 1217 cmd.resp_type = MMC_RSP_R1;
1206 cmd.cmdarg = (mode << 31) | 0xffffff; 1218 cmd.cmdarg = (mode << 31) | 0xffffff;
1207 cmd.cmdarg &= ~(0xf << (group * 4)); 1219 cmd.cmdarg &= ~(0xf << (group * 4));
1208 cmd.cmdarg |= value << (group * 4); 1220 cmd.cmdarg |= value << (group * 4);
1209 1221
1210 data.dest = (char *)resp; 1222 data.dest = (char *)resp;
1211 data.blocksize = 64; 1223 data.blocksize = 64;
1212 data.blocks = 1; 1224 data.blocks = 1;
1213 data.flags = MMC_DATA_READ; 1225 data.flags = MMC_DATA_READ;
1214 1226
1215 return mmc_send_cmd(mmc, &cmd, &data); 1227 return mmc_send_cmd(mmc, &cmd, &data);
1216 } 1228 }
1217 1229
1218 1230
1219 static int sd_get_capabilities(struct mmc *mmc) 1231 static int sd_get_capabilities(struct mmc *mmc)
1220 { 1232 {
1221 int err; 1233 int err;
1222 struct mmc_cmd cmd; 1234 struct mmc_cmd cmd;
1223 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2); 1235 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1224 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16); 1236 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
1225 struct mmc_data data; 1237 struct mmc_data data;
1226 int timeout; 1238 int timeout;
1227 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 1239 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1228 u32 sd3_bus_mode; 1240 u32 sd3_bus_mode;
1229 #endif 1241 #endif
1230 1242
1231 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY); 1243 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
1232 1244
1233 if (mmc_host_is_spi(mmc)) 1245 if (mmc_host_is_spi(mmc))
1234 return 0; 1246 return 0;
1235 1247
1236 /* Read the SCR to find out if this card supports higher speeds */ 1248 /* Read the SCR to find out if this card supports higher speeds */
1237 cmd.cmdidx = MMC_CMD_APP_CMD; 1249 cmd.cmdidx = MMC_CMD_APP_CMD;
1238 cmd.resp_type = MMC_RSP_R1; 1250 cmd.resp_type = MMC_RSP_R1;
1239 cmd.cmdarg = mmc->rca << 16; 1251 cmd.cmdarg = mmc->rca << 16;
1240 1252
1241 err = mmc_send_cmd(mmc, &cmd, NULL); 1253 err = mmc_send_cmd(mmc, &cmd, NULL);
1242 1254
1243 if (err) 1255 if (err)
1244 return err; 1256 return err;
1245 1257
1246 cmd.cmdidx = SD_CMD_APP_SEND_SCR; 1258 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1247 cmd.resp_type = MMC_RSP_R1; 1259 cmd.resp_type = MMC_RSP_R1;
1248 cmd.cmdarg = 0; 1260 cmd.cmdarg = 0;
1249 1261
1250 timeout = 3; 1262 timeout = 3;
1251 1263
1252 retry_scr: 1264 retry_scr:
1253 data.dest = (char *)scr; 1265 data.dest = (char *)scr;
1254 data.blocksize = 8; 1266 data.blocksize = 8;
1255 data.blocks = 1; 1267 data.blocks = 1;
1256 data.flags = MMC_DATA_READ; 1268 data.flags = MMC_DATA_READ;
1257 1269
1258 err = mmc_send_cmd(mmc, &cmd, &data); 1270 err = mmc_send_cmd(mmc, &cmd, &data);
1259 1271
1260 if (err) { 1272 if (err) {
1261 if (timeout--) 1273 if (timeout--)
1262 goto retry_scr; 1274 goto retry_scr;
1263 1275
1264 return err; 1276 return err;
1265 } 1277 }
1266 1278
1267 mmc->scr[0] = __be32_to_cpu(scr[0]); 1279 mmc->scr[0] = __be32_to_cpu(scr[0]);
1268 mmc->scr[1] = __be32_to_cpu(scr[1]); 1280 mmc->scr[1] = __be32_to_cpu(scr[1]);
1269 1281
1270 switch ((mmc->scr[0] >> 24) & 0xf) { 1282 switch ((mmc->scr[0] >> 24) & 0xf) {
1271 case 0: 1283 case 0:
1272 mmc->version = SD_VERSION_1_0; 1284 mmc->version = SD_VERSION_1_0;
1273 break; 1285 break;
1274 case 1: 1286 case 1:
1275 mmc->version = SD_VERSION_1_10; 1287 mmc->version = SD_VERSION_1_10;
1276 break; 1288 break;
1277 case 2: 1289 case 2:
1278 mmc->version = SD_VERSION_2; 1290 mmc->version = SD_VERSION_2;
1279 if ((mmc->scr[0] >> 15) & 0x1) 1291 if ((mmc->scr[0] >> 15) & 0x1)
1280 mmc->version = SD_VERSION_3; 1292 mmc->version = SD_VERSION_3;
1281 break; 1293 break;
1282 default: 1294 default:
1283 mmc->version = SD_VERSION_1_0; 1295 mmc->version = SD_VERSION_1_0;
1284 break; 1296 break;
1285 } 1297 }
1286 1298
1287 if (mmc->scr[0] & SD_DATA_4BIT) 1299 if (mmc->scr[0] & SD_DATA_4BIT)
1288 mmc->card_caps |= MMC_MODE_4BIT; 1300 mmc->card_caps |= MMC_MODE_4BIT;
1289 1301
1290 /* Version 1.0 doesn't support switching */ 1302 /* Version 1.0 doesn't support switching */
1291 if (mmc->version == SD_VERSION_1_0) 1303 if (mmc->version == SD_VERSION_1_0)
1292 return 0; 1304 return 0;
1293 1305
1294 timeout = 4; 1306 timeout = 4;
1295 while (timeout--) { 1307 while (timeout--) {
1296 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, 1308 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1297 (u8 *)switch_status); 1309 (u8 *)switch_status);
1298 1310
1299 if (err) 1311 if (err)
1300 return err; 1312 return err;
1301 1313
1302 /* The high-speed function is busy. Try again */ 1314 /* The high-speed function is busy. Try again */
1303 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) 1315 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1304 break; 1316 break;
1305 } 1317 }
1306 1318
1307 /* If high-speed isn't supported, we return */ 1319 /* If high-speed isn't supported, we return */
1308 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED) 1320 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1309 mmc->card_caps |= MMC_CAP(SD_HS); 1321 mmc->card_caps |= MMC_CAP(SD_HS);
1310 1322
1311 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 1323 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1312 /* Version before 3.0 don't support UHS modes */ 1324 /* Version before 3.0 don't support UHS modes */
1313 if (mmc->version < SD_VERSION_3) 1325 if (mmc->version < SD_VERSION_3)
1314 return 0; 1326 return 0;
1315 1327
1316 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f; 1328 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1317 if (sd3_bus_mode & SD_MODE_UHS_SDR104) 1329 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1318 mmc->card_caps |= MMC_CAP(UHS_SDR104); 1330 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1319 if (sd3_bus_mode & SD_MODE_UHS_SDR50) 1331 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1320 mmc->card_caps |= MMC_CAP(UHS_SDR50); 1332 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1321 if (sd3_bus_mode & SD_MODE_UHS_SDR25) 1333 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1322 mmc->card_caps |= MMC_CAP(UHS_SDR25); 1334 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1323 if (sd3_bus_mode & SD_MODE_UHS_SDR12) 1335 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1324 mmc->card_caps |= MMC_CAP(UHS_SDR12); 1336 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1325 if (sd3_bus_mode & SD_MODE_UHS_DDR50) 1337 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1326 mmc->card_caps |= MMC_CAP(UHS_DDR50); 1338 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1327 #endif 1339 #endif
1328 1340
1329 return 0; 1341 return 0;
1330 } 1342 }
1331 1343
1332 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode) 1344 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1333 { 1345 {
1334 int err; 1346 int err;
1335 1347
1336 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); 1348 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1337 int speed; 1349 int speed;
1338 1350
1339 switch (mode) { 1351 switch (mode) {
1340 case SD_LEGACY: 1352 case SD_LEGACY:
1341 speed = UHS_SDR12_BUS_SPEED; 1353 speed = UHS_SDR12_BUS_SPEED;
1342 break; 1354 break;
1343 case SD_HS: 1355 case SD_HS:
1344 speed = HIGH_SPEED_BUS_SPEED; 1356 speed = HIGH_SPEED_BUS_SPEED;
1345 break; 1357 break;
1346 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 1358 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1347 case UHS_SDR12: 1359 case UHS_SDR12:
1348 speed = UHS_SDR12_BUS_SPEED; 1360 speed = UHS_SDR12_BUS_SPEED;
1349 break; 1361 break;
1350 case UHS_SDR25: 1362 case UHS_SDR25:
1351 speed = UHS_SDR25_BUS_SPEED; 1363 speed = UHS_SDR25_BUS_SPEED;
1352 break; 1364 break;
1353 case UHS_SDR50: 1365 case UHS_SDR50:
1354 speed = UHS_SDR50_BUS_SPEED; 1366 speed = UHS_SDR50_BUS_SPEED;
1355 break; 1367 break;
1356 case UHS_DDR50: 1368 case UHS_DDR50:
1357 speed = UHS_DDR50_BUS_SPEED; 1369 speed = UHS_DDR50_BUS_SPEED;
1358 break; 1370 break;
1359 case UHS_SDR104: 1371 case UHS_SDR104:
1360 speed = UHS_SDR104_BUS_SPEED; 1372 speed = UHS_SDR104_BUS_SPEED;
1361 break; 1373 break;
1362 #endif 1374 #endif
1363 default: 1375 default:
1364 return -EINVAL; 1376 return -EINVAL;
1365 } 1377 }
1366 1378
1367 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status); 1379 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1368 if (err) 1380 if (err)
1369 return err; 1381 return err;
1370 1382
1371 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed) 1383 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
1372 return -ENOTSUPP; 1384 return -ENOTSUPP;
1373 1385
1374 return 0; 1386 return 0;
1375 } 1387 }
1376 1388
1377 int sd_select_bus_width(struct mmc *mmc, int w) 1389 int sd_select_bus_width(struct mmc *mmc, int w)
1378 { 1390 {
1379 int err; 1391 int err;
1380 struct mmc_cmd cmd; 1392 struct mmc_cmd cmd;
1381 1393
1382 if ((w != 4) && (w != 1)) 1394 if ((w != 4) && (w != 1))
1383 return -EINVAL; 1395 return -EINVAL;
1384 1396
1385 cmd.cmdidx = MMC_CMD_APP_CMD; 1397 cmd.cmdidx = MMC_CMD_APP_CMD;
1386 cmd.resp_type = MMC_RSP_R1; 1398 cmd.resp_type = MMC_RSP_R1;
1387 cmd.cmdarg = mmc->rca << 16; 1399 cmd.cmdarg = mmc->rca << 16;
1388 1400
1389 err = mmc_send_cmd(mmc, &cmd, NULL); 1401 err = mmc_send_cmd(mmc, &cmd, NULL);
1390 if (err) 1402 if (err)
1391 return err; 1403 return err;
1392 1404
1393 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; 1405 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1394 cmd.resp_type = MMC_RSP_R1; 1406 cmd.resp_type = MMC_RSP_R1;
1395 if (w == 4) 1407 if (w == 4)
1396 cmd.cmdarg = 2; 1408 cmd.cmdarg = 2;
1397 else if (w == 1) 1409 else if (w == 1)
1398 cmd.cmdarg = 0; 1410 cmd.cmdarg = 0;
1399 err = mmc_send_cmd(mmc, &cmd, NULL); 1411 err = mmc_send_cmd(mmc, &cmd, NULL);
1400 if (err) 1412 if (err)
1401 return err; 1413 return err;
1402 1414
1403 return 0; 1415 return 0;
1404 } 1416 }
1405 1417
1406 #if CONFIG_IS_ENABLED(MMC_WRITE) 1418 #if CONFIG_IS_ENABLED(MMC_WRITE)
1407 static int sd_read_ssr(struct mmc *mmc) 1419 static int sd_read_ssr(struct mmc *mmc)
1408 { 1420 {
1409 static const unsigned int sd_au_size[] = { 1421 static const unsigned int sd_au_size[] = {
1410 0, SZ_16K / 512, SZ_32K / 512, 1422 0, SZ_16K / 512, SZ_32K / 512,
1411 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512, 1423 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
1412 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512, 1424 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
1413 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512, 1425 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
1414 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, 1426 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1415 SZ_64M / 512, 1427 SZ_64M / 512,
1416 }; 1428 };
1417 int err, i; 1429 int err, i;
1418 struct mmc_cmd cmd; 1430 struct mmc_cmd cmd;
1419 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16); 1431 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1420 struct mmc_data data; 1432 struct mmc_data data;
1421 int timeout = 3; 1433 int timeout = 3;
1422 unsigned int au, eo, et, es; 1434 unsigned int au, eo, et, es;
1423 1435
1424 cmd.cmdidx = MMC_CMD_APP_CMD; 1436 cmd.cmdidx = MMC_CMD_APP_CMD;
1425 cmd.resp_type = MMC_RSP_R1; 1437 cmd.resp_type = MMC_RSP_R1;
1426 cmd.cmdarg = mmc->rca << 16; 1438 cmd.cmdarg = mmc->rca << 16;
1427 1439
1428 err = mmc_send_cmd(mmc, &cmd, NULL); 1440 err = mmc_send_cmd(mmc, &cmd, NULL);
1429 if (err) 1441 if (err)
1430 return err; 1442 return err;
1431 1443
1432 cmd.cmdidx = SD_CMD_APP_SD_STATUS; 1444 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1433 cmd.resp_type = MMC_RSP_R1; 1445 cmd.resp_type = MMC_RSP_R1;
1434 cmd.cmdarg = 0; 1446 cmd.cmdarg = 0;
1435 1447
1436 retry_ssr: 1448 retry_ssr:
1437 data.dest = (char *)ssr; 1449 data.dest = (char *)ssr;
1438 data.blocksize = 64; 1450 data.blocksize = 64;
1439 data.blocks = 1; 1451 data.blocks = 1;
1440 data.flags = MMC_DATA_READ; 1452 data.flags = MMC_DATA_READ;
1441 1453
1442 err = mmc_send_cmd(mmc, &cmd, &data); 1454 err = mmc_send_cmd(mmc, &cmd, &data);
1443 if (err) { 1455 if (err) {
1444 if (timeout--) 1456 if (timeout--)
1445 goto retry_ssr; 1457 goto retry_ssr;
1446 1458
1447 return err; 1459 return err;
1448 } 1460 }
1449 1461
1450 for (i = 0; i < 16; i++) 1462 for (i = 0; i < 16; i++)
1451 ssr[i] = be32_to_cpu(ssr[i]); 1463 ssr[i] = be32_to_cpu(ssr[i]);
1452 1464
1453 au = (ssr[2] >> 12) & 0xF; 1465 au = (ssr[2] >> 12) & 0xF;
1454 if ((au <= 9) || (mmc->version == SD_VERSION_3)) { 1466 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1455 mmc->ssr.au = sd_au_size[au]; 1467 mmc->ssr.au = sd_au_size[au];
1456 es = (ssr[3] >> 24) & 0xFF; 1468 es = (ssr[3] >> 24) & 0xFF;
1457 es |= (ssr[2] & 0xFF) << 8; 1469 es |= (ssr[2] & 0xFF) << 8;
1458 et = (ssr[3] >> 18) & 0x3F; 1470 et = (ssr[3] >> 18) & 0x3F;
1459 if (es && et) { 1471 if (es && et) {
1460 eo = (ssr[3] >> 16) & 0x3; 1472 eo = (ssr[3] >> 16) & 0x3;
1461 mmc->ssr.erase_timeout = (et * 1000) / es; 1473 mmc->ssr.erase_timeout = (et * 1000) / es;
1462 mmc->ssr.erase_offset = eo * 1000; 1474 mmc->ssr.erase_offset = eo * 1000;
1463 } 1475 }
1464 } else { 1476 } else {
1465 pr_debug("Invalid Allocation Unit Size.\n"); 1477 pr_debug("Invalid Allocation Unit Size.\n");
1466 } 1478 }
1467 1479
1468 return 0; 1480 return 0;
1469 } 1481 }
1470 #endif 1482 #endif
1471 /* frequency bases */ 1483 /* frequency bases */
1472 /* divided by 10 to be nice to platforms without floating point */ 1484 /* divided by 10 to be nice to platforms without floating point */
1473 static const int fbase[] = { 1485 static const int fbase[] = {
1474 10000, 1486 10000,
1475 100000, 1487 100000,
1476 1000000, 1488 1000000,
1477 10000000, 1489 10000000,
1478 }; 1490 };
1479 1491
1480 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice 1492 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1481 * to platforms without floating point. 1493 * to platforms without floating point.
1482 */ 1494 */
1483 static const u8 multipliers[] = { 1495 static const u8 multipliers[] = {
1484 0, /* reserved */ 1496 0, /* reserved */
1485 10, 1497 10,
1486 12, 1498 12,
1487 13, 1499 13,
1488 15, 1500 15,
1489 20, 1501 20,
1490 25, 1502 25,
1491 30, 1503 30,
1492 35, 1504 35,
1493 40, 1505 40,
1494 45, 1506 45,
1495 50, 1507 50,
1496 55, 1508 55,
1497 60, 1509 60,
1498 70, 1510 70,
1499 80, 1511 80,
1500 }; 1512 };
1501 1513
1502 static inline int bus_width(uint cap) 1514 static inline int bus_width(uint cap)
1503 { 1515 {
1504 if (cap == MMC_MODE_8BIT) 1516 if (cap == MMC_MODE_8BIT)
1505 return 8; 1517 return 8;
1506 if (cap == MMC_MODE_4BIT) 1518 if (cap == MMC_MODE_4BIT)
1507 return 4; 1519 return 4;
1508 if (cap == MMC_MODE_1BIT) 1520 if (cap == MMC_MODE_1BIT)
1509 return 1; 1521 return 1;
1510 pr_warn("invalid bus witdh capability 0x%x\n", cap); 1522 pr_warn("invalid bus witdh capability 0x%x\n", cap);
1511 return 0; 1523 return 0;
1512 } 1524 }
1513 1525
1514 #if !CONFIG_IS_ENABLED(DM_MMC) 1526 #if !CONFIG_IS_ENABLED(DM_MMC)
1515 #ifdef MMC_SUPPORTS_TUNING 1527 #ifdef MMC_SUPPORTS_TUNING
1516 static int mmc_execute_tuning(struct mmc *mmc, uint opcode) 1528 static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1517 { 1529 {
1518 return -ENOTSUPP; 1530 return -ENOTSUPP;
1519 } 1531 }
1520 #endif 1532 #endif
1521 1533
1522 static void mmc_send_init_stream(struct mmc *mmc) 1534 static void mmc_send_init_stream(struct mmc *mmc)
1523 { 1535 {
1524 } 1536 }
1525 1537
1526 static int mmc_set_ios(struct mmc *mmc) 1538 static int mmc_set_ios(struct mmc *mmc)
1527 { 1539 {
1528 int ret = 0; 1540 int ret = 0;
1529 1541
1530 if (mmc->cfg->ops->set_ios) 1542 if (mmc->cfg->ops->set_ios)
1531 ret = mmc->cfg->ops->set_ios(mmc); 1543 ret = mmc->cfg->ops->set_ios(mmc);
1532 1544
1533 return ret; 1545 return ret;
1534 } 1546 }
1535 #endif 1547 #endif
1536 1548
1537 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable) 1549 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
1538 { 1550 {
1539 if (!disable) { 1551 if (!disable) {
1540 if (clock > mmc->cfg->f_max) 1552 if (clock > mmc->cfg->f_max)
1541 clock = mmc->cfg->f_max; 1553 clock = mmc->cfg->f_max;
1542 1554
1543 if (clock < mmc->cfg->f_min) 1555 if (clock < mmc->cfg->f_min)
1544 clock = mmc->cfg->f_min; 1556 clock = mmc->cfg->f_min;
1545 } 1557 }
1546 1558
1547 mmc->clock = clock; 1559 mmc->clock = clock;
1548 mmc->clk_disable = disable; 1560 mmc->clk_disable = disable;
1549 1561
1550 return mmc_set_ios(mmc); 1562 return mmc_set_ios(mmc);
1551 } 1563 }
1552 1564
1553 static int mmc_set_bus_width(struct mmc *mmc, uint width) 1565 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1554 { 1566 {
1555 mmc->bus_width = width; 1567 mmc->bus_width = width;
1556 1568
1557 return mmc_set_ios(mmc); 1569 return mmc_set_ios(mmc);
1558 } 1570 }
1559 1571
1560 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) 1572 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1561 /* 1573 /*
1562 * helper function to display the capabilities in a human 1574 * helper function to display the capabilities in a human
1563 * friendly manner. The capabilities include bus width and 1575 * friendly manner. The capabilities include bus width and
1564 * supported modes. 1576 * supported modes.
1565 */ 1577 */
1566 void mmc_dump_capabilities(const char *text, uint caps) 1578 void mmc_dump_capabilities(const char *text, uint caps)
1567 { 1579 {
1568 enum bus_mode mode; 1580 enum bus_mode mode;
1569 1581
1570 pr_debug("%s: widths [", text); 1582 pr_debug("%s: widths [", text);
1571 if (caps & MMC_MODE_8BIT) 1583 if (caps & MMC_MODE_8BIT)
1572 pr_debug("8, "); 1584 pr_debug("8, ");
1573 if (caps & MMC_MODE_4BIT) 1585 if (caps & MMC_MODE_4BIT)
1574 pr_debug("4, "); 1586 pr_debug("4, ");
1575 if (caps & MMC_MODE_1BIT) 1587 if (caps & MMC_MODE_1BIT)
1576 pr_debug("1, "); 1588 pr_debug("1, ");
1577 pr_debug("\b\b] modes ["); 1589 pr_debug("\b\b] modes [");
1578 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++) 1590 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1579 if (MMC_CAP(mode) & caps) 1591 if (MMC_CAP(mode) & caps)
1580 pr_debug("%s, ", mmc_mode_name(mode)); 1592 pr_debug("%s, ", mmc_mode_name(mode));
1581 pr_debug("\b\b]\n"); 1593 pr_debug("\b\b]\n");
1582 } 1594 }
1583 #endif 1595 #endif
1584 1596
1585 struct mode_width_tuning { 1597 struct mode_width_tuning {
1586 enum bus_mode mode; 1598 enum bus_mode mode;
1587 uint widths; 1599 uint widths;
1588 #ifdef MMC_SUPPORTS_TUNING 1600 #ifdef MMC_SUPPORTS_TUNING
1589 uint tuning; 1601 uint tuning;
1590 #endif 1602 #endif
1591 }; 1603 };
1592 1604
1593 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE) 1605 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1594 int mmc_voltage_to_mv(enum mmc_voltage voltage) 1606 int mmc_voltage_to_mv(enum mmc_voltage voltage)
1595 { 1607 {
1596 switch (voltage) { 1608 switch (voltage) {
1597 case MMC_SIGNAL_VOLTAGE_000: return 0; 1609 case MMC_SIGNAL_VOLTAGE_000: return 0;
1598 case MMC_SIGNAL_VOLTAGE_330: return 3300; 1610 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1599 case MMC_SIGNAL_VOLTAGE_180: return 1800; 1611 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1600 case MMC_SIGNAL_VOLTAGE_120: return 1200; 1612 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1601 } 1613 }
1602 return -EINVAL; 1614 return -EINVAL;
1603 } 1615 }
1604 1616
1605 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage) 1617 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1606 { 1618 {
1607 int err; 1619 int err;
1608 1620
1609 if (mmc->signal_voltage == signal_voltage) 1621 if (mmc->signal_voltage == signal_voltage)
1610 return 0; 1622 return 0;
1611 1623
1612 mmc->signal_voltage = signal_voltage; 1624 mmc->signal_voltage = signal_voltage;
1613 err = mmc_set_ios(mmc); 1625 err = mmc_set_ios(mmc);
1614 if (err) 1626 if (err)
1615 pr_debug("unable to set voltage (err %d)\n", err); 1627 pr_debug("unable to set voltage (err %d)\n", err);
1616 1628
1617 return err; 1629 return err;
1618 } 1630 }
1619 #else 1631 #else
1620 static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage) 1632 static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1621 { 1633 {
1622 return 0; 1634 return 0;
1623 } 1635 }
1624 #endif 1636 #endif
1625 1637
1626 static const struct mode_width_tuning sd_modes_by_pref[] = { 1638 static const struct mode_width_tuning sd_modes_by_pref[] = {
1627 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 1639 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1628 #ifdef MMC_SUPPORTS_TUNING 1640 #ifdef MMC_SUPPORTS_TUNING
1629 { 1641 {
1630 .mode = UHS_SDR104, 1642 .mode = UHS_SDR104,
1631 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, 1643 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1632 .tuning = MMC_CMD_SEND_TUNING_BLOCK 1644 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1633 }, 1645 },
1634 #endif 1646 #endif
1635 { 1647 {
1636 .mode = UHS_SDR50, 1648 .mode = UHS_SDR50,
1637 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, 1649 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1638 }, 1650 },
1639 { 1651 {
1640 .mode = UHS_DDR50, 1652 .mode = UHS_DDR50,
1641 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, 1653 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1642 }, 1654 },
1643 { 1655 {
1644 .mode = UHS_SDR25, 1656 .mode = UHS_SDR25,
1645 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, 1657 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1646 }, 1658 },
1647 #endif 1659 #endif
1648 { 1660 {
1649 .mode = SD_HS, 1661 .mode = SD_HS,
1650 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, 1662 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1651 }, 1663 },
1652 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 1664 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1653 { 1665 {
1654 .mode = UHS_SDR12, 1666 .mode = UHS_SDR12,
1655 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, 1667 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1656 }, 1668 },
1657 #endif 1669 #endif
1658 { 1670 {
1659 .mode = SD_LEGACY, 1671 .mode = SD_LEGACY,
1660 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, 1672 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1661 } 1673 }
1662 }; 1674 };
1663 1675
1664 #define for_each_sd_mode_by_pref(caps, mwt) \ 1676 #define for_each_sd_mode_by_pref(caps, mwt) \
1665 for (mwt = sd_modes_by_pref;\ 1677 for (mwt = sd_modes_by_pref;\
1666 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\ 1678 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1667 mwt++) \ 1679 mwt++) \
1668 if (caps & MMC_CAP(mwt->mode)) 1680 if (caps & MMC_CAP(mwt->mode))
1669 1681
1670 static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps) 1682 static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
1671 { 1683 {
1672 int err; 1684 int err;
1673 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT}; 1685 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1674 const struct mode_width_tuning *mwt; 1686 const struct mode_width_tuning *mwt;
1675 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 1687 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1676 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false; 1688 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1677 #else 1689 #else
1678 bool uhs_en = false; 1690 bool uhs_en = false;
1679 #endif 1691 #endif
1680 uint caps; 1692 uint caps;
1681 1693
1682 #ifdef DEBUG 1694 #ifdef DEBUG
1683 mmc_dump_capabilities("sd card", card_caps); 1695 mmc_dump_capabilities("sd card", card_caps);
1684 mmc_dump_capabilities("host", mmc->host_caps); 1696 mmc_dump_capabilities("host", mmc->host_caps);
1685 #endif 1697 #endif
1686 1698
1687 /* Restrict card's capabilities by what the host can do */ 1699 /* Restrict card's capabilities by what the host can do */
1688 caps = card_caps & mmc->host_caps; 1700 caps = card_caps & mmc->host_caps;
1689 1701
1690 if (!uhs_en) 1702 if (!uhs_en)
1691 caps &= ~UHS_CAPS; 1703 caps &= ~UHS_CAPS;
1692 1704
1693 for_each_sd_mode_by_pref(caps, mwt) { 1705 for_each_sd_mode_by_pref(caps, mwt) {
1694 uint *w; 1706 uint *w;
1695 1707
1696 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) { 1708 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1697 if (*w & caps & mwt->widths) { 1709 if (*w & caps & mwt->widths) {
1698 pr_debug("trying mode %s width %d (at %d MHz)\n", 1710 pr_debug("trying mode %s width %d (at %d MHz)\n",
1699 mmc_mode_name(mwt->mode), 1711 mmc_mode_name(mwt->mode),
1700 bus_width(*w), 1712 bus_width(*w),
1701 mmc_mode2freq(mmc, mwt->mode) / 1000000); 1713 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1702 1714
1703 /* configure the bus width (card + host) */ 1715 /* configure the bus width (card + host) */
1704 err = sd_select_bus_width(mmc, bus_width(*w)); 1716 err = sd_select_bus_width(mmc, bus_width(*w));
1705 if (err) 1717 if (err)
1706 goto error; 1718 goto error;
1707 mmc_set_bus_width(mmc, bus_width(*w)); 1719 mmc_set_bus_width(mmc, bus_width(*w));
1708 1720
1709 /* configure the bus mode (card) */ 1721 /* configure the bus mode (card) */
1710 err = sd_set_card_speed(mmc, mwt->mode); 1722 err = sd_set_card_speed(mmc, mwt->mode);
1711 if (err) 1723 if (err)
1712 goto error; 1724 goto error;
1713 1725
1714 /* configure the bus mode (host) */ 1726 /* configure the bus mode (host) */
1715 mmc_select_mode(mmc, mwt->mode); 1727 mmc_select_mode(mmc, mwt->mode);
1716 mmc_set_clock(mmc, mmc->tran_speed, false); 1728 mmc_set_clock(mmc, mmc->tran_speed, false);
1717 1729
1718 #ifdef MMC_SUPPORTS_TUNING 1730 #ifdef MMC_SUPPORTS_TUNING
1719 /* execute tuning if needed */ 1731 /* execute tuning if needed */
1720 if (mwt->tuning && !mmc_host_is_spi(mmc)) { 1732 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1721 err = mmc_execute_tuning(mmc, 1733 err = mmc_execute_tuning(mmc,
1722 mwt->tuning); 1734 mwt->tuning);
1723 if (err) { 1735 if (err) {
1724 pr_debug("tuning failed\n"); 1736 pr_debug("tuning failed\n");
1725 goto error; 1737 goto error;
1726 } 1738 }
1727 } 1739 }
1728 #endif 1740 #endif
1729 1741
1730 #if CONFIG_IS_ENABLED(MMC_WRITE) 1742 #if CONFIG_IS_ENABLED(MMC_WRITE)
1731 err = sd_read_ssr(mmc); 1743 err = sd_read_ssr(mmc);
1732 if (err) 1744 if (err)
1733 pr_warn("unable to read ssr\n"); 1745 pr_warn("unable to read ssr\n");
1734 #endif 1746 #endif
1735 if (!err) 1747 if (!err)
1736 return 0; 1748 return 0;
1737 1749
1738 error: 1750 error:
1739 /* revert to a safer bus speed */ 1751 /* revert to a safer bus speed */
1740 mmc_select_mode(mmc, SD_LEGACY); 1752 mmc_select_mode(mmc, SD_LEGACY);
1741 mmc_set_clock(mmc, mmc->tran_speed, false); 1753 mmc_set_clock(mmc, mmc->tran_speed, false);
1742 } 1754 }
1743 } 1755 }
1744 } 1756 }
1745 1757
1746 pr_err("unable to select a mode\n"); 1758 pr_err("unable to select a mode\n");
1747 return -ENOTSUPP; 1759 return -ENOTSUPP;
1748 } 1760 }
1749 1761
1750 /* 1762 /*
1751 * read the compare the part of ext csd that is constant. 1763 * read the compare the part of ext csd that is constant.
1752 * This can be used to check that the transfer is working 1764 * This can be used to check that the transfer is working
1753 * as expected. 1765 * as expected.
1754 */ 1766 */
1755 static int mmc_read_and_compare_ext_csd(struct mmc *mmc) 1767 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1756 { 1768 {
1757 int err; 1769 int err;
1758 const u8 *ext_csd = mmc->ext_csd; 1770 const u8 *ext_csd = mmc->ext_csd;
1759 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 1771 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1760 1772
1761 if (mmc->version < MMC_VERSION_4) 1773 if (mmc->version < MMC_VERSION_4)
1762 return 0; 1774 return 0;
1763 1775
1764 err = mmc_send_ext_csd(mmc, test_csd); 1776 err = mmc_send_ext_csd(mmc, test_csd);
1765 if (err) 1777 if (err)
1766 return err; 1778 return err;
1767 1779
1768 /* Only compare read only fields */ 1780 /* Only compare read only fields */
1769 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] 1781 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1770 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && 1782 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1771 ext_csd[EXT_CSD_HC_WP_GRP_SIZE] 1783 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1772 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && 1784 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1773 ext_csd[EXT_CSD_REV] 1785 ext_csd[EXT_CSD_REV]
1774 == test_csd[EXT_CSD_REV] && 1786 == test_csd[EXT_CSD_REV] &&
1775 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1787 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1776 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && 1788 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1777 memcmp(&ext_csd[EXT_CSD_SEC_CNT], 1789 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1778 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) 1790 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1779 return 0; 1791 return 0;
1780 1792
1781 return -EBADMSG; 1793 return -EBADMSG;
1782 } 1794 }
1783 1795
1784 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE) 1796 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1785 static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode, 1797 static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1786 uint32_t allowed_mask) 1798 uint32_t allowed_mask)
1787 { 1799 {
1788 u32 card_mask = 0; 1800 u32 card_mask = 0;
1789 1801
1790 switch (mode) { 1802 switch (mode) {
1791 case MMC_HS_400_ES: 1803 case MMC_HS_400_ES:
1792 case MMC_HS_400: 1804 case MMC_HS_400:
1793 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS400_1_8V) 1805 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS400_1_8V)
1794 card_mask |= MMC_SIGNAL_VOLTAGE_180; 1806 card_mask |= MMC_SIGNAL_VOLTAGE_180;
1795 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS400_1_2V) 1807 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS400_1_2V)
1796 card_mask |= MMC_SIGNAL_VOLTAGE_120; 1808 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1797 break; 1809 break;
1798 case MMC_HS_200: 1810 case MMC_HS_200:
1799 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V) 1811 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V)
1800 card_mask |= MMC_SIGNAL_VOLTAGE_180; 1812 card_mask |= MMC_SIGNAL_VOLTAGE_180;
1801 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V) 1813 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V)
1802 card_mask |= MMC_SIGNAL_VOLTAGE_120; 1814 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1803 break; 1815 break;
1804 case MMC_DDR_52: 1816 case MMC_DDR_52:
1805 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) 1817 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1806 card_mask |= MMC_SIGNAL_VOLTAGE_330 | 1818 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1807 MMC_SIGNAL_VOLTAGE_180; 1819 MMC_SIGNAL_VOLTAGE_180;
1808 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V) 1820 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1809 card_mask |= MMC_SIGNAL_VOLTAGE_120; 1821 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1810 break; 1822 break;
1811 default: 1823 default:
1812 card_mask |= MMC_SIGNAL_VOLTAGE_330; 1824 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1813 break; 1825 break;
1814 } 1826 }
1815 1827
1816 while (card_mask & allowed_mask) { 1828 while (card_mask & allowed_mask) {
1817 enum mmc_voltage best_match; 1829 enum mmc_voltage best_match;
1818 1830
1819 best_match = 1 << (ffs(card_mask & allowed_mask) - 1); 1831 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1820 if (!mmc_set_signal_voltage(mmc, best_match)) 1832 if (!mmc_set_signal_voltage(mmc, best_match))
1821 return 0; 1833 return 0;
1822 1834
1823 allowed_mask &= ~best_match; 1835 allowed_mask &= ~best_match;
1824 } 1836 }
1825 1837
1826 return -ENOTSUPP; 1838 return -ENOTSUPP;
1827 } 1839 }
1828 #else 1840 #else
1829 static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode, 1841 static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1830 uint32_t allowed_mask) 1842 uint32_t allowed_mask)
1831 { 1843 {
1832 return 0; 1844 return 0;
1833 } 1845 }
1834 #endif 1846 #endif
1835 1847
1836 static const struct mode_width_tuning mmc_modes_by_pref[] = { 1848 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1837 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) 1849 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1838 { 1850 {
1839 .mode = MMC_HS_400_ES, 1851 .mode = MMC_HS_400_ES,
1840 .widths = MMC_MODE_8BIT, 1852 .widths = MMC_MODE_8BIT,
1841 }, 1853 },
1842 #endif 1854 #endif
1843 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) 1855 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1844 { 1856 {
1845 .mode = MMC_HS_400, 1857 .mode = MMC_HS_400,
1846 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT, 1858 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1847 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200 1859 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1848 }, 1860 },
1849 #endif 1861 #endif
1850 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) 1862 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
1851 { 1863 {
1852 .mode = MMC_HS_200, 1864 .mode = MMC_HS_200,
1853 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT, 1865 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1854 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200 1866 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1855 }, 1867 },
1856 #endif 1868 #endif
1857 { 1869 {
1858 .mode = MMC_DDR_52, 1870 .mode = MMC_DDR_52,
1859 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT, 1871 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1860 }, 1872 },
1861 { 1873 {
1862 .mode = MMC_HS_52, 1874 .mode = MMC_HS_52,
1863 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT, 1875 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1864 }, 1876 },
1865 { 1877 {
1866 .mode = MMC_HS, 1878 .mode = MMC_HS,
1867 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT, 1879 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1868 }, 1880 },
1869 { 1881 {
1870 .mode = MMC_LEGACY, 1882 .mode = MMC_LEGACY,
1871 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT, 1883 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1872 } 1884 }
1873 }; 1885 };
1874 1886
1875 #define for_each_mmc_mode_by_pref(caps, mwt) \ 1887 #define for_each_mmc_mode_by_pref(caps, mwt) \
1876 for (mwt = mmc_modes_by_pref;\ 1888 for (mwt = mmc_modes_by_pref;\
1877 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\ 1889 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1878 mwt++) \ 1890 mwt++) \
1879 if (caps & MMC_CAP(mwt->mode)) 1891 if (caps & MMC_CAP(mwt->mode))
1880 1892
1881 static const struct ext_csd_bus_width { 1893 static const struct ext_csd_bus_width {
1882 uint cap; 1894 uint cap;
1883 bool is_ddr; 1895 bool is_ddr;
1884 uint ext_csd_bits; 1896 uint ext_csd_bits;
1885 } ext_csd_bus_width[] = { 1897 } ext_csd_bus_width[] = {
1886 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8}, 1898 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1887 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4}, 1899 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1888 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8}, 1900 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1889 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4}, 1901 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1890 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1}, 1902 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1891 }; 1903 };
1892 1904
1893 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) 1905 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1894 static int mmc_select_hs400(struct mmc *mmc) 1906 static int mmc_select_hs400(struct mmc *mmc)
1895 { 1907 {
1896 int err; 1908 int err;
1897 1909
1898 /* Set timing to HS200 for tuning */ 1910 /* Set timing to HS200 for tuning */
1899 err = mmc_set_card_speed(mmc, MMC_HS_200, false); 1911 err = mmc_set_card_speed(mmc, MMC_HS_200, false);
1900 if (err) 1912 if (err)
1901 return err; 1913 return err;
1902 1914
1903 /* configure the bus mode (host) */ 1915 /* configure the bus mode (host) */
1904 mmc_select_mode(mmc, MMC_HS_200); 1916 mmc_select_mode(mmc, MMC_HS_200);
1905 mmc_set_clock(mmc, mmc->tran_speed, false); 1917 mmc_set_clock(mmc, mmc->tran_speed, false);
1906 1918
1907 /* execute tuning if needed */ 1919 /* execute tuning if needed */
1908 err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200); 1920 err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
1909 if (err) { 1921 if (err) {
1910 debug("tuning failed\n"); 1922 debug("tuning failed\n");
1911 return err; 1923 return err;
1912 } 1924 }
1913 1925
1914 /* Set back to HS */ 1926 /* Set back to HS */
1915 mmc_set_card_speed(mmc, MMC_HS, false); 1927 mmc_set_card_speed(mmc, MMC_HS, false);
1916 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false); 1928 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
1917 1929
1918 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, 1930 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1919 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG); 1931 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
1920 if (err) 1932 if (err)
1921 return err; 1933 return err;
1922 1934
1923 err = mmc_set_card_speed(mmc, MMC_HS_400, false); 1935 err = mmc_set_card_speed(mmc, MMC_HS_400, false);
1924 if (err) 1936 if (err)
1925 return err; 1937 return err;
1926 1938
1927 mmc_select_mode(mmc, MMC_HS_400); 1939 mmc_select_mode(mmc, MMC_HS_400);
1928 err = mmc_set_clock(mmc, mmc->tran_speed, false); 1940 err = mmc_set_clock(mmc, mmc->tran_speed, false);
1929 if (err) 1941 if (err)
1930 return err; 1942 return err;
1931 1943
1932 return 0; 1944 return 0;
1933 } 1945 }
1934 #else 1946 #else
1935 static int mmc_select_hs400(struct mmc *mmc) 1947 static int mmc_select_hs400(struct mmc *mmc)
1936 { 1948 {
1937 return -ENOTSUPP; 1949 return -ENOTSUPP;
1938 } 1950 }
1939 #endif 1951 #endif
1940 1952
1941 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) 1953 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1942 #if !CONFIG_IS_ENABLED(DM_MMC) 1954 #if !CONFIG_IS_ENABLED(DM_MMC)
1943 static void mmc_set_enhanced_strobe(struct mmc *mmc) 1955 static void mmc_set_enhanced_strobe(struct mmc *mmc)
1944 { 1956 {
1945 return; 1957 return;
1946 } 1958 }
1947 #endif 1959 #endif
1948 1960
1949 static int mmc_select_hs400es(struct mmc *mmc) 1961 static int mmc_select_hs400es(struct mmc *mmc)
1950 { 1962 {
1951 int err; 1963 int err;
1952 1964
1953 err = mmc_set_card_speed(mmc, MMC_HS, false); 1965 err = mmc_set_card_speed(mmc, MMC_HS, false);
1954 if (err) 1966 if (err)
1955 return err; 1967 return err;
1956 1968
1957 /* configure the bus mode (host) */ 1969 /* configure the bus mode (host) */
1958 mmc_select_mode(mmc, MMC_HS); 1970 mmc_select_mode(mmc, MMC_HS);
1959 mmc_set_clock(mmc, mmc->tran_speed, false); 1971 mmc_set_clock(mmc, mmc->tran_speed, false);
1960 1972
1961 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1973 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1962 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8 | 1974 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8 |
1963 EXT_CSD_DDR_FLAG | EXT_CSD_BUS_WIDTH_STROBE); 1975 EXT_CSD_DDR_FLAG | EXT_CSD_BUS_WIDTH_STROBE);
1964 if (err) { 1976 if (err) {
1965 printf("switch to bus width for hs400 failed\n"); 1977 printf("switch to bus width for hs400 failed\n");
1966 return err; 1978 return err;
1967 } 1979 }
1968 /* TODO: driver strength */ 1980 /* TODO: driver strength */
1969 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1981 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1970 EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS400 | (0 << EXT_CSD_DRV_STR_SHIFT)); 1982 EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS400 | (0 << EXT_CSD_DRV_STR_SHIFT));
1971 if (err) { 1983 if (err) {
1972 printf("switch to hs400 failed\n"); 1984 printf("switch to hs400 failed\n");
1973 return err; 1985 return err;
1974 } 1986 }
1975 1987
1976 mmc_select_mode(mmc, MMC_HS_400_ES); 1988 mmc_select_mode(mmc, MMC_HS_400_ES);
1977 mmc_set_clock(mmc, mmc->tran_speed, false); 1989 mmc_set_clock(mmc, mmc->tran_speed, false);
1978 mmc_set_enhanced_strobe(mmc); 1990 mmc_set_enhanced_strobe(mmc);
1979 1991
1980 return 0; 1992 return 0;
1981 } 1993 }
1982 1994
1983 #else 1995 #else
1984 static int mmc_select_hs400es(struct mmc *mmc) 1996 static int mmc_select_hs400es(struct mmc *mmc)
1985 { 1997 {
1986 return -ENOTSUPP; 1998 return -ENOTSUPP;
1987 } 1999 }
1988 #endif 2000 #endif
1989 2001
1990 #define for_each_supported_width(caps, ddr, ecbv) \ 2002 #define for_each_supported_width(caps, ddr, ecbv) \
1991 for (ecbv = ext_csd_bus_width;\ 2003 for (ecbv = ext_csd_bus_width;\
1992 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\ 2004 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1993 ecbv++) \ 2005 ecbv++) \
1994 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap)) 2006 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1995 2007
1996 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) 2008 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
1997 { 2009 {
1998 int err; 2010 int err;
1999 const struct mode_width_tuning *mwt; 2011 const struct mode_width_tuning *mwt;
2000 const struct ext_csd_bus_width *ecbw; 2012 const struct ext_csd_bus_width *ecbw;
2001 2013
2002 #ifdef DEBUG 2014 #ifdef DEBUG
2003 mmc_dump_capabilities("mmc", card_caps); 2015 mmc_dump_capabilities("mmc", card_caps);
2004 mmc_dump_capabilities("host", mmc->host_caps); 2016 mmc_dump_capabilities("host", mmc->host_caps);
2005 #endif 2017 #endif
2006 2018
2007 /* Restrict card's capabilities by what the host can do */ 2019 /* Restrict card's capabilities by what the host can do */
2008 card_caps &= mmc->host_caps; 2020 card_caps &= mmc->host_caps;
2009 2021
2010 /* Only version 4 of MMC supports wider bus widths */ 2022 /* Only version 4 of MMC supports wider bus widths */
2011 if (mmc->version < MMC_VERSION_4) 2023 if (mmc->version < MMC_VERSION_4)
2012 return 0; 2024 return 0;
2013 2025
2014 if (!mmc->ext_csd) { 2026 if (!mmc->ext_csd) {
2015 pr_debug("No ext_csd found!\n"); /* this should enver happen */ 2027 pr_debug("No ext_csd found!\n"); /* this should enver happen */
2016 return -ENOTSUPP; 2028 return -ENOTSUPP;
2017 } 2029 }
2018 2030
2019 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ 2031 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2020 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) 2032 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2021 /* 2033 /*
2022 * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode 2034 * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
2023 * before doing anything else, since a transition from either of 2035 * before doing anything else, since a transition from either of
2024 * the HS200/HS400 mode directly to legacy mode is not supported. 2036 * the HS200/HS400 mode directly to legacy mode is not supported.
2025 */ 2037 */
2026 if (mmc->selected_mode == MMC_HS_200 || 2038 if (mmc->selected_mode == MMC_HS_200 ||
2027 mmc->selected_mode == MMC_HS_400) 2039 mmc->selected_mode == MMC_HS_400)
2028 mmc_set_card_speed(mmc, MMC_HS, true); 2040 mmc_set_card_speed(mmc, MMC_HS, true);
2029 else 2041 else
2030 #endif 2042 #endif
2031 mmc_set_clock(mmc, mmc->legacy_speed, false); 2043 mmc_set_clock(mmc, mmc->legacy_speed, false);
2032 2044
2033 for_each_mmc_mode_by_pref(card_caps, mwt) { 2045 for_each_mmc_mode_by_pref(card_caps, mwt) {
2034 for_each_supported_width(card_caps & mwt->widths, 2046 for_each_supported_width(card_caps & mwt->widths,
2035 mmc_is_mode_ddr(mwt->mode), ecbw) { 2047 mmc_is_mode_ddr(mwt->mode), ecbw) {
2036 enum mmc_voltage old_voltage; 2048 enum mmc_voltage old_voltage;
2037 pr_debug("trying mode %s width %d (at %d MHz)\n", 2049 pr_debug("trying mode %s width %d (at %d MHz)\n",
2038 mmc_mode_name(mwt->mode), 2050 mmc_mode_name(mwt->mode),
2039 bus_width(ecbw->cap), 2051 bus_width(ecbw->cap),
2040 mmc_mode2freq(mmc, mwt->mode) / 1000000); 2052 mmc_mode2freq(mmc, mwt->mode) / 1000000);
2041 old_voltage = mmc->signal_voltage; 2053 old_voltage = mmc->signal_voltage;
2042 err = mmc_set_lowest_voltage(mmc, mwt->mode, 2054 err = mmc_set_lowest_voltage(mmc, mwt->mode,
2043 MMC_ALL_SIGNAL_VOLTAGE); 2055 MMC_ALL_SIGNAL_VOLTAGE);
2044 if (err) 2056 if (err)
2045 continue; 2057 continue;
2046 2058
2047 /* configure the bus width (card + host) */ 2059 /* configure the bus width (card + host) */
2048 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 2060 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2049 EXT_CSD_BUS_WIDTH, 2061 EXT_CSD_BUS_WIDTH,
2050 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG); 2062 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
2051 if (err) 2063 if (err)
2052 goto error; 2064 goto error;
2053 mmc_set_bus_width(mmc, bus_width(ecbw->cap)); 2065 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
2054 2066
2055 if (mwt->mode == MMC_HS_400) { 2067 if (mwt->mode == MMC_HS_400) {
2056 err = mmc_select_hs400(mmc); 2068 err = mmc_select_hs400(mmc);
2057 if (err) 2069 if (err)
2058 goto error; 2070 goto error;
2059 } else if (mwt->mode == MMC_HS_400_ES) { 2071 } else if (mwt->mode == MMC_HS_400_ES) {
2060 err = mmc_select_hs400es(mmc); 2072 err = mmc_select_hs400es(mmc);
2061 if (err) 2073 if (err)
2062 goto error; 2074 goto error;
2063 } else { 2075 } else {
2064 /* configure the bus speed (card) */ 2076 /* configure the bus speed (card) */
2065 err = mmc_set_card_speed(mmc, mwt->mode, false); 2077 err = mmc_set_card_speed(mmc, mwt->mode, false);
2066 if (err) 2078 if (err)
2067 goto error; 2079 goto error;
2068 2080
2069 /* 2081 /*
2070 * configure the bus width AND the ddr mode 2082 * configure the bus width AND the ddr mode
2071 * (card). The host side will be taken care 2083 * (card). The host side will be taken care
2072 * of in the next step 2084 * of in the next step
2073 */ 2085 */
2074 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) { 2086 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2075 err = mmc_switch(mmc, 2087 err = mmc_switch(mmc,
2076 EXT_CSD_CMD_SET_NORMAL, 2088 EXT_CSD_CMD_SET_NORMAL,
2077 EXT_CSD_BUS_WIDTH, 2089 EXT_CSD_BUS_WIDTH,
2078 ecbw->ext_csd_bits); 2090 ecbw->ext_csd_bits);
2079 if (err) 2091 if (err)
2080 goto error; 2092 goto error;
2081 } 2093 }
2082 2094
2083 /* configure the bus mode (host) */ 2095 /* configure the bus mode (host) */
2084 mmc_select_mode(mmc, mwt->mode); 2096 mmc_select_mode(mmc, mwt->mode);
2085 mmc_set_clock(mmc, mmc->tran_speed, false); 2097 mmc_set_clock(mmc, mmc->tran_speed, false);
2086 #ifdef MMC_SUPPORTS_TUNING 2098 #ifdef MMC_SUPPORTS_TUNING
2087 2099
2088 /* execute tuning if needed */ 2100 /* execute tuning if needed */
2089 if (mwt->tuning) { 2101 if (mwt->tuning) {
2090 err = mmc_execute_tuning(mmc, 2102 err = mmc_execute_tuning(mmc,
2091 mwt->tuning); 2103 mwt->tuning);
2092 if (err) { 2104 if (err) {
2093 pr_debug("tuning failed\n"); 2105 pr_debug("tuning failed\n");
2094 goto error; 2106 goto error;
2095 } 2107 }
2096 } 2108 }
2097 #endif 2109 #endif
2098 } 2110 }
2099 2111
2100 /* do a transfer to check the configuration */ 2112 /* do a transfer to check the configuration */
2101 err = mmc_read_and_compare_ext_csd(mmc); 2113 err = mmc_read_and_compare_ext_csd(mmc);
2102 if (!err) 2114 if (!err)
2103 return 0; 2115 return 0;
2104 error: 2116 error:
2105 mmc_set_signal_voltage(mmc, old_voltage); 2117 mmc_set_signal_voltage(mmc, old_voltage);
2106 /* if an error occured, revert to a safer bus mode */ 2118 /* if an error occured, revert to a safer bus mode */
2107 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 2119 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2108 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1); 2120 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2109 mmc_select_mode(mmc, MMC_LEGACY); 2121 mmc_select_mode(mmc, MMC_LEGACY);
2110 mmc_set_bus_width(mmc, 1); 2122 mmc_set_bus_width(mmc, 1);
2111 } 2123 }
2112 } 2124 }
2113 2125
2114 pr_err("unable to select a mode\n"); 2126 pr_err("unable to select a mode\n");
2115 2127
2116 return -ENOTSUPP; 2128 return -ENOTSUPP;
2117 } 2129 }
2118 2130
2119 static int mmc_startup_v4(struct mmc *mmc) 2131 static int mmc_startup_v4(struct mmc *mmc)
2120 { 2132 {
2121 int err, i; 2133 int err, i;
2122 u64 capacity; 2134 u64 capacity;
2123 bool has_parts = false; 2135 bool has_parts = false;
2124 bool part_completed; 2136 bool part_completed;
2125 static const u32 mmc_versions[] = { 2137 static const u32 mmc_versions[] = {
2126 MMC_VERSION_4, 2138 MMC_VERSION_4,
2127 MMC_VERSION_4_1, 2139 MMC_VERSION_4_1,
2128 MMC_VERSION_4_2, 2140 MMC_VERSION_4_2,
2129 MMC_VERSION_4_3, 2141 MMC_VERSION_4_3,
2130 MMC_VERSION_4_4, 2142 MMC_VERSION_4_4,
2131 MMC_VERSION_4_41, 2143 MMC_VERSION_4_41,
2132 MMC_VERSION_4_5, 2144 MMC_VERSION_4_5,
2133 MMC_VERSION_5_0, 2145 MMC_VERSION_5_0,
2134 MMC_VERSION_5_1 2146 MMC_VERSION_5_1
2135 }; 2147 };
2136 2148
2137 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 2149 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2138 2150
2139 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4)) 2151 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2140 return 0; 2152 return 0;
2141 2153
2142 /* check ext_csd version and capacity */ 2154 /* check ext_csd version and capacity */
2143 err = mmc_send_ext_csd(mmc, ext_csd); 2155 err = mmc_send_ext_csd(mmc, ext_csd);
2144 if (err) 2156 if (err)
2145 goto error; 2157 goto error;
2146 2158
2147 /* store the ext csd for future reference */ 2159 /* store the ext csd for future reference */
2148 if (!mmc->ext_csd) 2160 if (!mmc->ext_csd)
2149 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN); 2161 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2150 if (!mmc->ext_csd) 2162 if (!mmc->ext_csd)
2151 return -ENOMEM; 2163 return -ENOMEM;
2152 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN); 2164 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
2153 2165
2154 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions)) 2166 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
2155 return -EINVAL; 2167 return -EINVAL;
2156 2168
2157 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]]; 2169 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2158 2170
2159 if (mmc->version >= MMC_VERSION_4_2) { 2171 if (mmc->version >= MMC_VERSION_4_2) {
2160 /* 2172 /*
2161 * According to the JEDEC Standard, the value of 2173 * According to the JEDEC Standard, the value of
2162 * ext_csd's capacity is valid if the value is more 2174 * ext_csd's capacity is valid if the value is more
2163 * than 2GB 2175 * than 2GB
2164 */ 2176 */
2165 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 2177 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2166 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 2178 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2167 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 2179 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2168 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; 2180 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2169 capacity *= MMC_MAX_BLOCK_LEN; 2181 capacity *= MMC_MAX_BLOCK_LEN;
2170 if ((capacity >> 20) > 2 * 1024) 2182 if ((capacity >> 20) > 2 * 1024)
2171 mmc->capacity_user = capacity; 2183 mmc->capacity_user = capacity;
2172 } 2184 }
2173 2185
2174 /* The partition data may be non-zero but it is only 2186 /* The partition data may be non-zero but it is only
2175 * effective if PARTITION_SETTING_COMPLETED is set in 2187 * effective if PARTITION_SETTING_COMPLETED is set in
2176 * EXT_CSD, so ignore any data if this bit is not set, 2188 * EXT_CSD, so ignore any data if this bit is not set,
2177 * except for enabling the high-capacity group size 2189 * except for enabling the high-capacity group size
2178 * definition (see below). 2190 * definition (see below).
2179 */ 2191 */
2180 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & 2192 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2181 EXT_CSD_PARTITION_SETTING_COMPLETED); 2193 EXT_CSD_PARTITION_SETTING_COMPLETED);
2182 2194
2183 /* store the partition info of emmc */ 2195 /* store the partition info of emmc */
2184 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; 2196 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2185 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || 2197 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2186 ext_csd[EXT_CSD_BOOT_MULT]) 2198 ext_csd[EXT_CSD_BOOT_MULT])
2187 mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; 2199 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2188 if (part_completed && 2200 if (part_completed &&
2189 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) 2201 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2190 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; 2202 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2191 2203
2192 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; 2204 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2193 2205
2194 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; 2206 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2195 2207
2196 for (i = 0; i < 4; i++) { 2208 for (i = 0; i < 4; i++) {
2197 int idx = EXT_CSD_GP_SIZE_MULT + i * 3; 2209 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2198 uint mult = (ext_csd[idx + 2] << 16) + 2210 uint mult = (ext_csd[idx + 2] << 16) +
2199 (ext_csd[idx + 1] << 8) + ext_csd[idx]; 2211 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2200 if (mult) 2212 if (mult)
2201 has_parts = true; 2213 has_parts = true;
2202 if (!part_completed) 2214 if (!part_completed)
2203 continue; 2215 continue;
2204 mmc->capacity_gp[i] = mult; 2216 mmc->capacity_gp[i] = mult;
2205 mmc->capacity_gp[i] *= 2217 mmc->capacity_gp[i] *=
2206 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 2218 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2207 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 2219 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2208 mmc->capacity_gp[i] <<= 19; 2220 mmc->capacity_gp[i] <<= 19;
2209 } 2221 }
2210 2222
2211 #ifndef CONFIG_SPL_BUILD 2223 #ifndef CONFIG_SPL_BUILD
2212 if (part_completed) { 2224 if (part_completed) {
2213 mmc->enh_user_size = 2225 mmc->enh_user_size =
2214 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) + 2226 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2215 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) + 2227 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2216 ext_csd[EXT_CSD_ENH_SIZE_MULT]; 2228 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2217 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 2229 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2218 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 2230 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2219 mmc->enh_user_size <<= 19; 2231 mmc->enh_user_size <<= 19;
2220 mmc->enh_user_start = 2232 mmc->enh_user_start =
2221 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) + 2233 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2222 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) + 2234 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2223 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) + 2235 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2224 ext_csd[EXT_CSD_ENH_START_ADDR]; 2236 ext_csd[EXT_CSD_ENH_START_ADDR];
2225 if (mmc->high_capacity) 2237 if (mmc->high_capacity)
2226 mmc->enh_user_start <<= 9; 2238 mmc->enh_user_start <<= 9;
2227 } 2239 }
2228 #endif 2240 #endif
2229 2241
2230 /* 2242 /*
2231 * Host needs to enable ERASE_GRP_DEF bit if device is 2243 * Host needs to enable ERASE_GRP_DEF bit if device is
2232 * partitioned. This bit will be lost every time after a reset 2244 * partitioned. This bit will be lost every time after a reset
2233 * or power off. This will affect erase size. 2245 * or power off. This will affect erase size.
2234 */ 2246 */
2235 if (part_completed) 2247 if (part_completed)
2236 has_parts = true; 2248 has_parts = true;
2237 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && 2249 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2238 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) 2250 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2239 has_parts = true; 2251 has_parts = true;
2240 if (has_parts) { 2252 if (has_parts) {
2241 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 2253 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2242 EXT_CSD_ERASE_GROUP_DEF, 1); 2254 EXT_CSD_ERASE_GROUP_DEF, 1);
2243 2255
2244 if (err) 2256 if (err)
2245 goto error; 2257 goto error;
2246 2258
2247 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 2259 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2248 } 2260 }
2249 2261
2250 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { 2262 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
2251 #if CONFIG_IS_ENABLED(MMC_WRITE) 2263 #if CONFIG_IS_ENABLED(MMC_WRITE)
2252 /* Read out group size from ext_csd */ 2264 /* Read out group size from ext_csd */
2253 mmc->erase_grp_size = 2265 mmc->erase_grp_size =
2254 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 2266 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
2255 #endif 2267 #endif
2256 /* 2268 /*
2257 * if high capacity and partition setting completed 2269 * if high capacity and partition setting completed
2258 * SEC_COUNT is valid even if it is smaller than 2 GiB 2270 * SEC_COUNT is valid even if it is smaller than 2 GiB
2259 * JEDEC Standard JESD84-B45, 6.2.4 2271 * JEDEC Standard JESD84-B45, 6.2.4
2260 */ 2272 */
2261 if (mmc->high_capacity && part_completed) { 2273 if (mmc->high_capacity && part_completed) {
2262 capacity = (ext_csd[EXT_CSD_SEC_CNT]) | 2274 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2263 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | 2275 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2264 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | 2276 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2265 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); 2277 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2266 capacity *= MMC_MAX_BLOCK_LEN; 2278 capacity *= MMC_MAX_BLOCK_LEN;
2267 mmc->capacity_user = capacity; 2279 mmc->capacity_user = capacity;
2268 } 2280 }
2269 } 2281 }
2270 #if CONFIG_IS_ENABLED(MMC_WRITE) 2282 #if CONFIG_IS_ENABLED(MMC_WRITE)
2271 else { 2283 else {
2272 /* Calculate the group size from the csd value. */ 2284 /* Calculate the group size from the csd value. */
2273 int erase_gsz, erase_gmul; 2285 int erase_gsz, erase_gmul;
2274 2286
2275 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; 2287 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2276 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; 2288 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2277 mmc->erase_grp_size = (erase_gsz + 1) 2289 mmc->erase_grp_size = (erase_gsz + 1)
2278 * (erase_gmul + 1); 2290 * (erase_gmul + 1);
2279 } 2291 }
2280 #endif 2292 #endif
2281 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) 2293 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
2282 mmc->hc_wp_grp_size = 1024 2294 mmc->hc_wp_grp_size = 1024
2283 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 2295 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2284 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 2296 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2285 #endif 2297 #endif
2286 2298
2287 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 2299 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2288 2300
2289 return 0; 2301 return 0;
2290 error: 2302 error:
2291 if (mmc->ext_csd) { 2303 if (mmc->ext_csd) {
2292 free(mmc->ext_csd); 2304 free(mmc->ext_csd);
2293 mmc->ext_csd = NULL; 2305 mmc->ext_csd = NULL;
2294 } 2306 }
2295 return err; 2307 return err;
2296 } 2308 }
2297 2309
2298 static int mmc_startup(struct mmc *mmc) 2310 static int mmc_startup(struct mmc *mmc)
2299 { 2311 {
2300 int err, i; 2312 int err, i;
2301 uint mult, freq; 2313 uint mult, freq;
2302 u64 cmult, csize; 2314 u64 cmult, csize;
2303 struct mmc_cmd cmd; 2315 struct mmc_cmd cmd;
2304 struct blk_desc *bdesc; 2316 struct blk_desc *bdesc;
2305 2317
2306 #ifdef CONFIG_MMC_SPI_CRC_ON 2318 #ifdef CONFIG_MMC_SPI_CRC_ON
2307 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ 2319 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2308 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; 2320 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2309 cmd.resp_type = MMC_RSP_R1; 2321 cmd.resp_type = MMC_RSP_R1;
2310 cmd.cmdarg = 1; 2322 cmd.cmdarg = 1;
2311 err = mmc_send_cmd(mmc, &cmd, NULL); 2323 err = mmc_send_cmd(mmc, &cmd, NULL);
2312 if (err) 2324 if (err)
2313 return err; 2325 return err;
2314 } 2326 }
2315 #endif 2327 #endif
2316 2328
2317 /* Put the Card in Identify Mode */ 2329 /* Put the Card in Identify Mode */
2318 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : 2330 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2319 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ 2331 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
2320 cmd.resp_type = MMC_RSP_R2; 2332 cmd.resp_type = MMC_RSP_R2;
2321 cmd.cmdarg = 0; 2333 cmd.cmdarg = 0;
2322 2334
2323 err = mmc_send_cmd(mmc, &cmd, NULL); 2335 err = mmc_send_cmd(mmc, &cmd, NULL);
2324 2336
2325 #ifdef CONFIG_MMC_QUIRKS 2337 #ifdef CONFIG_MMC_QUIRKS
2326 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) { 2338 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2327 int retries = 4; 2339 int retries = 4;
2328 /* 2340 /*
2329 * It has been seen that SEND_CID may fail on the first 2341 * It has been seen that SEND_CID may fail on the first
2330 * attempt, let's try a few more time 2342 * attempt, let's try a few more time
2331 */ 2343 */
2332 do { 2344 do {
2333 err = mmc_send_cmd(mmc, &cmd, NULL); 2345 err = mmc_send_cmd(mmc, &cmd, NULL);
2334 if (!err) 2346 if (!err)
2335 break; 2347 break;
2336 } while (retries--); 2348 } while (retries--);
2337 } 2349 }
2338 #endif 2350 #endif
2339 2351
2340 if (err) 2352 if (err)
2341 return err; 2353 return err;
2342 2354
2343 memcpy(mmc->cid, cmd.response, 16); 2355 memcpy(mmc->cid, cmd.response, 16);
2344 2356
2345 /* 2357 /*
2346 * For MMC cards, set the Relative Address. 2358 * For MMC cards, set the Relative Address.
2347 * For SD cards, get the Relatvie Address. 2359 * For SD cards, get the Relatvie Address.
2348 * This also puts the cards into Standby State 2360 * This also puts the cards into Standby State
2349 */ 2361 */
2350 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 2362 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2351 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; 2363 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2352 cmd.cmdarg = mmc->rca << 16; 2364 cmd.cmdarg = mmc->rca << 16;
2353 cmd.resp_type = MMC_RSP_R6; 2365 cmd.resp_type = MMC_RSP_R6;
2354 2366
2355 err = mmc_send_cmd(mmc, &cmd, NULL); 2367 err = mmc_send_cmd(mmc, &cmd, NULL);
2356 2368
2357 if (err) 2369 if (err)
2358 return err; 2370 return err;
2359 2371
2360 if (IS_SD(mmc)) 2372 if (IS_SD(mmc))
2361 mmc->rca = (cmd.response[0] >> 16) & 0xffff; 2373 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2362 } 2374 }
2363 2375
2364 /* Get the Card-Specific Data */ 2376 /* Get the Card-Specific Data */
2365 cmd.cmdidx = MMC_CMD_SEND_CSD; 2377 cmd.cmdidx = MMC_CMD_SEND_CSD;
2366 cmd.resp_type = MMC_RSP_R2; 2378 cmd.resp_type = MMC_RSP_R2;
2367 cmd.cmdarg = mmc->rca << 16; 2379 cmd.cmdarg = mmc->rca << 16;
2368 2380
2369 err = mmc_send_cmd(mmc, &cmd, NULL); 2381 err = mmc_send_cmd(mmc, &cmd, NULL);
2370 2382
2371 if (err) 2383 if (err)
2372 return err; 2384 return err;
2373 2385
2374 mmc->csd[0] = cmd.response[0]; 2386 mmc->csd[0] = cmd.response[0];
2375 mmc->csd[1] = cmd.response[1]; 2387 mmc->csd[1] = cmd.response[1];
2376 mmc->csd[2] = cmd.response[2]; 2388 mmc->csd[2] = cmd.response[2];
2377 mmc->csd[3] = cmd.response[3]; 2389 mmc->csd[3] = cmd.response[3];
2378 2390
2379 if (mmc->version == MMC_VERSION_UNKNOWN) { 2391 if (mmc->version == MMC_VERSION_UNKNOWN) {
2380 int version = (cmd.response[0] >> 26) & 0xf; 2392 int version = (cmd.response[0] >> 26) & 0xf;
2381 2393
2382 switch (version) { 2394 switch (version) {
2383 case 0: 2395 case 0:
2384 mmc->version = MMC_VERSION_1_2; 2396 mmc->version = MMC_VERSION_1_2;
2385 break; 2397 break;
2386 case 1: 2398 case 1:
2387 mmc->version = MMC_VERSION_1_4; 2399 mmc->version = MMC_VERSION_1_4;
2388 break; 2400 break;
2389 case 2: 2401 case 2:
2390 mmc->version = MMC_VERSION_2_2; 2402 mmc->version = MMC_VERSION_2_2;
2391 break; 2403 break;
2392 case 3: 2404 case 3:
2393 mmc->version = MMC_VERSION_3; 2405 mmc->version = MMC_VERSION_3;
2394 break; 2406 break;
2395 case 4: 2407 case 4:
2396 mmc->version = MMC_VERSION_4; 2408 mmc->version = MMC_VERSION_4;
2397 break; 2409 break;
2398 default: 2410 default:
2399 mmc->version = MMC_VERSION_1_2; 2411 mmc->version = MMC_VERSION_1_2;
2400 break; 2412 break;
2401 } 2413 }
2402 } 2414 }
2403 2415
2404 /* divide frequency by 10, since the mults are 10x bigger */ 2416 /* divide frequency by 10, since the mults are 10x bigger */
2405 freq = fbase[(cmd.response[0] & 0x7)]; 2417 freq = fbase[(cmd.response[0] & 0x7)];
2406 mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; 2418 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
2407 2419
2408 mmc->legacy_speed = freq * mult; 2420 mmc->legacy_speed = freq * mult;
2409 mmc_select_mode(mmc, MMC_LEGACY); 2421 mmc_select_mode(mmc, MMC_LEGACY);
2410 2422
2411 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); 2423 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
2412 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); 2424 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
2413 #if CONFIG_IS_ENABLED(MMC_WRITE) 2425 #if CONFIG_IS_ENABLED(MMC_WRITE)
2414 2426
2415 if (IS_SD(mmc)) 2427 if (IS_SD(mmc))
2416 mmc->write_bl_len = mmc->read_bl_len; 2428 mmc->write_bl_len = mmc->read_bl_len;
2417 else 2429 else
2418 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); 2430 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
2419 #endif 2431 #endif
2420 2432
2421 if (mmc->high_capacity) { 2433 if (mmc->high_capacity) {
2422 csize = (mmc->csd[1] & 0x3f) << 16 2434 csize = (mmc->csd[1] & 0x3f) << 16
2423 | (mmc->csd[2] & 0xffff0000) >> 16; 2435 | (mmc->csd[2] & 0xffff0000) >> 16;
2424 cmult = 8; 2436 cmult = 8;
2425 } else { 2437 } else {
2426 csize = (mmc->csd[1] & 0x3ff) << 2 2438 csize = (mmc->csd[1] & 0x3ff) << 2
2427 | (mmc->csd[2] & 0xc0000000) >> 30; 2439 | (mmc->csd[2] & 0xc0000000) >> 30;
2428 cmult = (mmc->csd[2] & 0x00038000) >> 15; 2440 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2429 } 2441 }
2430 2442
2431 mmc->capacity_user = (csize + 1) << (cmult + 2); 2443 mmc->capacity_user = (csize + 1) << (cmult + 2);
2432 mmc->capacity_user *= mmc->read_bl_len; 2444 mmc->capacity_user *= mmc->read_bl_len;
2433 mmc->capacity_boot = 0; 2445 mmc->capacity_boot = 0;
2434 mmc->capacity_rpmb = 0; 2446 mmc->capacity_rpmb = 0;
2435 for (i = 0; i < 4; i++) 2447 for (i = 0; i < 4; i++)
2436 mmc->capacity_gp[i] = 0; 2448 mmc->capacity_gp[i] = 0;
2437 2449
2438 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) 2450 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2439 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 2451 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2440 2452
2441 #if CONFIG_IS_ENABLED(MMC_WRITE) 2453 #if CONFIG_IS_ENABLED(MMC_WRITE)
2442 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) 2454 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2443 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 2455 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2444 #endif 2456 #endif
2445 2457
2446 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { 2458 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2447 cmd.cmdidx = MMC_CMD_SET_DSR; 2459 cmd.cmdidx = MMC_CMD_SET_DSR;
2448 cmd.cmdarg = (mmc->dsr & 0xffff) << 16; 2460 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2449 cmd.resp_type = MMC_RSP_NONE; 2461 cmd.resp_type = MMC_RSP_NONE;
2450 if (mmc_send_cmd(mmc, &cmd, NULL)) 2462 if (mmc_send_cmd(mmc, &cmd, NULL))
2451 pr_warn("MMC: SET_DSR failed\n"); 2463 pr_warn("MMC: SET_DSR failed\n");
2452 } 2464 }
2453 2465
2454 /* Select the card, and put it into Transfer Mode */ 2466 /* Select the card, and put it into Transfer Mode */
2455 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 2467 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2456 cmd.cmdidx = MMC_CMD_SELECT_CARD; 2468 cmd.cmdidx = MMC_CMD_SELECT_CARD;
2457 cmd.resp_type = MMC_RSP_R1; 2469 cmd.resp_type = MMC_RSP_R1;
2458 cmd.cmdarg = mmc->rca << 16; 2470 cmd.cmdarg = mmc->rca << 16;
2459 err = mmc_send_cmd(mmc, &cmd, NULL); 2471 err = mmc_send_cmd(mmc, &cmd, NULL);
2460 2472
2461 if (err) 2473 if (err)
2462 return err; 2474 return err;
2463 } 2475 }
2464 2476
2465 /* 2477 /*
2466 * For SD, its erase group is always one sector 2478 * For SD, its erase group is always one sector
2467 */ 2479 */
2468 #if CONFIG_IS_ENABLED(MMC_WRITE) 2480 #if CONFIG_IS_ENABLED(MMC_WRITE)
2469 mmc->erase_grp_size = 1; 2481 mmc->erase_grp_size = 1;
2470 #endif 2482 #endif
2471 mmc->part_config = MMCPART_NOAVAILABLE; 2483 mmc->part_config = MMCPART_NOAVAILABLE;
2472 2484
2473 err = mmc_startup_v4(mmc); 2485 err = mmc_startup_v4(mmc);
2474 if (err) 2486 if (err)
2475 return err; 2487 return err;
2476 2488
2477 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart); 2489 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
2478 if (err) 2490 if (err)
2479 return err; 2491 return err;
2480 2492
2481 if (IS_SD(mmc)) { 2493 if (IS_SD(mmc)) {
2482 err = sd_get_capabilities(mmc); 2494 err = sd_get_capabilities(mmc);
2483 if (err) 2495 if (err)
2484 return err; 2496 return err;
2485 err = sd_select_mode_and_width(mmc, mmc->card_caps); 2497 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2486 } else { 2498 } else {
2487 err = mmc_get_capabilities(mmc); 2499 err = mmc_get_capabilities(mmc);
2488 if (err) 2500 if (err)
2489 return err; 2501 return err;
2490 mmc_select_mode_and_width(mmc, mmc->card_caps); 2502 mmc_select_mode_and_width(mmc, mmc->card_caps);
2491 } 2503 }
2492 2504
2493 if (err) 2505 if (err)
2494 return err; 2506 return err;
2495 2507
2496 mmc->best_mode = mmc->selected_mode; 2508 mmc->best_mode = mmc->selected_mode;
2497 2509
2498 /* Fix the block length for DDR mode */ 2510 /* Fix the block length for DDR mode */
2499 if (mmc->ddr_mode) { 2511 if (mmc->ddr_mode) {
2500 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 2512 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2501 #if CONFIG_IS_ENABLED(MMC_WRITE) 2513 #if CONFIG_IS_ENABLED(MMC_WRITE)
2502 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 2514 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2503 #endif 2515 #endif
2504 } 2516 }
2505 2517
2506 /* fill in device description */ 2518 /* fill in device description */
2507 bdesc = mmc_get_blk_desc(mmc); 2519 bdesc = mmc_get_blk_desc(mmc);
2508 bdesc->lun = 0; 2520 bdesc->lun = 0;
2509 bdesc->hwpart = 0; 2521 bdesc->hwpart = 0;
2510 bdesc->type = 0; 2522 bdesc->type = 0;
2511 bdesc->blksz = mmc->read_bl_len; 2523 bdesc->blksz = mmc->read_bl_len;
2512 bdesc->log2blksz = LOG2(bdesc->blksz); 2524 bdesc->log2blksz = LOG2(bdesc->blksz);
2513 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); 2525 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
2514 #if !defined(CONFIG_SPL_BUILD) || \ 2526 #if !defined(CONFIG_SPL_BUILD) || \
2515 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ 2527 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2516 !defined(CONFIG_USE_TINY_PRINTF)) 2528 !defined(CONFIG_USE_TINY_PRINTF))
2517 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x", 2529 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
2518 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), 2530 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2519 (mmc->cid[3] >> 16) & 0xffff); 2531 (mmc->cid[3] >> 16) & 0xffff);
2520 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, 2532 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
2521 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, 2533 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2522 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, 2534 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2523 (mmc->cid[2] >> 24) & 0xff); 2535 (mmc->cid[2] >> 24) & 0xff);
2524 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, 2536 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
2525 (mmc->cid[2] >> 16) & 0xf); 2537 (mmc->cid[2] >> 16) & 0xf);
2526 #else 2538 #else
2527 bdesc->vendor[0] = 0; 2539 bdesc->vendor[0] = 0;
2528 bdesc->product[0] = 0; 2540 bdesc->product[0] = 0;
2529 bdesc->revision[0] = 0; 2541 bdesc->revision[0] = 0;
2530 #endif 2542 #endif
2531 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) 2543 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
2532 part_init(bdesc); 2544 part_init(bdesc);
2533 #endif 2545 #endif
2534 2546
2535 return 0; 2547 return 0;
2536 } 2548 }
2537 2549
2538 static int mmc_send_if_cond(struct mmc *mmc) 2550 static int mmc_send_if_cond(struct mmc *mmc)
2539 { 2551 {
2540 struct mmc_cmd cmd; 2552 struct mmc_cmd cmd;
2541 int err; 2553 int err;
2542 2554
2543 cmd.cmdidx = SD_CMD_SEND_IF_COND; 2555 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2544 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 2556 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
2545 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; 2557 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
2546 cmd.resp_type = MMC_RSP_R7; 2558 cmd.resp_type = MMC_RSP_R7;
2547 2559
2548 err = mmc_send_cmd(mmc, &cmd, NULL); 2560 err = mmc_send_cmd(mmc, &cmd, NULL);
2549 2561
2550 if (err) 2562 if (err)
2551 return err; 2563 return err;
2552 2564
2553 if ((cmd.response[0] & 0xff) != 0xaa) 2565 if ((cmd.response[0] & 0xff) != 0xaa)
2554 return -EOPNOTSUPP; 2566 return -EOPNOTSUPP;
2555 else 2567 else
2556 mmc->version = SD_VERSION_2; 2568 mmc->version = SD_VERSION_2;
2557 2569
2558 return 0; 2570 return 0;
2559 } 2571 }
2560 2572
2561 #if !CONFIG_IS_ENABLED(DM_MMC) 2573 #if !CONFIG_IS_ENABLED(DM_MMC)
2562 /* board-specific MMC power initializations. */ 2574 /* board-specific MMC power initializations. */
2563 __weak void board_mmc_power_init(void) 2575 __weak void board_mmc_power_init(void)
2564 { 2576 {
2565 } 2577 }
2566 #endif 2578 #endif
2567 2579
2568 static int mmc_power_init(struct mmc *mmc) 2580 static int mmc_power_init(struct mmc *mmc)
2569 { 2581 {
2570 #if CONFIG_IS_ENABLED(DM_MMC) 2582 #if CONFIG_IS_ENABLED(DM_MMC)
2571 #if CONFIG_IS_ENABLED(DM_REGULATOR) 2583 #if CONFIG_IS_ENABLED(DM_REGULATOR)
2572 int ret; 2584 int ret;
2573 2585
2574 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply", 2586 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
2575 &mmc->vmmc_supply); 2587 &mmc->vmmc_supply);
2576 if (ret) 2588 if (ret)
2577 pr_debug("%s: No vmmc supply\n", mmc->dev->name); 2589 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2578 2590
2579 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply", 2591 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2580 &mmc->vqmmc_supply); 2592 &mmc->vqmmc_supply);
2581 if (ret) 2593 if (ret)
2582 pr_debug("%s: No vqmmc supply\n", mmc->dev->name); 2594 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
2583 #endif 2595 #endif
2584 #else /* !CONFIG_DM_MMC */ 2596 #else /* !CONFIG_DM_MMC */
2585 /* 2597 /*
2586 * Driver model should use a regulator, as above, rather than calling 2598 * Driver model should use a regulator, as above, rather than calling
2587 * out to board code. 2599 * out to board code.
2588 */ 2600 */
2589 board_mmc_power_init(); 2601 board_mmc_power_init();
2590 #endif 2602 #endif
2591 return 0; 2603 return 0;
2592 } 2604 }
2593 2605
2594 /* 2606 /*
2595 * put the host in the initial state: 2607 * put the host in the initial state:
2596 * - turn on Vdd (card power supply) 2608 * - turn on Vdd (card power supply)
2597 * - configure the bus width and clock to minimal values 2609 * - configure the bus width and clock to minimal values
2598 */ 2610 */
2599 static void mmc_set_initial_state(struct mmc *mmc) 2611 static void mmc_set_initial_state(struct mmc *mmc)
2600 { 2612 {
2601 int err; 2613 int err;
2602 2614
2603 /* First try to set 3.3V. If it fails set to 1.8V */ 2615 /* First try to set 3.3V. If it fails set to 1.8V */
2604 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330); 2616 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2605 if (err != 0) 2617 if (err != 0)
2606 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180); 2618 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2607 if (err != 0) 2619 if (err != 0)
2608 pr_warn("mmc: failed to set signal voltage\n"); 2620 pr_warn("mmc: failed to set signal voltage\n");
2609 2621
2610 mmc_select_mode(mmc, MMC_LEGACY); 2622 mmc_select_mode(mmc, MMC_LEGACY);
2611 mmc_set_bus_width(mmc, 1); 2623 mmc_set_bus_width(mmc, 1);
2612 mmc_set_clock(mmc, 0, false); 2624 mmc_set_clock(mmc, 0, false);
2613 } 2625 }
2614 2626
2615 static int mmc_power_on(struct mmc *mmc) 2627 static int mmc_power_on(struct mmc *mmc)
2616 { 2628 {
2617 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR) 2629 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2618 if (mmc->vmmc_supply) { 2630 if (mmc->vmmc_supply) {
2619 int ret = regulator_set_enable(mmc->vmmc_supply, true); 2631 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2620 2632
2621 if (ret) { 2633 if (ret) {
2622 puts("Error enabling VMMC supply\n"); 2634 puts("Error enabling VMMC supply\n");
2623 return ret; 2635 return ret;
2624 } 2636 }
2625 } 2637 }
2626 #endif 2638 #endif
2627 return 0; 2639 return 0;
2628 } 2640 }
2629 2641
2630 static int mmc_power_off(struct mmc *mmc) 2642 static int mmc_power_off(struct mmc *mmc)
2631 { 2643 {
2632 mmc_set_clock(mmc, 0, true); 2644 mmc_set_clock(mmc, 0, true);
2633 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR) 2645 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2634 if (mmc->vmmc_supply) { 2646 if (mmc->vmmc_supply) {
2635 int ret = regulator_set_enable(mmc->vmmc_supply, false); 2647 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2636 2648
2637 if (ret) { 2649 if (ret) {
2638 pr_debug("Error disabling VMMC supply\n"); 2650 pr_debug("Error disabling VMMC supply\n");
2639 return ret; 2651 return ret;
2640 } 2652 }
2641 } 2653 }
2642 #endif 2654 #endif
2643 return 0; 2655 return 0;
2644 } 2656 }
2645 2657
2646 static int mmc_power_cycle(struct mmc *mmc) 2658 static int mmc_power_cycle(struct mmc *mmc)
2647 { 2659 {
2648 int ret; 2660 int ret;
2649 2661
2650 ret = mmc_power_off(mmc); 2662 ret = mmc_power_off(mmc);
2651 if (ret) 2663 if (ret)
2652 return ret; 2664 return ret;
2653 /* 2665 /*
2654 * SD spec recommends at least 1ms of delay. Let's wait for 2ms 2666 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2655 * to be on the safer side. 2667 * to be on the safer side.
2656 */ 2668 */
2657 udelay(2000); 2669 udelay(2000);
2658 return mmc_power_on(mmc); 2670 return mmc_power_on(mmc);
2659 } 2671 }
2660 2672
2661 int mmc_start_init(struct mmc *mmc) 2673 int mmc_start_init(struct mmc *mmc)
2662 { 2674 {
2663 bool no_card; 2675 bool no_card;
2664 bool uhs_en = supports_uhs(mmc->cfg->host_caps); 2676 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2665 int err; 2677 int err;
2666 2678
2667 /* 2679 /*
2668 * all hosts are capable of 1 bit bus-width and able to use the legacy 2680 * all hosts are capable of 1 bit bus-width and able to use the legacy
2669 * timings. 2681 * timings.
2670 */ 2682 */
2671 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) | 2683 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2672 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT; 2684 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2673 2685
2674 #if !defined(CONFIG_MMC_BROKEN_CD) 2686 #if !defined(CONFIG_MMC_BROKEN_CD)
2675 /* we pretend there's no card when init is NULL */ 2687 /* we pretend there's no card when init is NULL */
2676 no_card = mmc_getcd(mmc) == 0; 2688 no_card = mmc_getcd(mmc) == 0;
2677 #else 2689 #else
2678 no_card = 0; 2690 no_card = 0;
2679 #endif 2691 #endif
2680 #if !CONFIG_IS_ENABLED(DM_MMC) 2692 #if !CONFIG_IS_ENABLED(DM_MMC)
2681 no_card = no_card || (mmc->cfg->ops->init == NULL); 2693 no_card = no_card || (mmc->cfg->ops->init == NULL);
2682 #endif 2694 #endif
2683 if (no_card) { 2695 if (no_card) {
2684 mmc->has_init = 0; 2696 mmc->has_init = 0;
2685 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 2697 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2686 pr_err("MMC: no card present\n"); 2698 pr_err("MMC: no card present\n");
2687 #endif 2699 #endif
2688 return -ENOMEDIUM; 2700 return -ENOMEDIUM;
2689 } 2701 }
2690 2702
2691 if (mmc->has_init) 2703 if (mmc->has_init)
2692 return 0; 2704 return 0;
2693 2705
2694 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 2706 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2695 mmc_adapter_card_type_ident(); 2707 mmc_adapter_card_type_ident();
2696 #endif 2708 #endif
2697 err = mmc_power_init(mmc); 2709 err = mmc_power_init(mmc);
2698 if (err) 2710 if (err)
2699 return err; 2711 return err;
2700 2712
2701 #ifdef CONFIG_MMC_QUIRKS 2713 #ifdef CONFIG_MMC_QUIRKS
2702 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN | 2714 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2703 MMC_QUIRK_RETRY_SEND_CID; 2715 MMC_QUIRK_RETRY_SEND_CID;
2704 #endif 2716 #endif
2705 2717
2706 err = mmc_power_cycle(mmc); 2718 err = mmc_power_cycle(mmc);
2707 if (err) { 2719 if (err) {
2708 /* 2720 /*
2709 * if power cycling is not supported, we should not try 2721 * if power cycling is not supported, we should not try
2710 * to use the UHS modes, because we wouldn't be able to 2722 * to use the UHS modes, because we wouldn't be able to
2711 * recover from an error during the UHS initialization. 2723 * recover from an error during the UHS initialization.
2712 */ 2724 */
2713 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n"); 2725 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2714 uhs_en = false; 2726 uhs_en = false;
2715 mmc->host_caps &= ~UHS_CAPS; 2727 mmc->host_caps &= ~UHS_CAPS;
2716 err = mmc_power_on(mmc); 2728 err = mmc_power_on(mmc);
2717 } 2729 }
2718 if (err) 2730 if (err)
2719 return err; 2731 return err;
2720 2732
2721 #if CONFIG_IS_ENABLED(DM_MMC) 2733 #if CONFIG_IS_ENABLED(DM_MMC)
2722 /* The device has already been probed ready for use */ 2734 /* The device has already been probed ready for use */
2723 #else 2735 #else
2724 /* made sure it's not NULL earlier */ 2736 /* made sure it's not NULL earlier */
2725 err = mmc->cfg->ops->init(mmc); 2737 err = mmc->cfg->ops->init(mmc);
2726 if (err) 2738 if (err)
2727 return err; 2739 return err;
2728 #endif 2740 #endif
2729 mmc->ddr_mode = 0; 2741 mmc->ddr_mode = 0;
2730 2742
2731 retry: 2743 retry:
2732 mmc_set_initial_state(mmc); 2744 mmc_set_initial_state(mmc);
2733 mmc_send_init_stream(mmc); 2745 mmc_send_init_stream(mmc);
2734 2746
2735 /* Reset the Card */ 2747 /* Reset the Card */
2736 err = mmc_go_idle(mmc); 2748 err = mmc_go_idle(mmc);
2737 2749
2738 if (err) 2750 if (err)
2739 return err; 2751 return err;
2740 2752
2741 /* The internal partition reset to user partition(0) at every CMD0*/ 2753 /* The internal partition reset to user partition(0) at every CMD0*/
2742 mmc_get_blk_desc(mmc)->hwpart = 0; 2754 mmc_get_blk_desc(mmc)->hwpart = 0;
2743 2755
2744 /* Test for SD version 2 */ 2756 /* Test for SD version 2 */
2745 err = mmc_send_if_cond(mmc); 2757 err = mmc_send_if_cond(mmc);
2746 2758
2747 /* Now try to get the SD card's operating condition */ 2759 /* Now try to get the SD card's operating condition */
2748 err = sd_send_op_cond(mmc, uhs_en); 2760 err = sd_send_op_cond(mmc, uhs_en);
2749 if (err && uhs_en) { 2761 if (err && uhs_en) {
2750 uhs_en = false; 2762 uhs_en = false;
2751 mmc_power_cycle(mmc); 2763 mmc_power_cycle(mmc);
2752 goto retry; 2764 goto retry;
2753 } 2765 }
2754 2766
2755 /* If the command timed out, we check for an MMC card */ 2767 /* If the command timed out, we check for an MMC card */
2756 if (err == -ETIMEDOUT) { 2768 if (err == -ETIMEDOUT) {
2757 err = mmc_send_op_cond(mmc); 2769 err = mmc_send_op_cond(mmc);
2758 2770
2759 if (err) { 2771 if (err) {
2760 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 2772 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2761 pr_err("Card did not respond to voltage select!\n"); 2773 pr_err("Card did not respond to voltage select!\n");
2762 #endif 2774 #endif
2763 return -EOPNOTSUPP; 2775 return -EOPNOTSUPP;
2764 } 2776 }
2765 } 2777 }
2766 2778
2767 if (!err) 2779 if (!err)
2768 mmc->init_in_progress = 1; 2780 mmc->init_in_progress = 1;
2769 2781
2770 return err; 2782 return err;
2771 } 2783 }
2772 2784
2773 static int mmc_complete_init(struct mmc *mmc) 2785 static int mmc_complete_init(struct mmc *mmc)
2774 { 2786 {
2775 int err = 0; 2787 int err = 0;
2776 2788
2777 mmc->init_in_progress = 0; 2789 mmc->init_in_progress = 0;
2778 if (mmc->op_cond_pending) 2790 if (mmc->op_cond_pending)
2779 err = mmc_complete_op_cond(mmc); 2791 err = mmc_complete_op_cond(mmc);
2780 2792
2781 if (!err) 2793 if (!err)
2782 err = mmc_startup(mmc); 2794 err = mmc_startup(mmc);
2783 if (err) 2795 if (err)
2784 mmc->has_init = 0; 2796 mmc->has_init = 0;
2785 else 2797 else
2786 mmc->has_init = 1; 2798 mmc->has_init = 1;
2787 return err; 2799 return err;
2788 } 2800 }
2789 2801
2790 int mmc_init(struct mmc *mmc) 2802 int mmc_init(struct mmc *mmc)
2791 { 2803 {
2792 int err = 0; 2804 int err = 0;
2793 __maybe_unused unsigned start; 2805 __maybe_unused unsigned start;
2794 #if CONFIG_IS_ENABLED(DM_MMC) 2806 #if CONFIG_IS_ENABLED(DM_MMC)
2795 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev); 2807 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2796 2808
2797 upriv->mmc = mmc; 2809 upriv->mmc = mmc;
2798 #endif 2810 #endif
2799 if (mmc->has_init) 2811 if (mmc->has_init)
2800 return 0; 2812 return 0;
2801 2813
2802 start = get_timer(0); 2814 start = get_timer(0);
2803 2815
2804 if (!mmc->init_in_progress) 2816 if (!mmc->init_in_progress)
2805 err = mmc_start_init(mmc); 2817 err = mmc_start_init(mmc);
2806 2818
2807 if (!err) 2819 if (!err)
2808 err = mmc_complete_init(mmc); 2820 err = mmc_complete_init(mmc);
2809 if (err) 2821 if (err)
2810 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start)); 2822 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
2811 2823
2812 return err; 2824 return err;
2813 } 2825 }
2814 2826
2815 int mmc_set_dsr(struct mmc *mmc, u16 val) 2827 int mmc_set_dsr(struct mmc *mmc, u16 val)
2816 { 2828 {
2817 mmc->dsr = val; 2829 mmc->dsr = val;
2818 return 0; 2830 return 0;
2819 } 2831 }
2820 2832
2821 /* CPU-specific MMC initializations */ 2833 /* CPU-specific MMC initializations */
2822 __weak int cpu_mmc_init(bd_t *bis) 2834 __weak int cpu_mmc_init(bd_t *bis)
2823 { 2835 {
2824 return -1; 2836 return -1;
2825 } 2837 }
2826 2838
2827 /* board-specific MMC initializations. */ 2839 /* board-specific MMC initializations. */
2828 __weak int board_mmc_init(bd_t *bis) 2840 __weak int board_mmc_init(bd_t *bis)
2829 { 2841 {
2830 return -1; 2842 return -1;
2831 } 2843 }
2832 2844
2833 void mmc_set_preinit(struct mmc *mmc, int preinit) 2845 void mmc_set_preinit(struct mmc *mmc, int preinit)
2834 { 2846 {
2835 mmc->preinit = preinit; 2847 mmc->preinit = preinit;
2836 } 2848 }
2837 2849
2838 #if CONFIG_IS_ENABLED(DM_MMC) 2850 #if CONFIG_IS_ENABLED(DM_MMC)
2839 static int mmc_probe(bd_t *bis) 2851 static int mmc_probe(bd_t *bis)
2840 { 2852 {
2841 int ret, i; 2853 int ret, i;
2842 struct uclass *uc; 2854 struct uclass *uc;
2843 struct udevice *dev; 2855 struct udevice *dev;
2844 2856
2845 ret = uclass_get(UCLASS_MMC, &uc); 2857 ret = uclass_get(UCLASS_MMC, &uc);
2846 if (ret) 2858 if (ret)
2847 return ret; 2859 return ret;
2848 2860
2849 /* 2861 /*
2850 * Try to add them in sequence order. Really with driver model we 2862 * Try to add them in sequence order. Really with driver model we
2851 * should allow holes, but the current MMC list does not allow that. 2863 * should allow holes, but the current MMC list does not allow that.
2852 * So if we request 0, 1, 3 we will get 0, 1, 2. 2864 * So if we request 0, 1, 3 we will get 0, 1, 2.
2853 */ 2865 */
2854 for (i = 0; ; i++) { 2866 for (i = 0; ; i++) {
2855 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev); 2867 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2856 if (ret == -ENODEV) 2868 if (ret == -ENODEV)
2857 break; 2869 break;
2858 } 2870 }
2859 uclass_foreach_dev(dev, uc) { 2871 uclass_foreach_dev(dev, uc) {
2860 ret = device_probe(dev); 2872 ret = device_probe(dev);
2861 if (ret) 2873 if (ret)
2862 pr_err("%s - probe failed: %d\n", dev->name, ret); 2874 pr_err("%s - probe failed: %d\n", dev->name, ret);
2863 } 2875 }
2864 2876
2865 return 0; 2877 return 0;
2866 } 2878 }
2867 #else 2879 #else
2868 static int mmc_probe(bd_t *bis) 2880 static int mmc_probe(bd_t *bis)
2869 { 2881 {
2870 if (board_mmc_init(bis) < 0) 2882 if (board_mmc_init(bis) < 0)
2871 cpu_mmc_init(bis); 2883 cpu_mmc_init(bis);
2872 2884
2873 return 0; 2885 return 0;
2874 } 2886 }
2875 #endif 2887 #endif
2876 2888
2877 int mmc_initialize(bd_t *bis) 2889 int mmc_initialize(bd_t *bis)
2878 { 2890 {
2879 static int initialized = 0; 2891 static int initialized = 0;
2880 int ret; 2892 int ret;
2881 if (initialized) /* Avoid initializing mmc multiple times */ 2893 if (initialized) /* Avoid initializing mmc multiple times */
2882 return 0; 2894 return 0;
2883 initialized = 1; 2895 initialized = 1;
2884 2896
2885 #if !CONFIG_IS_ENABLED(BLK) 2897 #if !CONFIG_IS_ENABLED(BLK)
2886 #if !CONFIG_IS_ENABLED(MMC_TINY) 2898 #if !CONFIG_IS_ENABLED(MMC_TINY)
2887 mmc_list_init(); 2899 mmc_list_init();
2888 #endif 2900 #endif
2889 #endif 2901 #endif
2890 ret = mmc_probe(bis); 2902 ret = mmc_probe(bis);
2891 if (ret) 2903 if (ret)
2892 return ret; 2904 return ret;
2893 2905
2894 #ifndef CONFIG_SPL_BUILD 2906 #ifndef CONFIG_SPL_BUILD
2895 print_mmc_devices(','); 2907 print_mmc_devices(',');
2896 #endif 2908 #endif
2897 2909
2898 mmc_do_preinit(); 2910 mmc_do_preinit();
2899 return 0; 2911 return 0;
2900 } 2912 }
2901 2913
2902 #ifdef CONFIG_CMD_BKOPS_ENABLE 2914 #ifdef CONFIG_CMD_BKOPS_ENABLE
2903 int mmc_set_bkops_enable(struct mmc *mmc) 2915 int mmc_set_bkops_enable(struct mmc *mmc)
2904 { 2916 {
2905 int err; 2917 int err;
2906 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 2918 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2907 2919
2908 err = mmc_send_ext_csd(mmc, ext_csd); 2920 err = mmc_send_ext_csd(mmc, ext_csd);
2909 if (err) { 2921 if (err) {
2910 puts("Could not get ext_csd register values\n"); 2922 puts("Could not get ext_csd register values\n");
2911 return err; 2923 return err;
2912 } 2924 }
2913 2925
2914 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) { 2926 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2915 puts("Background operations not supported on device\n"); 2927 puts("Background operations not supported on device\n");
2916 return -EMEDIUMTYPE; 2928 return -EMEDIUMTYPE;
2917 } 2929 }
2918 2930
2919 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) { 2931 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2920 puts("Background operations already enabled\n"); 2932 puts("Background operations already enabled\n");
2921 return 0; 2933 return 0;
2922 } 2934 }
2923 2935
2924 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1); 2936 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2925 if (err) { 2937 if (err) {
2926 puts("Failed to enable manual background operations\n"); 2938 puts("Failed to enable manual background operations\n");
2927 return err; 2939 return err;
2928 } 2940 }
2929 2941
2930 puts("Enabled manual background operations\n"); 2942 puts("Enabled manual background operations\n");
2931 2943
2932 return 0; 2944 return 0;
2933 } 2945 }
2934 #endif 2946 #endif