Eric Lee / smarc-uboot

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Commit c44d3cd1c436af20ffc5f70451151f4de69a2278

Authored by Tom Rini
2 parents f10834e166 c469703ba0
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'master' of git://git.denx.de/u-boot-i2c

Showing 25 changed files Side-by-side Diff

drivers/i2c/Makefile
Diff comments   View file @ c44d3cd
... ... @@ -5,7 +5,7 @@
5 5 # SPDX-License-Identifier: GPL-2.0+
6 6 #
7 7  
8   -obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
  8 +obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o
9 9 obj-$(CONFIG_I2C_MV) += mv_i2c.o
10 10 obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
11 11 obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
drivers/i2c/adi_i2c.c
Diff comments   View file @ c44d3cd
  1 +/*
  2 + * i2c.c - driver for ADI TWI/I2C
  3 + *
  4 + * Copyright (c) 2006-2014 Analog Devices Inc.
  5 + *
  6 + * Licensed under the GPL-2 or later.
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <i2c.h>
  11 +
  12 +#include <asm/clock.h>
  13 +#include <asm/twi.h>
  14 +#include <asm/io.h>
  15 +
  16 +static struct twi_regs *i2c_get_base(struct i2c_adapter *adap);
  17 +
  18 +/* Every register is 32bit aligned, but only 16bits in size */
  19 +#define ureg(name) u16 name; u16 __pad_##name;
  20 +struct twi_regs {
  21 + ureg(clkdiv);
  22 + ureg(control);
  23 + ureg(slave_ctl);
  24 + ureg(slave_stat);
  25 + ureg(slave_addr);
  26 + ureg(master_ctl);
  27 + ureg(master_stat);
  28 + ureg(master_addr);
  29 + ureg(int_stat);
  30 + ureg(int_mask);
  31 + ureg(fifo_ctl);
  32 + ureg(fifo_stat);
  33 + char __pad[0x50];
  34 + ureg(xmt_data8);
  35 + ureg(xmt_data16);
  36 + ureg(rcv_data8);
  37 + ureg(rcv_data16);
  38 +};
  39 +#undef ureg
  40 +
  41 +#ifdef TWI_CLKDIV
  42 +#define TWI0_CLKDIV TWI_CLKDIV
  43 +# ifdef CONFIG_SYS_MAX_I2C_BUS
  44 +# undef CONFIG_SYS_MAX_I2C_BUS
  45 +# endif
  46 +#define CONFIG_SYS_MAX_I2C_BUS 1
  47 +#endif
  48 +
  49 +/*
  50 + * The way speed is changed into duty often results in integer truncation
  51 + * with 50% duty, so we'll force rounding up to the next duty by adding 1
  52 + * to the max. In practice this will get us a speed of something like
  53 + * 385 KHz. The other limit is easy to handle as it is only 8 bits.
  54 + */
  55 +#define I2C_SPEED_MAX 400000
  56 +#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
  57 +#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
  58 +#define I2C_DUTY_MIN 0xff /* 8 bit limited */
  59 +#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
  60 +/* Note: duty is inverse of speed, so the comparisons below are correct */
  61 +#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
  62 +# error "The I2C hardware can only operate 20KHz - 400KHz"
  63 +#endif
  64 +
  65 +/* All transfers are described by this data structure */
  66 +struct i2c_msg {
  67 + u8 flags;
  68 +#define I2C_M_COMBO 0x4
  69 +#define I2C_M_STOP 0x2
  70 +#define I2C_M_READ 0x1
  71 + int len; /* msg length */
  72 + u8 *buf; /* pointer to msg data */
  73 + int alen; /* addr length */
  74 + u8 *abuf; /* addr buffer */
  75 +};
  76 +
  77 +/* Allow msec timeout per ~byte transfer */
  78 +#define I2C_TIMEOUT 10
  79 +
  80 +/**
  81 + * wait_for_completion - manage the actual i2c transfer
  82 + * @msg: the i2c msg
  83 + */
  84 +static int wait_for_completion(struct twi_regs *twi, struct i2c_msg *msg)
  85 +{
  86 + u16 int_stat, ctl;
  87 + ulong timebase = get_timer(0);
  88 +
  89 + do {
  90 + int_stat = readw(&twi->int_stat);
  91 +
  92 + if (int_stat & XMTSERV) {
  93 + writew(XMTSERV, &twi->int_stat);
  94 + if (msg->alen) {
  95 + writew(*(msg->abuf++), &twi->xmt_data8);
  96 + --msg->alen;
  97 + } else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
  98 + writew(*(msg->buf++), &twi->xmt_data8);
  99 + --msg->len;
  100 + } else {
  101 + ctl = readw(&twi->master_ctl);
  102 + if (msg->flags & I2C_M_COMBO)
  103 + writew(ctl | RSTART | MDIR,
  104 + &twi->master_ctl);
  105 + else
  106 + writew(ctl | STOP, &twi->master_ctl);
  107 + }
  108 + }
  109 + if (int_stat & RCVSERV) {
  110 + writew(RCVSERV, &twi->int_stat);
  111 + if (msg->len) {
  112 + *(msg->buf++) = readw(&twi->rcv_data8);
  113 + --msg->len;
  114 + } else if (msg->flags & I2C_M_STOP) {
  115 + ctl = readw(&twi->master_ctl);
  116 + writew(ctl | STOP, &twi->master_ctl);
  117 + }
  118 + }
  119 + if (int_stat & MERR) {
  120 + writew(MERR, &twi->int_stat);
  121 + return msg->len;
  122 + }
  123 + if (int_stat & MCOMP) {
  124 + writew(MCOMP, &twi->int_stat);
  125 + if (msg->flags & I2C_M_COMBO && msg->len) {
  126 + ctl = readw(&twi->master_ctl);
  127 + ctl = (ctl & ~RSTART) |
  128 + (min(msg->len, 0xff) << 6) | MEN | MDIR;
  129 + writew(ctl, &twi->master_ctl);
  130 + } else
  131 + break;
  132 + }
  133 +
  134 + /* If we were able to do something, reset timeout */
  135 + if (int_stat)
  136 + timebase = get_timer(0);
  137 +
  138 + } while (get_timer(timebase) < I2C_TIMEOUT);
  139 +
  140 + return msg->len;
  141 +}
  142 +
  143 +static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr,
  144 + int alen, uint8_t *buffer, int len, uint8_t flags)
  145 +{
  146 + struct twi_regs *twi = i2c_get_base(adap);
  147 + int ret;
  148 + u16 ctl;
  149 + uchar addr_buffer[] = {
  150 + (addr >> 0),
  151 + (addr >> 8),
  152 + (addr >> 16),
  153 + };
  154 + struct i2c_msg msg = {
  155 + .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
  156 + .buf = buffer,
  157 + .len = len,
  158 + .abuf = addr_buffer,
  159 + .alen = alen,
  160 + };
  161 +
  162 + /* wait for things to settle */
  163 + while (readw(&twi->master_stat) & BUSBUSY)
  164 + if (ctrlc())
  165 + return 1;
  166 +
  167 + /* Set Transmit device address */
  168 + writew(chip, &twi->master_addr);
  169 +
  170 + /* Clear the FIFO before starting things */
  171 + writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl);
  172 + writew(0, &twi->fifo_ctl);
  173 +
  174 + /* prime the pump */
  175 + if (msg.alen) {
  176 + len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
  177 + writew(*(msg.abuf++), &twi->xmt_data8);
  178 + --msg.alen;
  179 + } else if (!(msg.flags & I2C_M_READ) && msg.len) {
  180 + writew(*(msg.buf++), &twi->xmt_data8);
  181 + --msg.len;
  182 + }
  183 +
  184 + /* clear int stat */
  185 + writew(-1, &twi->master_stat);
  186 + writew(-1, &twi->int_stat);
  187 + writew(0, &twi->int_mask);
  188 +
  189 + /* Master enable */
  190 + ctl = readw(&twi->master_ctl);
  191 + ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN |
  192 + ((msg.flags & I2C_M_READ) ? MDIR : 0);
  193 + writew(ctl, &twi->master_ctl);
  194 +
  195 + /* process the rest */
  196 + ret = wait_for_completion(twi, &msg);
  197 +
  198 + if (ret) {
  199 + ctl = readw(&twi->master_ctl) & ~MEN;
  200 + writew(ctl, &twi->master_ctl);
  201 + ctl = readw(&twi->control) & ~TWI_ENA;
  202 + writew(ctl, &twi->control);
  203 + ctl = readw(&twi->control) | TWI_ENA;
  204 + writew(ctl, &twi->control);
  205 + }
  206 +
  207 + return ret;
  208 +}
  209 +
  210 +static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed)
  211 +{
  212 + struct twi_regs *twi = i2c_get_base(adap);
  213 + u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
  214 +
  215 + /* Set TWI interface clock */
  216 + if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
  217 + return -1;
  218 + clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
  219 + writew(clkdiv, &twi->clkdiv);
  220 +
  221 + /* Don't turn it on */
  222 + writew(speed > 100000 ? FAST : 0, &twi->master_ctl);
  223 +
  224 + return 0;
  225 +}
  226 +
  227 +static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  228 +{
  229 + struct twi_regs *twi = i2c_get_base(adap);
  230 + u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
  231 +
  232 + /* Set TWI internal clock as 10MHz */
  233 + writew(prescale, &twi->control);
  234 +
  235 + /* Set TWI interface clock as specified */
  236 + i2c_set_bus_speed(speed);
  237 +
  238 + /* Enable it */
  239 + writew(TWI_ENA | prescale, &twi->control);
  240 +}
  241 +
  242 +static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip,
  243 + uint addr, int alen, uint8_t *buffer, int len)
  244 +{
  245 + return i2c_transfer(adap, chip, addr, alen, buffer,
  246 + len, alen ? I2C_M_COMBO : I2C_M_READ);
  247 +}
  248 +
  249 +static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip,
  250 + uint addr, int alen, uint8_t *buffer, int len)
  251 +{
  252 + return i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
  253 +}
  254 +
  255 +static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
  256 +{
  257 + u8 byte;
  258 + return adi_i2c_read(adap, chip, 0, 0, &byte, 1);
  259 +}
  260 +
  261 +static struct twi_regs *i2c_get_base(struct i2c_adapter *adap)
  262 +{
  263 + switch (adap->hwadapnr) {
  264 +#if CONFIG_SYS_MAX_I2C_BUS > 2
  265 + case 2:
  266 + return (struct twi_regs *)TWI2_CLKDIV;
  267 +#endif
  268 +#if CONFIG_SYS_MAX_I2C_BUS > 1
  269 + case 1:
  270 + return (struct twi_regs *)TWI1_CLKDIV;
  271 +#endif
  272 + case 0:
  273 + return (struct twi_regs *)TWI0_CLKDIV;
  274 +
  275 + default:
  276 + printf("wrong hwadapnr: %d\n", adap->hwadapnr);
  277 + }
  278 +
  279 + return NULL;
  280 +}
  281 +
  282 +U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe,
  283 + adi_i2c_read, adi_i2c_write,
  284 + adi_i2c_setspeed,
  285 + CONFIG_SYS_I2C_SPEED,
  286 + 0,
  287 + 0)
  288 +
  289 +#if CONFIG_SYS_MAX_I2C_BUS > 1
  290 +U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe,
  291 + adi_i2c_read, adi_i2c_write,
  292 + adi_i2c_setspeed,
  293 + CONFIG_SYS_I2C_SPEED,
  294 + 0,
  295 + 1)
  296 +#endif
  297 +
  298 +#if CONFIG_SYS_MAX_I2C_BUS > 2
  299 +U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe,
  300 + adi_i2c_read, adi_i2c_write,
  301 + adi_i2c_setspeed,
  302 + CONFIG_SYS_I2C_SPEED,
  303 + 0,
  304 + 2)
  305 +#endif
drivers/i2c/bfin-twi_i2c.c
View file @ c44d3cd
1   -/*
2   - * i2c.c - driver for Blackfin on-chip TWI/I2C
3   - *
4   - * Copyright (c) 2006-2010 Analog Devices Inc.
5   - *
6   - * Licensed under the GPL-2 or later.
7   - */
8   -
9   -#include <common.h>
10   -#include <i2c.h>
11   -
12   -#include <asm/blackfin.h>
13   -#include <asm/clock.h>
14   -#include <asm/mach-common/bits/twi.h>
15   -
16   -/* Every register is 32bit aligned, but only 16bits in size */
17   -#define ureg(name) u16 name; u16 __pad_##name;
18   -struct twi_regs {
19   - ureg(clkdiv);
20   - ureg(control);
21   - ureg(slave_ctl);
22   - ureg(slave_stat);
23   - ureg(slave_addr);
24   - ureg(master_ctl);
25   - ureg(master_stat);
26   - ureg(master_addr);
27   - ureg(int_stat);
28   - ureg(int_mask);
29   - ureg(fifo_ctl);
30   - ureg(fifo_stat);
31   - char __pad[0x50];
32   - ureg(xmt_data8);
33   - ureg(xmt_data16);
34   - ureg(rcv_data8);
35   - ureg(rcv_data16);
36   -};
37   -#undef ureg
38   -
39   -/* U-Boot I2C framework allows only one active device at a time. */
40   -#ifdef TWI_CLKDIV
41   -#define TWI0_CLKDIV TWI_CLKDIV
42   -#endif
43   -static volatile struct twi_regs *twi = (void *)TWI0_CLKDIV;
44   -
45   -#ifdef DEBUG
46   -# define dmemset(s, c, n) memset(s, c, n)
47   -#else
48   -# define dmemset(s, c, n)
49   -#endif
50   -#define debugi(fmt, args...) \
51   - debug( \
52   - "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \
53   - twi->master_stat, twi->fifo_stat, twi->int_stat, \
54   - __func__, __LINE__, ## args)
55   -
56   -#ifdef CONFIG_TWICLK_KHZ
57   -# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED
58   -#endif
59   -
60   -/*
61   - * The way speed is changed into duty often results in integer truncation
62   - * with 50% duty, so we'll force rounding up to the next duty by adding 1
63   - * to the max. In practice this will get us a speed of something like
64   - * 385 KHz. The other limit is easy to handle as it is only 8 bits.
65   - */
66   -#define I2C_SPEED_MAX 400000
67   -#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
68   -#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
69   -#define I2C_DUTY_MIN 0xff /* 8 bit limited */
70   -#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
71   -/* Note: duty is inverse of speed, so the comparisons below are correct */
72   -#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
73   -# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz"
74   -#endif
75   -
76   -/* All transfers are described by this data structure */
77   -struct i2c_msg {
78   - u8 flags;
79   -#define I2C_M_COMBO 0x4
80   -#define I2C_M_STOP 0x2
81   -#define I2C_M_READ 0x1
82   - int len; /* msg length */
83   - u8 *buf; /* pointer to msg data */
84   - int alen; /* addr length */
85   - u8 *abuf; /* addr buffer */
86   -};
87   -
88   -/* Allow msec timeout per ~byte transfer */
89   -#define I2C_TIMEOUT 10
90   -
91   -/**
92   - * wait_for_completion - manage the actual i2c transfer
93   - * @msg: the i2c msg
94   - */
95   -static int wait_for_completion(struct i2c_msg *msg)
96   -{
97   - uint16_t int_stat;
98   - ulong timebase = get_timer(0);
99   -
100   - do {
101   - int_stat = twi->int_stat;
102   -
103   - if (int_stat & XMTSERV) {
104   - debugi("processing XMTSERV");
105   - twi->int_stat = XMTSERV;
106   - SSYNC();
107   - if (msg->alen) {
108   - twi->xmt_data8 = *(msg->abuf++);
109   - --msg->alen;
110   - } else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
111   - twi->xmt_data8 = *(msg->buf++);
112   - --msg->len;
113   - } else {
114   - twi->master_ctl |= (msg->flags & I2C_M_COMBO) ? RSTART | MDIR : STOP;
115   - SSYNC();
116   - }
117   - }
118   - if (int_stat & RCVSERV) {
119   - debugi("processing RCVSERV");
120   - twi->int_stat = RCVSERV;
121   - SSYNC();
122   - if (msg->len) {
123   - *(msg->buf++) = twi->rcv_data8;
124   - --msg->len;
125   - } else if (msg->flags & I2C_M_STOP) {
126   - twi->master_ctl |= STOP;
127   - SSYNC();
128   - }
129   - }
130   - if (int_stat & MERR) {
131   - debugi("processing MERR");
132   - twi->int_stat = MERR;
133   - SSYNC();
134   - return msg->len;
135   - }
136   - if (int_stat & MCOMP) {
137   - debugi("processing MCOMP");
138   - twi->int_stat = MCOMP;
139   - SSYNC();
140   - if (msg->flags & I2C_M_COMBO && msg->len) {
141   - twi->master_ctl = (twi->master_ctl & ~RSTART) |
142   - (min(msg->len, 0xff) << 6) | MEN | MDIR;
143   - SSYNC();
144   - } else
145   - break;
146   - }
147   -
148   - /* If we were able to do something, reset timeout */
149   - if (int_stat)
150   - timebase = get_timer(0);
151   -
152   - } while (get_timer(timebase) < I2C_TIMEOUT);
153   -
154   - return msg->len;
155   -}
156   -
157   -/**
158   - * i2c_transfer - setup an i2c transfer
159   - * @return: 0 if things worked, non-0 if things failed
160   - *
161   - * Here we just get the i2c stuff all prepped and ready, and then tail off
162   - * into wait_for_completion() for all the bits to go.
163   - */
164   -static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags)
165   -{
166   - uchar addr_buffer[] = {
167   - (addr >> 0),
168   - (addr >> 8),
169   - (addr >> 16),
170   - };
171   - struct i2c_msg msg = {
172   - .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
173   - .buf = buffer,
174   - .len = len,
175   - .abuf = addr_buffer,
176   - .alen = alen,
177   - };
178   - int ret;
179   -
180   - dmemset(buffer, 0xff, len);
181   - debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ",
182   - chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr"));
183   -
184   - /* wait for things to settle */
185   - while (twi->master_stat & BUSBUSY)
186   - if (ctrlc())
187   - return 1;
188   -
189   - /* Set Transmit device address */
190   - twi->master_addr = chip;
191   -
192   - /* Clear the FIFO before starting things */
193   - twi->fifo_ctl = XMTFLUSH | RCVFLUSH;
194   - SSYNC();
195   - twi->fifo_ctl = 0;
196   - SSYNC();
197   -
198   - /* prime the pump */
199   - if (msg.alen) {
200   - len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
201   - debugi("first byte=0x%02x", *msg.abuf);
202   - twi->xmt_data8 = *(msg.abuf++);
203   - --msg.alen;
204   - } else if (!(msg.flags & I2C_M_READ) && msg.len) {
205   - debugi("first byte=0x%02x", *msg.buf);
206   - twi->xmt_data8 = *(msg.buf++);
207   - --msg.len;
208   - }
209   -
210   - /* clear int stat */
211   - twi->master_stat = -1;
212   - twi->int_stat = -1;
213   - twi->int_mask = 0;
214   - SSYNC();
215   -
216   - /* Master enable */
217   - twi->master_ctl =
218   - (twi->master_ctl & FAST) |
219   - (min(len, 0xff) << 6) | MEN |
220   - ((msg.flags & I2C_M_READ) ? MDIR : 0);
221   - SSYNC();
222   - debugi("CTL=0x%04x", twi->master_ctl);
223   -
224   - /* process the rest */
225   - ret = wait_for_completion(&msg);
226   - debugi("ret=%d", ret);
227   -
228   - if (ret) {
229   - twi->master_ctl &= ~MEN;
230   - twi->control &= ~TWI_ENA;
231   - SSYNC();
232   - twi->control |= TWI_ENA;
233   - SSYNC();
234   - }
235   -
236   - return ret;
237   -}
238   -
239   -/**
240   - * i2c_set_bus_speed - set i2c bus speed
241   - * @speed: bus speed (in HZ)
242   - */
243   -int i2c_set_bus_speed(unsigned int speed)
244   -{
245   - u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
246   -
247   - /* Set TWI interface clock */
248   - if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
249   - return -1;
250   - twi->clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
251   -
252   - /* Don't turn it on */
253   - twi->master_ctl = (speed > 100000 ? FAST : 0);
254   -
255   - return 0;
256   -}
257   -
258   -/**
259   - * i2c_get_bus_speed - get i2c bus speed
260   - * @speed: bus speed (in HZ)
261   - */
262   -unsigned int i2c_get_bus_speed(void)
263   -{
264   - /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */
265   - return 5000000 / (twi->clkdiv & 0xff);
266   -}
267   -
268   -/**
269   - * i2c_init - initialize the i2c bus
270   - * @speed: bus speed (in HZ)
271   - * @slaveaddr: address of device in slave mode (0 - not slave)
272   - *
273   - * Slave mode isn't actually implemented. It'll stay that way until
274   - * we get a real request for it.
275   - */
276   -void i2c_init(int speed, int slaveaddr)
277   -{
278   - uint8_t prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
279   -
280   - /* Set TWI internal clock as 10MHz */
281   - twi->control = prescale;
282   -
283   - /* Set TWI interface clock as specified */
284   - i2c_set_bus_speed(speed);
285   -
286   - /* Enable it */
287   - twi->control = TWI_ENA | prescale;
288   - SSYNC();
289   -
290   - debugi("CONTROL:0x%04x CLKDIV:0x%04x", twi->control, twi->clkdiv);
291   -
292   -#if CONFIG_SYS_I2C_SLAVE
293   -# error I2C slave support not tested/supported
294   - /* If they want us as a slave, do it */
295   - if (slaveaddr) {
296   - twi->slave_addr = slaveaddr;
297   - twi->slave_ctl = SEN;
298   - }
299   -#endif
300   -}
301   -
302   -/**
303   - * i2c_probe - test if a chip exists at a given i2c address
304   - * @chip: i2c chip addr to search for
305   - * @return: 0 if found, non-0 if not found
306   - */
307   -int i2c_probe(uchar chip)
308   -{
309   - u8 byte;
310   - return i2c_read(chip, 0, 0, &byte, 1);
311   -}
312   -
313   -/**
314   - * i2c_read - read data from an i2c device
315   - * @chip: i2c chip addr
316   - * @addr: memory (register) address in the chip
317   - * @alen: byte size of address
318   - * @buffer: buffer to store data read from chip
319   - * @len: how many bytes to read
320   - * @return: 0 on success, non-0 on failure
321   - */
322   -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
323   -{
324   - return i2c_transfer(chip, addr, alen, buffer, len, (alen ? I2C_M_COMBO : I2C_M_READ));
325   -}
326   -
327   -/**
328   - * i2c_write - write data to an i2c device
329   - * @chip: i2c chip addr
330   - * @addr: memory (register) address in the chip
331   - * @alen: byte size of address
332   - * @buffer: buffer holding data to write to chip
333   - * @len: how many bytes to write
334   - * @return: 0 on success, non-0 on failure
335   - */
336   -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
337   -{
338   - return i2c_transfer(chip, addr, alen, buffer, len, 0);
339   -}
340   -
341   -/**
342   - * i2c_set_bus_num - change active I2C bus
343   - * @bus: bus index, zero based
344   - * @returns: 0 on success, non-0 on failure
345   - */
346   -int i2c_set_bus_num(unsigned int bus)
347   -{
348   - switch (bus) {
349   -#if CONFIG_SYS_MAX_I2C_BUS > 0
350   - case 0: twi = (void *)TWI0_CLKDIV; return 0;
351   -#endif
352   -#if CONFIG_SYS_MAX_I2C_BUS > 1
353   - case 1: twi = (void *)TWI1_CLKDIV; return 0;
354   -#endif
355   -#if CONFIG_SYS_MAX_I2C_BUS > 2
356   - case 2: twi = (void *)TWI2_CLKDIV; return 0;
357   -#endif
358   - default: return -1;
359   - }
360   -}
361   -
362   -/**
363   - * i2c_get_bus_num - returns index of active I2C bus
364   - */
365   -unsigned int i2c_get_bus_num(void)
366   -{
367   - switch ((unsigned long)twi) {
368   -#if CONFIG_SYS_MAX_I2C_BUS > 0
369   - case TWI0_CLKDIV: return 0;
370   -#endif
371   -#if CONFIG_SYS_MAX_I2C_BUS > 1
372   - case TWI1_CLKDIV: return 1;
373   -#endif
374   -#if CONFIG_SYS_MAX_I2C_BUS > 2
375   - case TWI2_CLKDIV: return 2;
376   -#endif
377   - default: return -1;
378   - }
379   -}
include/configs/bct-brettl2.h
Diff comments   View file @ c44d3cd
... ... @@ -122,8 +122,8 @@
122 122 /*
123 123 * I2C Settings
124 124 */
125   -#define CONFIG_BFIN_TWI_I2C 1
126   -#define CONFIG_HARD_I2C 1
  125 +#define CONFIG_SYS_I2C
  126 +#define CONFIG_SYS_I2C_ADI
127 127  
128 128  
129 129 /*
include/configs/bf518f-ezbrd.h
Diff comments   View file @ c44d3cd
... ... @@ -134,8 +134,8 @@
134 134 /*
135 135 * I2C Settings
136 136 */
137   -#define CONFIG_BFIN_TWI_I2C 1
138   -#define CONFIG_HARD_I2C 1
  137 +#define CONFIG_SYS_I2C
  138 +#define CONFIG_SYS_I2C_ADI
139 139  
140 140  
141 141 /*
include/configs/bf526-ezbrd.h
Diff comments   View file @ c44d3cd
... ... @@ -131,8 +131,8 @@
131 131 /*
132 132 * I2C Settings
133 133 */
134   -#define CONFIG_BFIN_TWI_I2C 1
135   -#define CONFIG_HARD_I2C 1
  134 +#define CONFIG_SYS_I2C
  135 +#define CONFIG_SYS_I2C_ADI
136 136  
137 137  
138 138 /*
include/configs/bf527-ad7160-eval.h
Diff comments   View file @ c44d3cd
... ... @@ -119,8 +119,8 @@
119 119 /*
120 120 * I2C Settings
121 121 */
122   -#define CONFIG_BFIN_TWI_I2C 1
123   -#define CONFIG_HARD_I2C 1
  122 +#define CONFIG_SYS_I2C
  123 +#define CONFIG_SYS_I2C_ADI
124 124  
125 125  
126 126 /*
include/configs/bf527-ezkit.h
Diff comments   View file @ c44d3cd
... ... @@ -134,8 +134,8 @@
134 134 /*
135 135 * I2C Settings
136 136 */
137   -#define CONFIG_BFIN_TWI_I2C 1
138   -#define CONFIG_HARD_I2C 1
  137 +#define CONFIG_SYS_I2C
  138 +#define CONFIG_SYS_I2C_ADI
139 139  
140 140  
141 141 /*
include/configs/bf527-sdp.h
Diff comments   View file @ c44d3cd
... ... @@ -103,8 +103,8 @@
103 103 /*
104 104 * I2C Settings
105 105 */
106   -#define CONFIG_BFIN_TWI_I2C 1
107   -#define CONFIG_HARD_I2C 1
  106 +#define CONFIG_SYS_I2C
  107 +#define CONFIG_SYS_I2C_ADI
108 108  
109 109  
110 110 /*
include/configs/bf537-minotaur.h
Diff comments   View file @ c44d3cd
... ... @@ -121,8 +121,8 @@
121 121 /*
122 122 * I2C settings
123 123 */
124   -#define CONFIG_BFIN_TWI_I2C 1
125   -#define CONFIG_HARD_I2C 1
  124 +#define CONFIG_SYS_I2C
  125 +#define CONFIG_SYS_I2C_ADI
126 126 #define CONFIG_SYS_I2C_SPEED 50000
127 127 #define CONFIG_SYS_I2C_SLAVE 0
128 128  
include/configs/bf537-pnav.h
Diff comments   View file @ c44d3cd
... ... @@ -142,8 +142,8 @@
142 142 /*
143 143 * I2C settings
144 144 */
145   -#define CONFIG_BFIN_TWI_I2C 1
146   -#define CONFIG_HARD_I2C 1
  145 +#define CONFIG_SYS_I2C
  146 +#define CONFIG_SYS_I2C_ADI
147 147  
148 148  
149 149 /*
include/configs/bf537-srv1.h
Diff comments   View file @ c44d3cd
... ... @@ -120,8 +120,8 @@
120 120 /*
121 121 * I2C settings
122 122 */
123   -#define CONFIG_BFIN_TWI_I2C 1
124   -#define CONFIG_HARD_I2C 1
  123 +#define CONFIG_SYS_I2C
  124 +#define CONFIG_SYS_I2C_ADI
125 125 #define CONFIG_SYS_I2C_SPEED 50000
126 126 #define CONFIG_SYS_I2C_SLAVE 0
127 127  
include/configs/bf537-stamp.h
Diff comments   View file @ c44d3cd
... ... @@ -128,8 +128,8 @@
128 128 /*
129 129 * I2C Settings
130 130 */
131   -#define CONFIG_BFIN_TWI_I2C 1
132   -#define CONFIG_HARD_I2C 1
  131 +#define CONFIG_SYS_I2C
  132 +#define CONFIG_SYS_I2C_ADI
133 133  
134 134  
135 135 /*
include/configs/bf538f-ezkit.h
Diff comments   View file @ c44d3cd
... ... @@ -126,8 +126,8 @@
126 126 /*
127 127 * I2C Settings
128 128 */
129   -#define CONFIG_BFIN_TWI_I2C 1
130   -#define CONFIG_HARD_I2C 1
  129 +#define CONFIG_SYS_I2C
  130 +#define CONFIG_SYS_I2C_ADI
131 131  
132 132  
133 133 /*
include/configs/bf548-ezkit.h
Diff comments   View file @ c44d3cd
... ... @@ -134,8 +134,8 @@
134 134 /*
135 135 * I2C Settings
136 136 */
137   -#define CONFIG_BFIN_TWI_I2C 1
138   -#define CONFIG_HARD_I2C 1
  137 +#define CONFIG_SYS_I2C
  138 +#define CONFIG_SYS_I2C_ADI
139 139  
140 140  
141 141 /*
include/configs/bf609-ezkit.h
Diff comments   View file @ c44d3cd
... ... @@ -81,8 +81,8 @@
81 81 #define CONFIG_PHYLIB
82 82  
83 83 /* i2c Settings */
84   -#define CONFIG_BFIN_TWI_I2C
85   -#define CONFIG_HARD_I2C
  84 +#define CONFIG_SYS_I2C
  85 +#define CONFIG_SYS_I2C_ADI
86 86  
87 87 /*
88 88 * Flash Settings
include/configs/bfin_adi_common.h
Diff comments   View file @ c44d3cd
... ... @@ -73,7 +73,7 @@
73 73 # ifdef CONFIG_SPI_FLASH
74 74 # define CONFIG_CMD_SF
75 75 # endif
76   -# if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
  76 +# if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT)
77 77 # define CONFIG_CMD_I2C
78 78 # define CONFIG_SOFT_I2C_READ_REPEATED_START
79 79 # endif
... ... @@ -301,7 +301,7 @@
301 301 /*
302 302 * I2C Settings
303 303 */
304   -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
  304 +#if defined(CONFIG_SYS_I2C) || defined(CONFIG_SYS_I2C_SOFT)
305 305 # ifndef CONFIG_SYS_I2C_SPEED
306 306 # define CONFIG_SYS_I2C_SPEED 50000
307 307 # endif
include/configs/br4.h
Diff comments   View file @ c44d3cd
... ... @@ -102,8 +102,8 @@
102 102 /*
103 103 * I2C Settings
104 104 */
105   -#define CONFIG_BFIN_TWI_I2C
106   -#define CONFIG_HARD_I2C
  105 +#define CONFIG_SYS_I2C
  106 +#define CONFIG_SYS_I2C_ADI
107 107  
108 108  
109 109 /*
include/configs/cm-bf527.h
Diff comments   View file @ c44d3cd
... ... @@ -113,8 +113,8 @@
113 113 /*
114 114 * I2C Settings
115 115 */
116   -#define CONFIG_BFIN_TWI_I2C 1
117   -#define CONFIG_HARD_I2C 1
  116 +#define CONFIG_SYS_I2C
  117 +#define CONFIG_SYS_I2C_ADI
118 118  
119 119  
120 120 /*
include/configs/cm-bf537e.h
Diff comments   View file @ c44d3cd
... ... @@ -122,8 +122,8 @@
122 122 /*
123 123 * I2C Settings
124 124 */
125   -#define CONFIG_BFIN_TWI_I2C 1
126   -#define CONFIG_HARD_I2C 1
  125 +#define CONFIG_SYS_I2C
  126 +#define CONFIG_SYS_I2C_ADI
127 127  
128 128  
129 129 /*
include/configs/cm-bf537u.h
Diff comments   View file @ c44d3cd
... ... @@ -120,8 +120,8 @@
120 120 /*
121 121 * I2C Settings
122 122 */
123   -#define CONFIG_BFIN_TWI_I2C 1
124   -#define CONFIG_HARD_I2C 1
  123 +#define CONFIG_SYS_I2C
  124 +#define CONFIG_SYS_I2C_ADI
125 125  
126 126  
127 127 /*
include/configs/cm-bf548.h
Diff comments   View file @ c44d3cd
... ... @@ -104,8 +104,8 @@
104 104 /*
105 105 * I2C Settings
106 106 */
107   -#define CONFIG_BFIN_TWI_I2C 1
108   -#define CONFIG_HARD_I2C 1
  107 +#define CONFIG_SYS_I2C
  108 +#define CONFIG_SYS_I2C_ADI
109 109  
110 110  
111 111 /*
include/configs/pr1.h
Diff comments   View file @ c44d3cd
... ... @@ -102,8 +102,8 @@
102 102 /*
103 103 * I2C Settings
104 104 */
105   -#define CONFIG_BFIN_TWI_I2C
106   -#define CONFIG_HARD_I2C
  105 +#define CONFIG_SYS_I2C
  106 +#define CONFIG_SYS_I2C_ADI
107 107  
108 108  
109 109 /*
include/configs/tcm-bf518.h
Diff comments   View file @ c44d3cd
... ... @@ -103,8 +103,8 @@
103 103 /*
104 104 * I2C Settings
105 105 */
106   -#define CONFIG_BFIN_TWI_I2C 1
107   -#define CONFIG_HARD_I2C 1
  106 +#define CONFIG_SYS_I2C
  107 +#define CONFIG_SYS_I2C_ADI
108 108  
109 109  
110 110 /*
include/configs/tcm-bf537.h
Diff comments   View file @ c44d3cd
... ... @@ -122,8 +122,8 @@
122 122 /*
123 123 * I2C Settings
124 124 */
125   -#define CONFIG_BFIN_TWI_I2C 1
126   -#define CONFIG_HARD_I2C 1
  125 +#define CONFIG_SYS_I2C
  126 +#define CONFIG_SYS_I2C_ADI
127 127  
128 128  
129 129 /*