Eric Lee / smarc-uboot

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Commit c46bf09e0b567dda477da53163fe646e66c4912e

Authored by Thomas Weber
Committed by Anatolij Gustschin
1 parent 7e71dc6884
Exists in master and in 57 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

doc: Fix some typos in different files 

adresses/addresses
alernate/alternate
asssuming/assuming
calcualted/calculated
enviroment/environment
evalutation/evaluation
falsh/flash
labled/labeled
paramaters/parameters

Signed-off-by: Thomas Weber <thomas@tomweber.eu>
Acked-by: Anatolij Gustschin <agust@denx.de>

Showing 17 changed files with 26 additions and 26 deletions Inline Diff

doc/README.AVR32-port-muxing
Diff comments   View file @ c46bf09
1 AVR32 Port multiplexer configuration 1 AVR32 Port multiplexer configuration
2 ==================================== 2 ====================================
3 3
4 On AVR32 chips, most external I/O pins are routed through a port 4 On AVR32 chips, most external I/O pins are routed through a port
5 multiplexer. There are currently two kinds of port multiplexer 5 multiplexer. There are currently two kinds of port multiplexer
6 hardware around with different register interfaces: 6 hardware around with different register interfaces:
7 7
8 * PIO (AT32AP700x; this is also used on ARM AT91 chips) 8 * PIO (AT32AP700x; this is also used on ARM AT91 chips)
9 * GPIO (all other AVR32 chips) 9 * GPIO (all other AVR32 chips)
10 10
11 The "PIO" variant supports multiplexing up to two peripherals per pin 11 The "PIO" variant supports multiplexing up to two peripherals per pin
12 in addition to GPIO (software control). Each pin has configurable 12 in addition to GPIO (software control). Each pin has configurable
13 pull-up, glitch filter, interrupt and multi-drive capabilities. 13 pull-up, glitch filter, interrupt and multi-drive capabilities.
14 14
15 The "GPIO" variant supports multiplexing up to four peripherals per 15 The "GPIO" variant supports multiplexing up to four peripherals per
16 pin in addition to GPIO. Each pin has configurable 16 pin in addition to GPIO. Each pin has configurable
17 pull-up/pull-down/buskeeper, glitch filter, interrupt, open-drain and 17 pull-up/pull-down/buskeeper, glitch filter, interrupt, open-drain and
18 schmitt-trigger capabilities, as well as configurable drive strength 18 schmitt-trigger capabilities, as well as configurable drive strength
19 and slew rate control. 19 and slew rate control.
20 20
21 Both controllers are configured using the same API, but the functions 21 Both controllers are configured using the same API, but the functions
22 may accept different values for some parameters depending on the 22 may accept different values for some parameters depending on the
23 actual portmux implementation, and some parameters may be ignored by 23 actual portmux implementation, and some parameters may be ignored by
24 one of the implementation (e.g. the "PIO" implementation will ignore 24 one of the implementation (e.g. the "PIO" implementation will ignore
25 the drive strength flags since the hardware doesn't support 25 the drive strength flags since the hardware doesn't support
26 configurable drive strength.) 26 configurable drive strength.)
27 27
28 Selecting the portmux implementation 28 Selecting the portmux implementation
29 ------------------------------------ 29 ------------------------------------
30 Since u-boot is lacking a Kconfig-style configuration engine, the 30 Since u-boot is lacking a Kconfig-style configuration engine, the
31 portmux implementation must be selected manually by defining one of 31 portmux implementation must be selected manually by defining one of
32 the following symbols: 32 the following symbols:
33 33
34 CONFIG_PORTMUX_PIO 34 CONFIG_PORTMUX_PIO
35 CONFIG_PORTMUX_GPIO 35 CONFIG_PORTMUX_GPIO
36 36
37 depending on which implementation the chip in question uses. 37 depending on which implementation the chip in question uses.
38 38
39 Identifying pins 39 Identifying pins
40 ---------------- 40 ----------------
41 The portmux configuration functions described below identify the pins 41 The portmux configuration functions described below identify the pins
42 to act on based on two parameters: A "port" (i.e. a block of pins 42 to act on based on two parameters: A "port" (i.e. a block of pins
43 that somehow belong together) and a pin mask. Both are defined in an 43 that somehow belong together) and a pin mask. Both are defined in an
44 implementation-specific manner. 44 implementation-specific manner.
45 45
46 The available ports are defined on the form 46 The available ports are defined on the form
47 47
48 #define PORTMUX_PORT_A (something) 48 #define PORTMUX_PORT_A (something)
49 49
50 where "A" matches the identifier given in the chip's data sheet, and 50 where "A" matches the identifier given in the chip's data sheet, and
51 "something" is whatever the portmux implementation needs to identify 51 "something" is whatever the portmux implementation needs to identify
52 the port (usually a memory address). 52 the port (usually a memory address).
53 53
54 The pin mask is a bitmask where each '1' bit indicates a pin to apply 54 The pin mask is a bitmask where each '1' bit indicates a pin to apply
55 the current operation to. The width of the bitmask may vary from port 55 the current operation to. The width of the bitmask may vary from port
56 to port, but it is never wider than 32 bits (which is the width of 56 to port, but it is never wider than 32 bits (which is the width of
57 'unsigned long' on avr32). 57 'unsigned long' on avr32).
58 58
59 Selecting functions 59 Selecting functions
60 ------------------- 60 -------------------
61 Each pin can either be assigned to one of a predefined set of on-chip 61 Each pin can either be assigned to one of a predefined set of on-chip
62 peripherals, or it can be set up to be controlled by software. For the 62 peripherals, or it can be set up to be controlled by software. For the
63 former case, the portmux implementation defines an enum containing all 63 former case, the portmux implementation defines an enum containing all
64 the possible peripheral functions that can be selected. For example, 64 the possible peripheral functions that can be selected. For example,
65 the PIO implementation, which allows multiplexing two peripherals per 65 the PIO implementation, which allows multiplexing two peripherals per
66 pin, defines it like this: 66 pin, defines it like this:
67 67
68 enum portmux_function { 68 enum portmux_function {
69 PORTMUX_FUNC_A, 69 PORTMUX_FUNC_A,
70 PORTMUX_FUNC_B, 70 PORTMUX_FUNC_B,
71 }; 71 };
72 72
73 To configure a set of pins to be connected to a given peripheral 73 To configure a set of pins to be connected to a given peripheral
74 function, the following function is used. 74 function, the following function is used.
75 75
76 void portmux_select_peripheral(void *port, unsigned long pin_mask, 76 void portmux_select_peripheral(void *port, unsigned long pin_mask,
77 enum portmux_function func, unsigned long flags); 77 enum portmux_function func, unsigned long flags);
78 78
79 To configure a set of pins to be controlled by software (GPIO), the 79 To configure a set of pins to be controlled by software (GPIO), the
80 following function is used. In this case, no "function" argument is 80 following function is used. In this case, no "function" argument is
81 required since "GPIO" is a function in its own right. 81 required since "GPIO" is a function in its own right.
82 82
83 void portmux_select_gpio(void *port, unsigned int pin_mask, 83 void portmux_select_gpio(void *port, unsigned int pin_mask,
84 unsigned long flags); 84 unsigned long flags);
85 85
86 Both of these functions take a "flags" parameter which may be used to 86 Both of these functions take a "flags" parameter which may be used to
87 alter the default configuration of the pin. This is a bitmask of 87 alter the default configuration of the pin. This is a bitmask of
88 various flags defined in an implementation-specific way, but the names 88 various flags defined in an implementation-specific way, but the names
89 of the flags are the same on all implementations. 89 of the flags are the same on all implementations.
90 90
91 PORTMUX_DIR_OUTPUT 91 PORTMUX_DIR_OUTPUT
92 PORTMUX_DIR_INPUT 92 PORTMUX_DIR_INPUT
93 93
94 These mutually-exlusive flags configure the initial direction of the 94 These mutually-exclusive flags configure the initial direction of the
95 pins. PORTMUX_DIR_OUTPUT means that the pins are driven by the CPU, 95 pins. PORTMUX_DIR_OUTPUT means that the pins are driven by the CPU,
96 while PORTMUX_DIR_INPUT means that the pins are tristated by the CPU. 96 while PORTMUX_DIR_INPUT means that the pins are tristated by the CPU.
97 These flags are ignored by portmux_select_peripheral(). 97 These flags are ignored by portmux_select_peripheral().
98 98
99 PORTMUX_INIT_HIGH 99 PORTMUX_INIT_HIGH
100 PORTMUX_INIT_LOW 100 PORTMUX_INIT_LOW
101 101
102 These mutually-exclusive flags configure the initial state of the 102 These mutually-exclusive flags configure the initial state of the
103 pins: High (Vdd) or low (Vss). They are only effective when 103 pins: High (Vdd) or low (Vss). They are only effective when
104 portmux_select_gpio() is called with the PORTMUX_DIR_OUTPUT flag set. 104 portmux_select_gpio() is called with the PORTMUX_DIR_OUTPUT flag set.
105 105
106 PORTMUX_PULL_UP 106 PORTMUX_PULL_UP
107 PORTMUX_PULL_DOWN 107 PORTMUX_PULL_DOWN
108 PORTMUX_BUSKEEPER 108 PORTMUX_BUSKEEPER
109 109
110 These mutually-exclusive flags are used to enable any on-chip CMOS 110 These mutually-exclusive flags are used to enable any on-chip CMOS
111 resistors connected to the pins. PORTMUX_PULL_UP causes the pins to be 111 resistors connected to the pins. PORTMUX_PULL_UP causes the pins to be
112 pulled up to Vdd, PORTMUX_PULL_DOWN causes the pins to be pulled down 112 pulled up to Vdd, PORTMUX_PULL_DOWN causes the pins to be pulled down
113 to Vss, and PORTMUX_BUSKEEPER will keep the pins in whatever state 113 to Vss, and PORTMUX_BUSKEEPER will keep the pins in whatever state
114 they were left in by whatever was driving them last. If none of the 114 they were left in by whatever was driving them last. If none of the
115 flags are specified, the pins are left floating if no one are driving 115 flags are specified, the pins are left floating if no one are driving
116 them; this is only recommended for always-output pins (e.g. extern 116 them; this is only recommended for always-output pins (e.g. extern
117 address and control lines driven by the CPU.) 117 address and control lines driven by the CPU.)
118 118
119 Note that the "PIO" implementation will silently ignore the 119 Note that the "PIO" implementation will silently ignore the
120 PORTMUX_PULL_DOWN flag and interpret PORTMUX_BUSKEEPER as 120 PORTMUX_PULL_DOWN flag and interpret PORTMUX_BUSKEEPER as
121 PORTMUX_PULL_UP. 121 PORTMUX_PULL_UP.
122 122
123 PORTMUX_DRIVE_MIN 123 PORTMUX_DRIVE_MIN
124 PORTMUX_DRIVE_LOW 124 PORTMUX_DRIVE_LOW
125 PORTMUX_DRIVE_HIGH 125 PORTMUX_DRIVE_HIGH
126 PORTMUX_DRIVE_MAX 126 PORTMUX_DRIVE_MAX
127 127
128 These mutually-exlusive flags determine the drive strength of the 128 These mutually-exclusive flags determine the drive strength of the
129 pins. PORTMUX_DRIVE_MIN will give low power-consumption, but may cause 129 pins. PORTMUX_DRIVE_MIN will give low power-consumption, but may cause
130 corruption of high-speed signals. PORTMUX_DRIVE_MAX will give high 130 corruption of high-speed signals. PORTMUX_DRIVE_MAX will give high
131 power-consumption, but may be necessary on pins toggling at very high 131 power-consumption, but may be necessary on pins toggling at very high
132 speeds. PORTMUX_DRIVE_LOW and PORTMUX_DRIVE_HIGH specify something in 132 speeds. PORTMUX_DRIVE_LOW and PORTMUX_DRIVE_HIGH specify something in
133 between the other two. 133 between the other two.
134 134
135 Note that setting the drive strength too high may cause excessive 135 Note that setting the drive strength too high may cause excessive
136 overshoot and EMI problems, which may in turn cause signal corruption. 136 overshoot and EMI problems, which may in turn cause signal corruption.
137 Also note that the "PIO" implementation will silently ignore these 137 Also note that the "PIO" implementation will silently ignore these
138 flags. 138 flags.
139 139
140 PORTMUX_OPEN_DRAIN 140 PORTMUX_OPEN_DRAIN
141 141
142 This flag will configure the pins as "open drain", i.e. setting the 142 This flag will configure the pins as "open drain", i.e. setting the
143 pin state to 0 will drive it low, while setting it to 1 will leave it 143 pin state to 0 will drive it low, while setting it to 1 will leave it
144 floating (or, in most cases, let it be pulled high by an internal or 144 floating (or, in most cases, let it be pulled high by an internal or
145 external pull-up resistor.) In the data sheet for chips using the 145 external pull-up resistor.) In the data sheet for chips using the
146 "PIO" variant, this mode is called "multi-driver". 146 "PIO" variant, this mode is called "multi-driver".
147 147
148 Enabling specific peripherals 148 Enabling specific peripherals
149 ----------------------------- 149 -----------------------------
150 In addition to the above functions, each chip provides a set of 150 In addition to the above functions, each chip provides a set of
151 functions for setting up the port multiplexer to use a given 151 functions for setting up the port multiplexer to use a given
152 peripheral. The following are some of the functions available. 152 peripheral. The following are some of the functions available.
153 153
154 All the functions below take a "drive_strength" parameter, which must 154 All the functions below take a "drive_strength" parameter, which must
155 be one of the PORTMUX_DRIVE_x flags specified above. Any other 155 be one of the PORTMUX_DRIVE_x flags specified above. Any other
156 portmux flags will be silently filtered out. 156 portmux flags will be silently filtered out.
157 157
158 To set up the External Bus Interface (EBI), call 158 To set up the External Bus Interface (EBI), call
159 159
160 void portmux_enable_ebi(unsigned int bus_width, 160 void portmux_enable_ebi(unsigned int bus_width,
161 unsigned long flags, unsigned long drive_strength) 161 unsigned long flags, unsigned long drive_strength)
162 162
163 where "bus_width" must be either 16 or 32. "flags" can be any 163 where "bus_width" must be either 16 or 32. "flags" can be any
164 combination of the following flags. 164 combination of the following flags.
165 165
166 PORTMUX_EBI_CS(x) /* Enable chip select x */ 166 PORTMUX_EBI_CS(x) /* Enable chip select x */
167 PORTMUX_EBI_NAND /* Enable NAND flash interface */ 167 PORTMUX_EBI_NAND /* Enable NAND flash interface */
168 PORTMUX_EBI_CF(x) /* Enable CompactFlash interface x */ 168 PORTMUX_EBI_CF(x) /* Enable CompactFlash interface x */
169 PORTMUX_EBI_NWAIT /* Enable NWAIT signal */ 169 PORTMUX_EBI_NWAIT /* Enable NWAIT signal */
170 170
171 To set up a USART, call 171 To set up a USART, call
172 172
173 void portmux_enable_usartX(unsigned long drive_strength); 173 void portmux_enable_usartX(unsigned long drive_strength);
174 174
175 where X is replaced by the USART instance to be configured. 175 where X is replaced by the USART instance to be configured.
176 176
177 To set up an ethernet MAC: 177 To set up an ethernet MAC:
178 178
179 void portmux_enable_macbX(unsigned long flags, 179 void portmux_enable_macbX(unsigned long flags,
180 unsigned long drive_strength); 180 unsigned long drive_strength);
181 181
182 where X is replaced by the MACB instance to be configured. "flags" can 182 where X is replaced by the MACB instance to be configured. "flags" can
183 be any combination of the following flags. 183 be any combination of the following flags.
184 184
185 PORTMUX_MACB_RMII /* Just set up the RMII interface */ 185 PORTMUX_MACB_RMII /* Just set up the RMII interface */
186 PORTMUX_MACB_MII /* Set up full MII interface */ 186 PORTMUX_MACB_MII /* Set up full MII interface */
187 PORTMUX_MACB_SPEED /* Enable the SPEED pin */ 187 PORTMUX_MACB_SPEED /* Enable the SPEED pin */
188 188
189 To set up the MMC controller: 189 To set up the MMC controller:
190 190
191 void portmux_enable_mmci(unsigned long slot, unsigned long flags 191 void portmux_enable_mmci(unsigned long slot, unsigned long flags
192 unsigned long drive_strength); 192 unsigned long drive_strength);
193 193
194 where "slot" identifies which of the alternative SD card slots to 194 where "slot" identifies which of the alternative SD card slots to
195 enable. "flags" can be any combination of the following flags: 195 enable. "flags" can be any combination of the following flags:
196 196
197 PORTMUX_MMCI_4BIT /* Enable 4-bit SD card interface */ 197 PORTMUX_MMCI_4BIT /* Enable 4-bit SD card interface */
198 PORTMUX_MMCI_8BIT /* Enable 8-bit MMC+ interface */ 198 PORTMUX_MMCI_8BIT /* Enable 8-bit MMC+ interface */
199 PORTMUX_MMCI_EXT_PULLUP /* Board has external pull-ups */ 199 PORTMUX_MMCI_EXT_PULLUP /* Board has external pull-ups */
200 200
201 To set up a SPI controller: 201 To set up a SPI controller:
202 202
203 void portmux_enable_spiX(unsigned long cs_mask, 203 void portmux_enable_spiX(unsigned long cs_mask,
204 unsigned long drive_strength); 204 unsigned long drive_strength);
205 205
206 where X is replaced by the SPI instance to be configured. "cs_mask" is 206 where X is replaced by the SPI instance to be configured. "cs_mask" is
207 a 4-bit bitmask specifying which of the four standard chip select 207 a 4-bit bitmask specifying which of the four standard chip select
208 lines to set up as GPIOs. 208 lines to set up as GPIOs.
209 209
1 To use SNTP support, add define CONFIG_CMD_SNTP to the 1 To use SNTP support, add define CONFIG_CMD_SNTP to the
2 configuration file of the board. 2 configuration file of the board.
3 3
4 The "sntp" command gets network time from NTP time server and 4 The "sntp" command gets network time from NTP time server and
5 syncronize RTC of the board. This command needs the command line 5 syncronize RTC of the board. This command needs the command line
6 parameter of server's IP address or environment variable 6 parameter of server's IP address or environment variable
7 "ntpserverip". The network time is sent as UTC. So if you want to 7 "ntpserverip". The network time is sent as UTC. So if you want to
8 set local time to RTC, set the offset in second from UTC to the 8 set local time to RTC, set the offset in second from UTC to the
9 enviroment variable "time offset". 9 environment variable "time offset".
10 10
11 If the DHCP server provides time server's IP or time offset, you 11 If the DHCP server provides time server's IP or time offset, you
12 don't need to set the above environment variables yourself. 12 don't need to set the above environment variables yourself.
13 13
14 Current limitations of SNTP support: 14 Current limitations of SNTP support:
15 1. The roundtrip time is ignored. 15 1. The roundtrip time is ignored.
16 2. Only the 1st NTP server IP, in the option ntp-servers of DHCP, will 16 2. Only the 1st NTP server IP, in the option ntp-servers of DHCP, will
17 be used. 17 be used.
18 18
doc/README.Sandpoint8240
Diff comments   View file @ c46bf09
1 The port was tested on a Sandpoint 8240 X3 board, with U-Boot 1 The port was tested on a Sandpoint 8240 X3 board, with U-Boot
2 installed in the flash memory of the CPU card. Please use the 2 installed in the flash memory of the CPU card. Please use the
3 following DIP switch settings: 3 following DIP switch settings:
4 4
5 Motherboard: 5 Motherboard:
6 6
7 SW1.1: on SW1.2: on SW1.3: on SW1.4: on 7 SW1.1: on SW1.2: on SW1.3: on SW1.4: on
8 SW1.5: on SW1.6: on SW1.7: on SW1.8: on 8 SW1.5: on SW1.6: on SW1.7: on SW1.8: on
9 9
10 SW2.1: on SW2.2: on SW2.3: on SW2.4: on 10 SW2.1: on SW2.2: on SW2.3: on SW2.4: on
11 SW2.5: on SW2.6: on SW2.7: on SW2.8: on 11 SW2.5: on SW2.6: on SW2.7: on SW2.8: on
12 12
13 13
14 CPU Card: 14 CPU Card:
15 15
16 SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on 16 SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on
17 SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF 17 SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF
18 18
19 SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF 19 SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF
20 SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on 20 SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on
21 21
22 22
23 The followind detailed description of installation and initial steps 23 The followind detailed description of installation and initial steps
24 with U-Boot and QNX was provided by Jim Sandoz <sandoz@lucent.com>: 24 with U-Boot and QNX was provided by Jim Sandoz <sandoz@lucent.com>:
25 25
26 26
27 Directions for installing U-Boot on Sandpoint+Unity8240 27 Directions for installing U-Boot on Sandpoint+Unity8240
28 using the Abatron BDI2000 BDM/JTAG debugger ... 28 using the Abatron BDI2000 BDM/JTAG debugger ...
29 29
30 Background and Reference info: 30 Background and Reference info:
31 http://u-boot.sourceforge.net/ 31 http://u-boot.sourceforge.net/
32 http://www.abatron.ch/ 32 http://www.abatron.ch/
33 http://www.abatron.ch/BDI/bdihw.html 33 http://www.abatron.ch/BDI/bdihw.html
34 http://www.abatron.ch/DataSheets/BDI2000.pdf 34 http://www.abatron.ch/DataSheets/BDI2000.pdf
35 http://www.abatron.ch/Manuals/ManGdbCOP-2000C.pdf 35 http://www.abatron.ch/Manuals/ManGdbCOP-2000C.pdf
36 http://e-www.motorola.com/collateral/SPX3UM.pdf 36 http://e-www.motorola.com/collateral/SPX3UM.pdf
37 http://e-www.motorola.com/collateral/UNITYX4CONFIG.pdf 37 http://e-www.motorola.com/collateral/UNITYX4CONFIG.pdf
38 38
39 39
40 Connection Diagram: 40 Connection Diagram:
41 =========== 41 ===========
42 === ===== |----- | 42 === ===== |----- |
43 | | <---------------> | | | | | 43 | | <---------------> | | | | |
44 |PC | rs232 | BDI |=============[] | | 44 |PC | rs232 | BDI |=============[] | |
45 | | |2000 | BDM probe | | | 45 | | |2000 | BDM probe | | |
46 | | <---------------> | | |----- | 46 | | <---------------> | | |----- |
47 === ethernet ===== | | 47 === ethernet ===== | |
48 | | 48 | |
49 =========== 49 ===========
50 Sandpoint X3 with 50 Sandpoint X3 with
51 Unity 8240 proc 51 Unity 8240 proc
52 52
53 53
54 PART 1) 54 PART 1)
55 DIP Switch Settings: 55 DIP Switch Settings:
56 56
57 Sandpoint X3 8240 processor board DIP switch settings, with 57 Sandpoint X3 8240 processor board DIP switch settings, with
58 U-Boot to be installed in the flash memory of the CPU card: 58 U-Boot to be installed in the flash memory of the CPU card:
59 59
60 Motorola Sandpoint X3 Motherboard: 60 Motorola Sandpoint X3 Motherboard:
61 SW1.1: on SW1.2: on SW1.3: on SW1.4: on 61 SW1.1: on SW1.2: on SW1.3: on SW1.4: on
62 SW1.5: on SW1.6: on SW1.7: on SW1.8: on 62 SW1.5: on SW1.6: on SW1.7: on SW1.8: on
63 SW2.1: on SW2.2: on SW2.3: on SW2.4: on 63 SW2.1: on SW2.2: on SW2.3: on SW2.4: on
64 SW2.5: on SW2.6: on SW2.7: on SW2.8: on 64 SW2.5: on SW2.6: on SW2.7: on SW2.8: on
65 65
66 Motorola Unity 8240 CPU Card: 66 Motorola Unity 8240 CPU Card:
67 SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on 67 SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on
68 SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF 68 SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF
69 SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF 69 SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF
70 SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on 70 SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on
71 71
72 72
73 PART 2) 73 PART 2)
74 Connect the BDI2000 Cable to the Sandpoint/Unity 8240: 74 Connect the BDI2000 Cable to the Sandpoint/Unity 8240:
75 75
76 BDM Pin 1 on the Unity 8240 processor board is towards the 76 BDM Pin 1 on the Unity 8240 processor board is towards the
77 PCI PMC connectors, or away from the socketed SDRAM, i.e.: 77 PCI PMC connectors, or away from the socketed SDRAM, i.e.:
78 78
79 ==================== 79 ====================
80 | ---------------- | 80 | ---------------- |
81 | | SDRAM | | 81 | | SDRAM | |
82 | | | | 82 | | | |
83 | ---------------- | 83 | ---------------- |
84 | |~| | 84 | |~| |
85 | |B| ++++++ | 85 | |B| ++++++ |
86 | |D| + uP + | 86 | |D| + uP + |
87 | |M| +8240+ | 87 | |M| +8240+ |
88 | ~ 1 ++++++ | 88 | ~ 1 ++++++ |
89 | | 89 | |
90 | | 90 | |
91 | | 91 | |
92 | PMC conn ====== | 92 | PMC conn ====== |
93 | ===== ====== | 93 | ===== ====== |
94 | | 94 | |
95 ==================== 95 ====================
96 96
97 97
98 PART 3) 98 PART 3)
99 Setting up the BDI2000, and preparing for TCP/IP network comms: 99 Setting up the BDI2000, and preparing for TCP/IP network comms:
100 100
101 Connect the BDI2000 to the PC using the supplied serial cable. 101 Connect the BDI2000 to the PC using the supplied serial cable.
102 Download the BDI2000 software and install it using setup.exe. 102 Download the BDI2000 software and install it using setup.exe.
103 103
104 [Note: of course you can also use the Linux command line tool 104 [Note: of course you can also use the Linux command line tool
105 "bdisetup" to configure your BDI2000 - the sources are included on 105 "bdisetup" to configure your BDI2000 - the sources are included on
106 the floppy disk that comes with your BDI2000. Just in case you don't 106 the floppy disk that comes with your BDI2000. Just in case you don't
107 have any Windows PC's - like me :-) -- wd ] 107 have any Windows PC's - like me :-) -- wd ]
108 108
109 Power up the BDI2000; then follow directions to assign the IP 109 Power up the BDI2000; then follow directions to assign the IP
110 address and related network information. Note that U-Boot 110 address and related network information. Note that U-Boot
111 will be loaded to the Sandpoint via tftp. You need to either 111 will be loaded to the Sandpoint via tftp. You need to either
112 use the Abatron-provided tftp application or provide a tftp 112 use the Abatron-provided tftp application or provide a tftp
113 server (e.g. Linux/Solaris/*BSD) somewhere on your network. 113 server (e.g. Linux/Solaris/*BSD) somewhere on your network.
114 Once the IP address etc are assigned via the RS232 port, 114 Once the IP address etc are assigned via the RS232 port,
115 further communication with the BDI2000 will happen via the 115 further communication with the BDI2000 will happen via the
116 ethernet connection. 116 ethernet connection.
117 117
118 PART 4) 118 PART 4)
119 Making a TCP/IP network connection to the Abatron BDI2000: 119 Making a TCP/IP network connection to the Abatron BDI2000:
120 120
121 Telnet to the Abatron BDI2000. Assuming that all of the 121 Telnet to the Abatron BDI2000. Assuming that all of the
122 networking info was loaded via RS232 correctly, you will see 122 networking info was loaded via RS232 correctly, you will see
123 the following (scrolling): 123 the following (scrolling):
124 124
125 - TARGET: waiting for target Vcc 125 - TARGET: waiting for target Vcc
126 - TARGET: waiting for target Vcc 126 - TARGET: waiting for target Vcc
127 127
128 128
129 PART 5) 129 PART 5)
130 Power up the target Sandpoint: 130 Power up the target Sandpoint:
131 If the BDM connections are correct, the following will now appear: 131 If the BDM connections are correct, the following will now appear:
132 132
133 - TARGET: waiting for target Vcc 133 - TARGET: waiting for target Vcc
134 - TARGET: waiting for target Vcc 134 - TARGET: waiting for target Vcc
135 - TARGET: processing power-up delay 135 - TARGET: processing power-up delay
136 - TARGET: processing user reset request 136 - TARGET: processing user reset request
137 - BDI asserts HRESET 137 - BDI asserts HRESET
138 - Reset JTAG controller passed 138 - Reset JTAG controller passed
139 - Bypass check: 0x55 => 0xAA 139 - Bypass check: 0x55 => 0xAA
140 - Bypass check: 0x55 => 0xAA 140 - Bypass check: 0x55 => 0xAA
141 - JTAG exists check passed 141 - JTAG exists check passed
142 - Target PVR is 0x00810101 142 - Target PVR is 0x00810101
143 - COP status is 0x01 143 - COP status is 0x01
144 - Check running state passed 144 - Check running state passed
145 - BDI scans COP freeze command 145 - BDI scans COP freeze command
146 - BDI removes HRESET 146 - BDI removes HRESET
147 - COP status is 0x05 147 - COP status is 0x05
148 - Check stopped state passed 148 - Check stopped state passed
149 - Check LSRL length passed 149 - Check LSRL length passed
150 - BDI sets breakpoint at 0xFFF00100 150 - BDI sets breakpoint at 0xFFF00100
151 - BDI resumes program execution 151 - BDI resumes program execution
152 - Waiting for target stop passed 152 - Waiting for target stop passed
153 - TARGET: Target PVR is 0x00810101 153 - TARGET: Target PVR is 0x00810101
154 - TARGET: reseting target passed 154 - TARGET: reseting target passed
155 - TARGET: processing target startup .... 155 - TARGET: processing target startup ....
156 - TARGET: processing target startup passed 156 - TARGET: processing target startup passed
157 BDI> 157 BDI>
158 158
159 159
160 PART 6) 160 PART 6)
161 Erase the current contents of the flash memory: 161 Erase the current contents of the flash memory:
162 162
163 BDI>era 0xFFF00000 163 BDI>era 0xFFF00000
164 Erasing flash at 0xfff00000 164 Erasing flash at 0xfff00000
165 Erasing flash passed 165 Erasing flash passed
166 BDI>era 0xFFF04000 166 BDI>era 0xFFF04000
167 Erasing flash at 0xfff04000 167 Erasing flash at 0xfff04000
168 Erasing flash passed 168 Erasing flash passed
169 BDI>era 0xFFF06000 169 BDI>era 0xFFF06000
170 Erasing flash at 0xfff06000 170 Erasing flash at 0xfff06000
171 Erasing flash passed 171 Erasing flash passed
172 BDI>era 0xFFF08000 172 BDI>era 0xFFF08000
173 Erasing flash at 0xfff08000 173 Erasing flash at 0xfff08000
174 Erasing flash passed 174 Erasing flash passed
175 BDI>era 0xFFF10000 175 BDI>era 0xFFF10000
176 Erasing flash at 0xfff10000 176 Erasing flash at 0xfff10000
177 Erasing flash passed 177 Erasing flash passed
178 BDI>era 0xFFF20000 178 BDI>era 0xFFF20000
179 Erasing flash at 0xfff20000 179 Erasing flash at 0xfff20000
180 Erasing flash passed 180 Erasing flash passed
181 181
182 182
183 PART 7) 183 PART 7)
184 Program the flash memory with the U-Boot image: 184 Program the flash memory with the U-Boot image:
185 185
186 BDI>prog 0xFFF00000 u-boot.bin bin 186 BDI>prog 0xFFF00000 u-boot.bin bin
187 Programming u-boot.bin , please wait .... 187 Programming u-boot.bin , please wait ....
188 Programming flash passed 188 Programming flash passed
189 189
190 190
191 PART 8) 191 PART 8)
192 Connect PC to Sandpoint: 192 Connect PC to Sandpoint:
193 Using a crossover serial cable, attach the PC serial port to the 193 Using a crossover serial cable, attach the PC serial port to the
194 Sandpoint's COM1. Set communications parameters to 8N1 / 9600 baud. 194 Sandpoint's COM1. Set communications parameters to 8N1 / 9600 baud.
195 195
196 196
197 PART 9) 197 PART 9)
198 Reset the Unity and begin U-Boot execution: 198 Reset the Unity and begin U-Boot execution:
199 199
200 BDI>reset 200 BDI>reset
201 - TARGET: processing user reset request 201 - TARGET: processing user reset request
202 - TARGET: Target PVR is 0x00810101 202 - TARGET: Target PVR is 0x00810101
203 - TARGET: reseting target passed 203 - TARGET: reseting target passed
204 - TARGET: processing target init list .... 204 - TARGET: processing target init list ....
205 - TARGET: processing target init list passed 205 - TARGET: processing target init list passed
206 206
207 BDI>go 207 BDI>go
208 208
209 Now see output from U-Boot running, sent via serial port: 209 Now see output from U-Boot running, sent via serial port:
210 210
211 U-Boot 1.1.4 (Jan 23 2002 - 18:29:19) 211 U-Boot 1.1.4 (Jan 23 2002 - 18:29:19)
212 212
213 CPU: MPC8240 Revision 1.1 at 264 MHz: 16 kB I-Cache 16 kB D-Cache 213 CPU: MPC8240 Revision 1.1 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
214 Board: Sandpoint 8240 Unity 214 Board: Sandpoint 8240 Unity
215 DRAM: 64 MB 215 DRAM: 64 MB
216 FLASH: 2 MB 216 FLASH: 2 MB
217 PCI: scanning bus0 ... 217 PCI: scanning bus0 ...
218 bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE 218 bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE
219 00 00 00 1057 0003 060000 13 00000008 00000000 01 00 219 00 00 00 1057 0003 060000 13 00000008 00000000 01 00
220 00 0b 00 10ad 0565 060100 10 00000000 00000000 00 00 220 00 0b 00 10ad 0565 060100 10 00000000 00000000 00 00
221 00 0f 00 8086 1229 020000 08 80000000 80000001 01 00 221 00 0f 00 8086 1229 020000 08 80000000 80000001 01 00
222 In: serial 222 In: serial
223 Out: serial 223 Out: serial
224 Err: serial 224 Err: serial
225 => 225 =>
226 226
227 227
228 PART 10) 228 PART 10)
229 Set and save any required environmental variables, examples of some: 229 Set and save any required environmental variables, examples of some:
230 230
231 => setenv ethaddr 00:03:47:97:D0:79 231 => setenv ethaddr 00:03:47:97:D0:79
232 => setenv bootfile your_qnx_image_here 232 => setenv bootfile your_qnx_image_here
233 => setenv hostname sandpointX 233 => setenv hostname sandpointX
234 => setenv netmask 255.255.255.0 234 => setenv netmask 255.255.255.0
235 => setenv ipaddr 192.168.0.11 235 => setenv ipaddr 192.168.0.11
236 => setenv serverip 192.168.0.10 236 => setenv serverip 192.168.0.10
237 => setenv gatewayip=192.168.0.1 237 => setenv gatewayip=192.168.0.1
238 => saveenv 238 => saveenv
239 Saving Enviroment to Flash... 239 Saving Environment to Flash...
240 Un-Protected 1 sectors 240 Un-Protected 1 sectors
241 Erasing Flash... 241 Erasing Flash...
242 done 242 done
243 Erased 1 sectors 243 Erased 1 sectors
244 Writing to Flash... done 244 Writing to Flash... done
245 Protected 1 sectors 245 Protected 1 sectors
246 => 246 =>
247 247
248 **** Example environment: **** 248 **** Example environment: ****
249 249
250 => printenv 250 => printenv
251 baudrate=9600 251 baudrate=9600
252 bootfile=telemetry 252 bootfile=telemetry
253 hostname=sp1 253 hostname=sp1
254 ethaddr=00:03:47:97:E4:6B 254 ethaddr=00:03:47:97:E4:6B
255 load=tftp 100000 u-boot.bin 255 load=tftp 100000 u-boot.bin
256 update=protect off all;era FFF00000 FFF3FFFF;cp.b 100000 FFF00000 ${filesize};saveenv 256 update=protect off all;era FFF00000 FFF3FFFF;cp.b 100000 FFF00000 ${filesize};saveenv
257 filesize=1f304 257 filesize=1f304
258 gatewayip=145.17.228.1 258 gatewayip=145.17.228.1
259 netmask=255.255.255.0 259 netmask=255.255.255.0
260 ipaddr=145.17.228.42 260 ipaddr=145.17.228.42
261 serverip=145.17.242.46 261 serverip=145.17.242.46
262 stdin=serial 262 stdin=serial
263 stdout=serial 263 stdout=serial
264 stderr=serial 264 stderr=serial
265 265
266 Environment size: 332/8188 bytes 266 Environment size: 332/8188 bytes
267 => 267 =>
268 268
269 here's some text useful stuff for cut-n-paste: 269 here's some text useful stuff for cut-n-paste:
270 setenv hostname sandpoint1 270 setenv hostname sandpoint1
271 setenv netmask 255.255.255.0 271 setenv netmask 255.255.255.0
272 setenv ipaddr 145.17.228.81 272 setenv ipaddr 145.17.228.81
273 setenv serverip 145.17.242.46 273 setenv serverip 145.17.242.46
274 setenv gatewayip 145.17.228.1 274 setenv gatewayip 145.17.228.1
275 saveenv 275 saveenv
276 276
277 PART 11) 277 PART 11)
278 Test U-Boot by tftp'ing new U-Boot, overwriting current: 278 Test U-Boot by tftp'ing new U-Boot, overwriting current:
279 279
280 => protect off all 280 => protect off all
281 Un-Protect Flash Bank # 1 281 Un-Protect Flash Bank # 1
282 => tftp 100000 u-boot.bin 282 => tftp 100000 u-boot.bin
283 eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) 283 eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
284 ARP broadcast 1 284 ARP broadcast 1
285 TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through 285 TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
286 gateway 145.17.228.1 286 gateway 145.17.228.1
287 Filename 'u-boot.bin'. 287 Filename 'u-boot.bin'.
288 Load address: 0x100000 288 Load address: 0x100000
289 Loading: ######################### 289 Loading: #########################
290 done 290 done
291 Bytes transferred = 127628 (1f28c hex) 291 Bytes transferred = 127628 (1f28c hex)
292 => era all 292 => era all
293 Erase Flash Bank # 1 293 Erase Flash Bank # 1
294 done 294 done
295 Erase Flash Bank # 2 - missing 295 Erase Flash Bank # 2 - missing
296 => cp.b 0x100000 FFF00000 1f28c 296 => cp.b 0x100000 FFF00000 1f28c
297 Copy to Flash... done 297 Copy to Flash... done
298 => saveenv 298 => saveenv
299 Saving Enviroment to Flash... 299 Saving Environment to Flash...
300 Un-Protected 1 sectors 300 Un-Protected 1 sectors
301 Erasing Flash... 301 Erasing Flash...
302 done 302 done
303 Erased 1 sectors 303 Erased 1 sectors
304 Writing to Flash... done 304 Writing to Flash... done
305 Protected 1 sectors 305 Protected 1 sectors
306 => reset 306 => reset
307 307
308 You can put these commands into some environment variables; 308 You can put these commands into some environment variables;
309 309
310 => setenv load tftp 100000 u-boot.bin 310 => setenv load tftp 100000 u-boot.bin
311 => setenv update protect off all\;era FFF00000 FFF3FFFF\;cp.b 100000 FFF00000 \${filesize}\;saveenv 311 => setenv update protect off all\;era FFF00000 FFF3FFFF\;cp.b 100000 FFF00000 \${filesize}\;saveenv
312 => saveenv 312 => saveenv
313 313
314 Then you just have to type "run load" then "run update" 314 Then you just have to type "run load" then "run update"
315 315
316 => run load 316 => run load
317 eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) 317 eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
318 ARP broadcast 1 318 ARP broadcast 1
319 TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through 319 TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
320 gateway 145.17.228.1 320 gateway 145.17.228.1
321 Filename 'u-boot.bin'. 321 Filename 'u-boot.bin'.
322 Load address: 0x100000 322 Load address: 0x100000
323 Loading: ######################### 323 Loading: #########################
324 done 324 done
325 Bytes transferred = 127748 (1f304 hex) 325 Bytes transferred = 127748 (1f304 hex)
326 => run update 326 => run update
327 Un-Protect Flash Bank # 1 327 Un-Protect Flash Bank # 1
328 Un-Protect Flash Bank # 2 328 Un-Protect Flash Bank # 2
329 Erase Flash from 0xfff00000 to 0xfff3ffff 329 Erase Flash from 0xfff00000 to 0xfff3ffff
330 done 330 done
331 Erased 7 sectors 331 Erased 7 sectors
332 Copy to Flash... done 332 Copy to Flash... done
333 Saving Enviroment to Flash... 333 Saving Environment to Flash...
334 Un-Protected 1 sectors 334 Un-Protected 1 sectors
335 Erasing Flash... 335 Erasing Flash...
336 done 336 done
337 Erased 1 sectors 337 Erased 1 sectors
338 Writing to Flash... done 338 Writing to Flash... done
339 Protected 1 sectors 339 Protected 1 sectors
340 => 340 =>
341 341
342 342
343 PART 12) 343 PART 12)
344 Load OS image (ELF format) via U-Boot using tftp 344 Load OS image (ELF format) via U-Boot using tftp
345 345
346 346
347 => tftp 800000 sandpoint-simple.elf 347 => tftp 800000 sandpoint-simple.elf
348 eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) 348 eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0)
349 ARP broadcast 1 349 ARP broadcast 1
350 TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through 350 TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through
351 gateway 145.17.228.1 351 gateway 145.17.228.1
352 Filename 'sandpoint-simple.elf'. 352 Filename 'sandpoint-simple.elf'.
353 Load address: 0x800000 353 Load address: 0x800000
354 Loading: ################################################################# 354 Loading: #################################################################
355 ################################################################# 355 #################################################################
356 ################################################################# 356 #################################################################
357 ######################## 357 ########################
358 done 358 done
359 Bytes transferred = 1120284 (11181c hex) 359 Bytes transferred = 1120284 (11181c hex)
360 ==> 360 ==>
361 361
362 PART 13) 362 PART 13)
363 Begin OS image execution: (note that unless you have the 363 Begin OS image execution: (note that unless you have the
364 serial parameters of your OS image set to 9600 (i.e. same as 364 serial parameters of your OS image set to 9600 (i.e. same as
365 the U-Boot binary) you will get garbage here until you change 365 the U-Boot binary) you will get garbage here until you change
366 the serial communications speed. 366 the serial communications speed.
367 367
368 => bootelf 800000 368 => bootelf 800000
369 Loading @ 0x001f0100 (1120028 bytes) 369 Loading @ 0x001f0100 (1120028 bytes)
370 ## Starting application at 0x001f1d28 ... 370 ## Starting application at 0x001f1d28 ...
371 Replace init_hwinfo() with a board specific version 371 Replace init_hwinfo() with a board specific version
372 372
373 Loading QNX6.... 373 Loading QNX6....
374 374
375 Header size=0x0000009c, Total Size=0x000005c0, #Cpu=1, Type=1 375 Header size=0x0000009c, Total Size=0x000005c0, #Cpu=1, Type=1
376 <...loader and kernel messages snipped...> 376 <...loader and kernel messages snipped...>
377 377
378 Welcome to Neutrino on the Sandpoint 378 Welcome to Neutrino on the Sandpoint
379 # 379 #
380 380
381 381
382 other information: 382 other information:
383 383
384 CVS Retrieval Notes: 384 CVS Retrieval Notes:
385 385
386 U-Boot's SourceForge CVS repository can be checked out 386 U-Boot's SourceForge CVS repository can be checked out
387 through anonymous (pserver) CVS with the following 387 through anonymous (pserver) CVS with the following
388 instruction set. The module you wish to check out must 388 instruction set. The module you wish to check out must
389 be specified as the modulename. When prompted for a 389 be specified as the modulename. When prompted for a
390 password for anonymous, simply press the Enter key. 390 password for anonymous, simply press the Enter key.
391 391
392 cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login 392 cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login
393 393
394 cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot 394 cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot
395 395
1 Atmel AT91 Evaluation kits 1 Atmel AT91 Evaluation kits
2 2
3 http://atmel.com/dyn/products/tools.asp?family_id=605#1443 3 http://atmel.com/dyn/products/tools.asp?family_id=605#1443
4 4
5 I. Board mapping & boot media 5 I. Board mapping & boot media
6 ------------------------------------------------------------------------------ 6 ------------------------------------------------------------------------------
7 AT91SAM9260EK, AT91SAM9G20EK & AT91SAM9XEEK 7 AT91SAM9260EK, AT91SAM9G20EK & AT91SAM9XEEK
8 ------------------------------------------------------------------------------ 8 ------------------------------------------------------------------------------
9 9
10 Memory map 10 Memory map
11 0x20000000 - 23FFFFFF SDRAM (64 MB) 11 0x20000000 - 23FFFFFF SDRAM (64 MB)
12 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J13) 12 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J13)
13 0xD0000000 - Dxxxxxxx Soldered Atmel Dataflash 13 0xD0000000 - Dxxxxxxx Soldered Atmel Dataflash
14 14
15 Environment variables 15 Environment variables
16 16
17 U-Boot environment variables can be stored at different places: 17 U-Boot environment variables can be stored at different places:
18 - Dataflash on SPI chip select 1 (default) 18 - Dataflash on SPI chip select 1 (default)
19 - Dataflash on SPI chip select 0 (dataflash card) 19 - Dataflash on SPI chip select 0 (dataflash card)
20 - Nand flash. 20 - Nand flash.
21 21
22 You can choose your storage location at config step (here for at91sam9260ek) : 22 You can choose your storage location at config step (here for at91sam9260ek) :
23 make at91sam9260ek_config - use data flash (spi cs1) (default) 23 make at91sam9260ek_config - use data flash (spi cs1) (default)
24 make at91sam9260ek_nandflash_config - use nand flash 24 make at91sam9260ek_nandflash_config - use nand flash
25 make at91sam9260ek_dataflash_cs0_config - use data flash (spi cs0) 25 make at91sam9260ek_dataflash_cs0_config - use data flash (spi cs0)
26 make at91sam9260ek_dataflash_cs1_config - use data flash (spi cs1) 26 make at91sam9260ek_dataflash_cs1_config - use data flash (spi cs1)
27 27
28 28
29 ------------------------------------------------------------------------------ 29 ------------------------------------------------------------------------------
30 AT91SAM9261EK, AT91SAM9G10EK 30 AT91SAM9261EK, AT91SAM9G10EK
31 ------------------------------------------------------------------------------ 31 ------------------------------------------------------------------------------
32 32
33 Memory map 33 Memory map
34 0x20000000 - 23FFFFFF SDRAM (64 MB) 34 0x20000000 - 23FFFFFF SDRAM (64 MB)
35 0xC0000000 - Cxxxxxxx Soldered Atmel Dataflash 35 0xC0000000 - Cxxxxxxx Soldered Atmel Dataflash
36 0xD0000000 - Dxxxxxxx Atmel Dataflash card (J22) 36 0xD0000000 - Dxxxxxxx Atmel Dataflash card (J22)
37 37
38 Environment variables 38 Environment variables
39 39
40 U-Boot environment variables can be stored at different places: 40 U-Boot environment variables can be stored at different places:
41 - Dataflash on SPI chip select 0 (default) 41 - Dataflash on SPI chip select 0 (default)
42 - Dataflash on SPI chip select 3 (dataflash card) 42 - Dataflash on SPI chip select 3 (dataflash card)
43 - Nand flash. 43 - Nand flash.
44 44
45 You can choose your storage location at config step (here for at91sam9260ek) : 45 You can choose your storage location at config step (here for at91sam9260ek) :
46 make at91sam9261ek_config - use data flash (spi cs0) (default) 46 make at91sam9261ek_config - use data flash (spi cs0) (default)
47 make at91sam9261ek_nandflash_config - use nand flash 47 make at91sam9261ek_nandflash_config - use nand flash
48 make at91sam9261ek_dataflash_cs0_config - use data flash (spi cs0) 48 make at91sam9261ek_dataflash_cs0_config - use data flash (spi cs0)
49 make at91sam9261ek_dataflash_cs3_config - use data flash (spi cs3) 49 make at91sam9261ek_dataflash_cs3_config - use data flash (spi cs3)
50 50
51 51
52 ------------------------------------------------------------------------------ 52 ------------------------------------------------------------------------------
53 AT91SAM9263EK 53 AT91SAM9263EK
54 ------------------------------------------------------------------------------ 54 ------------------------------------------------------------------------------
55 55
56 Memory map 56 Memory map
57 0x20000000 - 23FFFFFF SDRAM (64 MB) 57 0x20000000 - 23FFFFFF SDRAM (64 MB)
58 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J9) 58 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J9)
59 59
60 Environment variables 60 Environment variables
61 61
62 U-Boot environment variables can be stored at different places: 62 U-Boot environment variables can be stored at different places:
63 - Dataflash on SPI chip select 0 (dataflash card) 63 - Dataflash on SPI chip select 0 (dataflash card)
64 - Nand flash. 64 - Nand flash.
65 - Nor falsh (not populate by default) 65 - Nor flash (not populate by default)
66 66
67 You can choose your storage location at config step (here for at91sam9260ek) : 67 You can choose your storage location at config step (here for at91sam9260ek) :
68 make at91sam9263ek_config - use data flash (spi cs0) (default) 68 make at91sam9263ek_config - use data flash (spi cs0) (default)
69 make at91sam9263ek_nandflash_config - use nand flash 69 make at91sam9263ek_nandflash_config - use nand flash
70 make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0) 70 make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0)
71 make at91sam9263ek_norflash_config - use nor falsh 71 make at91sam9263ek_norflash_config - use nor flash
72 72
73 You can choose to boot directly from U-Boot at config step 73 You can choose to boot directly from U-Boot at config step
74 make at91sam9263ek_norflash_boot_config - boot from nor falsh 74 make at91sam9263ek_norflash_boot_config - boot from nor flash
75 75
76 76
77 ------------------------------------------------------------------------------ 77 ------------------------------------------------------------------------------
78 AT91SAM9M10G45EK 78 AT91SAM9M10G45EK
79 ------------------------------------------------------------------------------ 79 ------------------------------------------------------------------------------
80 80
81 Memory map 81 Memory map
82 0x20000000 - 23FFFFFF SDRAM (64 MB) 82 0x20000000 - 23FFFFFF SDRAM (64 MB)
83 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J12) 83 0xC0000000 - Cxxxxxxx Atmel Dataflash card (J12)
84 84
85 Environment variables 85 Environment variables
86 86
87 U-Boot environment variables can be stored at different places: 87 U-Boot environment variables can be stored at different places:
88 - Dataflash on SPI chip select 0 (dataflash card) 88 - Dataflash on SPI chip select 0 (dataflash card)
89 - Nand flash. 89 - Nand flash.
90 90
91 You can choose your storage location at config step (here for at91sam9m10g45ek) : 91 You can choose your storage location at config step (here for at91sam9m10g45ek) :
92 make at91sam9m10g45ek_config - use data flash (spi cs0) (default) 92 make at91sam9m10g45ek_config - use data flash (spi cs0) (default)
93 make at91sam9m10g45ek_nandflash_config - use nand flash 93 make at91sam9m10g45ek_nandflash_config - use nand flash
94 make at91sam9m10g45ek_dataflash_cs0_config - use data flash (spi cs0) 94 make at91sam9m10g45ek_dataflash_cs0_config - use data flash (spi cs0)
95 95
96 96
97 ------------------------------------------------------------------------------ 97 ------------------------------------------------------------------------------
98 AT91SAM9RLEK 98 AT91SAM9RLEK
99 ------------------------------------------------------------------------------ 99 ------------------------------------------------------------------------------
100 100
101 Memory map 101 Memory map
102 0x20000000 - 23FFFFFF SDRAM (64 MB) 102 0x20000000 - 23FFFFFF SDRAM (64 MB)
103 0xC0000000 - Cxxxxxxx Soldered Atmel Dataflash 103 0xC0000000 - Cxxxxxxx Soldered Atmel Dataflash
104 104
105 Environment variables 105 Environment variables
106 106
107 U-Boot environment variables can be stored at different places: 107 U-Boot environment variables can be stored at different places:
108 - Dataflash on SPI chip select 0 108 - Dataflash on SPI chip select 0
109 - Nand flash. 109 - Nand flash.
110 110
111 You can choose your storage location at config step (here for at91sam9260ek) : 111 You can choose your storage location at config step (here for at91sam9260ek) :
112 make at91sam9263ek_config - use data flash (spi cs0) (default) 112 make at91sam9263ek_config - use data flash (spi cs0) (default)
113 make at91sam9263ek_nandflash_config - use nand flash 113 make at91sam9263ek_nandflash_config - use nand flash
114 make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0) 114 make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0)
115 115
116 II. Watchdog support 116 II. Watchdog support
117 117
118 For security reasons, the at91 watchdog is running at boot time and, 118 For security reasons, the at91 watchdog is running at boot time and,
119 if deactivated, cannot be used anymore. 119 if deactivated, cannot be used anymore.
120 If you want to use the watchdog, you will need to keep it running in 120 If you want to use the watchdog, you will need to keep it running in
121 your code (make sure not to disable it in AT91Bootstrap for instance). 121 your code (make sure not to disable it in AT91Bootstrap for instance).
122 122
123 In the U-Boot configuration, the AT91 watchdog support is enabled using 123 In the U-Boot configuration, the AT91 watchdog support is enabled using
124 the CONFIG_AT91SAM9_WATCHDOG and CONFIG_HW_WATCHDOG options. 124 the CONFIG_AT91SAM9_WATCHDOG and CONFIG_HW_WATCHDOG options.
125 125
1 AMCC Ebony Board 1 AMCC Ebony Board
2 2
3 Last Update: September 12, 2002 3 Last Update: September 12, 2002
4 ======================================================================= 4 =======================================================================
5 5
6 This file contains some handy info regarding U-Boot and the AMCC 6 This file contains some handy info regarding U-Boot and the AMCC
7 Ebony evalutation board. See the README.ppc440 for additional 7 Ebony evaluation board. See the README.ppc440 for additional
8 information. 8 information.
9 9
10 10
11 SWITCH SETTINGS & JUMPERS 11 SWITCH SETTINGS & JUMPERS
12 ========================== 12 ==========================
13 13
14 Here's what I've been using successfully. If you feel inclined to 14 Here's what I've been using successfully. If you feel inclined to
15 change things ... please read the docs! 15 change things ... please read the docs!
16 16
17 DIPSW U46 U80 17 DIPSW U46 U80
18 ------------------------ 18 ------------------------
19 SW 1 off on 19 SW 1 off on
20 SW 2 on on 20 SW 2 on on
21 SW 3 on on 21 SW 3 on on
22 SW 4 off on 22 SW 4 off on
23 SW 5 on off 23 SW 5 on off
24 SW 6 on on 24 SW 6 on on
25 SW 7 on off 25 SW 7 on off
26 SW 8 on off 26 SW 8 on off
27 27
28 J41: strapped 28 J41: strapped
29 J42: open 29 J42: open
30 30
31 All others are factory default. 31 All others are factory default.
32 32
33 33
34 I2C probe 34 I2C probe
35 ===================== 35 =====================
36 36
37 The i2c utilities have been tested on both Rev B. and Rev C. and 37 The i2c utilities have been tested on both Rev B. and Rev C. and
38 look good. The CONFIG_SYS_I2C_NOPROBES macro is defined to prevent 38 look good. The CONFIG_SYS_I2C_NOPROBES macro is defined to prevent
39 probing the CDCV850 clock controller at address 0x69 (since reading 39 probing the CDCV850 clock controller at address 0x69 (since reading
40 it causes the i2c implementation to misbehave. The output of 40 it causes the i2c implementation to misbehave. The output of
41 'i2c probe' should look like this (assuming you are only using a single 41 'i2c probe' should look like this (assuming you are only using a single
42 SO-DIMM: 42 SO-DIMM:
43 43
44 => i2c probe 44 => i2c probe
45 Valid chip addresses: 50 53 54 45 Valid chip addresses: 50 53 54
46 Excluded chip addresses: 69 46 Excluded chip addresses: 69
47 47
48 48
49 GETTING OUT OF I2C TROUBLE 49 GETTING OUT OF I2C TROUBLE
50 =========================== 50 ===========================
51 51
52 If you're like me ... you may have screwed up your bootstrap serial 52 If you're like me ... you may have screwed up your bootstrap serial
53 eeprom ... or worse, your SPD eeprom when experimenting with the 53 eeprom ... or worse, your SPD eeprom when experimenting with the
54 i2c commands. If so, here are some ideas on how to get out of 54 i2c commands. If so, here are some ideas on how to get out of
55 trouble: 55 trouble:
56 56
57 Serial bootstrap eeprom corruption: 57 Serial bootstrap eeprom corruption:
58 ----------------------------------- 58 -----------------------------------
59 Power down the board and set the following straps: 59 Power down the board and set the following straps:
60 60
61 J41 - open 61 J41 - open
62 J42 - strapped 62 J42 - strapped
63 63
64 This will select the default sys0 and sys1 settings (the serial 64 This will select the default sys0 and sys1 settings (the serial
65 eeproms are not used). Then power up the board and fix the serial 65 eeproms are not used). Then power up the board and fix the serial
66 eeprom using the 'i2c mm' command. Here are the values I currently 66 eeprom using the 'i2c mm' command. Here are the values I currently
67 use: 67 use:
68 68
69 => i2c md 50 0 10 69 => i2c md 50 0 10
70 0000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00 ................ 70 0000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00 ................
71 71
72 => i2c md 54 0 10 72 => i2c md 54 0 10
73 0000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00 ..$.M........... 73 0000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00 ..$.M...........
74 74
75 Once you have the eeproms set correctly change the 75 Once you have the eeproms set correctly change the
76 J41/J42 straps as you desire. 76 J41/J42 straps as you desire.
77 77
78 SPD eeprom corruption: 78 SPD eeprom corruption:
79 ------------------------ 79 ------------------------
80 I've corrupted the SPD eeprom several times ... perhaps too much coffee 80 I've corrupted the SPD eeprom several times ... perhaps too much coffee
81 and not enough presence of mind ;-). By default, the ebony code uses 81 and not enough presence of mind ;-). By default, the ebony code uses
82 the SPD to initialize the DDR SDRAM control registers. So if the SPD 82 the SPD to initialize the DDR SDRAM control registers. So if the SPD
83 eeprom is corrupted, U-Boot will never get into ram. Here's how I got 83 eeprom is corrupted, U-Boot will never get into ram. Here's how I got
84 out of this situation: 84 out of this situation:
85 85
86 0. First, _before_ playing with the i2c utilities, do an 'i2c probe', then 86 0. First, _before_ playing with the i2c utilities, do an 'i2c probe', then
87 use 'i2c md' to capture the various device contents to a file. Some day 87 use 'i2c md' to capture the various device contents to a file. Some day
88 you may be glad you did this ... trust me :-). Otherwise try the 88 you may be glad you did this ... trust me :-). Otherwise try the
89 following: 89 following:
90 90
91 1. In the include/configs/EBONY.h file find the line that defines 91 1. In the include/configs/EBONY.h file find the line that defines
92 the CONFIG_SPD_EEPROM macro and undefine it. E.g: 92 the CONFIG_SPD_EEPROM macro and undefine it. E.g:
93 93
94 #undef CONFIG_SPD_EEPROM 94 #undef CONFIG_SPD_EEPROM
95 95
96 This will make the code use default SDRAM control register 96 This will make the code use default SDRAM control register
97 settings without using the SPD eeprom. 97 settings without using the SPD eeprom.
98 98
99 2. Rebuild U-Boot 99 2. Rebuild U-Boot
100 100
101 3. Load the new U-Boot image and reboot ebony. 101 3. Load the new U-Boot image and reboot ebony.
102 102
103 4. Repair the SPD eeprom using the 'i2c mm' command. Here's the eeprom 103 4. Repair the SPD eeprom using the 'i2c mm' command. Here's the eeprom
104 contents that work with the default SO-DIMM that comes with the 104 contents that work with the default SO-DIMM that comes with the
105 ebony board (micron 8VDDT164AG-265A1). Note: these are probably 105 ebony board (micron 8VDDT164AG-265A1). Note: these are probably
106 _not_ the factory settings ... but they work. 106 _not_ the factory settings ... but they work.
107 107
108 => i2c md 53 0 10 80 108 => i2c md 53 0 10 80
109 0000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01 ......@..uu..... 109 0000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01 ......@..uu.....
110 0010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20 ..... ..u..P<P- 110 0010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20 ..... ..u..P<P-
111 0020: 90 90 50 50 00 00 00 00 00 41 4b 34 32 75 00 00 ..PP.....AK42u.. 111 0020: 90 90 50 50 00 00 00 00 00 41 4b 34 32 75 00 00 ..PP.....AK42u..
112 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9c ................ 112 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9c ................
113 0040: 2c 00 00 00 00 00 00 00 08 38 56 44 44 54 31 36 ,........8VDDT16 113 0040: 2c 00 00 00 00 00 00 00 08 38 56 44 44 54 31 36 ,........8VDDT16
114 0050: 36 34 41 47 2d 32 36 35 41 31 20 01 00 01 2c 63 64AG-265A1 ...,c 114 0050: 36 34 41 47 2d 32 36 35 41 31 20 01 00 01 2c 63 64AG-265A1 ...,c
115 0060: 22 25 ab 00 00 00 00 00 00 00 00 00 00 00 00 00 "%.............. 115 0060: 22 25 ab 00 00 00 00 00 00 00 00 00 00 00 00 00 "%..............
116 0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 116 0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
117 117
118 118
119 PCI DOUBLE-ENUMERATION WOES 119 PCI DOUBLE-ENUMERATION WOES
120 =========================== 120 ===========================
121 121
122 If you're not using PCI-X cards and are simply using 32-bit and/or 122 If you're not using PCI-X cards and are simply using 32-bit and/or
123 33 MHz cards via extenders and the like, you may notice that the 123 33 MHz cards via extenders and the like, you may notice that the
124 initial pci scan reports various devices twice ... and configuration 124 initial pci scan reports various devices twice ... and configuration
125 does not succeed (one or more devices are enumerated twice). To correct 125 does not succeed (one or more devices are enumerated twice). To correct
126 this we replaced the 2K ohm resistor on the IDSEL line(s) with a 126 this we replaced the 2K ohm resistor on the IDSEL line(s) with a
127 22 ohm resistor and the problem went away. This change hasn't broken 127 22 ohm resistor and the problem went away. This change hasn't broken
128 anything yet -- use at your own risk. 128 anything yet -- use at your own risk.
129 129
130 We never tested anything other than 33 MHz/32-bit cards. If you have 130 We never tested anything other than 33 MHz/32-bit cards. If you have
131 the chance to do this, please let me know how things turn out :-) 131 the chance to do this, please let me know how things turn out :-)
132 132
133 133
134 Regards, 134 Regards,
135 --Scott 135 --Scott
136 <smcnutt@artesyncp.com> 136 <smcnutt@artesyncp.com>
137 137
1 1
2 Table of interleaving modes supported in cpu/8xxx/ddr/ 2 Table of interleaving modes supported in cpu/8xxx/ddr/
3 ====================================================== 3 ======================================================
4 +-------------+---------------------------------------------------------+ 4 +-------------+---------------------------------------------------------+
5 | | Rank Interleaving | 5 | | Rank Interleaving |
6 | +--------+-----------+-----------+------------+-----------+ 6 | +--------+-----------+-----------+------------+-----------+
7 |Memory | | | | 2x2 | 4x1 | 7 |Memory | | | | 2x2 | 4x1 |
8 |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ | 8 |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
9 |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} | 9 |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
10 +-------------+--------+-----------+-----------+------------+-----------+ 10 +-------------+--------+-----------+-----------+------------+-----------+
11 |None | Yes | Yes | Yes | Yes | Yes | 11 |None | Yes | Yes | Yes | Yes | Yes |
12 +-------------+--------+-----------+-----------+------------+-----------+ 12 +-------------+--------+-----------+-----------+------------+-----------+
13 |Cacheline | Yes | Yes | No | No, Only(*)| Yes | 13 |Cacheline | Yes | Yes | No | No, Only(*)| Yes |
14 | |CS0 Only| | | {CS0+CS1} | | 14 | |CS0 Only| | | {CS0+CS1} | |
15 +-------------+--------+-----------+-----------+------------+-----------+ 15 +-------------+--------+-----------+-----------+------------+-----------+
16 |Page | Yes | Yes | No | No, Only(*)| Yes | 16 |Page | Yes | Yes | No | No, Only(*)| Yes |
17 | |CS0 Only| | | {CS0+CS1} | | 17 | |CS0 Only| | | {CS0+CS1} | |
18 +-------------+--------+-----------+-----------+------------+-----------+ 18 +-------------+--------+-----------+-----------+------------+-----------+
19 |Bank | Yes | Yes | No | No, Only(*)| Yes | 19 |Bank | Yes | Yes | No | No, Only(*)| Yes |
20 | |CS0 Only| | | {CS0+CS1} | | 20 | |CS0 Only| | | {CS0+CS1} | |
21 +-------------+--------+-----------+-----------+------------+-----------+ 21 +-------------+--------+-----------+-----------+------------+-----------+
22 |Superbank | No | Yes | No | No, Only(*)| Yes | 22 |Superbank | No | Yes | No | No, Only(*)| Yes |
23 | | | | | {CS0+CS1} | | 23 | | | | | {CS0+CS1} | |
24 +-------------+--------+-----------+-----------+------------+-----------+ 24 +-------------+--------+-----------+-----------+------------+-----------+
25 (*) Although the hardware can be configured with memory controller 25 (*) Although the hardware can be configured with memory controller
26 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1} 26 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
27 from each controller. {CS2+CS3} on each controller are only rank 27 from each controller. {CS2+CS3} on each controller are only rank
28 interleaved on that controller. 28 interleaved on that controller.
29 29
30 For memory controller interleaving, identical DIMMs are suggested. Software 30 For memory controller interleaving, identical DIMMs are suggested. Software
31 doesn't check the size or organization of interleaved DIMMs. 31 doesn't check the size or organization of interleaved DIMMs.
32 32
33 The ways to configure the ddr interleaving mode 33 The ways to configure the ddr interleaving mode
34 ============================================== 34 ==============================================
35 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting 35 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
36 under "CONFIG_EXTRA_ENV_SETTINGS", like: 36 under "CONFIG_EXTRA_ENV_SETTINGS", like:
37 #define CONFIG_EXTRA_ENV_SETTINGS \ 37 #define CONFIG_EXTRA_ENV_SETTINGS \
38 "hwconfig=fsl_ddr:ctlr_intlv=bank" \ 38 "hwconfig=fsl_ddr:ctlr_intlv=bank" \
39 ...... 39 ......
40 40
41 2. Run u-boot "setenv" command to configure the memory interleaving mode. 41 2. Run u-boot "setenv" command to configure the memory interleaving mode.
42 Either numerical or string value is accepted. 42 Either numerical or string value is accepted.
43 43
44 # disable memory controller interleaving 44 # disable memory controller interleaving
45 setenv hwconfig "fsl_ddr:ctlr_intlv=null" 45 setenv hwconfig "fsl_ddr:ctlr_intlv=null"
46 46
47 # cacheline interleaving 47 # cacheline interleaving
48 setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline" 48 setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
49 49
50 # page interleaving 50 # page interleaving
51 setenv hwconfig "fsl_ddr:ctlr_intlv=page" 51 setenv hwconfig "fsl_ddr:ctlr_intlv=page"
52 52
53 # bank interleaving 53 # bank interleaving
54 setenv hwconfig "fsl_ddr:ctlr_intlv=bank" 54 setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
55 55
56 # superbank 56 # superbank
57 setenv hwconfig "fsl_ddr:ctlr_intlv=superbank" 57 setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
58 58
59 # disable bank (chip-select) interleaving 59 # disable bank (chip-select) interleaving
60 setenv hwconfig "fsl_ddr:bank_intlv=null" 60 setenv hwconfig "fsl_ddr:bank_intlv=null"
61 61
62 # bank(chip-select) interleaving cs0+cs1 62 # bank(chip-select) interleaving cs0+cs1
63 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1" 63 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
64 64
65 # bank(chip-select) interleaving cs2+cs3 65 # bank(chip-select) interleaving cs2+cs3
66 setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3" 66 setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
67 67
68 # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2) 68 # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2)
69 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3" 69 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
70 70
71 # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) 71 # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
72 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" 72 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
73 73
74 Memory controller address hashing 74 Memory controller address hashing
75 ================================== 75 ==================================
76 If the DDR controller supports address hashing, it can be enabled by hwconfig. 76 If the DDR controller supports address hashing, it can be enabled by hwconfig.
77 77
78 Syntax is: 78 Syntax is:
79 hwconfig=fsl_ddr:addr_hash=true 79 hwconfig=fsl_ddr:addr_hash=true
80 80
81 Memory controller ECC on/off 81 Memory controller ECC on/off
82 ============================ 82 ============================
83 If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC, 83 If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC,
84 ECC can be turned on/off by hwconfig. 84 ECC can be turned on/off by hwconfig.
85 85
86 Syntax is 86 Syntax is
87 hwconfig=fsl_ddr:ecc=off 87 hwconfig=fsl_ddr:ecc=off
88 88
89 Memory testing options for mpc85xx 89 Memory testing options for mpc85xx
90 ================================== 90 ==================================
91 1. Memory test can be done once U-boot prompt comes up using mtest, or 91 1. Memory test can be done once U-boot prompt comes up using mtest, or
92 2. Memory test can be done with Power-On-Self-Test function, activated at 92 2. Memory test can be done with Power-On-Self-Test function, activated at
93 compile time. 93 compile time.
94 94
95 In order to enable the POST memory test, CONFIG_POST needs to be 95 In order to enable the POST memory test, CONFIG_POST needs to be
96 defined in board configuraiton header file. By default, POST memory test 96 defined in board configuraiton header file. By default, POST memory test
97 performs a fast test. A slow test can be enabled by changing the flag at 97 performs a fast test. A slow test can be enabled by changing the flag at
98 compiling time. To test memory bigger than 2GB, 36BIT support is needed. 98 compiling time. To test memory bigger than 2GB, 36BIT support is needed.
99 Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB 99 Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
100 window to physical address so that all physical memory can be tested. 100 window to physical address so that all physical memory can be tested.
101 101
102 Combination of hwconfig 102 Combination of hwconfig
103 ======================= 103 =======================
104 Hwconfig can be combined with multiple parameters, for example, on a supported 104 Hwconfig can be combined with multiple parameters, for example, on a supported
105 platform 105 platform
106 106
107 hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on 107 hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
108 108
109 Table for dynamic ODT for DDR3 109 Table for dynamic ODT for DDR3
110 ============================== 110 ==============================
111 For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may 111 For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may
112 be needed, depending on the configuration. The numbers in the following tables are 112 be needed, depending on the configuration. The numbers in the following tables are
113 in Ohms. 113 in Ohms.
114 114
115 * denotes dynamic ODT 115 * denotes dynamic ODT
116 116
117 Two slots system 117 Two slots system
118 +-----------------------+----------+---------------+-----------------------------+-----------------------------+ 118 +-----------------------+----------+---------------+-----------------------------+-----------------------------+
119 | Configuration | |DRAM controller| Slot 1 | Slot 2 | 119 | Configuration | |DRAM controller| Slot 1 | Slot 2 |
120 +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+ 120 +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
121 | | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 | 121 | | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
122 + Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+ 122 + Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
123 | | | | | | Write | Read | Write | Read | Write | Read | Write | Read | 123 | | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
124 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 124 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
125 | | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 | 125 | | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 |
126 | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 126 | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
127 | | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off | 127 | | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off |
128 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 128 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
129 | | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | | 129 | | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | |
130 | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 130 | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
131 | | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | | 131 | | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | |
132 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 132 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
133 | | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 | 133 | | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 |
134 |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 134 |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
135 | | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off | 135 | | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off |
136 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 136 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
137 | | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | | 137 | | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | |
138 |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 138 |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
139 | | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | | 139 | | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | |
140 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 140 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
141 | Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | | 141 | Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | |
142 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 142 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
143 | Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off | 143 | Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off |
144 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 144 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
145 |Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | | 145 |Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | |
146 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 146 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
147 | Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | | 147 | Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | |
148 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 148 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
149 149
150 Single slot system 150 Single slot system
151 +-------------+------------+---------------+-----------------------------+-----------------------------+ 151 +-------------+------------+---------------+-----------------------------+-----------------------------+
152 | | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 | 152 | | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 |
153 |Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+ 153 |Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+
154 | | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read | 154 | | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read |
155 +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 155 +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
156 | | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off | 156 | | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off |
157 | |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 157 | |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
158 | | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off | 158 | | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off |
159 | Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 159 | Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
160 | | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off | 160 | | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off |
161 | |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 161 | |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
162 | | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off | 162 | | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off |
163 +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 163 +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
164 | | R1 | off | 75 | 40 | off | off | off | 164 | | R1 | off | 75 | 40 | off | off | off |
165 | Dual Rank |------------+-------+-------+-------+------+-------+------+ 165 | Dual Rank |------------+-------+-------+-------+------+-------+------+
166 | | R2 | off | 75 | 40 | off | off | off | 166 | | R2 | off | 75 | 40 | off | off | off |
167 +-------------+------------+-------+-------+-------+------+-------+------+ 167 +-------------+------------+-------+-------+-------+------+-------+------+
168 | Single Rank | R1 | off | 75 | 40 | off | 168 | Single Rank | R1 | off | 75 | 40 | off |
169 +-------------+------------+-------+-------+-------+------+ 169 +-------------+------------+-------+-------+-------+------+
170 170
171 Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf 171 Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf
172 http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf 172 http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf
173 173
174 174
175 Table for ODT for DDR2 175 Table for ODT for DDR2
176 ====================== 176 ======================
177 Two slots system 177 Two slots system
178 +-----------------------+----------+---------------+-----------------------------+-----------------------------+ 178 +-----------------------+----------+---------------+-----------------------------+-----------------------------+
179 | Configuration | |DRAM controller| Slot 1 | Slot 2 | 179 | Configuration | |DRAM controller| Slot 1 | Slot 2 |
180 +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+ 180 +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
181 | | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 | 181 | | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
182 + Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+ 182 + Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
183 | | | | | | Write | Read | Write | Read | Write | Read | Write | Read | 183 | | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
184 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 184 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
185 | | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | off | off | 185 | | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | off | off |
186 | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 186 | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
187 | | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | off | off | 187 | | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | off | off |
188 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 188 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
189 | | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | | | 189 | | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | | |
190 | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 190 | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
191 | | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | | | 191 | | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | | |
192 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 192 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
193 | | | Slot 1 | off | 150 | off | off | | | 75 | 75 | off | off | 193 | | | Slot 1 | off | 150 | off | off | | | 75 | 75 | off | off |
194 |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 194 |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
195 | | | Slot 2 | off | 150 | 75 | 75 | | | off | off | off | off | 195 | | | Slot 2 | off | 150 | 75 | 75 | | | off | off | off | off |
196 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 196 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
197 | | | Slot 1 | off | 150 | off | off | | | 75 | 75 | | | 197 | | | Slot 1 | off | 150 | off | off | | | 75 | 75 | | |
198 |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 198 |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
199 | | | Slot 2 | off | 150 | 75 | 75 | | | off | off | | | 199 | | | Slot 2 | off | 150 | 75 | 75 | | | off | off | | |
200 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 200 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
201 | Dual Rank | Empty | Slot 1 | off | 75 | 150 | off | off | off | | | | | 201 | Dual Rank | Empty | Slot 1 | off | 75 | 150 | off | off | off | | | | |
202 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 202 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
203 | Empty | Dual Rank | Slot 2 | off | 75 | | | | | 150 | off | off | off | 203 | Empty | Dual Rank | Slot 2 | off | 75 | | | | | 150 | off | off | off |
204 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 204 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
205 |Single Rank| Empty | Slot 1 | off | 75 | 150 | off | | | | | | | 205 |Single Rank| Empty | Slot 1 | off | 75 | 150 | off | | | | | | |
206 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 206 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
207 | Empty |Single Rank| Slot 2 | off | 75 | | | | | 150 | off | | | 207 | Empty |Single Rank| Slot 2 | off | 75 | | | | | 150 | off | | |
208 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+ 208 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
209 209
210 Single slot system 210 Single slot system
211 +-------------+------------+---------------+-----------------------------+ 211 +-------------+------------+---------------+-----------------------------+
212 | | |DRAM controller| Rank 1 | Rank 2 | 212 | | |DRAM controller| Rank 1 | Rank 2 |
213 |Configuration| Write/Read |-------+-------+-------+------+-------+------+ 213 |Configuration| Write/Read |-------+-------+-------+------+-------+------+
214 | | | Write | Read | Write | Read | Write | Read | 214 | | | Write | Read | Write | Read | Write | Read |
215 +-------------+------------+-------+-------+-------+------+-------+------+ 215 +-------------+------------+-------+-------+-------+------+-------+------+
216 | | R1 | off | 75 | 150 | off | off | off | 216 | | R1 | off | 75 | 150 | off | off | off |
217 | Dual Rank |------------+-------+-------+-------+------+-------+------+ 217 | Dual Rank |------------+-------+-------+-------+------+-------+------+
218 | | R2 | off | 75 | 150 | off | off | off | 218 | | R2 | off | 75 | 150 | off | off | off |
219 +-------------+------------+-------+-------+-------+------+-------+------+ 219 +-------------+------------+-------+-------+-------+------+-------+------+
220 | Single Rank | R1 | off | 75 | 150 | off | 220 | Single Rank | R1 | off | 75 | 150 | off |
221 +-------------+------------+-------+-------+-------+------+ 221 +-------------+------------+-------+-------+-------+------+
222 222
223 Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf 223 Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf
224 224
225 225
226 Interactive DDR debugging 226 Interactive DDR debugging
227 =========================== 227 ===========================
228 228
229 For DDR parameter tuning up and debugging, the interactive DDR debugging can 229 For DDR parameter tuning up and debugging, the interactive DDR debugging can
230 be activated by saving an environment variable "ddr_interactive". The value 230 be activated by saving an environment variable "ddr_interactive". The value
231 doesn't matter. Once activated, U-boot prompts "FSL DDR>" before enabling DDR 231 doesn't matter. Once activated, U-boot prompts "FSL DDR>" before enabling DDR
232 controller. The available commands can be seen by typing "help". 232 controller. The available commands can be seen by typing "help".
233 233
234 The example flow of using interactive debugging is 234 The example flow of using interactive debugging is
235 type command "compute" to calculate the parameters from the default 235 type command "compute" to calculate the parameters from the default
236 type command "print" with arguments to show SPD, options, registers 236 type command "print" with arguments to show SPD, options, registers
237 type command "edit" with arguments to change any if desired 237 type command "edit" with arguments to change any if desired
238 type command "go" to continue calculation and enable DDR controller 238 type command "go" to continue calculation and enable DDR controller
239 type command "reset" to reset the board 239 type command "reset" to reset the board
240 type command "recompute" to reload SPD and start over 240 type command "recompute" to reload SPD and start over
241 241
242 Note, check "next_step" to show the flow. For example, after edit opts, the 242 Note, check "next_step" to show the flow. For example, after edit opts, the
243 next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is 243 next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is
244 STEP_PROGRAM_REGS. Upon issuing command "go", DDR controller will be enabled 244 STEP_PROGRAM_REGS. Upon issuing command "go", DDR controller will be enabled
245 with current setting without further calculation. 245 with current setting without further calculation.
246 246
247 The detail syntax for each commands are 247 The detail syntax for each commands are
248 248
249 print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs] 249 print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
250 c<n> - the controller number, eg. c0, c1 250 c<n> - the controller number, eg. c0, c1
251 d<n> - the DIMM number, eg. d0, d1 251 d<n> - the DIMM number, eg. d0, d1
252 spd - print SPD data 252 spd - print SPD data
253 dimmparms - DIMM paramaters, calcualted from SPD 253 dimmparms - DIMM parameters, calculated from SPD
254 commonparms - lowest common parameters for all DIMMs 254 commonparms - lowest common parameters for all DIMMs
255 opts - options 255 opts - options
256 addresses - address assignment (not implemented yet) 256 addresses - address assignment (not implemented yet)
257 regs - controller registers 257 regs - controller registers
258 258
259 edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value> 259 edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value>
260 c<n> - the controller number, eg. c0, c1 260 c<n> - the controller number, eg. c0, c1
261 d<n> - the DIMM number, eg. d0, d1 261 d<n> - the DIMM number, eg. d0, d1
262 spd - print SPD data 262 spd - print SPD data
263 dimmparms - DIMM paramaters, calcualted from SPD 263 dimmparms - DIMM parameters, calculated from SPD
264 commonparms - lowest common parameters for all DIMMs 264 commonparms - lowest common parameters for all DIMMs
265 opts - options 265 opts - options
266 addresses - address assignment (not implemented yet) 266 addresses - address assignment (not implemented yet)
267 regs - controller registers 267 regs - controller registers
268 <element> - name of the modified element 268 <element> - name of the modified element
269 byte number if the object is SPD 269 byte number if the object is SPD
270 <value> - decimal or heximal (prefixed with 0x) numbers 270 <value> - decimal or heximal (prefixed with 0x) numbers
271 271
272 reset 272 reset
273 no arguement - reset the board 273 no arguement - reset the board
274 274
275 recompute 275 recompute
276 no argument - reload SPD and start over 276 no argument - reload SPD and start over
277 277
278 compute 278 compute
279 no argument - recompute from current next_step 279 no argument - recompute from current next_step
280 280
281 next_step 281 next_step
282 no argument - show current next_step 282 no argument - show current next_step
283 283
284 help 284 help
285 no argument - print a list of all commands 285 no argument - print a list of all commands
286 286
287 go 287 go
288 no argument - program memory controller(s) and continue with U-boot 288 no argument - program memory controller(s) and continue with U-boot
289 289
290 Examples of debugging flow 290 Examples of debugging flow
291 291
292 FSL DDR>compute 292 FSL DDR>compute
293 Detected UDIMM UG51U6400N8SU-ACF 293 Detected UDIMM UG51U6400N8SU-ACF
294 SL DDR>print 294 SL DDR>print
295 print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs] 295 print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
296 FSL DDR>print dimmparms 296 FSL DDR>print dimmparms
297 DIMM parameters: Controller=0 DIMM=0 297 DIMM parameters: Controller=0 DIMM=0
298 DIMM organization parameters: 298 DIMM organization parameters:
299 module part name = UG51U6400N8SU-ACF 299 module part name = UG51U6400N8SU-ACF
300 rank_density = 2147483648 bytes (2048 megabytes) 300 rank_density = 2147483648 bytes (2048 megabytes)
301 capacity = 4294967296 bytes (4096 megabytes) 301 capacity = 4294967296 bytes (4096 megabytes)
302 burst_lengths_bitmask = 0C 302 burst_lengths_bitmask = 0C
303 base_addresss = 0 (00000000 00000000) 303 base_addresss = 0 (00000000 00000000)
304 n_ranks = 2 304 n_ranks = 2
305 data_width = 64 305 data_width = 64
306 primary_sdram_width = 64 306 primary_sdram_width = 64
307 ec_sdram_width = 0 307 ec_sdram_width = 0
308 registered_dimm = 0 308 registered_dimm = 0
309 n_row_addr = 15 309 n_row_addr = 15
310 n_col_addr = 10 310 n_col_addr = 10
311 edc_config = 0 311 edc_config = 0
312 n_banks_per_sdram_device = 8 312 n_banks_per_sdram_device = 8
313 tCKmin_X_ps = 1500 313 tCKmin_X_ps = 1500
314 tCKmin_X_minus_1_ps = 0 314 tCKmin_X_minus_1_ps = 0
315 tCKmin_X_minus_2_ps = 0 315 tCKmin_X_minus_2_ps = 0
316 tCKmax_ps = 0 316 tCKmax_ps = 0
317 caslat_X = 960 317 caslat_X = 960
318 tAA_ps = 13125 318 tAA_ps = 13125
319 caslat_X_minus_1 = 0 319 caslat_X_minus_1 = 0
320 caslat_X_minus_2 = 0 320 caslat_X_minus_2 = 0
321 caslat_lowest_derated = 0 321 caslat_lowest_derated = 0
322 tRCD_ps = 13125 322 tRCD_ps = 13125
323 tRP_ps = 13125 323 tRP_ps = 13125
324 tRAS_ps = 36000 324 tRAS_ps = 36000
325 tWR_ps = 15000 325 tWR_ps = 15000
326 tWTR_ps = 7500 326 tWTR_ps = 7500
327 tRFC_ps = 160000 327 tRFC_ps = 160000
328 tRRD_ps = 6000 328 tRRD_ps = 6000
329 tRC_ps = 49125 329 tRC_ps = 49125
330 refresh_rate_ps = 7800000 330 refresh_rate_ps = 7800000
331 tIS_ps = 0 331 tIS_ps = 0
332 tIH_ps = 0 332 tIH_ps = 0
333 tDS_ps = 0 333 tDS_ps = 0
334 tDH_ps = 0 334 tDH_ps = 0
335 tRTP_ps = 7500 335 tRTP_ps = 7500
336 tDQSQ_max_ps = 0 336 tDQSQ_max_ps = 0
337 tQHS_ps = 0 337 tQHS_ps = 0
338 FSL DDR>edit c0 opts ECC_mode 0 338 FSL DDR>edit c0 opts ECC_mode 0
339 FSL DDR>edit c0 regs cs0_bnds 0x000000FF 339 FSL DDR>edit c0 regs cs0_bnds 0x000000FF
340 FSL DDR>go 340 FSL DDR>go
341 2 GiB left unmapped 341 2 GiB left unmapped
342 4 GiB (DDR3, 64-bit, CL=9, ECC off) 342 4 GiB (DDR3, 64-bit, CL=9, ECC off)
343 DDR Chip-Select Interleaving Mode: CS0+CS1 343 DDR Chip-Select Interleaving Mode: CS0+CS1
344 Testing 0x00000000 - 0x7fffffff 344 Testing 0x00000000 - 0x7fffffff
345 Testing 0x80000000 - 0xffffffff 345 Testing 0x80000000 - 0xffffffff
346 Remap DDR 2 GiB left unmapped 346 Remap DDR 2 GiB left unmapped
347 347
348 POST memory PASSED 348 POST memory PASSED
349 Flash: 128 MiB 349 Flash: 128 MiB
350 L2: 128 KB enabled 350 L2: 128 KB enabled
351 Corenet Platform Cache: 1024 KB enabled 351 Corenet Platform Cache: 1024 KB enabled
352 SERDES: timeout resetting bank 3 352 SERDES: timeout resetting bank 3
353 SRIO1: disabled 353 SRIO1: disabled
354 SRIO2: disabled 354 SRIO2: disabled
355 MMC: FSL_ESDHC: 0 355 MMC: FSL_ESDHC: 0
356 EEPROM: Invalid ID (ff ff ff ff) 356 EEPROM: Invalid ID (ff ff ff ff)
357 PCIe1: disabled 357 PCIe1: disabled
358 PCIe2: Root Complex, x1, regs @ 0xfe201000 358 PCIe2: Root Complex, x1, regs @ 0xfe201000
359 01:00.0 - 8086:10d3 - Network controller 359 01:00.0 - 8086:10d3 - Network controller
360 PCIe2: Bus 00 - 01 360 PCIe2: Bus 00 - 01
361 PCIe3: disabled 361 PCIe3: disabled
362 In: serial 362 In: serial
363 Out: serial 363 Out: serial
364 Err: serial 364 Err: serial
365 Net: Initializing Fman 365 Net: Initializing Fman
366 Fman1: Uploading microcode version 101.8.0 366 Fman1: Uploading microcode version 101.8.0
367 e1000: 00:1b:21:81:d2:e0 367 e1000: 00:1b:21:81:d2:e0
368 FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME] 368 FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME]
369 Warning: e1000#0 MAC addresses don't match: 369 Warning: e1000#0 MAC addresses don't match:
370 Address in SROM is 00:1b:21:81:d2:e0 370 Address in SROM is 00:1b:21:81:d2:e0
371 Address in environment is 00:e0:0c:00:ea:05 371 Address in environment is 00:e0:0c:00:ea:05
372 372
373 Hit any key to stop autoboot: 0 373 Hit any key to stop autoboot: 0
374 => 374 =>
375 375
doc/README.mpc832xemds
Diff comments   View file @ c46bf09
1 Freescale MPC832XEMDS Board 1 Freescale MPC832XEMDS Board
2 ----------------------------------------- 2 -----------------------------------------
3 1. Board Switches and Jumpers 3 1. Board Switches and Jumpers
4 1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board 4 1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
5 For some reason, the HW designers describe the switch settings 5 For some reason, the HW designers describe the switch settings
6 in terms of 0 and 1, and then map that to physical switches where 6 in terms of 0 and 1, and then map that to physical switches where
7 the label "On" refers to logic 0 and "Off" is logic 1. 7 the label "On" refers to logic 0 and "Off" is logic 1.
8 8
9 Switch bits are numbered 1 through, like, 4 6 8 or 10, but the 9 Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
10 bits may contribute to signals that are numbered based at 0, 10 bits may contribute to signals that are numbered based at 0,
11 and some of those signals may be high-bit-number-0 too. Heed 11 and some of those signals may be high-bit-number-0 too. Heed
12 well the names and labels and do not get confused. 12 well the names and labels and do not get confused.
13 13
14 "Off" == 1 14 "Off" == 1
15 "On" == 0 15 "On" == 0
16 16
17 SW3 is switch 18 as silk-screened onto the board. 17 SW3 is switch 18 as silk-screened onto the board.
18 SW4[8] is the bit labled 8 on Switch 4. 18 SW4[8] is the bit labeled 8 on Switch 4.
19 SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5. 19 SW5[1:6] refers to bits labeled 1 through 6 in order on switch 5.
20 SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6. 20 SW6[7:1] refers to bits labeled 7 through 1 in order on switch 6.
21 SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" 21 SW7[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
22 and bits labeled 8 is set as "Off". 22 and bits labeled 8 is set as "Off".
23 23
24 1.1 For the MPC832XEMDS PROTO Board 24 1.1 For the MPC832XEMDS PROTO Board
25 25
26 First, make sure the board default setting is consistent with the document 26 First, make sure the board default setting is consistent with the document
27 shipped with your board. Then apply the following setting: 27 shipped with your board. Then apply the following setting:
28 SW3[1-8]= 0000_1000 (core PLL setting, core enable) 28 SW3[1-8]= 0000_1000 (core PLL setting, core enable)
29 SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting) 29 SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
30 SW5[1-8]= 0010_0110 (Boot from high end) 30 SW5[1-8]= 0010_0110 (Boot from high end)
31 SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus) 31 SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus)
32 SW7[1-8]= 1000_0011 (QE PLL setting) 32 SW7[1-8]= 1000_0011 (QE PLL setting)
33 33
34 ENET3/4 MII mode settings: 34 ENET3/4 MII mode settings:
35 J1 1-2 (ETH3_TXER) 35 J1 1-2 (ETH3_TXER)
36 J2 2-3 (MII mode) 36 J2 2-3 (MII mode)
37 J3 2-3 (MII mode) 37 J3 2-3 (MII mode)
38 J4 2-3 (ADSL clockOscillator) 38 J4 2-3 (ADSL clockOscillator)
39 J5 1-2 (ETH4_TXER) 39 J5 1-2 (ETH4_TXER)
40 J6 2-3 (ClockOscillator) 40 J6 2-3 (ClockOscillator)
41 JP1 removed (don't force PORESET) 41 JP1 removed (don't force PORESET)
42 JP2 mounted (ETH4/2 MII) 42 JP2 mounted (ETH4/2 MII)
43 JP3 mounted (ETH3 MII) 43 JP3 mounted (ETH3 MII)
44 JP4 mounted (HRCW from BCSR) 44 JP4 mounted (HRCW from BCSR)
45 45
46 ENET3/4 RMII mode settings: 46 ENET3/4 RMII mode settings:
47 J1 1-2 (ETH3_TXER) 47 J1 1-2 (ETH3_TXER)
48 J2 1-2 (RMII mode) 48 J2 1-2 (RMII mode)
49 J3 1-2 (RMII mode) 49 J3 1-2 (RMII mode)
50 J4 2-3 (ADSL clockOscillator) 50 J4 2-3 (ADSL clockOscillator)
51 J5 1-2 (ETH4_TXER) 51 J5 1-2 (ETH4_TXER)
52 J6 2-3 (ClockOscillator) 52 J6 2-3 (ClockOscillator)
53 JP1 removed (don't force PORESET) 53 JP1 removed (don't force PORESET)
54 JP2 removed (ETH4/2 RMII) 54 JP2 removed (ETH4/2 RMII)
55 JP3 removed (ETH3 RMII) 55 JP3 removed (ETH3 RMII)
56 JP4 removed (HRCW from FLASH) 56 JP4 removed (HRCW from FLASH)
57 57
58 on board Oscillator: 66M 58 on board Oscillator: 66M
59 59
60 60
61 2. Memory Map 61 2. Memory Map
62 62
63 2.1 The memory map should look pretty much like this: 63 2.1 The memory map should look pretty much like this:
64 64
65 0x0000_0000 0x7fff_ffff DDR 2G 65 0x0000_0000 0x7fff_ffff DDR 2G
66 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 66 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
67 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 67 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
68 0xc000_0000 0xdfff_ffff Empty 512M 68 0xc000_0000 0xdfff_ffff Empty 512M
69 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M 69 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
70 0xe020_0000 0xe02f_ffff Empty 1M 70 0xe020_0000 0xe02f_ffff Empty 1M
71 0xe030_0000 0xe03f_ffff PCI IO 1M 71 0xe030_0000 0xe03f_ffff PCI IO 1M
72 0xe040_0000 0xefff_ffff Empty 252M 72 0xe040_0000 0xefff_ffff Empty 252M
73 0xf400_0000 0xf7ff_ffff Empty 64M 73 0xf400_0000 0xf7ff_ffff Empty 64M
74 0xf800_0000 0xf800_7fff BCSR on CS1 32K 74 0xf800_0000 0xf800_7fff BCSR on CS1 32K
75 0xf800_8000 0xf800_ffff PIB CS2 32K 75 0xf800_8000 0xf800_ffff PIB CS2 32K
76 0xf801_0000 0xf801_7fff PIB CS3 32K 76 0xf801_0000 0xf801_7fff PIB CS3 32K
77 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M 77 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
78 78
79 79
80 3. Definitions 80 3. Definitions
81 81
82 3.1 Explanation of NEW definitions in: 82 3.1 Explanation of NEW definitions in:
83 83
84 include/configs/MPC832XEPB.h 84 include/configs/MPC832XEPB.h
85 85
86 CONFIG_MPC83xx MPC83xx family for MPC8349, MPC8360 and MPC832x 86 CONFIG_MPC83xx MPC83xx family for MPC8349, MPC8360 and MPC832x
87 CONFIG_MPC832x MPC832x specific 87 CONFIG_MPC832x MPC832x specific
88 CONFIG_MPC832XEMDS MPC832XEMDS board specific 88 CONFIG_MPC832XEMDS MPC832XEMDS board specific
89 89
90 4. Compilation 90 4. Compilation
91 91
92 Assuming you're using BASH shell: 92 Assuming you're using BASH shell:
93 93
94 export CROSS_COMPILE=your-cross-compile-prefix 94 export CROSS_COMPILE=your-cross-compile-prefix
95 cd u-boot 95 cd u-boot
96 make distclean 96 make distclean
97 make MPC832XEMDS_config 97 make MPC832XEMDS_config
98 make 98 make
99 99
100 MPC832x support PCI 33MHz and PCI 66MHz, to make u-boot support PCI: 100 MPC832x support PCI 33MHz and PCI 66MHz, to make u-boot support PCI:
101 101
102 1)Make sure the DIP SW support PCI mode as described in Section 1.1. 102 1)Make sure the DIP SW support PCI mode as described in Section 1.1.
103 103
104 2)To Make U-Boot image support PCI 33MHz, use 104 2)To Make U-Boot image support PCI 33MHz, use
105 Make MPC832XEMDS_HOST_33_config 105 Make MPC832XEMDS_HOST_33_config
106 106
107 3)To Make U-Boot image support PCI 66MHz, use 107 3)To Make U-Boot image support PCI 66MHz, use
108 Make MPC832XEMDS_HOST_66M_config 108 Make MPC832XEMDS_HOST_66M_config
109 109
110 5. Downloading and Flashing Images 110 5. Downloading and Flashing Images
111 111
112 5.0 Download over network: 112 5.0 Download over network:
113 113
114 tftp 10000 u-boot.bin 114 tftp 10000 u-boot.bin
115 115
116 5.1 Reflash U-boot Image using U-boot 116 5.1 Reflash U-boot Image using U-boot
117 117
118 tftp 20000 u-boot.bin 118 tftp 20000 u-boot.bin
119 protect off fe000000 fe0fffff 119 protect off fe000000 fe0fffff
120 erase fe000000 fe0fffff 120 erase fe000000 fe0fffff
121 cp.b 20000 fe000000 xxxx 121 cp.b 20000 fe000000 xxxx
122 122
123 You have to supply the correct byte count with 'xxxx' from the TFTP result log. 123 You have to supply the correct byte count with 'xxxx' from the TFTP result log.
124 Maybe 3ffff will work too, that corresponds to the erased sectors. 124 Maybe 3ffff will work too, that corresponds to the erased sectors.
125 125
126 126
127 6. Notes 127 6. Notes
128 1) The console baudrate for MPC832XEMDS is 115200bps. 128 1) The console baudrate for MPC832XEMDS is 115200bps.
129 129
doc/README.mpc8360emds
Diff comments   View file @ c46bf09
1 Freescale MPC8360EMDS Board 1 Freescale MPC8360EMDS Board
2 ----------------------------------------- 2 -----------------------------------------
3 1. Board Switches and Jumpers 3 1. Board Switches and Jumpers
4 1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board 4 1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC8360EMDS board
5 For some reason, the HW designers describe the switch settings 5 For some reason, the HW designers describe the switch settings
6 in terms of 0 and 1, and then map that to physical switches where 6 in terms of 0 and 1, and then map that to physical switches where
7 the label "On" refers to logic 0 and "Off" is logic 1. 7 the label "On" refers to logic 0 and "Off" is logic 1.
8 8
9 Switch bits are numbered 1 through, like, 4 6 8 or 10, but the 9 Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
10 bits may contribute to signals that are numbered based at 0, 10 bits may contribute to signals that are numbered based at 0,
11 and some of those signals may be high-bit-number-0 too. Heed 11 and some of those signals may be high-bit-number-0 too. Heed
12 well the names and labels and do not get confused. 12 well the names and labels and do not get confused.
13 13
14 "Off" == 1 14 "Off" == 1
15 "On" == 0 15 "On" == 0
16 16
17 SW18 is switch 18 as silk-screened onto the board. 17 SW18 is switch 18 as silk-screened onto the board.
18 SW4[8] is the bit labled 8 on Switch 4. 18 SW4[8] is the bit labeled 8 on Switch 4.
19 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. 19 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
20 SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3. 20 SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3.
21 SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On" 21 SW3[1:8]= 0000_0001 refers to bits labeled 1 through 6 is set as "On"
22 and bits labeled 8 is set as "Off". 22 and bits labeled 8 is set as "Off".
23 23
24 1.1 There are three type boards for MPC8360E silicon up to now, They are 24 1.1 There are three type boards for MPC8360E silicon up to now, They are
25 25
26 * MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE) 26 * MPC8360E-MDS-PB PROTO (a.k.a 8360SYS PROTOTYPE)
27 * MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT) 27 * MPC8360E-MDS-PB PILOT (a.k.a 8360SYS PILOT)
28 * MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE) 28 * MPC8360EA-MDS-PB PROTO (a.k.a 8360SYS2 PROTOTYPE)
29 29
30 1.2 For all the MPC8360EMDS Board 30 1.2 For all the MPC8360EMDS Board
31 31
32 First, make sure the board default setting is consistent with the 32 First, make sure the board default setting is consistent with the
33 document shipped with your board. Then apply the following setting: 33 document shipped with your board. Then apply the following setting:
34 SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus) 34 SW3[1-8]= 0000_0100 (HRCW setting value is performed on local bus)
35 SW4[1-8]= 0011_0000 (Flash boot on local bus) 35 SW4[1-8]= 0011_0000 (Flash boot on local bus)
36 SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH) 36 SW9[1-8]= 0110_0110 (PCI Mode enabled. HRCW is read from FLASH)
37 SW10[1-8]= 0000_1000 (core PLL setting) 37 SW10[1-8]= 0000_1000 (core PLL setting)
38 SW11[1-8]= 0000_0100 (SW11 is on the another side of the board) 38 SW11[1-8]= 0000_0100 (SW11 is on the another side of the board)
39 JP6 1-2 39 JP6 1-2
40 on board Oscillator: 66M 40 on board Oscillator: 66M
41 41
42 1.3 Since different board/chip rev. combinations have AC timing issues, 42 1.3 Since different board/chip rev. combinations have AC timing issues,
43 u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default 43 u-boot forces RGMII-ID (RGMII with Internal Delay) mode on by default
44 by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers). 44 by the patch (mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers).
45 45
46 When the rev2.x silicon mount on these boards, and if you are using 46 When the rev2.x silicon mount on these boards, and if you are using
47 u-boot version after this patch, to make the ethernet interfaces usable, 47 u-boot version after this patch, to make the ethernet interfaces usable,
48 and to enable RGMII-ID on your board, you have to setup the jumpers 48 and to enable RGMII-ID on your board, you have to setup the jumpers
49 correctly. 49 correctly.
50 50
51 * MPC8360E-MDS-PB PROTO 51 * MPC8360E-MDS-PB PROTO
52 nothing to do 52 nothing to do
53 * MPC8360E-MDS-PB PILOT 53 * MPC8360E-MDS-PB PILOT
54 JP9 and JP8 should be ON 54 JP9 and JP8 should be ON
55 * MPC8360EA-MDS-PB PROTO 55 * MPC8360EA-MDS-PB PROTO
56 JP2 and JP3 should be ON 56 JP2 and JP3 should be ON
57 57
58 2. Memory Map 58 2. Memory Map
59 59
60 2.1. The memory map should look pretty much like this: 60 2.1. The memory map should look pretty much like this:
61 61
62 0x0000_0000 0x7fff_ffff DDR 2G 62 0x0000_0000 0x7fff_ffff DDR 2G
63 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 63 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
64 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 64 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
65 0xc000_0000 0xdfff_ffff Empty 512M 65 0xc000_0000 0xdfff_ffff Empty 512M
66 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M 66 0xe000_0000 0xe01f_ffff Int Mem Reg Space 2M
67 0xe020_0000 0xe02f_ffff Empty 1M 67 0xe020_0000 0xe02f_ffff Empty 1M
68 0xe030_0000 0xe03f_ffff PCI IO 1M 68 0xe030_0000 0xe03f_ffff PCI IO 1M
69 0xe040_0000 0xefff_ffff Empty 252M 69 0xe040_0000 0xefff_ffff Empty 252M
70 0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M 70 0xf000_0000 0xf3ff_ffff Local Bus SDRAM 64M
71 0xf400_0000 0xf7ff_ffff Empty 64M 71 0xf400_0000 0xf7ff_ffff Empty 64M
72 0xf800_0000 0xf800_7fff BCSR on CS1 32K 72 0xf800_0000 0xf800_7fff BCSR on CS1 32K
73 0xf800_8000 0xf800_ffff PIB CS4 32K 73 0xf800_8000 0xf800_ffff PIB CS4 32K
74 0xf801_0000 0xf801_7fff PIB CS5 32K 74 0xf801_0000 0xf801_7fff PIB CS5 32K
75 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M 75 0xfe00_0000 0xfeff_ffff FLASH on CS0 16M
76 76
77 77
78 3. Definitions 78 3. Definitions
79 79
80 3.1 Explanation of NEW definitions in: 80 3.1 Explanation of NEW definitions in:
81 81
82 include/configs/MPC8360EMDS.h 82 include/configs/MPC8360EMDS.h
83 83
84 CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360 84 CONFIG_MPC83xx MPC83xx family for both MPC8349 and MPC8360
85 CONFIG_MPC8360 MPC8360 specific 85 CONFIG_MPC8360 MPC8360 specific
86 CONFIG_MPC8360EMDS MPC8360EMDS board specific 86 CONFIG_MPC8360EMDS MPC8360EMDS board specific
87 87
88 4. Compilation 88 4. Compilation
89 89
90 MPC8360EMDS shipped with 33.33MHz or 66MHz oscillator(check U41 chip). 90 MPC8360EMDS shipped with 33.33MHz or 66MHz oscillator(check U41 chip).
91 91
92 Assuming you're using BASH shell: 92 Assuming you're using BASH shell:
93 93
94 export CROSS_COMPILE=your-cross-compile-prefix 94 export CROSS_COMPILE=your-cross-compile-prefix
95 cd u-boot 95 cd u-boot
96 make distclean 96 make distclean
97 make MPC8360EMDS_XX_config 97 make MPC8360EMDS_XX_config
98 make 98 make
99 99
100 MPC8360EMDS support ATM, PCI in host and slave mode. 100 MPC8360EMDS support ATM, PCI in host and slave mode.
101 101
102 To make u-boot support ATM : 102 To make u-boot support ATM :
103 1) Make MPC8360EMDS_XX_ATM_config 103 1) Make MPC8360EMDS_XX_ATM_config
104 104
105 To make u-boot support PCI host 66M : 105 To make u-boot support PCI host 66M :
106 1) DIP SW support PCI mode as described in Section 1.1. 106 1) DIP SW support PCI mode as described in Section 1.1.
107 2) Make MPC8360EMDS_XX_HOST_66_config 107 2) Make MPC8360EMDS_XX_HOST_66_config
108 108
109 To make u-boot support PCI host 33M : 109 To make u-boot support PCI host 33M :
110 1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1 110 1) DIP SW setting is similar as Section 1.1, except for SW3[4] is 1
111 2) Make MPC8360EMDS_XX_HOST_33_config 111 2) Make MPC8360EMDS_XX_HOST_33_config
112 112
113 To make u-boot support PCI slave 66M : 113 To make u-boot support PCI slave 66M :
114 1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1 114 1) DIP SW setting is similar as Section 1.1, except for SW9[3] is 1
115 2) Make MPC8360EMDS_XX_SLAVE_config 115 2) Make MPC8360EMDS_XX_SLAVE_config
116 116
117 (where XX is: 117 (where XX is:
118 33 - 33.33MHz oscillator 118 33 - 33.33MHz oscillator
119 66 - 66MHz oscillator) 119 66 - 66MHz oscillator)
120 120
121 5. Downloading and Flashing Images 121 5. Downloading and Flashing Images
122 122
123 5.0 Download over serial line using Kermit: 123 5.0 Download over serial line using Kermit:
124 124
125 loadb 125 loadb
126 [Drop to kermit: 126 [Drop to kermit:
127 ^\c 127 ^\c
128 send <u-boot-bin-image> 128 send <u-boot-bin-image>
129 c 129 c
130 ] 130 ]
131 131
132 132
133 Or via tftp: 133 Or via tftp:
134 134
135 tftp 10000 u-boot.bin 135 tftp 10000 u-boot.bin
136 136
137 5.1 Reflash U-boot Image using U-boot 137 5.1 Reflash U-boot Image using U-boot
138 138
139 tftp 20000 u-boot.bin 139 tftp 20000 u-boot.bin
140 protect off fef00000 fef3ffff 140 protect off fef00000 fef3ffff
141 erase fef00000 fef3ffff 141 erase fef00000 fef3ffff
142 142
143 cp.b 20000 fef00000 xxxx 143 cp.b 20000 fef00000 xxxx
144 144
145 or 145 or
146 146
147 cp.b 20000 fef00000 3ffff 147 cp.b 20000 fef00000 3ffff
148 148
149 149
150 You have to supply the correct byte count with 'xxxx' from the TFTP result log. 150 You have to supply the correct byte count with 'xxxx' from the TFTP result log.
151 Maybe 3ffff will work too, that corresponds to the erased sectors. 151 Maybe 3ffff will work too, that corresponds to the erased sectors.
152 152
153 153
154 6. Notes 154 6. Notes
155 1) The console baudrate for MPC8360EMDS is 115200bps. 155 1) The console baudrate for MPC8360EMDS is 115200bps.
156 156
doc/README.mpc837xemds
Diff comments   View file @ c46bf09
1 Freescale MPC837xEMDS Board 1 Freescale MPC837xEMDS Board
2 ----------------------------------------- 2 -----------------------------------------
3 1. Board Switches and Jumpers 3 1. Board Switches and Jumpers
4 1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board 4 1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
5 For some reason, the HW designers describe the switch settings 5 For some reason, the HW designers describe the switch settings
6 in terms of 0 and 1, and then map that to physical switches where 6 in terms of 0 and 1, and then map that to physical switches where
7 the label "On" refers to logic 0 and "Off" is logic 1. 7 the label "On" refers to logic 0 and "Off" is logic 1.
8 8
9 Switch bits are numbered 1 through, like, 4 6 8 or 10, but the 9 Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
10 bits may contribute to signals that are numbered based at 0, 10 bits may contribute to signals that are numbered based at 0,
11 and some of those signals may be high-bit-number-0 too. Heed 11 and some of those signals may be high-bit-number-0 too. Heed
12 well the names and labels and do not get confused. 12 well the names and labels and do not get confused.
13 13
14 "Off" == 1 14 "Off" == 1
15 "On" == 0 15 "On" == 0
16 16
17 SW4[8] is the bit labled 8 on Switch 4. 17 SW4[8] is the bit labeled 8 on Switch 4.
18 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2. 18 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
19 SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On" 19 SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
20 and bits labeled 8 is set as "Off". 20 and bits labeled 8 is set as "Off".
21 21
22 1.1 For the MPC837xEMDS Processor Board 22 1.1 For the MPC837xEMDS Processor Board
23 23
24 First, make sure the board default setting is consistent with the 24 First, make sure the board default setting is consistent with the
25 document shipped with your board. Then apply the following setting: 25 document shipped with your board. Then apply the following setting:
26 SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting) 26 SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting)
27 SW4[1-8]= 0000_0110 (core PLL setting) 27 SW4[1-8]= 0000_0110 (core PLL setting)
28 SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash) 28 SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash)
29 SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH) 29 SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH)
30 SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII) 30 SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII)
31 J3 2-3, TSEC1 LVDD1 with 2.5V 31 J3 2-3, TSEC1 LVDD1 with 2.5V
32 J6 2-3, TSEC2 LVDD2 with 2.5V 32 J6 2-3, TSEC2 LVDD2 with 2.5V
33 J9 2-3, CLKIN from osc on board 33 J9 2-3, CLKIN from osc on board
34 J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND 34 J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
35 J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND) 35 J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND)
36 mounted, HRCW load from BCSR. 36 mounted, HRCW load from BCSR.
37 37
38 on board Oscillator: 66M 38 on board Oscillator: 66M
39 39
40 2. Memory Map 40 2. Memory Map
41 41
42 2.1. The memory map should look pretty much like this: 42 2.1. The memory map should look pretty much like this:
43 43
44 0x0000_0000 0x7fff_ffff DDR 2G 44 0x0000_0000 0x7fff_ffff DDR 2G
45 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M 45 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
46 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M 46 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
47 0xc000_0000 0xdfff_ffff Empty 512M 47 0xc000_0000 0xdfff_ffff Empty 512M
48 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M 48 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M
49 0xe010_0000 0xe02f_ffff Empty 2M 49 0xe010_0000 0xe02f_ffff Empty 2M
50 0xe030_0000 0xe03f_ffff PCI IO 1M 50 0xe030_0000 0xe03f_ffff PCI IO 1M
51 0xe040_0000 0xe05f_ffff Empty 2M 51 0xe040_0000 0xe05f_ffff Empty 2M
52 0xe060_0000 0xe060_7fff NAND Flash 32K 52 0xe060_0000 0xe060_7fff NAND Flash 32K
53 0xf400_0000 0xf7ff_ffff Empty 64M 53 0xf400_0000 0xf7ff_ffff Empty 64M
54 0xf800_0000 0xf800_7fff BCSR on CS1 32K 54 0xf800_0000 0xf800_7fff BCSR on CS1 32K
55 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M 55 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M
56 56
57 3. Definitions 57 3. Definitions
58 58
59 3.1 Explanation of NEW definitions in: 59 3.1 Explanation of NEW definitions in:
60 60
61 include/configs/MPC837XEMDS.h 61 include/configs/MPC837XEMDS.h
62 62
63 CONFIG_MPC83xx MPC83xx family for both MPC837x and MPC8360 63 CONFIG_MPC83xx MPC83xx family for both MPC837x and MPC8360
64 CONFIG_MPC837x MPC837x specific 64 CONFIG_MPC837x MPC837x specific
65 CONFIG_MPC837XEMDS MPC837XEMDS board specific 65 CONFIG_MPC837XEMDS MPC837XEMDS board specific
66 66
67 4. Compilation 67 4. Compilation
68 68
69 Assuming you're using BASH shell: 69 Assuming you're using BASH shell:
70 70
71 export CROSS_COMPILE=your-cross-compile-prefix 71 export CROSS_COMPILE=your-cross-compile-prefix
72 cd u-boot 72 cd u-boot
73 make distclean 73 make distclean
74 make MPC837XEMDS_config 74 make MPC837XEMDS_config
75 make 75 make
76 76
77 5. Downloading and Flashing Images 77 5. Downloading and Flashing Images
78 78
79 5.0 Download over serial line using Kermit: 79 5.0 Download over serial line using Kermit:
80 80
81 loadb 81 loadb
82 [Drop to kermit: 82 [Drop to kermit:
83 ^\c 83 ^\c
84 send <u-boot-bin-image> 84 send <u-boot-bin-image>
85 c 85 c
86 ] 86 ]
87 87
88 88
89 Or via tftp: 89 Or via tftp:
90 90
91 tftp 40000 u-boot.bin 91 tftp 40000 u-boot.bin
92 92
93 5.1 Reflash U-boot Image using U-boot 93 5.1 Reflash U-boot Image using U-boot
94 94
95 tftp 40000 u-boot.bin 95 tftp 40000 u-boot.bin
96 protect off fe000000 fe1fffff 96 protect off fe000000 fe1fffff
97 erase fe000000 fe1fffff 97 erase fe000000 fe1fffff
98 98
99 cp.b 40000 fe000000 xxxx 99 cp.b 40000 fe000000 xxxx
100 100
101 You have to supply the correct byte count with 'xxxx' from the TFTP result log. 101 You have to supply the correct byte count with 'xxxx' from the TFTP result log.
102 102
103 6. Notes 103 6. Notes
104 1) The console baudrate for MPC837XEMDS is 115200bps. 104 1) The console baudrate for MPC837XEMDS is 115200bps.
105 105
doc/README.mpc8544ds
Diff comments   View file @ c46bf09
1 Overview 1 Overview
2 -------- 2 --------
3 The MPC8544DS system is similar to the 85xx CDS systems such 3 The MPC8544DS system is similar to the 85xx CDS systems such
4 as the MPC8548CDS due to the similar E500 core. However, it 4 as the MPC8548CDS due to the similar E500 core. However, it
5 is placed on the same board as the 8641 HPCN system. 5 is placed on the same board as the 8641 HPCN system.
6 6
7 7
8 Flash Banks 8 Flash Banks
9 ----------- 9 -----------
10 Like the 85xx CDS systems, the 8544 DS board has two flash banks. 10 Like the 85xx CDS systems, the 8544 DS board has two flash banks.
11 They are both present on boot, but there locations can be swapped 11 They are both present on boot, but there locations can be swapped
12 using the dip-switch SW10, bit 2. 12 using the dip-switch SW10, bit 2.
13 13
14 However, unlike the CDS systems, but similar to the 8641 HPCN 14 However, unlike the CDS systems, but similar to the 8641 HPCN
15 board, a runtime reset through the FPGA can also affect a swap 15 board, a runtime reset through the FPGA can also affect a swap
16 on the flash bank mappings for the next reset cycle. 16 on the flash bank mappings for the next reset cycle.
17 17
18 Irrespective of the switch SW10[2], booting is always from the 18 Irrespective of the switch SW10[2], booting is always from the
19 boot bank at 0xfff8_0000. 19 boot bank at 0xfff8_0000.
20 20
21 21
22 Memory Map 22 Memory Map
23 ---------- 23 ----------
24 24
25 0xff80_0000 - 0xffbf_ffff Alernate bank 4MB 25 0xff80_0000 - 0xffbf_ffff Alternate bank 4MB
26 0xffc0_0000 - 0xffff_ffff Boot bank 4MB 26 0xffc0_0000 - 0xffff_ffff Boot bank 4MB
27 27
28 0xffb8_0000 Alternate image start 512KB 28 0xffb8_0000 Alternate image start 512KB
29 0xfff8_0000 Boot image start 512KB 29 0xfff8_0000 Boot image start 512KB
30 30
31 31
32 Flashing Images 32 Flashing Images
33 --------------- 33 ---------------
34 34
35 For example, to place a new image in the alternate flash bank 35 For example, to place a new image in the alternate flash bank
36 and then reset with that new image temporarily, use this: 36 and then reset with that new image temporarily, use this:
37 37
38 tftp 1000000 u-boot.bin.8544ds 38 tftp 1000000 u-boot.bin.8544ds
39 erase ffb80000 ffbfffff 39 erase ffb80000 ffbfffff
40 cp.b 1000000 ffb80000 80000 40 cp.b 1000000 ffb80000 80000
41 pixis_reset altbank 41 pixis_reset altbank
42 42
43 43
44 To overwrite the image in the boot flash bank: 44 To overwrite the image in the boot flash bank:
45 45
46 tftp 1000000 u-boot.bin.8544ds 46 tftp 1000000 u-boot.bin.8544ds
47 protect off all 47 protect off all
48 erase fff80000 ffffffff 48 erase fff80000 ffffffff
49 cp.b 1000000 fff80000 80000 49 cp.b 1000000 fff80000 80000
50 50
51 Other example U-Boot image and flash manipulations examples 51 Other example U-Boot image and flash manipulations examples
52 can be found in the README.mpc85xxcds file as well. 52 can be found in the README.mpc85xxcds file as well.
53 53
54 54
55 The pixis_reset command 55 The pixis_reset command
56 ----------------------- 56 -----------------------
57 A new command, "pixis_reset", is introduced to reset mpc8641hpcn board 57 A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
58 using the FPGA sequencer. When the board restarts, it has the option 58 using the FPGA sequencer. When the board restarts, it has the option
59 of using either the current or alternate flash bank as the boot 59 of using either the current or alternate flash bank as the boot
60 image, with or without the watchdog timer enabled, and finally with 60 image, with or without the watchdog timer enabled, and finally with
61 or without frequency changes. 61 or without frequency changes.
62 62
63 Usage is; 63 Usage is;
64 64
65 pixis_reset 65 pixis_reset
66 pixis_reset altbank 66 pixis_reset altbank
67 pixis_reset altbank wd 67 pixis_reset altbank wd
68 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> 68 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
69 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> 69 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
70 70
71 Examples; 71 Examples;
72 72
73 /* reset to current bank, like "reset" command */ 73 /* reset to current bank, like "reset" command */
74 pixis_reset 74 pixis_reset
75 75
76 /* reset board but use the to alternate flash bank */ 76 /* reset board but use the to alternate flash bank */
77 pixis_reset altbank 77 pixis_reset altbank
78 78
79 /* reset board, use alternate flash bank with watchdog timer enabled*/ 79 /* reset board, use alternate flash bank with watchdog timer enabled*/
80 pixis_reset altbank wd 80 pixis_reset altbank wd
81 81
82 /* reset board to alternate bank with frequency changed. 82 /* reset board to alternate bank with frequency changed.
83 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio 83 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
84 */ 84 */
85 pixis-reset altbank cf 40 2.5 10 85 pixis-reset altbank cf 40 2.5 10
86 86
87 Valid clock choices are in the 8641 Reference Manuals. 87 Valid clock choices are in the 8641 Reference Manuals.
88 88
89 89
90 Using the Device Tree Source File 90 Using the Device Tree Source File
91 --------------------------------- 91 ---------------------------------
92 To create the DTB (Device Tree Binary) image file, 92 To create the DTB (Device Tree Binary) image file,
93 use a command similar to this: 93 use a command similar to this:
94 94
95 dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb 95 dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb
96 96
97 Likely, that .dts file will come from here; 97 Likely, that .dts file will come from here;
98 98
99 linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts 99 linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts
100 100
101 After placing the DTB file in your TFTP disk area, 101 After placing the DTB file in your TFTP disk area,
102 you can download that dtb file using a command like: 102 you can download that dtb file using a command like:
103 103
104 tftp 900000 mpc8544ds.dtb 104 tftp 900000 mpc8544ds.dtb
105 105
106 Burn it to flash if you want. 106 Burn it to flash if you want.
107 107
108 108
109 Booting Linux 109 Booting Linux
110 ------------- 110 -------------
111 111
112 Place a linux uImage in the TFTP disk area too. 112 Place a linux uImage in the TFTP disk area too.
113 113
114 tftp 1000000 uImage.8544 114 tftp 1000000 uImage.8544
115 tftp 900000 mpc8544ds.dtb 115 tftp 900000 mpc8544ds.dtb
116 bootm 1000000 - 900000 116 bootm 1000000 - 900000
117 117
118 Watch your ethact, netdev and bootargs U-Boot environment variables. 118 Watch your ethact, netdev and bootargs U-Boot environment variables.
119 You may want to do something like this too: 119 You may want to do something like this too:
120 120
121 setenv ethact eTSEC3 121 setenv ethact eTSEC3
122 setenv netdev eth1 122 setenv netdev eth1
123 123
doc/README.mpc8572ds
Diff comments   View file @ c46bf09
1 Overview 1 Overview
2 -------- 2 --------
3 MPC8572DS is a high-performance computing, evaluation and development platform 3 MPC8572DS is a high-performance computing, evaluation and development platform
4 supporting the mpc8572 PowerTM processor. 4 supporting the mpc8572 PowerTM processor.
5 5
6 Building U-boot 6 Building U-boot
7 ----------- 7 -----------
8 make MPC8572DS_config 8 make MPC8572DS_config
9 make 9 make
10 10
11 Flash Banks 11 Flash Banks
12 ----------- 12 -----------
13 MPC8572DS board has two flash banks. They are both present on boot, but their 13 MPC8572DS board has two flash banks. They are both present on boot, but their
14 locations can be swapped using the dip-switch SW9[1:2]. 14 locations can be swapped using the dip-switch SW9[1:2].
15 15
16 Booting is always from the boot bank at 0xec00_0000. 16 Booting is always from the boot bank at 0xec00_0000.
17 17
18 18
19 Memory Map 19 Memory Map
20 ---------- 20 ----------
21 21
22 0xe800_0000 - 0xebff_ffff Alernate bank 64MB 22 0xe800_0000 - 0xebff_ffff Alternate bank 64MB
23 0xec00_0000 - 0xefff_ffff Boot bank 64MB 23 0xec00_0000 - 0xefff_ffff Boot bank 64MB
24 24
25 0xebf8_0000 - 0xebff_ffff Alternate u-boot address 512KB 25 0xebf8_0000 - 0xebff_ffff Alternate u-boot address 512KB
26 0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB 26 0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB
27 27
28 28
29 Flashing Images 29 Flashing Images
30 --------------- 30 ---------------
31 31
32 To place a new u-boot image in the alternate flash bank and then reset with that 32 To place a new u-boot image in the alternate flash bank and then reset with that
33 new image temporarily, use this: 33 new image temporarily, use this:
34 34
35 tftp 1000000 u-boot.bin 35 tftp 1000000 u-boot.bin
36 erase ebf80000 ebffffff 36 erase ebf80000 ebffffff
37 cp.b 1000000 ebf80000 80000 37 cp.b 1000000 ebf80000 80000
38 pixis_reset altbank 38 pixis_reset altbank
39 39
40 40
41 To program the image in the boot flash bank: 41 To program the image in the boot flash bank:
42 42
43 tftp 1000000 u-boot.bin 43 tftp 1000000 u-boot.bin
44 protect off all 44 protect off all
45 erase eff80000 ffffffff 45 erase eff80000 ffffffff
46 cp.b 1000000 eff80000 80000 46 cp.b 1000000 eff80000 80000
47 47
48 48
49 The pixis_reset command 49 The pixis_reset command
50 ----------------------- 50 -----------------------
51 The command - "pixis_reset", is introduced to reset mpc8572ds board 51 The command - "pixis_reset", is introduced to reset mpc8572ds board
52 using the FPGA sequencer. When the board restarts, it has the option 52 using the FPGA sequencer. When the board restarts, it has the option
53 of using either the current or alternate flash bank as the boot 53 of using either the current or alternate flash bank as the boot
54 image, with or without the watchdog timer enabled, and finally with 54 image, with or without the watchdog timer enabled, and finally with
55 or without frequency changes. 55 or without frequency changes.
56 56
57 Usage is; 57 Usage is;
58 58
59 pixis_reset 59 pixis_reset
60 pixis_reset altbank 60 pixis_reset altbank
61 pixis_reset altbank wd 61 pixis_reset altbank wd
62 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> 62 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
63 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio> 63 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
64 64
65 Examples: 65 Examples:
66 66
67 /* reset to current bank, like "reset" command */ 67 /* reset to current bank, like "reset" command */
68 pixis_reset 68 pixis_reset
69 69
70 /* reset board but use the to alternate flash bank */ 70 /* reset board but use the to alternate flash bank */
71 pixis_reset altbank 71 pixis_reset altbank
72 72
73 73
74 Using the Device Tree Source File 74 Using the Device Tree Source File
75 --------------------------------- 75 ---------------------------------
76 To create the DTB (Device Tree Binary) image file, 76 To create the DTB (Device Tree Binary) image file,
77 use a command similar to this: 77 use a command similar to this:
78 78
79 dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb 79 dtc -b 0 -f -I dts -O dtb mpc8572ds.dts > mpc8572ds.dtb
80 80
81 Likely, that .dts file will come from here; 81 Likely, that .dts file will come from here;
82 82
83 linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts 83 linux-2.6/arch/powerpc/boot/dts/mpc8572ds.dts
84 84
85 85
86 Booting Linux 86 Booting Linux
87 ------------- 87 -------------
88 88
89 Place a linux uImage in the TFTP disk area. 89 Place a linux uImage in the TFTP disk area.
90 90
91 tftp 1000000 uImage.8572 91 tftp 1000000 uImage.8572
92 tftp c00000 mpc8572ds.dtb 92 tftp c00000 mpc8572ds.dtb
93 bootm 1000000 - c00000 93 bootm 1000000 - c00000
94 94
95 95
96 Implementing AMP(Asymmetric MultiProcessing) 96 Implementing AMP(Asymmetric MultiProcessing)
97 ------------- 97 -------------
98 1. Build kernel image for core0: 98 1. Build kernel image for core0:
99 99
100 a. $ make 85xx/mpc8572_ds_defconfig 100 a. $ make 85xx/mpc8572_ds_defconfig
101 101
102 b. $ make menuconfig 102 b. $ make menuconfig
103 - un-select "Processor support"->"Symetric multi-processing support" 103 - un-select "Processor support"->"Symetric multi-processing support"
104 104
105 c. $ make uImage 105 c. $ make uImage
106 106
107 d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0 107 d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
108 108
109 2. Build kernel image for core1: 109 2. Build kernel image for core1:
110 110
111 a. $ make 85xx/mpc8572_ds_defconfig 111 a. $ make 85xx/mpc8572_ds_defconfig
112 112
113 b. $ make menuconfig 113 b. $ make menuconfig
114 - Un-select "Processor support"->"Symetric multi-processing support" 114 - Un-select "Processor support"->"Symetric multi-processing support"
115 - Select "Advanced setup" -> " Prompt for advanced kernel 115 - Select "Advanced setup" -> " Prompt for advanced kernel
116 configuration options" 116 configuration options"
117 - Select "Set physical address where the kernel is loaded" and 117 - Select "Set physical address where the kernel is loaded" and
118 set it to 0x20000000, asssuming core1 will start from 512MB. 118 set it to 0x20000000, assuming core1 will start from 512MB.
119 - Select "Set custom page offset address" 119 - Select "Set custom page offset address"
120 - Select "Set custom kernel base address" 120 - Select "Set custom kernel base address"
121 - Select "Set maximum low memory" 121 - Select "Set maximum low memory"
122 - "Exit" and save the selection. 122 - "Exit" and save the selection.
123 123
124 c. $ make uImage 124 c. $ make uImage
125 125
126 d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1 126 d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
127 127
128 3. Create dtb for core0: 128 3. Create dtb for core0:
129 129
130 $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb 130 $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb
131 131
132 4. Create dtb for core1: 132 4. Create dtb for core1:
133 133
134 $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb 134 $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb
135 135
136 5. Bring up two cores separately: 136 5. Bring up two cores separately:
137 137
138 a. Power on the board, under u-boot prompt: 138 a. Power on the board, under u-boot prompt:
139 => setenv <serverip> 139 => setenv <serverip>
140 => setenv <ipaddr> 140 => setenv <ipaddr>
141 => setenv bootargs root=/dev/ram rw console=ttyS0,115200 141 => setenv bootargs root=/dev/ram rw console=ttyS0,115200
142 b. Bring up core1's kernel first: 142 b. Bring up core1's kernel first:
143 => setenv bootm_low 0x20000000 143 => setenv bootm_low 0x20000000
144 => setenv bootm_size 0x10000000 144 => setenv bootm_size 0x10000000
145 => tftp 21000000 8572/uImage.core1 145 => tftp 21000000 8572/uImage.core1
146 => tftp 22000000 8572/ramdiskfile 146 => tftp 22000000 8572/ramdiskfile
147 => tftp 20c00000 8572/mpc8572ds_core1.dtb 147 => tftp 20c00000 8572/mpc8572ds_core1.dtb
148 => interrupts off 148 => interrupts off
149 => bootm start 21000000 22000000 20c00000 149 => bootm start 21000000 22000000 20c00000
150 => bootm loados 150 => bootm loados
151 => bootm ramdisk 151 => bootm ramdisk
152 => bootm fdt 152 => bootm fdt
153 => fdt boardsetup 153 => fdt boardsetup
154 => fdt chosen $initrd_start $initrd_end 154 => fdt chosen $initrd_start $initrd_end
155 => bootm prep 155 => bootm prep
156 => cpu 1 release $bootm_low - $fdtaddr - 156 => cpu 1 release $bootm_low - $fdtaddr -
157 c. Bring up core0's kernel(on the same u-boot console): 157 c. Bring up core0's kernel(on the same u-boot console):
158 => setenv bootm_low 0 158 => setenv bootm_low 0
159 => setenv bootm_size 0x20000000 159 => setenv bootm_size 0x20000000
160 => tftp 1000000 8572/uImage.core0 160 => tftp 1000000 8572/uImage.core0
161 => tftp 2000000 8572/ramdiskfile 161 => tftp 2000000 8572/ramdiskfile
162 => tftp c00000 8572/mpc8572ds_core0.dtb 162 => tftp c00000 8572/mpc8572ds_core0.dtb
163 => bootm 1000000 2000000 c00000 163 => bootm 1000000 2000000 c00000
164 164
165 Please note only core0 will run u-boot, core1 starts kernel directly after 165 Please note only core0 will run u-boot, core1 starts kernel directly after
166 "cpu release" command is issued. 166 "cpu release" command is issued.
167 167
doc/README.mpc85xxads
Diff comments   View file @ c46bf09
1 Motorola MPC8540ADS and MPC8560ADS board 1 Motorola MPC8540ADS and MPC8560ADS board
2 2
3 Created 10/15/03 Xianghua Xiao 3 Created 10/15/03 Xianghua Xiao
4 Updated 13-July-2004 Jon Loeliger 4 Updated 13-July-2004 Jon Loeliger
5 ----------------------------------------- 5 -----------------------------------------
6 6
7 0. Toolchain 7 0. Toolchain
8 8
9 The Binutils in current ELDK toolchain will not support MPC85xx 9 The Binutils in current ELDK toolchain will not support MPC85xx
10 chip. You need to use binutils-2.14.tar.bz2 (or newer) from 10 chip. You need to use binutils-2.14.tar.bz2 (or newer) from
11 http://ftp.gnu.org/gnu/binutils. 11 http://ftp.gnu.org/gnu/binutils.
12 12
13 The 8540/8560 ADS code base is known to compile using: 13 The 8540/8560 ADS code base is known to compile using:
14 gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a) 14 gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a)
15 15
16 16
17 1. SWITCH SETTINGS & JUMPERS 17 1. SWITCH SETTINGS & JUMPERS
18 18
19 1.0 Nomenclature 19 1.0 Nomenclature
20 20
21 For some reason, the HW designers describe the switch settings 21 For some reason, the HW designers describe the switch settings
22 in terms of 0 and 1, and then map that to physical switches where 22 in terms of 0 and 1, and then map that to physical switches where
23 the label "On" refers to logic 0 and "Off" (unlabeled) is logic 1. 23 the label "On" refers to logic 0 and "Off" (unlabeled) is logic 1.
24 Luckily, we're SW types and virtual settings are handled daily. 24 Luckily, we're SW types and virtual settings are handled daily.
25 25
26 The switches for the Rev A board are numbered differently than 26 The switches for the Rev A board are numbered differently than
27 for the Pilot board. Oh yeah. 27 for the Pilot board. Oh yeah.
28 28
29 Switch bits are numbered 1 through, like, 4 6 8 or 10, but the 29 Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
30 bits may contribute to signals that are numbered based at 0, 30 bits may contribute to signals that are numbered based at 0,
31 and some of those signals may be high-bit-number-0 too. Heed 31 and some of those signals may be high-bit-number-0 too. Heed
32 well the names and labels and do not get confused. 32 well the names and labels and do not get confused.
33 33
34 "Off" == 1 34 "Off" == 1
35 "On" == 0 35 "On" == 0
36 36
37 SW18 is switch 18 as silk-screened onto the board. 37 SW18 is switch 18 as silk-screened onto the board.
38 SW4[8] is the bit labled 8 on Switch 4. 38 SW4[8] is the bit labeled 8 on Switch 4.
39 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2 39 SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2
40 SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3 40 SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3
41 41
42 1.1 For the MPC85xxADS Pilot Board 42 1.1 For the MPC85xxADS Pilot Board
43 43
44 First, make sure the board default setting is consistent with the document 44 First, make sure the board default setting is consistent with the document
45 shipped with your board. Then apply the following changes: 45 shipped with your board. Then apply the following changes:
46 SW3[1-6]="all OFF" (boot from 32bit flash, no boot sequence is used) 46 SW3[1-6]="all OFF" (boot from 32bit flash, no boot sequence is used)
47 SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560) 47 SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560)
48 SW11[2]='OFF for 8560, ON for 8540' (toggle 8540.8560 mode) 48 SW11[2]='OFF for 8560, ON for 8540' (toggle 8540.8560 mode)
49 SW11[7]='ON' (rev2), 'OFF' (rev1) 49 SW11[7]='ON' (rev2), 'OFF' (rev1)
50 SW4[7-8]="OFF OFF" (enable serial ports,I'm using the top serial connector) 50 SW4[7-8]="OFF OFF" (enable serial ports,I'm using the top serial connector)
51 SW22[1-4]="OFF OFF ON OFF" 51 SW22[1-4]="OFF OFF ON OFF"
52 SW5[1-10[="ON ON OFF OFF OFF OFF OFF OFF OFF OFF" 52 SW5[1-10[="ON ON OFF OFF OFF OFF OFF OFF OFF OFF"
53 J1 = "Enable Prog" (Make sure your flash is programmable for development) 53 J1 = "Enable Prog" (Make sure your flash is programmable for development)
54 54
55 If you want to test PCI functionality with a 33Mhz PCI card, you will 55 If you want to test PCI functionality with a 33Mhz PCI card, you will
56 have to change the system clock from the default 66Mhz to 33Mhz by 56 have to change the system clock from the default 66Mhz to 33Mhz by
57 setting SW15[1]="OFF" and SW17[8]="OFF". After that you may also need 57 setting SW15[1]="OFF" and SW17[8]="OFF". After that you may also need
58 double your platform clock(SW6) because the system clock is now only 58 double your platform clock(SW6) because the system clock is now only
59 half of its original value. For example, if at 66MHz your system 59 half of its original value. For example, if at 66MHz your system
60 clock showed SW6[0:1] = 01, then at 33MHz SW6[0:1] it should be 10. 60 clock showed SW6[0:1] = 01, then at 33MHz SW6[0:1] it should be 10.
61 61
62 SW17[8] ------+ SW6 62 SW17[8] ------+ SW6
63 SW15[1] ----+ | [0:1] 63 SW15[1] ----+ | [0:1]
64 V V V V 64 V V V V
65 33MHz 1 1 1 0 65 33MHz 1 1 1 0
66 66MHz 0 0 0 1 66 66MHz 0 0 0 1
67 67
68 Hmmm... That SW6 setting description is incomplete but it works. 68 Hmmm... That SW6 setting description is incomplete but it works.
69 69
70 70
71 1.3 For the MPC85xxADS Rev A Board 71 1.3 For the MPC85xxADS Rev A Board
72 72
73 As shipped, the board should be a 33MHz PCI bus with a CPU Clock 73 As shipped, the board should be a 33MHz PCI bus with a CPU Clock
74 rate of 825 +/- fuzz: 74 rate of 825 +/- fuzz:
75 75
76 Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz 76 Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz
77 77
78 For 33MHz PCI, the switch settings should be like this: 78 For 33MHz PCI, the switch settings should be like this:
79 79
80 SW18[7:1] = 0100001 = M==33 => 33MHz 80 SW18[7:1] = 0100001 = M==33 => 33MHz
81 SW18[8] = 1 => PWD Divider == 16 81 SW18[8] = 1 => PWD Divider == 16
82 SW16[1:2] = 11 => N == 16 as PWD==1 82 SW16[1:2] = 11 => N == 16 as PWD==1
83 83
84 Use the magical formula: 84 Use the magical formula:
85 Fout (MHz) = 16 * M / N = 16 * 33 / 16 = 33 MHz 85 Fout (MHz) = 16 * M / N = 16 * 33 / 16 = 33 MHz
86 86
87 SW7[1:4] = 1010 = 10 => 10 x 33 = 330 CCB Sysclk 87 SW7[1:4] = 1010 = 10 => 10 x 33 = 330 CCB Sysclk
88 SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock 88 SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock
89 89
90 90
91 For 66MHz PCI, the switch settings should be like this: 91 For 66MHz PCI, the switch settings should be like this:
92 92
93 SW18[7:1] = 0100001 = M==33 => 33MHz 93 SW18[7:1] = 0100001 = M==33 => 33MHz
94 SW18[8] = 0 => PWD Divider == 1 94 SW18[8] = 0 => PWD Divider == 1
95 SW16[1:2] = 01 => N == 8 as PWD == 0 95 SW16[1:2] = 01 => N == 8 as PWD == 0
96 96
97 Use the magical formula: 97 Use the magical formula:
98 Fout (MHz) = 16 * M / N = 16 * 33 / 8 = 66 MHz 98 Fout (MHz) = 16 * M / N = 16 * 33 / 8 = 66 MHz
99 99
100 SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk 100 SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk
101 SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock 101 SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock
102 102
103 In order to use PCI-X (only in the first PCI slot. The one with 103 In order to use PCI-X (only in the first PCI slot. The one with
104 the RIO connector), you need to set SW1[4] (config) to 1 (off). 104 the RIO connector), you need to set SW1[4] (config) to 1 (off).
105 Also, configure the board to run PCI at 66 MHz. 105 Also, configure the board to run PCI at 66 MHz.
106 106
107 2. MEMORY MAP TO WORK WITH LINUX KERNEL 107 2. MEMORY MAP TO WORK WITH LINUX KERNEL
108 108
109 2.1. For the initial bringup, we adopted a consistent memory scheme 109 2.1. For the initial bringup, we adopted a consistent memory scheme
110 between u-boot and linux kernel, you can customize it based on your 110 between u-boot and linux kernel, you can customize it based on your
111 system requirements: 111 system requirements:
112 112
113 0x0000_0000 0x7fff_ffff DDR 2G 113 0x0000_0000 0x7fff_ffff DDR 2G
114 0x8000_0000 0x9fff_ffff PCI MEM 512M 114 0x8000_0000 0x9fff_ffff PCI MEM 512M
115 0xc000_0000 0xdfff_ffff Rapid IO 512M 115 0xc000_0000 0xdfff_ffff Rapid IO 512M
116 0xe000_0000 0xe00f_ffff CCSR 1M 116 0xe000_0000 0xe00f_ffff CCSR 1M
117 0xe200_0000 0xe2ff_ffff PCI IO 16M 117 0xe200_0000 0xe2ff_ffff PCI IO 16M
118 0xf000_0000 0xf7ff_ffff SDRAM 128M 118 0xf000_0000 0xf7ff_ffff SDRAM 128M
119 0xf800_0000 0xf80f_ffff BCSR 1M 119 0xf800_0000 0xf80f_ffff BCSR 1M
120 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M 120 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
121 121
122 2.2 We are submitting Linux kernel patches for MPC8540 and MPC8560. You 122 2.2 We are submitting Linux kernel patches for MPC8540 and MPC8560. You
123 can download them from linuxppc-2.4 public source. Please make sure the 123 can download them from linuxppc-2.4 public source. Please make sure the
124 kernel's ppcboot.h is consistent with U-Boot's u-boot.h. You can use two 124 kernel's ppcboot.h is consistent with U-Boot's u-boot.h. You can use two
125 default configuration files as your starting points to configure the 125 default configuration files as your starting points to configure the
126 kernel: 126 kernel:
127 arch/powerpc/configs/mpc8540_ads_defconfig 127 arch/powerpc/configs/mpc8540_ads_defconfig
128 arch/powerpc/configs/mpc8560_ads_defconfig 128 arch/powerpc/configs/mpc8560_ads_defconfig
129 129
130 3. DEFINITIONS AND COMPILATION 130 3. DEFINITIONS AND COMPILATION
131 131
132 3.1 Explanation on NEW definitions in: 132 3.1 Explanation on NEW definitions in:
133 include/configs/MPC8540ADS.h 133 include/configs/MPC8540ADS.h
134 include/configs/MPC8560ADS.h 134 include/configs/MPC8560ADS.h
135 135
136 CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, AMCC 440, etc) 136 CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, AMCC 440, etc)
137 CONFIG_E500 BOOKE e500 family(Motorola) 137 CONFIG_E500 BOOKE e500 family(Motorola)
138 CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives 138 CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives
139 CONFIG_MPC8540 MPC8540 specific 139 CONFIG_MPC8540 MPC8540 specific
140 CONFIG_MPC8540ADS MPC8540ADS board specific 140 CONFIG_MPC8540ADS MPC8540ADS board specific
141 CONFIG_MPC8560ADS MPC8560ADS board specific 141 CONFIG_MPC8560ADS MPC8560ADS board specific
142 CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking 142 CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking
143 CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can 143 CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can
144 also manual config the DDR after undef this 144 also manual config the DDR after undef this
145 definition. 145 definition.
146 CONFIG_DDR_ECC only for ECC DDR module 146 CONFIG_DDR_ECC only for ECC DDR module
147 CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN DLL fix on some ADS boards needed 147 CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN DLL fix on some ADS boards needed
148 for more stability. 148 for more stability.
149 CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0. 149 CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0.
150 150
151 Other than the above definitions, the rest in the config files are 151 Other than the above definitions, the rest in the config files are
152 straightforward. 152 straightforward.
153 153
154 154
155 3.2 Compilation 155 3.2 Compilation
156 156
157 Assuming you're using BASH shell: 157 Assuming you're using BASH shell:
158 158
159 export CROSS_COMPILE=your-cross-compile-prefix 159 export CROSS_COMPILE=your-cross-compile-prefix
160 cd u-boot 160 cd u-boot
161 make distclean 161 make distclean
162 make MPC8560ADS_config (or make MPC8540ADS_config) 162 make MPC8560ADS_config (or make MPC8540ADS_config)
163 make 163 make
164 164
165 4. Notes: 165 4. Notes:
166 166
167 4.1 When connecting with kermit, the following commands must be present.in 167 4.1 When connecting with kermit, the following commands must be present.in
168 your .kermrc file. These are especially important when booting as 168 your .kermrc file. These are especially important when booting as
169 MPC8560, as the serial console will not work without them: 169 MPC8560, as the serial console will not work without them:
170 170
171 set speed 115200 171 set speed 115200
172 set carrier-watch off 172 set carrier-watch off
173 set handshake none 173 set handshake none
174 set flow-control none 174 set flow-control none
175 robust 175 robust
176 176
177 177
178 4.2 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC 178 4.2 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC
179 ethernet. If that happens, you can try the following steps to make 179 ethernet. If that happens, you can try the following steps to make
180 network work: 180 network work:
181 181
182 MPC8560ADS>tftp 1000000 pImage 182 MPC8560ADS>tftp 1000000 pImage
183 (if it hangs, use Ctrl-C to quit) 183 (if it hangs, use Ctrl-C to quit)
184 MPC8560ADS>nm fdf24524 184 MPC8560ADS>nm fdf24524
185 >0 185 >0
186 >1 186 >1
187 >. (to quit this memory operation) 187 >. (to quit this memory operation)
188 MPC8560ADS>tftp 1000000 pImage 188 MPC8560ADS>tftp 1000000 pImage
189 189
190 4.3 If you're one of the early developers using the Rev1 8540/8560 chips, 190 4.3 If you're one of the early developers using the Rev1 8540/8560 chips,
191 please use U-Boot 1.0.0, as the newer silicon will only support Rev2 191 please use U-Boot 1.0.0, as the newer silicon will only support Rev2
192 and future revisions of 8540/8560. 192 and future revisions of 8540/8560.
193 193
194 194
195 4.4 Reflash U-boot Image using U-boot 195 4.4 Reflash U-boot Image using U-boot
196 196
197 tftp 10000 u-boot.bin 197 tftp 10000 u-boot.bin
198 protect off fff80000 ffffffff 198 protect off fff80000 ffffffff
199 erase fff80000 ffffffff 199 erase fff80000 ffffffff
200 cp.b 10000 fff80000 80000 200 cp.b 10000 fff80000 80000
201 201
202 202
203 4.5 Reflash U-Boot with a BDI-2000 203 4.5 Reflash U-Boot with a BDI-2000
204 204
205 BDI> erase 0xFFF80000 0x4000 0x20 205 BDI> erase 0xFFF80000 0x4000 0x20
206 BDI> prog 0xfff80000 u-boot.bin.8560ads 206 BDI> prog 0xfff80000 u-boot.bin.8560ads
207 BDI> verify 207 BDI> verify
208 208
209 209
210 5. Screen dump MPC8540ADS board 210 5. Screen dump MPC8540ADS board
211 211
212 U-Boot 1.1.2(pq3-20040707-0) (Jul 6 2004 - 17:34:25) 212 U-Boot 1.1.2(pq3-20040707-0) (Jul 6 2004 - 17:34:25)
213 213
214 Freescale PowerPC 214 Freescale PowerPC
215 Core: E500, Version: 2.0, (0x80200020) 215 Core: E500, Version: 2.0, (0x80200020)
216 System: 8540, Version: 2.0, (0x80300020) 216 System: 8540, Version: 2.0, (0x80300020)
217 Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz 217 Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC: 82 MHz
218 L1 D-cache 32KB, L1 I-cache 32KB enabled. 218 L1 D-cache 32KB, L1 I-cache 32KB enabled.
219 Board: ADS 219 Board: ADS
220 PCI1: 32 bit, 66 MHz (compiled) 220 PCI1: 32 bit, 66 MHz (compiled)
221 I2C: ready 221 I2C: ready
222 DRAM: Initializing 222 DRAM: Initializing
223 SDRAM: 64 MB 223 SDRAM: 64 MB
224 DDR: 256 MB 224 DDR: 256 MB
225 FLASH: 16 MB 225 FLASH: 16 MB
226 L2 cache enabled: 256KB 226 L2 cache enabled: 256KB
227 *** Warning - bad CRC, using default environment 227 *** Warning - bad CRC, using default environment
228 228
229 In: serial 229 In: serial
230 Out: serial 230 Out: serial
231 Err: serial 231 Err: serial
232 Net: MOTO ENET0: PHY is Marvell 88E1011S (1410c62) 232 Net: MOTO ENET0: PHY is Marvell 88E1011S (1410c62)
233 MOTO ENET1: PHY is Marvell 88E1011S (1410c62) 233 MOTO ENET1: PHY is Marvell 88E1011S (1410c62)
234 MOTO ENET2: PHY is Davicom DM9161E (181b881) 234 MOTO ENET2: PHY is Davicom DM9161E (181b881)
235 MOTO ENET0, MOTO ENET1, MOTO ENET2 235 MOTO ENET0, MOTO ENET1, MOTO ENET2
236 Hit any key to stop autoboot: 0 236 Hit any key to stop autoboot: 0
237 => 237 =>
238 => fli 238 => fli
239 239
240 Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K) 240 Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
241 Size: 16 MB in 64 Sectors 241 Size: 16 MB in 64 Sectors
242 Sector Start Addresses: 242 Sector Start Addresses:
243 FF000000 FF040000 FF080000 FF0C0000 FF100000 243 FF000000 FF040000 FF080000 FF0C0000 FF100000
244 FF140000 FF180000 FF1C0000 FF200000 FF240000 244 FF140000 FF180000 FF1C0000 FF200000 FF240000
245 FF280000 FF2C0000 FF300000 FF340000 FF380000 245 FF280000 FF2C0000 FF300000 FF340000 FF380000
246 FF3C0000 FF400000 FF440000 FF480000 FF4C0000 246 FF3C0000 FF400000 FF440000 FF480000 FF4C0000
247 FF500000 FF540000 FF580000 FF5C0000 FF600000 247 FF500000 FF540000 FF580000 FF5C0000 FF600000
248 FF640000 FF680000 FF6C0000 FF700000 FF740000 248 FF640000 FF680000 FF6C0000 FF700000 FF740000
249 FF780000 FF7C0000 FF800000 FF840000 FF880000 249 FF780000 FF7C0000 FF800000 FF840000 FF880000
250 FF8C0000 FF900000 FF940000 FF980000 FF9C0000 250 FF8C0000 FF900000 FF940000 FF980000 FF9C0000
251 FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000 251 FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000
252 FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000 252 FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
253 FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000 253 FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
254 FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000 254 FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
255 FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO) 255 FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO)
256 256
257 => bdinfo 257 => bdinfo
258 memstart = 0x00000000 258 memstart = 0x00000000
259 memsize = 0x10000000 259 memsize = 0x10000000
260 flashstart = 0xFF000000 260 flashstart = 0xFF000000
261 flashsize = 0x01000000 261 flashsize = 0x01000000
262 flashoffset = 0x00000000 262 flashoffset = 0x00000000
263 sramstart = 0x00000000 263 sramstart = 0x00000000
264 sramsize = 0x00000000 264 sramsize = 0x00000000
265 immr_base = 0xE0000000 265 immr_base = 0xE0000000
266 bootflags = 0xE4013F80 266 bootflags = 0xE4013F80
267 intfreq = 825 MHz 267 intfreq = 825 MHz
268 busfreq = 330 MHz 268 busfreq = 330 MHz
269 ethaddr = 00:E0:0C:00:00:FD 269 ethaddr = 00:E0:0C:00:00:FD
270 eth1addr = 00:E0:0C:00:01:FD 270 eth1addr = 00:E0:0C:00:01:FD
271 eth2addr = 00:E0:0C:00:02:FD 271 eth2addr = 00:E0:0C:00:02:FD
272 IP addr = 192.168.1.253 272 IP addr = 192.168.1.253
273 baudrate = 115200 bps 273 baudrate = 115200 bps
274 274
275 275
276 => printenv 276 => printenv
277 bootcmd=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr 277 bootcmd=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr
278 ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;bootm $loadaddr $ramdiskaddr 278 ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;bootm $loadaddr $ramdiskaddr
279 nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr 279 nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr
280 bootdelay=10 280 bootdelay=10
281 baudrate=115200 281 baudrate=115200
282 loads_echo=1 282 loads_echo=1
283 ethaddr=00:E0:0C:00:00:FD 283 ethaddr=00:E0:0C:00:00:FD
284 eth1addr=00:E0:0C:00:01:FD 284 eth1addr=00:E0:0C:00:01:FD
285 eth2addr=00:E0:0C:00:02:FD 285 eth2addr=00:E0:0C:00:02:FD
286 ipaddr=192.168.1.253 286 ipaddr=192.168.1.253
287 serverip=192.168.1.1 287 serverip=192.168.1.1
288 rootpath=/nfsroot 288 rootpath=/nfsroot
289 gatewayip=192.168.1.1 289 gatewayip=192.168.1.1
290 netmask=255.255.255.0 290 netmask=255.255.255.0
291 hostname=unknown 291 hostname=unknown
292 bootfile=your.uImage 292 bootfile=your.uImage
293 loadaddr=200000 293 loadaddr=200000
294 netdev=eth0 294 netdev=eth0
295 consoledev=ttyS0 295 consoledev=ttyS0
296 ramdiskaddr=400000 296 ramdiskaddr=400000
297 ramdiskfile=your.ramdisk.u-boot 297 ramdiskfile=your.ramdisk.u-boot
298 stdin=serial 298 stdin=serial
299 stdout=serial 299 stdout=serial
300 stderr=serial 300 stderr=serial
301 ethact=MOTO ENET0 301 ethact=MOTO ENET0
302 302
303 Environment size: 1020/8188 bytes 303 Environment size: 1020/8188 bytes
304 304
1 Matrix Vision mvBlueCOUGAR-P (mvBC-P) 1 Matrix Vision mvBlueCOUGAR-P (mvBC-P)
2 ------------------------------------- 2 -------------------------------------
3 3
4 1. Board Description 4 1. Board Description
5 5
6 The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera 6 The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera
7 with main focus on GigEVision protocol in combination with local image 7 with main focus on GigEVision protocol in combination with local image
8 preprocessing. 8 preprocessing.
9 9
10 Power Supply is either VDC 48V or Pover over Ethernet (PoE). 10 Power Supply is either VDC 48V or Pover over Ethernet (PoE).
11 11
12 2 System Components 12 2 System Components
13 13
14 2.1 CPU 14 2.1 CPU
15 Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB. 15 Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
16 64MB SDRAM @ 133MHz. 16 64MB SDRAM @ 133MHz.
17 8 MByte Nor Flash on local bus. 17 8 MByte Nor Flash on local bus.
18 1 serial ports. Console running on ttyS0 @ 115200 8N1. 18 1 serial ports. Console running on ttyS0 @ 115200 8N1.
19 19
20 2.2 PCI 20 2.2 PCI
21 PCI clock fixed at 66MHz. Arbitration inside FPGA. 21 PCI clock fixed at 66MHz. Arbitration inside FPGA.
22 Intel GD82541ER network MAC/PHY and FPGA connected. 22 Intel GD82541ER network MAC/PHY and FPGA connected.
23 23
24 2.3 FPGA 24 2.3 FPGA
25 Altera Cyclone-II EP2C8 with PCI DMA engine. 25 Altera Cyclone-II EP2C8 with PCI DMA engine.
26 Connects to Matrix Vision specific CCD/CMOS sensor interface. 26 Connects to Matrix Vision specific CCD/CMOS sensor interface.
27 Utilizes 64MB Nand Flash. 27 Utilizes 64MB Nand Flash.
28 28
29 2.3.1 I/O @ FPGA 29 2.3.1 I/O @ FPGA
30 2 Outputs : photo coupler 30 2 Outputs : photo coupler
31 2 Inputs : photo coupler 31 2 Inputs : photo coupler
32 32
33 2.4 I2C 33 2.4 I2C
34 LM75 @ 0x90 for temperature monitoring. 34 LM75 @ 0x90 for temperature monitoring.
35 EEPROM @ 0xA0 for vendor specifics. 35 EEPROM @ 0xA0 for vendor specifics.
36 image sensor interface (slave adresses depend on sensor) 36 image sensor interface (slave addresses depend on sensor)
37 37
38 3 Flash layout. 38 3 Flash layout.
39 39
40 reset vector is 0x00000100, i.e. "LOWBOOT". 40 reset vector is 0x00000100, i.e. "LOWBOOT".
41 41
42 FF800000 u-boot 42 FF800000 u-boot
43 FF840000 u-boot script image 43 FF840000 u-boot script image
44 FF850000 redundant u-boot script image 44 FF850000 redundant u-boot script image
45 FF860000 FPGA raw bit file 45 FF860000 FPGA raw bit file
46 FF8A0000 tbd. 46 FF8A0000 tbd.
47 FF900000 root FS 47 FF900000 root FS
48 FFC00000 kernel 48 FFC00000 kernel
49 FFFC0000 device tree blob 49 FFFC0000 device tree blob
50 FFFD0000 redundant device tree blob 50 FFFD0000 redundant device tree blob
51 FFFE0000 environment 51 FFFE0000 environment
52 FFFF0000 redundant environment 52 FFFF0000 redundant environment
53 53
54 mtd partitions are propagated to linux kernel via device tree blob. 54 mtd partitions are propagated to linux kernel via device tree blob.
55 55
56 4 Booting 56 4 Booting
57 57
58 On startup the bootscript @ FF840000 is executed. This script can be 58 On startup the bootscript @ FF840000 is executed. This script can be
59 exchanged easily. Default boot mode is "boot from flash", i.e. system 59 exchanged easily. Default boot mode is "boot from flash", i.e. system
60 works stand-alone. 60 works stand-alone.
61 61
62 This behaviour depends on some environment variables : 62 This behaviour depends on some environment variables :
63 63
64 "netboot" : yes ->try dhcp/bootp and boot from network. 64 "netboot" : yes ->try dhcp/bootp and boot from network.
65 A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for 65 A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
66 DHCP server configuration, e.g. to provide different images to 66 DHCP server configuration, e.g. to provide different images to
67 different devices. 67 different devices.
68 68
69 During netboot the system tries to get 3 image files: 69 During netboot the system tries to get 3 image files:
70 1. Kernel - name + data is given during BOOTP. 70 1. Kernel - name + data is given during BOOTP.
71 2. Initrd - name is stored in "initrd_name" 71 2. Initrd - name is stored in "initrd_name"
72 3. device tree blob - name is stored in "dtb_name" 72 3. device tree blob - name is stored in "dtb_name"
73 Fallback files are the flash versions. 73 Fallback files are the flash versions.
74 74
1 Matrix Vision mvBlueLYNX-M7 (mvBL-M7) 1 Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
2 ------------------------------------- 2 -------------------------------------
3 3
4 1. Board Description 4 1. Board Description
5 5
6 The mvBL-M7 is a 120x120mm single board computing platform 6 The mvBL-M7 is a 120x120mm single board computing platform
7 with strong focus on stereo image processing applications. 7 with strong focus on stereo image processing applications.
8 8
9 Power Supply is either VDC 12-48V or Pover over Ethernet (PoE) 9 Power Supply is either VDC 12-48V or Pover over Ethernet (PoE)
10 on any port (requires add-on board). 10 on any port (requires add-on board).
11 11
12 2 System Components 12 2 System Components
13 13
14 2.1 CPU 14 2.1 CPU
15 Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb. 15 Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
16 512MByte DDR-II memory @ 133MHz. 16 512MByte DDR-II memory @ 133MHz.
17 8 MByte Nor Flash on local bus. 17 8 MByte Nor Flash on local bus.
18 2 Vitesse VSC8601 RGMII ethernet Phys. 18 2 Vitesse VSC8601 RGMII ethernet Phys.
19 1 USB host controller over ULPI I/F. 19 1 USB host controller over ULPI I/F.
20 2 serial ports. Console running on ttyS0 @ 115200 8N1. 20 2 serial ports. Console running on ttyS0 @ 115200 8N1.
21 1 SD-Card slot connected to SPI. 21 1 SD-Card slot connected to SPI.
22 System configuration (HRCW) is taken from I2C EEPROM. 22 System configuration (HRCW) is taken from I2C EEPROM.
23 23
24 2.2 PCI 24 2.2 PCI
25 A miniPCI Type-III socket is present. PCI clock fixed at 66MHz. 25 A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
26 26
27 2.3 FPGA 27 2.3 FPGA
28 Altera Cyclone-II EP2C20/35 with PCI DMA engines. 28 Altera Cyclone-II EP2C20/35 with PCI DMA engines.
29 Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces. 29 Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
30 Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash. 30 Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash.
31 31
32 2.3.1 I/O @ FPGA 32 2.3.1 I/O @ FPGA
33 2x8 Outputs : Infineon High-Side Switches to Main Supply. 33 2x8 Outputs : Infineon High-Side Switches to Main Supply.
34 2x8 Inputs : Programmable input threshold + trigger capabilities 34 2x8 Inputs : Programmable input threshold + trigger capabilities
35 2 dedicated flash interfaces for illuminator boards. 35 2 dedicated flash interfaces for illuminator boards.
36 Cross trigger for chaining several boards. 36 Cross trigger for chaining several boards.
37 37
38 2.4 I2C 38 2.4 I2C
39 Bus1: 39 Bus1:
40 MAX5381 DAC @ 0x60 for 1st digital input threshold. 40 MAX5381 DAC @ 0x60 for 1st digital input threshold.
41 LM75 @ 0x90 for temperature monitoring. 41 LM75 @ 0x90 for temperature monitoring.
42 EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics. 42 EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
43 1st image sensor interface (slave adresses depend on sensor) 43 1st image sensor interface (slave addresses depend on sensor)
44 Bus2: 44 Bus2:
45 MAX5381 DAC @ 0x60 for 2nd digital input threshold. 45 MAX5381 DAC @ 0x60 for 2nd digital input threshold.
46 2nd image sensor interface (slave adresses depend on sensor) 46 2nd image sensor interface (slave addresses depend on sensor)
47 47
48 3 Flash layout. 48 3 Flash layout.
49 49
50 reset vector is 0xFFF00100, i.e. "HIGHBOOT". 50 reset vector is 0xFFF00100, i.e. "HIGHBOOT".
51 51
52 FF800000 environment 52 FF800000 environment
53 FF802000 redundant environment 53 FF802000 redundant environment
54 FF804000 u-boot script image 54 FF804000 u-boot script image
55 FF806000 redundant u-boot script image 55 FF806000 redundant u-boot script image
56 FF808000 device tree blob 56 FF808000 device tree blob
57 FF80A000 redundant device tree blob 57 FF80A000 redundant device tree blob
58 FF80C000 tbd. 58 FF80C000 tbd.
59 FF80E000 tbd. 59 FF80E000 tbd.
60 FF810000 kernel 60 FF810000 kernel
61 FFC00000 root FS 61 FFC00000 root FS
62 FFF00000 u-boot 62 FFF00000 u-boot
63 FFF80000 FPGA raw bit file 63 FFF80000 FPGA raw bit file
64 64
65 mtd partitions are propagated to linux kernel via device tree blob. 65 mtd partitions are propagated to linux kernel via device tree blob.
66 66
67 4 Booting 67 4 Booting
68 68
69 On startup the bootscript @ FF804000 is executed. This script can be 69 On startup the bootscript @ FF804000 is executed. This script can be
70 exchanged easily. Default boot mode is "boot from flash", i.e. system 70 exchanged easily. Default boot mode is "boot from flash", i.e. system
71 works stand-alone. 71 works stand-alone.
72 72
73 This behaviour depends on some environment variables : 73 This behaviour depends on some environment variables :
74 74
75 "netboot" : yes ->try dhcp/bootp and boot from network. 75 "netboot" : yes ->try dhcp/bootp and boot from network.
76 A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for 76 A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
77 DHCP server configuration, e.g. to provide different images to 77 DHCP server configuration, e.g. to provide different images to
78 different devices. 78 different devices.
79 79
80 During netboot the system tries to get 3 image files: 80 During netboot the system tries to get 3 image files:
81 1. Kernel - name + data is given during BOOTP. 81 1. Kernel - name + data is given during BOOTP.
82 2. Initrd - name is stored in "initrd_name" 82 2. Initrd - name is stored in "initrd_name"
83 3. device tree blob - name is stored in "dtb_name" 83 3. device tree blob - name is stored in "dtb_name"
84 Fallback files are the flash versions. 84 Fallback files are the flash versions.
85 85
1 Matrix Vision mvSMR 1 Matrix Vision mvSMR
2 ------------------- 2 -------------------
3 3
4 1. Board Description 4 1. Board Description
5 5
6 The mvSMR is a 75x130mm single image processing board used 6 The mvSMR is a 75x130mm single image processing board used
7 in automation. Power Supply is 24VDC. 7 in automation. Power Supply is 24VDC.
8 8
9 2 System Components 9 2 System Components
10 10
11 2.1 CPU 11 2.1 CPU
12 Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB. 12 Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
13 64MB DDR-I @ 133MHz. 13 64MB DDR-I @ 133MHz.
14 8 MByte Nor Flash on local bus. 14 8 MByte Nor Flash on local bus.
15 2 serial ports. Console running on ttyS0 @ 115200 8N1. 15 2 serial ports. Console running on ttyS0 @ 115200 8N1.
16 16
17 2.2 PCI 17 2.2 PCI
18 PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core. 18 PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core.
19 19
20 2.3 FPGA 20 2.3 FPGA
21 Xilinx Spartan-3 XC3S200 with PCI DMA engine. 21 Xilinx Spartan-3 XC3S200 with PCI DMA engine.
22 Connects to Matrix Vision specific CCD/CMOS sensor interface. 22 Connects to Matrix Vision specific CCD/CMOS sensor interface.
23 23
24 2.4 I2C 24 2.4 I2C
25 EEPROM @ 0xA0 for vendor specifics. 25 EEPROM @ 0xA0 for vendor specifics.
26 image sensor interface (slave adresses depend on sensor) 26 image sensor interface (slave addresses depend on sensor)
27 27
28 3 Flash layout. 28 3 Flash layout.
29 29
30 reset vector is 0x00000100, i.e. "LOWBOOT". 30 reset vector is 0x00000100, i.e. "LOWBOOT".
31 31
32 FF800000 u-boot 32 FF800000 u-boot
33 FF806000 u-boot script image 33 FF806000 u-boot script image
34 FF808000 u-boot environment 34 FF808000 u-boot environment
35 FF840000 FPGA raw bit file 35 FF840000 FPGA raw bit file
36 FF880000 root FS 36 FF880000 root FS
37 FFF00000 kernel 37 FFF00000 kernel
38 38
39 4 Booting 39 4 Booting
40 40
41 On startup the bootscript @ FF806000 is executed. This script can be 41 On startup the bootscript @ FF806000 is executed. This script can be
42 exchanged easily. Default boot mode is "boot from flash", i.e. system 42 exchanged easily. Default boot mode is "boot from flash", i.e. system
43 works stand-alone. 43 works stand-alone.
44 44
45 This behaviour depends on some environment variables : 45 This behaviour depends on some environment variables :
46 46
47 "netboot" : yes ->try dhcp/bootp and boot from network. 47 "netboot" : yes ->try dhcp/bootp and boot from network.
48 A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for 48 A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
49 DHCP server configuration, e.g. to provide different images to 49 DHCP server configuration, e.g. to provide different images to
50 different devices. 50 different devices.
51 51
52 During netboot the system tries to get 3 image files: 52 During netboot the system tries to get 3 image files:
53 1. Kernel - name + data is given during BOOTP. 53 1. Kernel - name + data is given during BOOTP.
54 2. Initrd - name is stored in "initrd_name" 54 2. Initrd - name is stored in "initrd_name"
55 Fallback files are the flash versions. 55 Fallback files are the flash versions.
56 56
1 AMCC Ocotea Board 1 AMCC Ocotea Board
2 2
3 Last Update: March 2, 2004 3 Last Update: March 2, 2004
4 ======================================================================= 4 =======================================================================
5 5
6 This file contains some handy info regarding U-Boot and the AMCC 6 This file contains some handy info regarding U-Boot and the AMCC
7 Ocotea 440gx evalutation board. See the README.ppc440 for additional 7 Ocotea 440gx evaluation board. See the README.ppc440 for additional
8 information. 8 information.
9 9
10 10
11 SWITCH SETTINGS & JUMPERS 11 SWITCH SETTINGS & JUMPERS
12 ========================== 12 ==========================
13 13
14 Here's what I've been using successfully. If you feel inclined to 14 Here's what I've been using successfully. If you feel inclined to
15 change things ... please read the docs! 15 change things ... please read the docs!
16 16
17 DIPSW U46 U80 17 DIPSW U46 U80
18 ------------------------ 18 ------------------------
19 SW 1 off off 19 SW 1 off off
20 SW 2 on off 20 SW 2 on off
21 SW 3 off off 21 SW 3 off off
22 SW 4 off off 22 SW 4 off off
23 SW 5 off off 23 SW 5 off off
24 SW 6 on on 24 SW 6 on on
25 SW 7 on off 25 SW 7 on off
26 SW 8 on off 26 SW 8 on off
27 27
28 J41: strapped 28 J41: strapped
29 J42: open 29 J42: open
30 30
31 All others are factory default. 31 All others are factory default.
32 32
33 33
34 I2C Information 34 I2C Information
35 ===================== 35 =====================
36 36
37 See README.ebony for information. 37 See README.ebony for information.
38 38
39 PCI 39 PCI
40 =========================== 40 ===========================
41 41
42 Untested at the time of writing. 42 Untested at the time of writing.
43 43
44 PPC440GX Ethernet EMACs 44 PPC440GX Ethernet EMACs
45 =========================== 45 ===========================
46 46
47 All EMAC ports have been tested and are known to work 47 All EMAC ports have been tested and are known to work
48 with EPS Group 4. 48 with EPS Group 4.
49 49
50 Special note about the Cicada CIS8201: 50 Special note about the Cicada CIS8201:
51 The CIS8201 Gigabit PHY comes up in GMII mode by default. 51 The CIS8201 Gigabit PHY comes up in GMII mode by default.
52 One must hit an extended register to allow use of RGMII mode. 52 One must hit an extended register to allow use of RGMII mode.
53 This has been done in the 440gx_enet.c file with a #ifdef/endif 53 This has been done in the 440gx_enet.c file with a #ifdef/endif
54 pair. 54 pair.
55 55
56 AMCC does not store the EMAC ethernet addresses within their PIBS bootloader. 56 AMCC does not store the EMAC ethernet addresses within their PIBS bootloader.
57 The addresses contained in the config header file are from my particular 57 The addresses contained in the config header file are from my particular
58 board and you _*should*_ change them to reflect your board either in the 58 board and you _*should*_ change them to reflect your board either in the
59 config file and/or in your environment variables. I found the addresses on 59 config file and/or in your environment variables. I found the addresses on
60 labels on the bottom side of the board. 60 labels on the bottom side of the board.
61 61
62 62
63 BDI2k or JTAG Debugging 63 BDI2k or JTAG Debugging
64 =========================== 64 ===========================
65 65
66 For ease of debugging you can swap the small boot flash and external SRAM 66 For ease of debugging you can swap the small boot flash and external SRAM
67 by changing U46:3 to on. You can then use the sram as your boot flash by 67 by changing U46:3 to on. You can then use the sram as your boot flash by
68 loading the sram via the jtag debugger. 68 loading the sram via the jtag debugger.
69 69
70 70
71 Regards, 71 Regards,
72 --Travis 72 --Travis
73 <tsawyer@sandburst.com> 73 <tsawyer@sandburst.com>
74 74
1 Overview 1 Overview
2 -------- 2 --------
3 P2020RDB is a Low End Dual core platform supporting the P2020 processor 3 P2020RDB is a Low End Dual core platform supporting the P2020 processor
4 of QorIQ series. P2020 is an e500 based dual core SOC. 4 of QorIQ series. P2020 is an e500 based dual core SOC.
5 5
6 Building U-boot 6 Building U-boot
7 ----------- 7 -----------
8 To build the u-boot for P2020RDB: 8 To build the u-boot for P2020RDB:
9 make P2020RDB_config 9 make P2020RDB_config
10 make 10 make
11 11
12 NOR Flash Banks 12 NOR Flash Banks
13 ----------- 13 -----------
14 RDB board for P2020 has two flash banks. They are both present on boot. 14 RDB board for P2020 has two flash banks. They are both present on boot.
15 15
16 Booting by default is always from the boot bank at 0xef00_0000. 16 Booting by default is always from the boot bank at 0xef00_0000.
17 17
18 Memory Map 18 Memory Map
19 ---------- 19 ----------
20 0xef00_0000 - 0xef7f_ffff Alernate bank 8MB 20 0xef00_0000 - 0xef7f_ffff Alternate bank 8MB
21 0xe800_0000 - 0xefff_ffff Boot bank 8MB 21 0xe800_0000 - 0xefff_ffff Boot bank 8MB
22 22
23 0xef78_0000 - 0xef7f_ffff Alternate u-boot address 512KB 23 0xef78_0000 - 0xef7f_ffff Alternate u-boot address 512KB
24 0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB 24 0xeff8_0000 - 0xefff_ffff Boot u-boot address 512KB
25 25
26 Switch settings to boot from the NOR flash banks 26 Switch settings to boot from the NOR flash banks
27 ------------------------------------------------ 27 ------------------------------------------------
28 SW4[8]=0 default NOR Flash bank 28 SW4[8]=0 default NOR Flash bank
29 SW4[8]=1 Alternate NOR Flash bank 29 SW4[8]=1 Alternate NOR Flash bank
30 30
31 Flashing Images 31 Flashing Images
32 --------------- 32 ---------------
33 To place a new u-boot image in the alternate flash bank and then boot 33 To place a new u-boot image in the alternate flash bank and then boot
34 with that new image temporarily, use this: 34 with that new image temporarily, use this:
35 tftp 1000000 u-boot.bin 35 tftp 1000000 u-boot.bin
36 erase ef780000 ef7fffff 36 erase ef780000 ef7fffff
37 cp.b 1000000 ef780000 80000 37 cp.b 1000000 ef780000 80000
38 38
39 Now to boot from the alternate bank change the SW4[8] from 0 to 1. 39 Now to boot from the alternate bank change the SW4[8] from 0 to 1.
40 40
41 To program the image in the boot flash bank: 41 To program the image in the boot flash bank:
42 tftp 1000000 u-boot.bin 42 tftp 1000000 u-boot.bin
43 protect off all 43 protect off all
44 erase eff80000 ffffffff 44 erase eff80000 ffffffff
45 cp.b 1000000 eff80000 80000 45 cp.b 1000000 eff80000 80000
46 46
47 Using the Device Tree Source File 47 Using the Device Tree Source File
48 --------------------------------- 48 ---------------------------------
49 To create the DTB (Device Tree Binary) image file, 49 To create the DTB (Device Tree Binary) image file,
50 use a command similar to this: 50 use a command similar to this:
51 51
52 dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb 52 dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb
53 53
54 Likely, that .dts file will come from here; 54 Likely, that .dts file will come from here;
55 55
56 linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts 56 linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts
57 57
58 Booting Linux 58 Booting Linux
59 ------------- 59 -------------
60 Place a linux uImage in the TFTP disk area. 60 Place a linux uImage in the TFTP disk area.
61 61
62 tftp 1000000 uImage.p2020rdb 62 tftp 1000000 uImage.p2020rdb
63 tftp 2000000 rootfs.ext2.gz.uboot 63 tftp 2000000 rootfs.ext2.gz.uboot
64 tftp c00000 p2020rdb.dtb 64 tftp c00000 p2020rdb.dtb
65 bootm 1000000 2000000 c00000 65 bootm 1000000 2000000 c00000
66 66
67 Implementing AMP(Asymmetric MultiProcessing) 67 Implementing AMP(Asymmetric MultiProcessing)
68 --------------------------------------------- 68 ---------------------------------------------
69 1. Build kernel image for core0: 69 1. Build kernel image for core0:
70 70
71 a. $ make 85xx/p1_p2_rdb_defconfig 71 a. $ make 85xx/p1_p2_rdb_defconfig
72 72
73 b. $ make menuconfig 73 b. $ make menuconfig
74 - un-select "Processor support"-> 74 - un-select "Processor support"->
75 "Symetric multi-processing support" 75 "Symetric multi-processing support"
76 76
77 c. $ make uImage 77 c. $ make uImage
78 78
79 d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0 79 d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
80 80
81 2. Build kernel image for core1: 81 2. Build kernel image for core1:
82 82
83 a. $ make 85xx/p1_p2_rdb_defconfig 83 a. $ make 85xx/p1_p2_rdb_defconfig
84 84
85 b. $ make menuconfig 85 b. $ make menuconfig
86 - Un-select "Processor support"-> 86 - Un-select "Processor support"->
87 "Symetric multi-processing support" 87 "Symetric multi-processing support"
88 - Select "Advanced setup" -> 88 - Select "Advanced setup" ->
89 "Prompt for advanced kernel configuration options" 89 "Prompt for advanced kernel configuration options"
90 - Select 90 - Select
91 "Set physical address where the kernel is loaded" 91 "Set physical address where the kernel is loaded"
92 and set it to 0x20000000, asssuming core1 will 92 and set it to 0x20000000, assuming core1 will
93 start from 512MB. 93 start from 512MB.
94 - Select "Set custom page offset address" 94 - Select "Set custom page offset address"
95 - Select "Set custom kernel base address" 95 - Select "Set custom kernel base address"
96 - Select "Set maximum low memory" 96 - Select "Set maximum low memory"
97 - "Exit" and save the selection. 97 - "Exit" and save the selection.
98 98
99 c. $ make uImage 99 c. $ make uImage
100 100
101 d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1 101 d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
102 102
103 3. Create dtb for core0: 103 3. Create dtb for core0:
104 104
105 $ dtc -I dts -O dtb -f -b 0 105 $ dtc -I dts -O dtb -f -b 0
106 arch/powerpc/boot/dts/p2020rdb_camp_core0.dts > 106 arch/powerpc/boot/dts/p2020rdb_camp_core0.dts >
107 /tftpboot/p2020rdb_camp_core0.dtb 107 /tftpboot/p2020rdb_camp_core0.dtb
108 108
109 4. Create dtb for core1: 109 4. Create dtb for core1:
110 110
111 $ dtc -I dts -O dtb -f -b 1 111 $ dtc -I dts -O dtb -f -b 1
112 arch/powerpc/boot/dts/p2020rdb_camp_core1.dts > 112 arch/powerpc/boot/dts/p2020rdb_camp_core1.dts >
113 /tftpboot/p2020rdb_camp_core1.dtb 113 /tftpboot/p2020rdb_camp_core1.dtb
114 114
115 5. Bring up two cores separately: 115 5. Bring up two cores separately:
116 116
117 a. Power on the board, under u-boot prompt: 117 a. Power on the board, under u-boot prompt:
118 => setenv <serverip> 118 => setenv <serverip>
119 => setenv <ipaddr> 119 => setenv <ipaddr>
120 => setenv bootargs root=/dev/ram rw console=ttyS0,115200 120 => setenv bootargs root=/dev/ram rw console=ttyS0,115200
121 b. Bring up core1's kernel first: 121 b. Bring up core1's kernel first:
122 => setenv bootm_low 0x20000000 122 => setenv bootm_low 0x20000000
123 => setenv bootm_size 0x10000000 123 => setenv bootm_size 0x10000000
124 => tftp 21000000 uImage.core1 124 => tftp 21000000 uImage.core1
125 => tftp 22000000 ramdiskfile 125 => tftp 22000000 ramdiskfile
126 => tftp 20c00000 p2020rdb_camp_core1.dtb 126 => tftp 20c00000 p2020rdb_camp_core1.dtb
127 => interrupts off 127 => interrupts off
128 => bootm start 21000000 22000000 20c00000 128 => bootm start 21000000 22000000 20c00000
129 => bootm loados 129 => bootm loados
130 => bootm ramdisk 130 => bootm ramdisk
131 => bootm fdt 131 => bootm fdt
132 => fdt boardsetup 132 => fdt boardsetup
133 => fdt chosen $initrd_start $initrd_end 133 => fdt chosen $initrd_start $initrd_end
134 => bootm prep 134 => bootm prep
135 => cpu 1 release $bootm_low - $fdtaddr - 135 => cpu 1 release $bootm_low - $fdtaddr -
136 c. Bring up core0's kernel(on the same u-boot console): 136 c. Bring up core0's kernel(on the same u-boot console):
137 => setenv bootm_low 0 137 => setenv bootm_low 0
138 => setenv bootm_size 0x20000000 138 => setenv bootm_size 0x20000000
139 => tftp 1000000 uImage.core0 139 => tftp 1000000 uImage.core0
140 => tftp 2000000 ramdiskfile 140 => tftp 2000000 ramdiskfile
141 => tftp c00000 p2020rdb_camp_core0.dtb 141 => tftp c00000 p2020rdb_camp_core0.dtb
142 => bootm 1000000 2000000 c00000 142 => bootm 1000000 2000000 c00000
143 143
144 Please note only core0 will run u-boot, core1 starts kernel directly 144 Please note only core0 will run u-boot, core1 starts kernel directly
145 after "cpu release" command is issued. 145 after "cpu release" command is issued.
146 146