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Commit c4930b1a0ee5a35c49de10e0289f9c8253e78848

Authored by Shaveta Leekha
Committed by York Sun
1 parent 6df82e3c0f
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

B4860qds: Set SerDes2 refclk2 at to 156.25MHz for XFI to work 

Change setting of SerDes2 refclk2 to have the default value as it is
coming on board that is 156.25MHz, for XFI to work.
Also change PLL_NUM variable to the one defined in config_mpc85xx.h
for B4860 and B4420.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 1 changed file with 3 additions and 4 deletions Side-by-side Diff

board/freescale/b4860qds/b4860qds.c
Diff comments   View file @ c4930b1
... ... @@ -29,7 +29,6 @@
29 29  
30 30 #define CLK_MUX_SEL_MASK 0x4
31 31 #define ETH_PHY_CLK_OUT 0x4
32   -#define PLL_NUM 2
33 32  
34 33 DECLARE_GLOBAL_DATA_PTR;
35 34  
... ... @@ -386,7 +385,7 @@
386 385 /* Steps For SerDes PLLs reset and reconfiguration after
387 386 * changing SerDes's refclks
388 387 */
389   - for (i = 0; i < PLL_NUM; i++) {
  388 + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
390 389 debug("For PLL%d reset and reconfiguration after"
391 390 " changing refclks\n", i+1);
392 391 clrbits_be32(&srds_regs->bank[i].rstctl,
... ... @@ -453,7 +452,7 @@
453 452 if (!ret) {
454 453 ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
455 454 SERDES_REFCLK_100,
456   - SERDES_REFCLK_100, 0);
  455 + SERDES_REFCLK_156_25, 0);
457 456 if (ret) {
458 457 printf("IDT8T49N222A configuration failed.\n");
459 458 goto out;
... ... @@ -467,7 +466,7 @@
467 466 /* Steps For SerDes PLLs reset and reconfiguration after
468 467 * changing SerDes's refclks
469 468 */
470   - for (i = 0; i < PLL_NUM; i++) {
  469 + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
471 470 clrbits_be32(&srds2_regs->bank[i].rstctl,
472 471 SRDS_RSTCTL_SDRST_B);
473 472 udelay(10);