Eric Lee / smarc-uboot | Embedian Git Server

Commit c4e8862308d420e85c227498797c32410d9e47a8

Authored by Vignesh R 2019-02-05 13:59:23 +0800

Committed by Jagan Teki 2019-02-07 18:03:21 +0800

Exists in smarc_8mq_lf_v2020.04 and in 14 other branches

mtd: spi: Switch to new SPI NOR framework

Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/definitions

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

Showing 9 changed files with 113 additions and 365 deletions Inline Diff

drivers/mtd/spi/Kconfig
drivers/mtd/spi/Makefile
drivers/mtd/spi/sandbox.c
drivers/mtd/spi/sf_dataflash.c
drivers/mtd/spi/sf_internal.h
drivers/mtd/spi/sf_probe.c
drivers/mtd/spi/spi-nor-core.c
drivers/spi/stm32_qspi.c
include/spi_flash.h

drivers/mtd/spi/Kconfig

Diff comments View file @ c4e8862

 menu "SPI Flash Support"
 config DM_SPI_FLASH
 	bool "Enable Driver Model for SPI flash"
 	depends on DM && DM_SPI
 	help
 	  Enable driver model for SPI flash. This SPI flash interface
 	  (spi_flash_probe(), spi_flash_write(), etc.) is then
 	  implemented by the SPI flash uclass. There is one standard
 	  SPI flash driver which knows how to probe most chips
 	  supported by U-Boot. The uclass interface is defined in
 	  include/spi_flash.h, but is currently fully compatible
 	  with the old interface to avoid confusion and duplication
 	  during the transition parent. SPI and SPI flash must be
 	  enabled together (it is not possible to use driver model
 	  for one and not the other).
 config SPI_FLASH_SANDBOX
 	bool "Support sandbox SPI flash device"
 	depends on SANDBOX && DM_SPI_FLASH
 	help
 	  Since sandbox cannot access real devices, an emulation mechanism is
 	  provided instead. Drivers can be connected up to the sandbox SPI
 	  bus (see CONFIG_SANDBOX_SPI) and SPI traffic will be routed to this
 	  device. Typically the contents of the emulated SPI flash device is
 	  stored in a file on the host filesystem.
 config SPI_FLASH
 	bool "Legacy SPI Flash Interface support"
+	depends on SPI
+	select SPI_MEM
 	help
 	  Enable the legacy SPI flash support. This will include basic
 	  standard support for things like probing, read / write, and
 	  erasing through cmd_sf interface.
 	  If unsure, say N
 if SPI_FLASH
 config SPI_FLASH_SFDP_SUPPORT
 	bool "SFDP table parsing support for SPI NOR flashes"
 	depends on !SPI_FLASH_BAR
 	help
 	 Enable support for parsing and auto discovery of parameters for
 	 SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
 	 tables as per JESD216 standard.
 config SPI_FLASH_BAR
 	bool "SPI flash Bank/Extended address register support"
 	help
 	  Enable the SPI flash Bank/Extended address register support.
 	  Bank/Extended address registers are used to access the flash
 	  which has size > 16MiB in 3-byte addressing.
 config SF_DUAL_FLASH
 	bool "SPI DUAL flash memory support"
 	help
 	  Enable this option to support two flash memories connected to a single
 	  controller. Currently Xilinx Zynq qspi supports this.
 config SPI_FLASH_ATMEL
 	bool "Atmel SPI flash support"
 	help
 	  Add support for various Atmel SPI flash chips (AT45xxx and AT25xxx)
 config SPI_FLASH_EON
 	bool "EON SPI flash support"
 	help
 	  Add support for various EON SPI flash chips (EN25xxx)
 config SPI_FLASH_GIGADEVICE
 	bool "GigaDevice SPI flash support"
 	help
 	  Add support for various GigaDevice SPI flash chips (GD25xxx)
 config SPI_FLASH_ISSI
 	bool "ISSI SPI flash support"
 	help
 	  Add support for various ISSI SPI flash chips (ISxxx)
 config SPI_FLASH_MACRONIX
 	bool "Macronix SPI flash support"
 	help
 	  Add support for various Macronix SPI flash chips (MX25Lxxx)
 config SPI_FLASH_SPANSION
 	bool "Spansion SPI flash support"
 	help
 	  Add support for various Spansion SPI flash chips (S25FLxxx)
 config SPI_FLASH_STMICRO
 	bool "STMicro SPI flash support"
 	help
 	  Add support for various STMicro SPI flash chips (M25Pxxx and N25Qxxx)
 config SPI_FLASH_SST
 	bool "SST SPI flash support"
 	help
 	  Add support for various SST SPI flash chips (SST25xxx)
 config SPI_FLASH_WINBOND
 	bool "Winbond SPI flash support"
 	help
 	  Add support for various Winbond SPI flash chips (W25xxx)
 config SPI_FLASH_XMC
 	bool "XMC SPI flash support"
 	help
 	  Add support for various XMC (Wuhan Xinxin Semiconductor
 	  Manufacturing Corp.) SPI flash chips (XM25xxx)
 endif
 config SPI_FLASH_USE_4K_SECTORS
 	bool "Use small 4096 B erase sectors"
 	depends on SPI_FLASH
 	default y
 	help
 	  Many flash memories support erasing small (4096 B) sectors. Depending
 	  on the usage this feature may provide performance gain in comparison
 	  to erasing whole blocks (32/64 KiB).
 	  Changing a small part of the flash's contents is usually faster with
 	  small sectors. On the other hand erasing should be faster when using
 	  64 KiB block instead of 16 × 4 KiB sectors.
 	  Please note that some tools/drivers/filesystems may not work with
 	  4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum).
 config SPI_FLASH_DATAFLASH
 	bool "AT45xxx DataFlash support"
 	depends on SPI_FLASH && DM_SPI_FLASH
 	help
 	  Enable the access for SPI-flash-based AT45xxx DataFlash chips.
 	  DataFlash is a kind of SPI flash. Most AT45 chips have two buffers
 	  in each chip, which may be used for double buffered I/O; but this
 	  driver doesn't (yet) use these for any kind of i/o overlap or prefetching.
 	  Sometimes DataFlash is packaged in MMC-format cards, although the
 	  MMC stack can't (yet?) distinguish between MMC and DataFlash
 	  protocols during enumeration.
 	  If unsure, say N
 config SPI_FLASH_MTD
 	bool "SPI Flash MTD support"
 	depends on SPI_FLASH
 	help
           Enable the MTD support for spi flash layer, this adapter is for
 	  translating mtd_read/mtd_write commands into spi_flash_read/write
 	  commands. It is not intended to use it within sf_cmd or the SPI
 	  flash subsystem. Such an adapter is needed for subsystems like
 	  UBI which can only operate on top of the MTD layer.
 	  If unsure, say N
 endmenu # menu "SPI Flash Support"

drivers/mtd/spi/Makefile

Diff comments View file @ c4e8862

1	# SPDX-License-Identifier: GPL-2.0+	1	# SPDX-License-Identifier: GPL-2.0+
2	#	2	#
3	# (C) Copyright 2006	3	# (C) Copyright 2006
4	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.	4	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5		5
6	obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o	6	obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
7		7
8	ifdef CONFIG_SPL_BUILD	8	ifdef CONFIG_SPL_BUILD
9	obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o	9	obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
10	endif	10	endif
11		11
12	obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o spi_flash_ids.o sf.o	12	obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi-nor-core.o
13	obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o	13	obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o sf.o
14	obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o	14	obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
15	obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o	15	obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
16		16

drivers/mtd/spi/sandbox.c

Diff comments View file @ c4e8862

1	/*	1	/*
2	* Simulate a SPI flash	2	* Simulate a SPI flash
3	*	3	*
4	* Copyright (c) 2011-2013 The Chromium OS Authors.	4	* Copyright (c) 2011-2013 The Chromium OS Authors.
5	* See file CREDITS for list of people who contributed to this	5	* See file CREDITS for list of people who contributed to this
6	* project.	6	* project.
7	*	7	*
8	* Licensed under the GPL-2 or later.	8	* Licensed under the GPL-2 or later.
9	*/	9	*/
10		10
11	#define LOG_CATEGORY UCLASS_SPI_FLASH	11	#define LOG_CATEGORY UCLASS_SPI_FLASH
12		12
13	#include <common.h>	13	#include <common.h>
14	#include <dm.h>	14	#include <dm.h>
15	#include <malloc.h>	15	#include <malloc.h>
16	#include <spi.h>	16	#include <spi.h>
17	#include <os.h>	17	#include <os.h>
18		18
19	#include <spi_flash.h>	19	#include <spi_flash.h>
20	#include "sf_internal.h"	20	#include "sf_internal.h"
21		21
22	#include <asm/getopt.h>	22	#include <asm/getopt.h>
23	#include <asm/spi.h>	23	#include <asm/spi.h>
24	#include <asm/state.h>	24	#include <asm/state.h>
25	#include <dm/device-internal.h>	25	#include <dm/device-internal.h>
26	#include <dm/lists.h>	26	#include <dm/lists.h>
27	#include <dm/uclass-internal.h>	27	#include <dm/uclass-internal.h>
28		28
29	/*	29	/*
30	* The different states that our SPI flash transitions between.	30	* The different states that our SPI flash transitions between.
31	* We need to keep track of this across multiple xfer calls since	31	* We need to keep track of this across multiple xfer calls since
32	* the SPI bus could possibly call down into us multiple times.	32	* the SPI bus could possibly call down into us multiple times.
33	*/	33	*/
34	enum sandbox_sf_state {	34	enum sandbox_sf_state {
35	SF_CMD, /* default state -- we're awaiting a command */	35	SF_CMD, /* default state -- we're awaiting a command */
36	SF_ID, /* read the flash's (jedec) ID code */	36	SF_ID, /* read the flash's (jedec) ID code */
37	SF_ADDR, /* processing the offset in the flash to read/etc... */	37	SF_ADDR, /* processing the offset in the flash to read/etc... */
38	SF_READ, /* reading data from the flash */	38	SF_READ, /* reading data from the flash */
39	SF_WRITE, /* writing data to the flash, i.e. page programming */	39	SF_WRITE, /* writing data to the flash, i.e. page programming */
40	SF_ERASE, /* erase the flash */	40	SF_ERASE, /* erase the flash */
41	SF_READ_STATUS, /* read the flash's status register */	41	SF_READ_STATUS, /* read the flash's status register */
42	SF_READ_STATUS1, /* read the flash's status register upper 8 bits*/	42	SF_READ_STATUS1, /* read the flash's status register upper 8 bits*/
43	SF_WRITE_STATUS, /* write the flash's status register */	43	SF_WRITE_STATUS, /* write the flash's status register */
44	};	44	};
45		45
46	#if CONFIG_IS_ENABLED(LOG)	46	#if CONFIG_IS_ENABLED(LOG)
47	static const char *sandbox_sf_state_name(enum sandbox_sf_state state)	47	static const char *sandbox_sf_state_name(enum sandbox_sf_state state)
48	{	48	{
49	static const char * const states[] = {	49	static const char * const states[] = {
50	"CMD", "ID", "ADDR", "READ", "WRITE", "ERASE", "READ_STATUS",	50	"CMD", "ID", "ADDR", "READ", "WRITE", "ERASE", "READ_STATUS",
51	"READ_STATUS1", "WRITE_STATUS",	51	"READ_STATUS1", "WRITE_STATUS",
52	};	52	};
53	return states[state];	53	return states[state];
54	}	54	}
55	#endif /* LOG */	55	#endif /* LOG */
56		56
57	/* Bits for the status register */	57	/* Bits for the status register */
58	#define STAT_WIP (1 << 0)	58	#define STAT_WIP (1 << 0)
59	#define STAT_WEL (1 << 1)	59	#define STAT_WEL (1 << 1)
60	#define STAT_BP_SHIFT 2	60	#define STAT_BP_SHIFT 2
61	#define STAT_BP_MASK (7 << STAT_BP_SHIFT)	61	#define STAT_BP_MASK (7 << STAT_BP_SHIFT)
62		62
63	/* Assume all SPI flashes have 3 byte addresses since they do atm */	63	/* Assume all SPI flashes have 3 byte addresses since they do atm */
64	#define SF_ADDR_LEN 3	64	#define SF_ADDR_LEN 3
65		65
66	#define IDCODE_LEN 3	66	#define IDCODE_LEN 3
67		67
68	/* Used to quickly bulk erase backing store */	68	/* Used to quickly bulk erase backing store */
69	static u8 sandbox_sf_0xff[0x1000];	69	static u8 sandbox_sf_0xff[0x1000];
70		70
71	/* Internal state data for each SPI flash */	71	/* Internal state data for each SPI flash */
72	struct sandbox_spi_flash {	72	struct sandbox_spi_flash {
73	unsigned int cs; /* Chip select we are attached to */	73	unsigned int cs; /* Chip select we are attached to */
74	/*	74	/*
75	* As we receive data over the SPI bus, our flash transitions	75	* As we receive data over the SPI bus, our flash transitions
76	* between states. For example, we start off in the SF_CMD	76	* between states. For example, we start off in the SF_CMD
77	* state where the first byte tells us what operation to perform	77	* state where the first byte tells us what operation to perform
78	* (such as read or write the flash). But the operation itself	78	* (such as read or write the flash). But the operation itself
79	* can go through a few states such as first reading in the	79	* can go through a few states such as first reading in the
80	* offset in the flash to perform the requested operation.	80	* offset in the flash to perform the requested operation.
81	* Thus "state" stores the exact state that our machine is in	81	* Thus "state" stores the exact state that our machine is in
82	* while "cmd" stores the overall command we're processing.	82	* while "cmd" stores the overall command we're processing.
83	*/	83	*/
84	enum sandbox_sf_state state;	84	enum sandbox_sf_state state;
85	uint cmd;	85	uint cmd;
86	/* Erase size of current erase command */	86	/* Erase size of current erase command */
87	uint erase_size;	87	uint erase_size;
88	/* Current position in the flash; used when reading/writing/etc... */	88	/* Current position in the flash; used when reading/writing/etc... */
89	uint off;	89	uint off;
90	/* How many address bytes we've consumed */	90	/* How many address bytes we've consumed */
91	uint addr_bytes, pad_addr_bytes;	91	uint addr_bytes, pad_addr_bytes;
92	/* The current flash status (see STAT_XXX defines above) */	92	/* The current flash status (see STAT_XXX defines above) */
93	u16 status;	93	u16 status;
94	/* Data describing the flash we're emulating */	94	/* Data describing the flash we're emulating */
95	const struct spi_flash_info *data;	95	const struct flash_info *data;
96	/* The file on disk to serv up data from */	96	/* The file on disk to serv up data from */
97	int fd;	97	int fd;
98	};	98	};
99		99
100	struct sandbox_spi_flash_plat_data {	100	struct sandbox_spi_flash_plat_data {
101	const char *filename;	101	const char *filename;
102	const char *device_name;	102	const char *device_name;
103	int bus;	103	int bus;
104	int cs;	104	int cs;
105	};	105	};
106		106
107	void sandbox_sf_set_block_protect(struct udevice *dev, int bp_mask)	107	void sandbox_sf_set_block_protect(struct udevice *dev, int bp_mask)
108	{	108	{
109	struct sandbox_spi_flash *sbsf = dev_get_priv(dev);	109	struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
110		110
111	sbsf->status &= ~STAT_BP_MASK;	111	sbsf->status &= ~STAT_BP_MASK;
112	sbsf->status \|= bp_mask << STAT_BP_SHIFT;	112	sbsf->status \|= bp_mask << STAT_BP_SHIFT;
113	}	113	}
114		114
115	/**	115	/**
116	* This is a very strange probe function. If it has platform data (which may	116	* This is a very strange probe function. If it has platform data (which may
117	* have come from the device tree) then this function gets the filename and	117	* have come from the device tree) then this function gets the filename and
118	* device type from there.	118	* device type from there.
119	*/	119	*/
120	static int sandbox_sf_probe(struct udevice *dev)	120	static int sandbox_sf_probe(struct udevice *dev)
121	{	121	{
122	/* spec = idcode:file */	122	/* spec = idcode:file */
123	struct sandbox_spi_flash *sbsf = dev_get_priv(dev);	123	struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
124	size_t len, idname_len;	124	size_t len, idname_len;
125	const struct spi_flash_info *data;	125	const struct flash_info *data;
126	struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);	126	struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
127	struct sandbox_state *state = state_get_current();	127	struct sandbox_state *state = state_get_current();
128	struct dm_spi_slave_platdata *slave_plat;	128	struct dm_spi_slave_platdata *slave_plat;
129	struct udevice *bus = dev->parent;	129	struct udevice *bus = dev->parent;
130	const char *spec = NULL;	130	const char *spec = NULL;
131	struct udevice *emul;	131	struct udevice *emul;
132	int ret = 0;	132	int ret = 0;
133	int cs = -1;	133	int cs = -1;
134		134
135	debug("%s: bus %d, looking for emul=%p: ", __func__, bus->seq, dev);	135	debug("%s: bus %d, looking for emul=%p: ", __func__, bus->seq, dev);
136	ret = sandbox_spi_get_emul(state, bus, dev, &emul);	136	ret = sandbox_spi_get_emul(state, bus, dev, &emul);
137	if (ret) {	137	if (ret) {
138	printf("Error: Unknown chip select for device '%s'\n",	138	printf("Error: Unknown chip select for device '%s'\n",
139	dev->name);	139	dev->name);
140	return ret;	140	return ret;
141	}	141	}
142	slave_plat = dev_get_parent_platdata(dev);	142	slave_plat = dev_get_parent_platdata(dev);
143	cs = slave_plat->cs;	143	cs = slave_plat->cs;
144	debug("found at cs %d\n", cs);	144	debug("found at cs %d\n", cs);
145		145
146	if (!pdata->filename) {	146	if (!pdata->filename) {
147	printf("Error: No filename available\n");	147	printf("Error: No filename available\n");
148	return -EINVAL;	148	return -EINVAL;
149	}	149	}
150	spec = strchr(pdata->device_name, ',');	150	spec = strchr(pdata->device_name, ',');
151	if (spec)	151	if (spec)
152	spec++;	152	spec++;
153	else	153	else
154	spec = pdata->device_name;	154	spec = pdata->device_name;
155	idname_len = strlen(spec);	155	idname_len = strlen(spec);
156	debug("%s: device='%s'\n", __func__, spec);	156	debug("%s: device='%s'\n", __func__, spec);
157		157
158	for (data = spi_flash_ids; data->name; data++) {	158	for (data = spi_nor_ids; data->name; data++) {
159	len = strlen(data->name);	159	len = strlen(data->name);
160	if (idname_len != len)	160	if (idname_len != len)
161	continue;	161	continue;
162	if (!strncasecmp(spec, data->name, len))	162	if (!strncasecmp(spec, data->name, len))
163	break;	163	break;
164	}	164	}
165	if (!data->name) {	165	if (!data->name) {
166	printf("%s: unknown flash '%*s'\n", __func__, (int)idname_len,	166	printf("%s: unknown flash '%*s'\n", __func__, (int)idname_len,
167	spec);	167	spec);
168	ret = -EINVAL;	168	ret = -EINVAL;
169	goto error;	169	goto error;
170	}	170	}
171		171
172	if (sandbox_sf_0xff[0] == 0x00)	172	if (sandbox_sf_0xff[0] == 0x00)
173	memset(sandbox_sf_0xff, 0xff, sizeof(sandbox_sf_0xff));	173	memset(sandbox_sf_0xff, 0xff, sizeof(sandbox_sf_0xff));
174		174
175	sbsf->fd = os_open(pdata->filename, 02);	175	sbsf->fd = os_open(pdata->filename, 02);
176	if (sbsf->fd == -1) {	176	if (sbsf->fd == -1) {
177	printf("%s: unable to open file '%s'\n", __func__,	177	printf("%s: unable to open file '%s'\n", __func__,
178	pdata->filename);	178	pdata->filename);
179	ret = -EIO;	179	ret = -EIO;
180	goto error;	180	goto error;
181	}	181	}
182		182
183	sbsf->data = data;	183	sbsf->data = data;
184	sbsf->cs = cs;	184	sbsf->cs = cs;
185		185
186	return 0;	186	return 0;
187		187
188	error:	188	error:
189	debug("%s: Got error %d\n", __func__, ret);	189	debug("%s: Got error %d\n", __func__, ret);
190	return ret;	190	return ret;
191	}	191	}
192		192
193	static int sandbox_sf_remove(struct udevice *dev)	193	static int sandbox_sf_remove(struct udevice *dev)
194	{	194	{
195	struct sandbox_spi_flash *sbsf = dev_get_priv(dev);	195	struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
196		196
197	os_close(sbsf->fd);	197	os_close(sbsf->fd);
198		198
199	return 0;	199	return 0;
200	}	200	}
201		201
202	static void sandbox_sf_cs_activate(struct udevice *dev)	202	static void sandbox_sf_cs_activate(struct udevice *dev)
203	{	203	{
204	struct sandbox_spi_flash *sbsf = dev_get_priv(dev);	204	struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
205		205
206	log_content("sandbox_sf: CS activated; state is fresh!\n");	206	log_content("sandbox_sf: CS activated; state is fresh!\n");
207		207
208	/* CS is asserted, so reset state */	208	/* CS is asserted, so reset state */
209	sbsf->off = 0;	209	sbsf->off = 0;
210	sbsf->addr_bytes = 0;	210	sbsf->addr_bytes = 0;
211	sbsf->pad_addr_bytes = 0;	211	sbsf->pad_addr_bytes = 0;
212	sbsf->state = SF_CMD;	212	sbsf->state = SF_CMD;
213	sbsf->cmd = SF_CMD;	213	sbsf->cmd = SF_CMD;
214	}	214	}
215		215
216	static void sandbox_sf_cs_deactivate(struct udevice *dev)	216	static void sandbox_sf_cs_deactivate(struct udevice *dev)
217	{	217	{
218	log_content("sandbox_sf: CS deactivated; cmd done processing!\n");	218	log_content("sandbox_sf: CS deactivated; cmd done processing!\n");
219	}	219	}
220		220
221	/*	221	/*
222	* There are times when the data lines are allowed to tristate. What	222	* There are times when the data lines are allowed to tristate. What
223	* is actually sensed on the line depends on the hardware. It could	223	* is actually sensed on the line depends on the hardware. It could
224	* always be 0xFF/0x00 (if there are pull ups/downs), or things could	224	* always be 0xFF/0x00 (if there are pull ups/downs), or things could
225	* float and so we'd get garbage back. This func encapsulates that	225	* float and so we'd get garbage back. This func encapsulates that
226	* scenario so we can worry about the details here.	226	* scenario so we can worry about the details here.
227	*/	227	*/
228	static void sandbox_spi_tristate(u8 *buf, uint len)	228	static void sandbox_spi_tristate(u8 *buf, uint len)
229	{	229	{
230	/* XXX: make this into a user config option ? */	230	/* XXX: make this into a user config option ? */
231	memset(buf, 0xff, len);	231	memset(buf, 0xff, len);
232	}	232	}
233		233
234	/* Figure out what command this stream is telling us to do */	234	/* Figure out what command this stream is telling us to do */
235	static int sandbox_sf_process_cmd(struct sandbox_spi_flash sbsf, const u8 rx,	235	static int sandbox_sf_process_cmd(struct sandbox_spi_flash sbsf, const u8 rx,
236	u8 *tx)	236	u8 *tx)
237	{	237	{
238	enum sandbox_sf_state oldstate = sbsf->state;	238	enum sandbox_sf_state oldstate = sbsf->state;
239		239
240	/* We need to output a byte for the cmd byte we just ate */	240	/* We need to output a byte for the cmd byte we just ate */
241	if (tx)	241	if (tx)
242	sandbox_spi_tristate(tx, 1);	242	sandbox_spi_tristate(tx, 1);
243		243
244	sbsf->cmd = rx[0];	244	sbsf->cmd = rx[0];
245	switch (sbsf->cmd) {	245	switch (sbsf->cmd) {
246	case CMD_READ_ID:	246	case SPINOR_OP_RDID:
247	sbsf->state = SF_ID;	247	sbsf->state = SF_ID;
248	sbsf->cmd = SF_ID;	248	sbsf->cmd = SF_ID;
249	break;	249	break;
250	case CMD_READ_ARRAY_FAST:	250	case SPINOR_OP_READ_FAST:
251	sbsf->pad_addr_bytes = 1;	251	sbsf->pad_addr_bytes = 1;
252	case CMD_READ_ARRAY_SLOW:	252	case SPINOR_OP_READ:
253	case CMD_PAGE_PROGRAM:	253	case SPINOR_OP_PP:
254	sbsf->state = SF_ADDR;	254	sbsf->state = SF_ADDR;
255	break;	255	break;
256	case CMD_WRITE_DISABLE:	256	case SPINOR_OP_WRDI:
257	debug(" write disabled\n");	257	debug(" write disabled\n");
258	sbsf->status &= ~STAT_WEL;	258	sbsf->status &= ~STAT_WEL;
259	break;	259	break;
260	case CMD_READ_STATUS:	260	case SPINOR_OP_RDSR:
261	sbsf->state = SF_READ_STATUS;	261	sbsf->state = SF_READ_STATUS;
262	break;	262	break;
263	case CMD_READ_STATUS1:	263	case SPINOR_OP_RDSR2:
264	sbsf->state = SF_READ_STATUS1;	264	sbsf->state = SF_READ_STATUS1;
265	break;	265	break;
266	case CMD_WRITE_ENABLE:	266	case SPINOR_OP_WREN:
267	debug(" write enabled\n");	267	debug(" write enabled\n");
268	sbsf->status \|= STAT_WEL;	268	sbsf->status \|= STAT_WEL;
269	break;	269	break;
270	case CMD_WRITE_STATUS:	270	case SPINOR_OP_WRSR:
271	sbsf->state = SF_WRITE_STATUS;	271	sbsf->state = SF_WRITE_STATUS;
272	break;	272	break;
273	default: {	273	default: {
274	int flags = sbsf->data->flags;	274	int flags = sbsf->data->flags;
275		275
276	/* we only support erase here */	276	/* we only support erase here */
277	if (sbsf->cmd == CMD_ERASE_CHIP) {	277	if (sbsf->cmd == SPINOR_OP_CHIP_ERASE) {
278	sbsf->erase_size = sbsf->data->sector_size *	278	sbsf->erase_size = sbsf->data->sector_size *
279	sbsf->data->n_sectors;	279	sbsf->data->n_sectors;
280	} else if (sbsf->cmd == CMD_ERASE_4K && (flags & SECT_4K)) {	280	} else if (sbsf->cmd == SPINOR_OP_BE_4K && (flags & SECT_4K)) {
281	sbsf->erase_size = 4 << 10;	281	sbsf->erase_size = 4 << 10;
282	} else if (sbsf->cmd == CMD_ERASE_64K && !(flags & SECT_4K)) {	282	} else if (sbsf->cmd == SPINOR_OP_SE && !(flags & SECT_4K)) {
283	sbsf->erase_size = 64 << 10;	283	sbsf->erase_size = 64 << 10;
284	} else {	284	} else {
285	debug(" cmd unknown: %#x\n", sbsf->cmd);	285	debug(" cmd unknown: %#x\n", sbsf->cmd);
286	return -EIO;	286	return -EIO;
287	}	287	}
288	sbsf->state = SF_ADDR;	288	sbsf->state = SF_ADDR;
289	break;	289	break;
290	}	290	}
291	}	291	}
292		292
293	if (oldstate != sbsf->state)	293	if (oldstate != sbsf->state)
294	log_content(" cmd: transition to %s state\n",	294	log_content(" cmd: transition to %s state\n",
295	sandbox_sf_state_name(sbsf->state));	295	sandbox_sf_state_name(sbsf->state));
296		296
297	return 0;	297	return 0;
298	}	298	}
299		299
300	int sandbox_erase_part(struct sandbox_spi_flash *sbsf, int size)	300	int sandbox_erase_part(struct sandbox_spi_flash *sbsf, int size)
301	{	301	{
302	int todo;	302	int todo;
303	int ret;	303	int ret;
304		304
305	while (size > 0) {	305	while (size > 0) {
306	todo = min(size, (int)sizeof(sandbox_sf_0xff));	306	todo = min(size, (int)sizeof(sandbox_sf_0xff));
307	ret = os_write(sbsf->fd, sandbox_sf_0xff, todo);	307	ret = os_write(sbsf->fd, sandbox_sf_0xff, todo);
308	if (ret != todo)	308	if (ret != todo)
309	return ret;	309	return ret;
310	size -= todo;	310	size -= todo;
311	}	311	}
312		312
313	return 0;	313	return 0;
314	}	314	}
315		315
316	static int sandbox_sf_xfer(struct udevice *dev, unsigned int bitlen,	316	static int sandbox_sf_xfer(struct udevice *dev, unsigned int bitlen,
317	const void rxp, void txp, unsigned long flags)	317	const void rxp, void txp, unsigned long flags)
318	{	318	{
319	struct sandbox_spi_flash *sbsf = dev_get_priv(dev);	319	struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
320	const uint8_t *rx = rxp;	320	const uint8_t *rx = rxp;
321	uint8_t *tx = txp;	321	uint8_t *tx = txp;
322	uint cnt, pos = 0;	322	uint cnt, pos = 0;
323	int bytes = bitlen / 8;	323	int bytes = bitlen / 8;
324	int ret;	324	int ret;
325		325
326	log_content("sandbox_sf: state:%x(%s) bytes:%u\n", sbsf->state,	326	log_content("sandbox_sf: state:%x(%s) bytes:%u\n", sbsf->state,
327	sandbox_sf_state_name(sbsf->state), bytes);	327	sandbox_sf_state_name(sbsf->state), bytes);
328		328
329	if ((flags & SPI_XFER_BEGIN))	329	if ((flags & SPI_XFER_BEGIN))
330	sandbox_sf_cs_activate(dev);	330	sandbox_sf_cs_activate(dev);
331		331
332	if (sbsf->state == SF_CMD) {	332	if (sbsf->state == SF_CMD) {
333	/* Figure out the initial state */	333	/* Figure out the initial state */
334	ret = sandbox_sf_process_cmd(sbsf, rx, tx);	334	ret = sandbox_sf_process_cmd(sbsf, rx, tx);
335	if (ret)	335	if (ret)
336	return ret;	336	return ret;
337	++pos;	337	++pos;
338	}	338	}
339		339
340	/* Process the remaining data */	340	/* Process the remaining data */
341	while (pos < bytes) {	341	while (pos < bytes) {
342	switch (sbsf->state) {	342	switch (sbsf->state) {
343	case SF_ID: {	343	case SF_ID: {
344	u8 id;	344	u8 id;
345		345
346	log_content(" id: off:%u tx:", sbsf->off);	346	log_content(" id: off:%u tx:", sbsf->off);
347	if (sbsf->off < IDCODE_LEN) {	347	if (sbsf->off < IDCODE_LEN) {
348	/* Extract correct byte from ID 0x00aabbcc */	348	/* Extract correct byte from ID 0x00aabbcc */
349	id = ((JEDEC_MFR(sbsf->data) << 16) \|	349	id = ((JEDEC_MFR(sbsf->data) << 16) \|
350	JEDEC_ID(sbsf->data)) >>	350	JEDEC_ID(sbsf->data)) >>
351	(8 * (IDCODE_LEN - 1 - sbsf->off));	351	(8 * (IDCODE_LEN - 1 - sbsf->off));
352	} else {	352	} else {
353	id = 0;	353	id = 0;
354	}	354	}
355	log_content("%d %02x\n", sbsf->off, id);	355	log_content("%d %02x\n", sbsf->off, id);
356	tx[pos++] = id;	356	tx[pos++] = id;
357	++sbsf->off;	357	++sbsf->off;
358	break;	358	break;
359	}	359	}
360	case SF_ADDR:	360	case SF_ADDR:
361	log_content(" addr: bytes:%u rx:%02x ",	361	log_content(" addr: bytes:%u rx:%02x ",
362	sbsf->addr_bytes, rx[pos]);	362	sbsf->addr_bytes, rx[pos]);
363		363
364	if (sbsf->addr_bytes++ < SF_ADDR_LEN)	364	if (sbsf->addr_bytes++ < SF_ADDR_LEN)
365	sbsf->off = (sbsf->off << 8) \| rx[pos];	365	sbsf->off = (sbsf->off << 8) \| rx[pos];
366	log_content("addr:%06x\n", sbsf->off);	366	log_content("addr:%06x\n", sbsf->off);
367		367
368	if (tx)	368	if (tx)
369	sandbox_spi_tristate(&tx[pos], 1);	369	sandbox_spi_tristate(&tx[pos], 1);
370	pos++;	370	pos++;
371		371
372	/* See if we're done processing */	372	/* See if we're done processing */
373	if (sbsf->addr_bytes <	373	if (sbsf->addr_bytes <
374	SF_ADDR_LEN + sbsf->pad_addr_bytes)	374	SF_ADDR_LEN + sbsf->pad_addr_bytes)
375	break;	375	break;
376		376
377	/* Next state! */	377	/* Next state! */
378	if (os_lseek(sbsf->fd, sbsf->off, OS_SEEK_SET) < 0) {	378	if (os_lseek(sbsf->fd, sbsf->off, OS_SEEK_SET) < 0) {
379	puts("sandbox_sf: os_lseek() failed");	379	puts("sandbox_sf: os_lseek() failed");
380	return -EIO;	380	return -EIO;
381	}	381	}
382	switch (sbsf->cmd) {	382	switch (sbsf->cmd) {
383	case CMD_READ_ARRAY_FAST:	383	case SPINOR_OP_READ_FAST:
384	case CMD_READ_ARRAY_SLOW:	384	case SPINOR_OP_READ:
385	sbsf->state = SF_READ;	385	sbsf->state = SF_READ;
386	break;	386	break;
387	case CMD_PAGE_PROGRAM:	387	case SPINOR_OP_PP:
388	sbsf->state = SF_WRITE;	388	sbsf->state = SF_WRITE;
389	break;	389	break;
390	default:	390	default:
391	/* assume erase state ... */	391	/* assume erase state ... */
392	sbsf->state = SF_ERASE;	392	sbsf->state = SF_ERASE;
393	goto case_sf_erase;	393	goto case_sf_erase;
394	}	394	}
395	log_content(" cmd: transition to %s state\n",	395	log_content(" cmd: transition to %s state\n",
396	sandbox_sf_state_name(sbsf->state));	396	sandbox_sf_state_name(sbsf->state));
397	break;	397	break;
398	case SF_READ:	398	case SF_READ:
399	/*	399	/*
400	* XXX: need to handle exotic behavior:	400	* XXX: need to handle exotic behavior:
401	* - reading past end of device	401	* - reading past end of device
402	*/	402	*/
403		403
404	cnt = bytes - pos;	404	cnt = bytes - pos;
405	log_content(" tx: read(%u)\n", cnt);	405	log_content(" tx: read(%u)\n", cnt);
406	assert(tx);	406	assert(tx);
407	ret = os_read(sbsf->fd, tx + pos, cnt);	407	ret = os_read(sbsf->fd, tx + pos, cnt);
408	if (ret < 0) {	408	if (ret < 0) {
409	puts("sandbox_sf: os_read() failed\n");	409	puts("sandbox_sf: os_read() failed\n");
410	return -EIO;	410	return -EIO;
411	}	411	}
412	pos += ret;	412	pos += ret;
413	break;	413	break;
414	case SF_READ_STATUS:	414	case SF_READ_STATUS:
415	log_content(" read status: %#x\n", sbsf->status);	415	log_content(" read status: %#x\n", sbsf->status);
416	cnt = bytes - pos;	416	cnt = bytes - pos;
417	memset(tx + pos, sbsf->status, cnt);	417	memset(tx + pos, sbsf->status, cnt);
418	pos += cnt;	418	pos += cnt;
419	break;	419	break;
420	case SF_READ_STATUS1:	420	case SF_READ_STATUS1:
421	log_content(" read status: %#x\n", sbsf->status);	421	log_content(" read status: %#x\n", sbsf->status);
422	cnt = bytes - pos;	422	cnt = bytes - pos;
423	memset(tx + pos, sbsf->status >> 8, cnt);	423	memset(tx + pos, sbsf->status >> 8, cnt);
424	pos += cnt;	424	pos += cnt;
425	break;	425	break;
426	case SF_WRITE_STATUS:	426	case SF_WRITE_STATUS:
427	log_content(" write status: %#x (ignored)\n", rx[pos]);	427	log_content(" write status: %#x (ignored)\n", rx[pos]);
428	pos = bytes;	428	pos = bytes;
429	break;	429	break;
430	case SF_WRITE:	430	case SF_WRITE:
431	/*	431	/*
432	* XXX: need to handle exotic behavior:	432	* XXX: need to handle exotic behavior:
433	* - unaligned addresses	433	* - unaligned addresses
434	* - more than a page (256) worth of data	434	* - more than a page (256) worth of data
435	* - reading past end of device	435	* - reading past end of device
436	*/	436	*/
437	if (!(sbsf->status & STAT_WEL)) {	437	if (!(sbsf->status & STAT_WEL)) {
438	puts("sandbox_sf: write enable not set before write\n");	438	puts("sandbox_sf: write enable not set before write\n");
439	goto done;	439	goto done;
440	}	440	}
441		441
442	cnt = bytes - pos;	442	cnt = bytes - pos;
443	log_content(" rx: write(%u)\n", cnt);	443	log_content(" rx: write(%u)\n", cnt);
444	if (tx)	444	if (tx)
445	sandbox_spi_tristate(&tx[pos], cnt);	445	sandbox_spi_tristate(&tx[pos], cnt);
446	ret = os_write(sbsf->fd, rx + pos, cnt);	446	ret = os_write(sbsf->fd, rx + pos, cnt);
447	if (ret < 0) {	447	if (ret < 0) {
448	puts("sandbox_spi: os_write() failed\n");	448	puts("sandbox_spi: os_write() failed\n");
449	return -EIO;	449	return -EIO;
450	}	450	}
451	pos += ret;	451	pos += ret;
452	sbsf->status &= ~STAT_WEL;	452	sbsf->status &= ~STAT_WEL;
453	break;	453	break;
454	case SF_ERASE:	454	case SF_ERASE:
455	case_sf_erase: {	455	case_sf_erase: {
456	if (!(sbsf->status & STAT_WEL)) {	456	if (!(sbsf->status & STAT_WEL)) {
457	puts("sandbox_sf: write enable not set before erase\n");	457	puts("sandbox_sf: write enable not set before erase\n");
458	goto done;	458	goto done;
459	}	459	}
460		460
461	/* verify address is aligned */	461	/* verify address is aligned */
462	if (sbsf->off & (sbsf->erase_size - 1)) {	462	if (sbsf->off & (sbsf->erase_size - 1)) {
463	log_content(" sector erase: cmd:%#x needs align:%#x, but we got %#x\n",	463	log_content(" sector erase: cmd:%#x needs align:%#x, but we got %#x\n",
464	sbsf->cmd, sbsf->erase_size,	464	sbsf->cmd, sbsf->erase_size,
465	sbsf->off);	465	sbsf->off);
466	sbsf->status &= ~STAT_WEL;	466	sbsf->status &= ~STAT_WEL;
467	goto done;	467	goto done;
468	}	468	}
469		469
470	log_content(" sector erase addr: %u, size: %u\n",	470	log_content(" sector erase addr: %u, size: %u\n",
471	sbsf->off, sbsf->erase_size);	471	sbsf->off, sbsf->erase_size);
472		472
473	cnt = bytes - pos;	473	cnt = bytes - pos;
474	if (tx)	474	if (tx)
475	sandbox_spi_tristate(&tx[pos], cnt);	475	sandbox_spi_tristate(&tx[pos], cnt);
476	pos += cnt;	476	pos += cnt;
477		477
478	/*	478	/*
479	* TODO(vapier@gentoo.org): latch WIP in status, and	479	* TODO(vapier@gentoo.org): latch WIP in status, and
480	* delay before clearing it ?	480	* delay before clearing it ?
481	*/	481	*/
482	ret = sandbox_erase_part(sbsf, sbsf->erase_size);	482	ret = sandbox_erase_part(sbsf, sbsf->erase_size);
483	sbsf->status &= ~STAT_WEL;	483	sbsf->status &= ~STAT_WEL;
484	if (ret) {	484	if (ret) {
485	log_content("sandbox_sf: Erase failed\n");	485	log_content("sandbox_sf: Erase failed\n");
486	goto done;	486	goto done;
487	}	487	}
488	goto done;	488	goto done;
489	}	489	}
490	default:	490	default:
491	log_content(" ??? no idea what to do ???\n");	491	log_content(" ??? no idea what to do ???\n");
492	goto done;	492	goto done;
493	}	493	}
494	}	494	}
495		495
496	done:	496	done:
497	if (flags & SPI_XFER_END)	497	if (flags & SPI_XFER_END)
498	sandbox_sf_cs_deactivate(dev);	498	sandbox_sf_cs_deactivate(dev);
499	return pos == bytes ? 0 : -EIO;	499	return pos == bytes ? 0 : -EIO;
500	}	500	}
501		501
502	int sandbox_sf_ofdata_to_platdata(struct udevice *dev)	502	int sandbox_sf_ofdata_to_platdata(struct udevice *dev)
503	{	503	{
504	struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);	504	struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
505		505
506	pdata->filename = dev_read_string(dev, "sandbox,filename");	506	pdata->filename = dev_read_string(dev, "sandbox,filename");
507	pdata->device_name = dev_read_string(dev, "compatible");	507	pdata->device_name = dev_read_string(dev, "compatible");
508	if (!pdata->filename \|\| !pdata->device_name) {	508	if (!pdata->filename \|\| !pdata->device_name) {
509	debug("%s: Missing properties, filename=%s, device_name=%s\n",	509	debug("%s: Missing properties, filename=%s, device_name=%s\n",
510	__func__, pdata->filename, pdata->device_name);	510	__func__, pdata->filename, pdata->device_name);
511	return -EINVAL;	511	return -EINVAL;
512	}	512	}
513		513
514	return 0;	514	return 0;
515	}	515	}
516		516
517	static const struct dm_spi_emul_ops sandbox_sf_emul_ops = {	517	static const struct dm_spi_emul_ops sandbox_sf_emul_ops = {
518	.xfer = sandbox_sf_xfer,	518	.xfer = sandbox_sf_xfer,
519	};	519	};
520		520
521	#ifdef CONFIG_SPI_FLASH	521	#ifdef CONFIG_SPI_FLASH
522	int sandbox_sf_bind_emul(struct sandbox_state *state, int busnum, int cs,	522	int sandbox_sf_bind_emul(struct sandbox_state *state, int busnum, int cs,
523	struct udevice bus, ofnode node, const char spec)	523	struct udevice bus, ofnode node, const char spec)
524	{	524	{
525	struct udevice *emul;	525	struct udevice *emul;
526	char name[20], *str;	526	char name[20], *str;
527	struct driver *drv;	527	struct driver *drv;
528	int ret;	528	int ret;
529		529
530	/* now the emulator */	530	/* now the emulator */
531	strncpy(name, spec, sizeof(name) - 6);	531	strncpy(name, spec, sizeof(name) - 6);
532	name[sizeof(name) - 6] = '\0';	532	name[sizeof(name) - 6] = '\0';
533	strcat(name, "-emul");	533	strcat(name, "-emul");
534	drv = lists_driver_lookup_name("sandbox_sf_emul");	534	drv = lists_driver_lookup_name("sandbox_sf_emul");
535	if (!drv) {	535	if (!drv) {
536	puts("Cannot find sandbox_sf_emul driver\n");	536	puts("Cannot find sandbox_sf_emul driver\n");
537	return -ENOENT;	537	return -ENOENT;
538	}	538	}
539	str = strdup(name);	539	str = strdup(name);
540	if (!str)	540	if (!str)
541	return -ENOMEM;	541	return -ENOMEM;
542	ret = device_bind_ofnode(bus, drv, str, NULL, node, &emul);	542	ret = device_bind_ofnode(bus, drv, str, NULL, node, &emul);
543	if (ret) {	543	if (ret) {
544	free(str);	544	free(str);
545	printf("Cannot create emul device for spec '%s' (err=%d)\n",	545	printf("Cannot create emul device for spec '%s' (err=%d)\n",
546	spec, ret);	546	spec, ret);
547	return ret;	547	return ret;
548	}	548	}
549	state->spi[busnum][cs].emul = emul;	549	state->spi[busnum][cs].emul = emul;
550		550
551	return 0;	551	return 0;
552	}	552	}
553		553
554	void sandbox_sf_unbind_emul(struct sandbox_state *state, int busnum, int cs)	554	void sandbox_sf_unbind_emul(struct sandbox_state *state, int busnum, int cs)
555	{	555	{
556	struct udevice *dev;	556	struct udevice *dev;
557		557
558	dev = state->spi[busnum][cs].emul;	558	dev = state->spi[busnum][cs].emul;
559	device_remove(dev, DM_REMOVE_NORMAL);	559	device_remove(dev, DM_REMOVE_NORMAL);
560	device_unbind(dev);	560	device_unbind(dev);
561	state->spi[busnum][cs].emul = NULL;	561	state->spi[busnum][cs].emul = NULL;
562	}	562	}
563		563
564	int sandbox_spi_get_emul(struct sandbox_state *state,	564	int sandbox_spi_get_emul(struct sandbox_state *state,
565	struct udevice bus, struct udevice slave,	565	struct udevice bus, struct udevice slave,
566	struct udevice **emulp)	566	struct udevice **emulp)
567	{	567	{
568	struct sandbox_spi_info *info;	568	struct sandbox_spi_info *info;
569	int busnum = bus->seq;	569	int busnum = bus->seq;
570	int cs = spi_chip_select(slave);	570	int cs = spi_chip_select(slave);
571	int ret;	571	int ret;
572		572
573	info = &state->spi[busnum][cs];	573	info = &state->spi[busnum][cs];
574	if (!info->emul) {	574	if (!info->emul) {
575	/* Use the same device tree node as the SPI flash device */	575	/* Use the same device tree node as the SPI flash device */
576	debug("%s: busnum=%u, cs=%u: binding SPI flash emulation: ",	576	debug("%s: busnum=%u, cs=%u: binding SPI flash emulation: ",
577	__func__, busnum, cs);	577	__func__, busnum, cs);
578	ret = sandbox_sf_bind_emul(state, busnum, cs, bus,	578	ret = sandbox_sf_bind_emul(state, busnum, cs, bus,
579	dev_ofnode(slave), slave->name);	579	dev_ofnode(slave), slave->name);
580	if (ret) {	580	if (ret) {
581	debug("failed (err=%d)\n", ret);	581	debug("failed (err=%d)\n", ret);
582	return ret;	582	return ret;
583	}	583	}
584	debug("OK\n");	584	debug("OK\n");
585	}	585	}
586	*emulp = info->emul;	586	*emulp = info->emul;
587		587
588	return 0;	588	return 0;
589	}	589	}
590	#endif	590	#endif
591		591
592	static const struct udevice_id sandbox_sf_ids[] = {	592	static const struct udevice_id sandbox_sf_ids[] = {
593	{ .compatible = "sandbox,spi-flash" },	593	{ .compatible = "sandbox,spi-flash" },
594	{ }	594	{ }
595	};	595	};
596		596
597	U_BOOT_DRIVER(sandbox_sf_emul) = {	597	U_BOOT_DRIVER(sandbox_sf_emul) = {
598	.name = "sandbox_sf_emul",	598	.name = "sandbox_sf_emul",
599	.id = UCLASS_SPI_EMUL,	599	.id = UCLASS_SPI_EMUL,
600	.of_match = sandbox_sf_ids,	600	.of_match = sandbox_sf_ids,
601	.ofdata_to_platdata = sandbox_sf_ofdata_to_platdata,	601	.ofdata_to_platdata = sandbox_sf_ofdata_to_platdata,
602	.probe = sandbox_sf_probe,	602	.probe = sandbox_sf_probe,
603	.remove = sandbox_sf_remove,	603	.remove = sandbox_sf_remove,
604	.priv_auto_alloc_size = sizeof(struct sandbox_spi_flash),	604	.priv_auto_alloc_size = sizeof(struct sandbox_spi_flash),
605	.platdata_auto_alloc_size = sizeof(struct sandbox_spi_flash_plat_data),	605	.platdata_auto_alloc_size = sizeof(struct sandbox_spi_flash_plat_data),
606	.ops = &sandbox_sf_emul_ops,	606	.ops = &sandbox_sf_emul_ops,
607	};	607	};
608		608

drivers/mtd/spi/sf_dataflash.c

Diff comments View file @ c4e8862

 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Atmel DataFlash probing
  *
  * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
  * Haikun Wang (haikun.wang@freescale.com)
  */
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <spi.h>
 #include <spi_flash.h>
 #include <div64.h>
 #include <linux/err.h>
 #include <linux/math64.h>
 #include "sf_internal.h"
+#define CMD_READ_ID		0x9f
 /* reads can bypass the buffers */
 #define OP_READ_CONTINUOUS	0xE8
 #define OP_READ_PAGE		0xD2
 /* group B requests can run even while status reports "busy" */
 #define OP_READ_STATUS		0xD7	/* group B */
 /* move data between host and buffer */
 #define OP_READ_BUFFER1		0xD4	/* group B */
 #define OP_READ_BUFFER2		0xD6	/* group B */
 #define OP_WRITE_BUFFER1	0x84	/* group B */
 #define OP_WRITE_BUFFER2	0x87	/* group B */
 /* erasing flash */
 #define OP_ERASE_PAGE		0x81
 #define OP_ERASE_BLOCK		0x50
 /* move data between buffer and flash */
 #define OP_TRANSFER_BUF1	0x53
 #define OP_TRANSFER_BUF2	0x55
 #define OP_MREAD_BUFFER1	0xD4
 #define OP_MREAD_BUFFER2	0xD6
 #define OP_MWERASE_BUFFER1	0x83
 #define OP_MWERASE_BUFFER2	0x86
 #define OP_MWRITE_BUFFER1	0x88	/* sector must be pre-erased */
 #define OP_MWRITE_BUFFER2	0x89	/* sector must be pre-erased */
 /* write to buffer, then write-erase to flash */
 #define OP_PROGRAM_VIA_BUF1	0x82
 #define OP_PROGRAM_VIA_BUF2	0x85
 /* compare buffer to flash */
 #define OP_COMPARE_BUF1		0x60
 #define OP_COMPARE_BUF2		0x61
 /* read flash to buffer, then write-erase to flash */
 #define OP_REWRITE_VIA_BUF1	0x58
 #define OP_REWRITE_VIA_BUF2	0x59
 /*
  * newer chips report JEDEC manufacturer and device IDs; chip
  * serial number and OTP bits; and per-sector writeprotect.
  */
 #define OP_READ_ID		0x9F
 #define OP_READ_SECURITY	0x77
 #define OP_WRITE_SECURITY_REVC	0x9A
 #define OP_WRITE_SECURITY	0x9B	/* revision D */
 struct dataflash {
 	uint8_t			command[16];
 	unsigned short		page_offset;	/* offset in flash address */
 };
 /* Return the status of the DataFlash device */
 static inline int dataflash_status(struct spi_slave *spi)
 {
 	int ret;
 	u8 status;
 	/*
 	 * NOTE:  at45db321c over 25 MHz wants to write
 	 * a dummy byte after the opcode...
 	 */
 	ret = spi_flash_cmd(spi, OP_READ_STATUS, &status, 1);
 	return ret ? -EIO : status;
 }
 /*
  * Poll the DataFlash device until it is READY.
  * This usually takes 5-20 msec or so; more for sector erase.
  * ready: return > 0
  */
 static int dataflash_waitready(struct spi_slave *spi)
 {
 	int status;
 	int timeout = 2 * CONFIG_SYS_HZ;
 	int timebase;
 	timebase = get_timer(0);
 	do {
 		status = dataflash_status(spi);
 		if (status < 0)
 			status = 0;
 		if (status & (1 << 7))	/* RDY/nBSY */
 			return status;
 		mdelay(3);
 	} while (get_timer(timebase) < timeout);
 	return -ETIME;
 }
 /* Erase pages of flash */
 static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
 {
 	struct dataflash	*dataflash;
 	struct spi_flash	*spi_flash;
 	struct spi_slave	*spi;
 	unsigned		blocksize;
 	uint8_t			*command;
 	uint32_t		rem;
 	int			status;
 	dataflash = dev_get_priv(dev);
 	spi_flash = dev_get_uclass_priv(dev);
 	spi = spi_flash->spi;
 	blocksize = spi_flash->page_size << 3;
 	memset(dataflash->command, 0 , sizeof(dataflash->command));
 	command = dataflash->command;
 	debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
 	div_u64_rem(len, spi_flash->page_size, &rem);
 	if (rem) {
 		printf("%s: len(0x%x) isn't the multiple of page size(0x%x)\n",
 		       dev->name, len, spi_flash->page_size);
 		return -EINVAL;
 	}
 	div_u64_rem(offset, spi_flash->page_size, &rem);
 	if (rem) {
 		printf("%s: offset(0x%x) isn't the multiple of page size(0x%x)\n",
 		       dev->name, offset, spi_flash->page_size);
 		return -EINVAL;
 	}
 	status = spi_claim_bus(spi);
 	if (status) {
 		debug("dataflash: unable to claim SPI bus\n");
 		return status;
 	}
 	while (len > 0) {
 		unsigned int	pageaddr;
 		int		do_block;
 		/*
 		 * Calculate flash page address; use block erase (for speed) if
 		 * we're at a block boundary and need to erase the whole block.
 		 */
 		pageaddr = div_u64(offset, spi_flash->page_size);
 		do_block = (pageaddr & 0x7) == 0 && len >= blocksize;
 		pageaddr = pageaddr << dataflash->page_offset;
 		command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
 		command[1] = (uint8_t)(pageaddr >> 16);
 		command[2] = (uint8_t)(pageaddr >> 8);
 		command[3] = 0;
 		debug("%s ERASE %s: (%x) %x %x %x [%d]\n",
 		      dev->name, do_block ? "block" : "page",
 		      command[0], command[1], command[2], command[3],
 		      pageaddr);
 		status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
 		if (status < 0) {
 			debug("%s: erase send command error!\n", dev->name);
 			return -EIO;
 		}
 		status = dataflash_waitready(spi);
 		if (status < 0) {
 			debug("%s: erase waitready error!\n", dev->name);
 			return status;
 		}
 		if (do_block) {
 			offset += blocksize;
 			len -= blocksize;
 		} else {
 			offset += spi_flash->page_size;
 			len -= spi_flash->page_size;
 		}
 	}
 	spi_release_bus(spi);
 	return 0;
 }
 /*
  * Read from the DataFlash device.
  *   offset : Start offset in flash device
  *   len    : Amount to read
  *   buf    : Buffer containing the data
  */
 static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len,
 			      void *buf)
 {
 	struct dataflash	*dataflash;
 	struct spi_flash	*spi_flash;
 	struct spi_slave	*spi;
 	unsigned int		addr;
 	uint8_t			*command;
 	int			status;
 	dataflash = dev_get_priv(dev);
 	spi_flash = dev_get_uclass_priv(dev);
 	spi = spi_flash->spi;
 	memset(dataflash->command, 0 , sizeof(dataflash->command));
 	command = dataflash->command;
 	debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
 	debug("READ: (%x) %x %x %x\n",
 	      command[0], command[1], command[2], command[3]);
 	/* Calculate flash page/byte address */
 	addr = (((unsigned)offset / spi_flash->page_size)
 	       << dataflash->page_offset)
 	       + ((unsigned)offset % spi_flash->page_size);
 	status = spi_claim_bus(spi);
 	if (status) {
 		debug("dataflash: unable to claim SPI bus\n");
 		return status;
 	}
 	/*
 	 * Continuous read, max clock = f(car) which may be less than
 	 * the peak rate available.  Some chips support commands with
 	 * fewer "don't care" bytes.  Both buffers stay unchanged.
 	 */
 	command[0] = OP_READ_CONTINUOUS;
 	command[1] = (uint8_t)(addr >> 16);
 	command[2] = (uint8_t)(addr >> 8);
 	command[3] = (uint8_t)(addr >> 0);
 	/* plus 4 "don't care" bytes, command len: 4 + 4 "don't care" bytes */
 	status = spi_flash_cmd_read(spi, command, 8, buf, len);
 	spi_release_bus(spi);
 	return status;
 }
 /*
  * Write to the DataFlash device.
  *   offset     : Start offset in flash device
  *   len    : Amount to write
  *   buf    : Buffer containing the data
  */
 int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
 			const void *buf)
 {
 	struct dataflash	*dataflash;
 	struct spi_flash	*spi_flash;
 	struct spi_slave	*spi;
 	uint8_t			*command;
 	unsigned int		pageaddr, addr, to, writelen;
 	size_t			remaining = len;
 	u_char			*writebuf = (u_char *)buf;
 	int			status = -EINVAL;
 	dataflash = dev_get_priv(dev);
 	spi_flash = dev_get_uclass_priv(dev);
 	spi = spi_flash->spi;
 	memset(dataflash->command, 0 , sizeof(dataflash->command));
 	command = dataflash->command;
 	debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len));
 	pageaddr = ((unsigned)offset / spi_flash->page_size);
 	to = ((unsigned)offset % spi_flash->page_size);
 	if (to + len > spi_flash->page_size)
 		writelen = spi_flash->page_size - to;
 	else
 		writelen = len;
 	status = spi_claim_bus(spi);
 	if (status) {
 		debug("dataflash: unable to claim SPI bus\n");
 		return status;
 	}
 	while (remaining > 0) {
 		debug("write @ %d:%d len=%d\n", pageaddr, to, writelen);
 		/*
 		 * REVISIT:
 		 * (a) each page in a sector must be rewritten at least
 		 *     once every 10K sibling erase/program operations.
 		 * (b) for pages that are already erased, we could
 		 *     use WRITE+MWRITE not PROGRAM for ~30% speedup.
 		 * (c) WRITE to buffer could be done while waiting for
 		 *     a previous MWRITE/MWERASE to complete ...
 		 * (d) error handling here seems to be mostly missing.
 		 *
 		 * Two persistent bits per page, plus a per-sector counter,
 		 * could support (a) and (b) ... we might consider using
 		 * the second half of sector zero, which is just one block,
 		 * to track that state.  (On AT91, that sector should also
 		 * support boot-from-DataFlash.)
 		 */
 		addr = pageaddr << dataflash->page_offset;
 		/* (1) Maybe transfer partial page to Buffer1 */
 		if (writelen != spi_flash->page_size) {
 			command[0] = OP_TRANSFER_BUF1;
 			command[1] = (addr & 0x00FF0000) >> 16;
 			command[2] = (addr & 0x0000FF00) >> 8;
 			command[3] = 0;
 			debug("TRANSFER: (%x) %x %x %x\n",
 			      command[0], command[1], command[2], command[3]);
 			status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
 			if (status < 0) {
 				debug("%s: write(<pagesize) command error!\n",
 				      dev->name);
 				return -EIO;
 			}
 			status = dataflash_waitready(spi);
 			if (status < 0) {
 				debug("%s: write(<pagesize) waitready error!\n",
 				      dev->name);
 				return status;
 			}
 		}
 		/* (2) Program full page via Buffer1 */
 		addr += to;
 		command[0] = OP_PROGRAM_VIA_BUF1;
 		command[1] = (addr & 0x00FF0000) >> 16;
 		command[2] = (addr & 0x0000FF00) >> 8;
 		command[3] = (addr & 0x000000FF);
 		debug("PROGRAM: (%x) %x %x %x\n",
 		      command[0], command[1], command[2], command[3]);
 		status = spi_flash_cmd_write(spi, command,
 					     4, writebuf, writelen);
 		if (status < 0) {
 			debug("%s: write send command error!\n", dev->name);
 			return -EIO;
 		}
 		status = dataflash_waitready(spi);
 		if (status < 0) {
 			debug("%s: write waitready error!\n", dev->name);
 			return status;
 		}
 #ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY
 		/* (3) Compare to Buffer1 */
 		addr = pageaddr << dataflash->page_offset;
 		command[0] = OP_COMPARE_BUF1;
 		command[1] = (addr & 0x00FF0000) >> 16;
 		command[2] = (addr & 0x0000FF00) >> 8;
 		command[3] = 0;
 		debug("COMPARE: (%x) %x %x %x\n",
 		      command[0], command[1], command[2], command[3]);
 		status = spi_flash_cmd_write(spi, command,
 					     4, writebuf, writelen);
 		if (status < 0) {
 			debug("%s: write(compare) send command error!\n",
 			      dev->name);
 			return -EIO;
 		}
 		status = dataflash_waitready(spi);
 		/* Check result of the compare operation */
 		if (status & (1 << 6)) {
 			printf("dataflash: write compare page %u, err %d\n",
 			       pageaddr, status);
 			remaining = 0;
 			status = -EIO;
 			break;
 		} else {
 			status = 0;
 		}
 #endif	/* CONFIG_SPI_DATAFLASH_WRITE_VERIFY */
 		remaining = remaining - writelen;
 		pageaddr++;
 		to = 0;
 		writebuf += writelen;
 		if (remaining > spi_flash->page_size)
 			writelen = spi_flash->page_size;
 		else
 			writelen = remaining;
 	}
 	spi_release_bus(spi);
 	return 0;
 }
 static int add_dataflash(struct udevice *dev, char *name, int nr_pages,
 			     int pagesize, int pageoffset, char revision)
 {
 	struct spi_flash *spi_flash;
 	struct dataflash *dataflash;
 	dataflash = dev_get_priv(dev);
 	spi_flash = dev_get_uclass_priv(dev);
 	dataflash->page_offset = pageoffset;
 	spi_flash->name = name;
 	spi_flash->page_size = pagesize;
 	spi_flash->size = nr_pages * pagesize;
 	spi_flash->erase_size = pagesize;
 #ifndef CONFIG_SPL_BUILD
 	printf("SPI DataFlash: Detected %s with page size ", spi_flash->name);
 	print_size(spi_flash->page_size, ", erase size ");
 	print_size(spi_flash->erase_size, ", total ");
 	print_size(spi_flash->size, "");
 	printf(", revision %c", revision);
 	puts("\n");
 #endif
 	return 0;
 }
-struct flash_info {
+struct data_flash_info {
 	char		*name;
 	/*
 	 * JEDEC id has a high byte of zero plus three data bytes:
 	 * the manufacturer id, then a two byte device id.
 	 */
 	uint32_t	jedec_id;
 	/* The size listed here is what works with OP_ERASE_PAGE. */
 	unsigned	nr_pages;
 	uint16_t	pagesize;
 	uint16_t	pageoffset;
 	uint16_t	flags;
 #define SUP_POW2PS	0x0002		/* supports 2^N byte pages */
 #define IS_POW2PS	0x0001		/* uses 2^N byte pages */
 };
-static struct flash_info dataflash_data[] = {
+static struct data_flash_info dataflash_data[] = {
 	/*
 	 * NOTE:  chips with SUP_POW2PS (rev D and up) need two entries,
 	 * one with IS_POW2PS and the other without.  The entry with the
 	 * non-2^N byte page size can't name exact chip revisions without
 	 * losing backwards compatibility for cmdlinepart.
 	 *
 	 * Those two entries have different name spelling format in order to
 	 * show their difference obviously.
 	 * The upper case refer to the chip isn't in normal 2^N bytes page-size
 	 * mode.
 	 * The lower case refer to the chip is in normal 2^N bytes page-size
 	 * mode.
 	 *
 	 * These newer chips also support 128-byte security registers (with
 	 * 64 bytes one-time-programmable) and software write-protection.
 	 */
 	{ "AT45DB011B",  0x1f2200, 512, 264, 9, SUP_POW2PS},
 	{ "at45db011d",  0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS},
 	{ "AT45DB021B",  0x1f2300, 1024, 264, 9, SUP_POW2PS},
 	{ "at45db021d",  0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS},
 	{ "AT45DB041x",  0x1f2400, 2048, 264, 9, SUP_POW2PS},
 	{ "at45db041d",  0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS},
 	{ "AT45DB081B",  0x1f2500, 4096, 264, 9, SUP_POW2PS},
 	{ "at45db081d",  0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS},
 	{ "AT45DB161x",  0x1f2600, 4096, 528, 10, SUP_POW2PS},
 	{ "at45db161d",  0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS},
 	{ "AT45DB321x",  0x1f2700, 8192, 528, 10, 0},		/* rev C */
 	{ "AT45DB321x",  0x1f2701, 8192, 528, 10, SUP_POW2PS},
 	{ "at45db321d",  0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS},
 	{ "AT45DB642x",  0x1f2800, 8192, 1056, 11, SUP_POW2PS},
 	{ "at45db642d",  0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
 };
-static struct flash_info *jedec_probe(struct spi_slave *spi)
+static struct data_flash_info *jedec_probe(struct spi_slave *spi)
 {
 	int			tmp;
 	uint8_t			id[5];
 	uint32_t		jedec;
-	struct flash_info	*info;
+	struct data_flash_info	*info;
 	int status;
 	/*
 	 * JEDEC also defines an optional "extended device information"
 	 * string for after vendor-specific data, after the three bytes
 	 * we use here.  Supporting some chips might require using it.
 	 *
 	 * If the vendor ID isn't Atmel's (0x1f), assume this call failed.
 	 * That's not an error; only rev C and newer chips handle it, and
 	 * only Atmel sells these chips.
 	 */
 	tmp = spi_flash_cmd(spi, CMD_READ_ID, id, sizeof(id));
 	if (tmp < 0) {
 		printf("dataflash: error %d reading JEDEC ID\n", tmp);
 		return ERR_PTR(tmp);
 	}
 	if (id[0] != 0x1f)
 		return NULL;
 	jedec = id[0];
 	jedec = jedec << 8;
 	jedec |= id[1];
 	jedec = jedec << 8;
 	jedec |= id[2];
 	for (tmp = 0, info = dataflash_data;
 			tmp < ARRAY_SIZE(dataflash_data);
 			tmp++, info++) {
 		if (info->jedec_id == jedec) {
 			if (info->flags & SUP_POW2PS) {
 				status = dataflash_status(spi);
 				if (status < 0) {
 					debug("dataflash: status error %d\n",
 					      status);
 					return NULL;
 				}
 				if (status & 0x1) {
 					if (info->flags & IS_POW2PS)
 						return info;
 				} else {
 					if (!(info->flags & IS_POW2PS))
 						return info;
 				}
 			} else {
 				return info;
 			}
 		}
 	}
 	/*
 	 * Treat other chips as errors ... we won't know the right page
 	 * size (it might be binary) even when we can tell which density
 	 * class is involved (legacy chip id scheme).
 	 */
 	printf("dataflash: JEDEC id %06x not handled\n", jedec);
 	return ERR_PTR(-ENODEV);
 }
 /*
  * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
  * or else the ID code embedded in the status bits:
  *
  *   Device      Density         ID code          #Pages PageSize  Offset
  *   AT45DB011B  1Mbit   (128K)  xx0011xx (0x0c)    512    264      9
  *   AT45DB021B  2Mbit   (256K)  xx0101xx (0x14)   1024    264      9
  *   AT45DB041B  4Mbit   (512K)  xx0111xx (0x1c)   2048    264      9
  *   AT45DB081B  8Mbit   (1M)    xx1001xx (0x24)   4096    264      9
  *   AT45DB0161B 16Mbit  (2M)    xx1011xx (0x2c)   4096    528     10
  *   AT45DB0321B 32Mbit  (4M)    xx1101xx (0x34)   8192    528     10
  *   AT45DB0642  64Mbit  (8M)    xx111xxx (0x3c)   8192   1056     11
  *   AT45DB1282  128Mbit (16M)   xx0100xx (0x10)  16384   1056     11
  */
 static int spi_dataflash_probe(struct udevice *dev)
 {
 	struct spi_slave *spi = dev_get_parent_priv(dev);
 	struct spi_flash *spi_flash;
-	struct flash_info *info;
+	struct data_flash_info *info;
 	int status;
 	spi_flash = dev_get_uclass_priv(dev);
 	spi_flash->spi = spi;
 	spi_flash->dev = dev;
 	status = spi_claim_bus(spi);
 	if (status)
 		return status;
 	/*
 	 * Try to detect dataflash by JEDEC ID.
 	 * If it succeeds we know we have either a C or D part.
 	 * D will support power of 2 pagesize option.
 	 * Both support the security register, though with different
 	 * write procedures.
 	 */
 	info = jedec_probe(spi);
 	if (IS_ERR(info))
 		goto err_jedec_probe;
 	if (info != NULL) {
 		status = add_dataflash(dev, info->name, info->nr_pages,
 				info->pagesize, info->pageoffset,
 				(info->flags & SUP_POW2PS) ? 'd' : 'c');
 		if (status < 0)
 			goto err_status;
 	}
        /*
 	* Older chips support only legacy commands, identifing
 	* capacity using bits in the status byte.
 	*/
 	status = dataflash_status(spi);
 	if (status <= 0 || status == 0xff) {
 		printf("dataflash: read status error %d\n", status);
 		if (status == 0 || status == 0xff)
 			status = -ENODEV;
 		goto err_jedec_probe;
 	}
        /*
 	* if there's a device there, assume it's dataflash.
 	* board setup should have set spi->max_speed_max to
 	* match f(car) for continuous reads, mode 0 or 3.
 	*/
 	switch (status & 0x3c) {
 	case 0x0c:	/* 0 0 1 1 x x */
 		status = add_dataflash(dev, "AT45DB011B", 512, 264, 9, 0);
 		break;
 	case 0x14:	/* 0 1 0 1 x x */
 		status = add_dataflash(dev, "AT45DB021B", 1024, 264, 9, 0);
 		break;
 	case 0x1c:	/* 0 1 1 1 x x */
 		status = add_dataflash(dev, "AT45DB041x", 2048, 264, 9, 0);
 		break;
 	case 0x24:	/* 1 0 0 1 x x */
 		status = add_dataflash(dev, "AT45DB081B", 4096, 264, 9, 0);
 		break;
 	case 0x2c:	/* 1 0 1 1 x x */
 		status = add_dataflash(dev, "AT45DB161x", 4096, 528, 10, 0);
 		break;
 	case 0x34:	/* 1 1 0 1 x x */
 		status = add_dataflash(dev, "AT45DB321x", 8192, 528, 10, 0);
 		break;
 	case 0x38:	/* 1 1 1 x x x */
 	case 0x3c:
 		status = add_dataflash(dev, "AT45DB642x", 8192, 1056, 11, 0);
 		break;
 	/* obsolete AT45DB1282 not (yet?) supported */
 	default:
 		printf("dataflash: unsupported device (%x)\n", status & 0x3c);
 		status = -ENODEV;
 		goto err_status;
 	}
 	return status;
 err_status:
 	spi_free_slave(spi);
 err_jedec_probe:
 	spi_release_bus(spi);
 	return status;
 }
 static const struct dm_spi_flash_ops spi_dataflash_ops = {
 	.read = spi_dataflash_read,
 	.write = spi_dataflash_write,
 	.erase = spi_dataflash_erase,
 };
 static const struct udevice_id spi_dataflash_ids[] = {
 	{ .compatible = "atmel,at45", },
 	{ .compatible = "atmel,dataflash", },
 	{ }
 };
 U_BOOT_DRIVER(spi_dataflash) = {
 	.name		= "spi_dataflash",
 	.id		= UCLASS_SPI_FLASH,
 	.of_match	= spi_dataflash_ids,
 	.probe		= spi_dataflash_probe,
 	.priv_auto_alloc_size = sizeof(struct dataflash),
 	.ops		= &spi_dataflash_ops,
 };

drivers/mtd/spi/sf_internal.h

Diff comments View file @ c4e8862

1	/* SPDX-License-Identifier: GPL-2.0+ */	1	/* SPDX-License-Identifier: GPL-2.0+ */
2	/*	2	/*
3	* SPI flash internal definitions	3	* SPI flash internal definitions
4	*	4	*
5	* Copyright (C) 2008 Atmel Corporation	5	* Copyright (C) 2008 Atmel Corporation
6	* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.	6	* Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
7	*/	7	*/
8		8
9	#ifndef _SF_INTERNAL_H_	9	#ifndef _SF_INTERNAL_H_
10	#define _SF_INTERNAL_H_	10	#define _SF_INTERNAL_H_
11		11
12	#include <linux/types.h>	12	#include <linux/types.h>
13	#include <linux/compiler.h>	13	#include <linux/compiler.h>
14		14
15	/* Dual SPI flash memories - see SPI_COMM_DUAL_... */	15	#define SPI_NOR_MAX_ID_LEN 6
16	enum spi_dual_flash {	16	#define SPI_NOR_MAX_ADDR_WIDTH 4
17	SF_SINGLE_FLASH = 0,
18	SF_DUAL_STACKED_FLASH = BIT(0),
19	SF_DUAL_PARALLEL_FLASH = BIT(1),
20	};
21		17
22	enum spi_nor_option_flags {	18	struct flash_info {
23	SNOR_F_SST_WR = BIT(0),	19	char *name;
24	SNOR_F_USE_FSR = BIT(1),
25	SNOR_F_USE_UPAGE = BIT(3),
26	};
27		20
28	#define SPI_FLASH_3B_ADDR_LEN 3
29	#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
30	#define SPI_FLASH_16MB_BOUN 0x1000000
31
32	/* CFI Manufacture ID's */
33	#define SPI_FLASH_CFI_MFR_SPANSION 0x01
34	#define SPI_FLASH_CFI_MFR_STMICRO 0x20
35	#define SPI_FLASH_CFI_MFR_MICRON 0x2C
36	#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
37	#define SPI_FLASH_CFI_MFR_SST 0xbf
38	#define SPI_FLASH_CFI_MFR_WINBOND 0xef
39	#define SPI_FLASH_CFI_MFR_ATMEL 0x1f
40
41	/* Erase commands */
42	#define CMD_ERASE_4K 0x20
43	#define CMD_ERASE_CHIP 0xc7
44	#define CMD_ERASE_64K 0xd8
45
46	/* Write commands */
47	#define CMD_WRITE_STATUS 0x01
48	#define CMD_PAGE_PROGRAM 0x02
49	#define CMD_WRITE_DISABLE 0x04
50	#define CMD_WRITE_ENABLE 0x06
51	#define CMD_QUAD_PAGE_PROGRAM 0x32
52
53	/* Read commands */
54	#define CMD_READ_ARRAY_SLOW 0x03
55	#define CMD_READ_ARRAY_FAST 0x0b
56	#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
57	#define CMD_READ_DUAL_IO_FAST 0xbb
58	#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
59	#define CMD_READ_QUAD_IO_FAST 0xeb
60	#define CMD_READ_ID 0x9f
61	#define CMD_READ_STATUS 0x05
62	#define CMD_READ_STATUS1 0x35
63	#define CMD_READ_CONFIG 0x35
64	#define CMD_FLAG_STATUS 0x70
65
66	/* Bank addr access commands */
67	#ifdef CONFIG_SPI_FLASH_BAR
68	# define CMD_BANKADDR_BRWR 0x17
69	# define CMD_BANKADDR_BRRD 0x16
70	# define CMD_EXTNADDR_WREAR 0xC5
71	# define CMD_EXTNADDR_RDEAR 0xC8
72	#endif
73
74	/* Common status */
75	#define STATUS_WIP BIT(0)
76	#define STATUS_QEB_WINSPAN BIT(1)
77	#define STATUS_QEB_MXIC BIT(6)
78	#define STATUS_PEC BIT(7)
79	#define SR_BP0 BIT(2) /* Block protect 0 */
80	#define SR_BP1 BIT(3) /* Block protect 1 */
81	#define SR_BP2 BIT(4) /* Block protect 2 */
82
83	/* Flash timeout values */
84	#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
85	#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
86	#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
87
88	/* SST specific */
89	#ifdef CONFIG_SPI_FLASH_SST
90	#define SST26_CMD_READ_BPR 0x72
91	#define SST26_CMD_WRITE_BPR 0x42
92
93	#define SST26_BPR_8K_NUM 4
94	#define SST26_MAX_BPR_REG_LEN (18 + 1)
95	#define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
96
97	enum lock_ctl {
98	SST26_CTL_LOCK,
99	SST26_CTL_UNLOCK,
100	SST26_CTL_CHECK
101	};
102
103	# define CMD_SST_BP 0x02 /* Byte Program */
104	# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
105
106	int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
107	const void *buf);
108	int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
109	const void *buf);
110	#endif
111
112	#define JEDEC_MFR(info) ((info)->id[0])
113	#define JEDEC_ID(info) (((info)->id[1]) << 8 \| ((info)->id[2]))
114	#define JEDEC_EXT(info) (((info)->id[3]) << 8 \| ((info)->id[4]))
115	#define SPI_FLASH_MAX_ID_LEN 6
116
117	struct spi_flash_info {
118	/* Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) */
119	const char *name;
120
121	/*	21	/*
122	* This array stores the ID bytes.	22	* This array stores the ID bytes.
123	* The first three bytes are the JEDIC ID.	23	* The first three bytes are the JEDIC ID.
124	* JEDEC ID zero means "no ID" (mostly older chips).	24	* JEDEC ID zero means "no ID" (mostly older chips).
125	*/	25	*/
126	u8 id[SPI_FLASH_MAX_ID_LEN];	26	u8 id[SPI_NOR_MAX_ID_LEN];
127	u8 id_len;	27	u8 id_len;
128		28
129	/*	29	/* The size listed here is what works with SPINOR_OP_SE, which isn't
130	* The size listed here is what works with SPINOR_OP_SE, which isn't
131	* necessarily called a "sector" by the vendor.	30	* necessarily called a "sector" by the vendor.
132	*/	31	*/
133	u32 sector_size;	32	unsigned int sector_size;
134	u32 n_sectors;	33	u16 n_sectors;
135		34
136	u16 page_size;	35	u16 page_size;
		36	u16 addr_width;
137		37
138	u16 flags;	38	u16 flags;
139	#define SECT_4K BIT(0) /* CMD_ERASE_4K works uniformly */	39	#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
140	#define E_FSR BIT(1) /* use flag status register for */	40	#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
141	#define SST_WR BIT(2) /* use SST byte/word programming */	41	#define SST_WRITE BIT(2) /* use SST byte programming */
142	#define WR_QPP BIT(3) /* use Quad Page Program */	42	#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
143	#define RD_QUAD BIT(4) /* use Quad Read */	43	#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
144	#define RD_DUAL BIT(5) /* use Dual Read */	44	#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
145	#define RD_QUADIO BIT(6) /* use Quad IO Read */	45	#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
146	#define RD_DUALIO BIT(7) /* use Dual IO Read */	46	#define USE_FSR BIT(7) /* use flag status register */
147	#define RD_FULL (RD_QUAD \| RD_DUAL \| RD_QUADIO \| RD_DUALIO)	47	#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
		48	#define SPI_NOR_HAS_TB BIT(9) /*
		49	* Flash SR has Top/Bottom (TB) protect
		50	* bit. Must be used with
		51	* SPI_NOR_HAS_LOCK.
		52	*/
		53	#define SPI_S3AN BIT(10) /*
		54	* Xilinx Spartan 3AN In-System Flash
		55	* (MFR cannot be used for probing
		56	* because it has the same value as
		57	* ATMEL flashes)
		58	*/
		59	#define SPI_NOR_4B_OPCODES BIT(11) /*
		60	* Use dedicated 4byte address op codes
		61	* to support memory size above 128Mib.
		62	*/
		63	#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
		64	#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
		65	#define USE_CLSR BIT(14) /* use CLSR command */
148	};	66	};
149		67
150	extern const struct spi_flash_info spi_flash_ids[];	68	extern const struct flash_info spi_nor_ids[];
151		69
		70	#define JEDEC_MFR(info) ((info)->id[0])
		71	#define JEDEC_ID(info) (((info)->id[1]) << 8 \| ((info)->id[2]))
		72
152	/* Send a single-byte command to the device and read the response */	73	/* Send a single-byte command to the device and read the response */
153	int spi_flash_cmd(struct spi_slave spi, u8 cmd, void response, size_t len);	74	int spi_flash_cmd(struct spi_slave spi, u8 cmd, void response, size_t len);
154		75
155	/*	76	/*
156	* Send a multi-byte command to the device and read the response. Used	77	* Send a multi-byte command to the device and read the response. Used
157	* for flash array reads, etc.	78	* for flash array reads, etc.
158	*/	79	*/
159	int spi_flash_cmd_read(struct spi_slave spi, const u8 cmd,	80	int spi_flash_cmd_read(struct spi_slave spi, const u8 cmd,
160	size_t cmd_len, void *data, size_t data_len);	81	size_t cmd_len, void *data, size_t data_len);
161		82
162	/*	83	/*
163	* Send a multi-byte command to the device followed by (optional)	84	* Send a multi-byte command to the device followed by (optional)
164	* data. Used for programming the flash array, etc.	85	* data. Used for programming the flash array, etc.
165	*/	86	*/
166	int spi_flash_cmd_write(struct spi_slave spi, const u8 cmd, size_t cmd_len,	87	int spi_flash_cmd_write(struct spi_slave spi, const u8 cmd, size_t cmd_len,
167	const void *data, size_t data_len);	88	const void *data, size_t data_len);
168		89
169		90
170	/* Flash erase(sectors) operation, support all possible erase commands */
171	int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
172
173	/* Get software write-protect value (BP bits) */	91	/* Get software write-protect value (BP bits) */
174	int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash);	92	int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash);
175		93
176	/* Lock stmicro spi flash region */
177	int stm_lock(struct spi_flash *flash, u32 ofs, size_t len);
178		94
179	/* Unlock stmicro spi flash region */
180	int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len);
181
182	/* Check if a stmicro spi flash region is completely locked */
183	int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len);
184
185	/* Enable writing on the SPI flash */
186	static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
187	{
188	return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
189	}
190
191	/* Disable writing on the SPI flash */
192	static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
193	{
194	return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
195	}
196
197	/*
198	* Used for spi_flash write operation
199	* - SPI claim
200	* - spi_flash_cmd_write_enable
201	* - spi_flash_cmd_write
202	* - spi_flash_wait_till_ready
203	* - SPI release
204	*/
205	int spi_flash_write_common(struct spi_flash flash, const u8 cmd,
206	size_t cmd_len, const void *buf, size_t buf_len);
207
208	/*
209	* Flash write operation, support all possible write commands.
210	* Write the requested data out breaking it up into multiple write
211	* commands as needed per the write size.
212	*/
213	int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
214	size_t len, const void *buf);
215
216	/*
217	* Same as spi_flash_cmd_read() except it also claims/releases the SPI
218	* bus. Used as common part of the ->read() operation.
219	*/
220	int spi_flash_read_common(struct spi_flash flash, const u8 cmd,
221	size_t cmd_len, void *data, size_t data_len);
222
223	/* Flash read operation, support all possible read commands */

drivers/mtd/spi/sf_probe.c

Diff comments View file @ c4e8862

 // SPDX-License-Identifier: GPL-2.0+
 /*
  * SPI flash probing
  *
  * Copyright (C) 2008 Atmel Corporation
  * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
  */
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
 #include <spi.h>
 #include <spi_flash.h>
 #include "sf_internal.h"
 /**
  * spi_flash_probe_slave() - Probe for a SPI flash device on a bus
  *
  * @flashp: Pointer to place to put flash info, which may be NULL if the
  * space should be allocated
  */
 static int spi_flash_probe_slave(struct spi_flash *flash)
 {
 	struct spi_slave *spi = flash->spi;
 	int ret;
 	/* Setup spi_slave */
 	if (!spi) {
 		printf("SF: Failed to set up slave\n");
 		return -ENODEV;
 	}
 	/* Claim spi bus */
 	ret = spi_claim_bus(spi);
 	if (ret) {
 		debug("SF: Failed to claim SPI bus: %d\n", ret);
 		return ret;
 	}
-	ret = spi_flash_scan(flash);
+	ret = spi_nor_scan(flash);
 	if (ret)
 		goto err_read_id;
 #ifdef CONFIG_SPI_FLASH_MTD
 	ret = spi_flash_mtd_register(flash);
 #endif
 err_read_id:
 	spi_release_bus(spi);
 	return ret;
 }
 #ifndef CONFIG_DM_SPI_FLASH
 struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
 				  unsigned int max_hz, unsigned int spi_mode)
 {
 	struct spi_slave *bus;
 	struct spi_flash *flash;
 	bus = spi_setup_slave(busnum, cs, max_hz, spi_mode);
 	if (!bus)
 		return NULL;
 	/* Allocate space if needed (not used by sf-uclass */
 	flash = calloc(1, sizeof(*flash));
 	if (!flash) {
 		debug("SF: Failed to allocate spi_flash\n");
 		return NULL;
 	}
 	flash->spi = bus;
 	if (spi_flash_probe_slave(flash)) {
 		spi_free_slave(bus);
 		free(flash);
 		return NULL;
 	}
 	return flash;
 }
 void spi_flash_free(struct spi_flash *flash)
 {
 #ifdef CONFIG_SPI_FLASH_MTD
 	spi_flash_mtd_unregister();
 #endif
 	spi_free_slave(flash->spi);
 	free(flash);
 }
 #else /* defined CONFIG_DM_SPI_FLASH */
 static int spi_flash_std_read(struct udevice *dev, u32 offset, size_t len,
 			      void *buf)
 {
 	struct spi_flash *flash = dev_get_uclass_priv(dev);
+	struct mtd_info *mtd = &flash->mtd;
+	size_t retlen;
-	return log_ret(spi_flash_cmd_read_ops(flash, offset, len, buf));
+	return log_ret(mtd->_read(mtd, offset, len, &retlen, buf));
 }
 static int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len,
 			       const void *buf)
 {
 	struct spi_flash *flash = dev_get_uclass_priv(dev);
+	struct mtd_info *mtd = &flash->mtd;
+	size_t retlen;
-#if defined(CONFIG_SPI_FLASH_SST)
+	return mtd->_write(mtd, offset, len, &retlen, buf);
-	if (flash->flags & SNOR_F_SST_WR) {
-		if (flash->spi->mode & SPI_TX_BYTE)
-			return sst_write_bp(flash, offset, len, buf);
-		else
-			return sst_write_wp(flash, offset, len, buf);
-	}
-#endif
-	return spi_flash_cmd_write_ops(flash, offset, len, buf);
 }
 static int spi_flash_std_erase(struct udevice *dev, u32 offset, size_t len)
 {
 	struct spi_flash *flash = dev_get_uclass_priv(dev);
+	struct mtd_info *mtd = &flash->mtd;
+	struct erase_info instr;
-	return spi_flash_cmd_erase_ops(flash, offset, len);
+	if (offset % mtd->erasesize || len % mtd->erasesize) {
+		printf("SF: Erase offset/length not multiple of erase size\n");
+		return -EINVAL;
+	}
+	memset(&instr, 0, sizeof(instr));
+	instr.addr = offset;
+	instr.len = len;
+	return mtd->_erase(mtd, &instr);
 }
 static int spi_flash_std_get_sw_write_prot(struct udevice *dev)
 {
 	struct spi_flash *flash = dev_get_uclass_priv(dev);
 	return spi_flash_cmd_get_sw_write_prot(flash);
 }
 static int spi_flash_std_probe(struct udevice *dev)
 {
 	struct spi_slave *slave = dev_get_parent_priv(dev);
 	struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
 	struct spi_flash *flash;
 	flash = dev_get_uclass_priv(dev);
 	flash->dev = dev;
 	flash->spi = slave;
 	debug("%s: slave=%p, cs=%d\n", __func__, slave, plat->cs);
 	return spi_flash_probe_slave(flash);
 }
 static int spi_flash_std_remove(struct udevice *dev)
 {
 #ifdef CONFIG_SPI_FLASH_MTD
 	spi_flash_mtd_unregister();
 #endif
 	return 0;
 }
 static const struct dm_spi_flash_ops spi_flash_std_ops = {
 	.read = spi_flash_std_read,
 	.write = spi_flash_std_write,
 	.erase = spi_flash_std_erase,
 	.get_sw_write_prot = spi_flash_std_get_sw_write_prot,
 };
 static const struct udevice_id spi_flash_std_ids[] = {
 	{ .compatible = "spi-flash" },
 	{ .compatible = "jedec,spi-nor" },
 	{ }
 };
 U_BOOT_DRIVER(spi_flash_std) = {
 	.name		= "spi_flash_std",
 	.id		= UCLASS_SPI_FLASH,

drivers/mtd/spi/spi-nor-core.c

Diff comments View file @ c4e8862

 // SPDX-License-Identifier: GPL-2.0
 /*
  * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
  * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
  *
  * Copyright (C) 2005, Intec Automation Inc.
  * Copyright (C) 2014, Freescale Semiconductor, Inc.
  *
  * Synced from Linux v4.19
  */
 #include <common.h>
 #include <linux/err.h>
 #include <linux/errno.h>
 #include <linux/log2.h>
 #include <linux/math64.h>
 #include <linux/sizes.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/spi-nor.h>
 #include <spi-mem.h>
 #include <spi.h>
+#include "sf_internal.h"
 /* Define max times to check status register before we give up. */
 /*
  * For everything but full-chip erase; probably could be much smaller, but kept
  * around for safety for now
  */
 #define HZ					CONFIG_SYS_HZ
 #define DEFAULT_READY_WAIT_JIFFIES		(40UL * HZ)
-#define SPI_NOR_MAX_ID_LEN	6
-#define SPI_NOR_MAX_ADDR_WIDTH	4
-struct flash_info {
-	char		*name;
-	/*
-	 * This array stores the ID bytes.
-	 * The first three bytes are the JEDIC ID.
-	 * JEDEC ID zero means "no ID" (mostly older chips).
-	 */
-	u8		id[SPI_NOR_MAX_ID_LEN];
-	u8		id_len;
-	/* The size listed here is what works with SPINOR_OP_SE, which isn't
-	 * necessarily called a "sector" by the vendor.
-	 */
-	unsigned int	sector_size;
-	u16		n_sectors;
-	u16		page_size;
-	u16		addr_width;
-	u16		flags;
-#define SECT_4K			BIT(0)	/* SPINOR_OP_BE_4K works uniformly */
-#define SPI_NOR_NO_ERASE	BIT(1)	/* No erase command needed */
-#define SST_WRITE		BIT(2)	/* use SST byte programming */
-#define SPI_NOR_NO_FR		BIT(3)	/* Can't do fastread */
-#define SECT_4K_PMC		BIT(4)	/* SPINOR_OP_BE_4K_PMC works uniformly */
-#define SPI_NOR_DUAL_READ	BIT(5)	/* Flash supports Dual Read */
-#define SPI_NOR_QUAD_READ	BIT(6)	/* Flash supports Quad Read */
-#define USE_FSR			BIT(7)	/* use flag status register */
-#define SPI_NOR_HAS_LOCK	BIT(8)	/* Flash supports lock/unlock via SR */
-#define SPI_NOR_HAS_TB		BIT(9)	/*
-					 * Flash SR has Top/Bottom (TB) protect
-					 * bit. Must be used with
-					 * SPI_NOR_HAS_LOCK.
-					 */
-#define	SPI_S3AN		BIT(10)	/*
-					 * Xilinx Spartan 3AN In-System Flash
-					 * (MFR cannot be used for probing
-					 * because it has the same value as
-					 * ATMEL flashes)
-					 */
-#define SPI_NOR_4B_OPCODES	BIT(11)	/*
-					 * Use dedicated 4byte address op codes
-					 * to support memory size above 128Mib.
-					 */
-#define NO_CHIP_ERASE		BIT(12) /* Chip does not support chip erase */
-#define SPI_NOR_SKIP_SFDP	BIT(13)	/* Skip parsing of SFDP tables */
-#define USE_CLSR		BIT(14)	/* use CLSR command */
-	int	(*quad_enable)(struct spi_nor *nor);
-};
-#define JEDEC_MFR(info)	((info)->id[0])
 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
 		*op, void *buf)
 {
 	if (op->data.dir == SPI_MEM_DATA_IN)
 		op->data.buf.in = buf;
 	else
 		op->data.buf.out = buf;
 	return spi_mem_exec_op(nor->spi, op);
 }
 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
 {
 	struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1),
 					  SPI_MEM_OP_NO_ADDR,
 					  SPI_MEM_OP_NO_DUMMY,
 					  SPI_MEM_OP_DATA_IN(len, NULL, 1));
 	int ret;
 	ret = spi_nor_read_write_reg(nor, &op, val);
 	if (ret < 0)
 		dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret,
 			code);
 	return ret;
 }
 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 {
 	struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1),
 					  SPI_MEM_OP_NO_ADDR,
 					  SPI_MEM_OP_NO_DUMMY,
 					  SPI_MEM_OP_DATA_OUT(len, NULL, 1));
 	return spi_nor_read_write_reg(nor, &op, buf);
 }
 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
 				 u_char *buf)
 {
 	struct spi_mem_op op =
 			SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1),
 				   SPI_MEM_OP_ADDR(nor->addr_width, from, 1),
 				   SPI_MEM_OP_DUMMY(nor->read_dummy, 1),
 				   SPI_MEM_OP_DATA_IN(len, buf, 1));
 	size_t remaining = len;
 	int ret;
 	/* get transfer protocols. */
 	op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto);
 	op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto);
 	op.dummy.buswidth = op.addr.buswidth;
 	op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);
 	/* convert the dummy cycles to the number of bytes */
 	op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
 	while (remaining) {
 		op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
 		ret = spi_mem_adjust_op_size(nor->spi, &op);
 		if (ret)
 			return ret;
 		ret = spi_mem_exec_op(nor->spi, &op);
 		if (ret)
 			return ret;
 		op.addr.val += op.data.nbytes;
 		remaining -= op.data.nbytes;
 		op.data.buf.in += op.data.nbytes;
 	}
 	return len;
 }
 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
 				  const u_char *buf)
 {
 	struct spi_mem_op op =
 			SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1),
 				   SPI_MEM_OP_ADDR(nor->addr_width, to, 1),
 				   SPI_MEM_OP_NO_DUMMY,
 				   SPI_MEM_OP_DATA_OUT(len, buf, 1));
 	size_t remaining = len;
 	int ret;
 	/* get transfer protocols. */
 	op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto);
 	op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto);
 	op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);
 	if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
 		op.addr.nbytes = 0;
 	while (remaining) {
 		op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX;
 		ret = spi_mem_adjust_op_size(nor->spi, &op);
 		if (ret)
 			return ret;
 		ret = spi_mem_exec_op(nor->spi, &op);
 		if (ret)
 			return ret;
 		op.addr.val += op.data.nbytes;
 		remaining -= op.data.nbytes;
 		op.data.buf.out += op.data.nbytes;
 	}
 	return len;
 }
 /*
  * Read the status register, returning its value in the location
  * Return the status register value.
  * Returns negative if error occurred.
  */
 static int read_sr(struct spi_nor *nor)
 {
 	int ret;
 	u8 val;
 	ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
 	if (ret < 0) {
 		pr_debug("error %d reading SR\n", (int)ret);
 		return ret;
 	}
 	return val;
 }
 /*
  * Read the flag status register, returning its value in the location
  * Return the status register value.
  * Returns negative if error occurred.
  */
 static int read_fsr(struct spi_nor *nor)
 {
 	int ret;
 	u8 val;
 	ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
 	if (ret < 0) {
 		pr_debug("error %d reading FSR\n", ret);
 		return ret;
 	}
 	return val;
 }
 /*
  * Read configuration register, returning its value in the
  * location. Return the configuration register value.
  * Returns negative if error occurred.
  */
 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
 static int read_cr(struct spi_nor *nor)
 {
 	int ret;
 	u8 val;
 	ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
 	if (ret < 0) {
 		dev_dbg(nor->dev, "error %d reading CR\n", ret);
 		return ret;
 	}
 	return val;
 }
 #endif
 /*
  * Write status register 1 byte
  * Returns negative if error occurred.
  */
 static int write_sr(struct spi_nor *nor, u8 val)
 {
 	nor->cmd_buf[0] = val;
 	return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
 }
 /*
  * Set write enable latch with Write Enable command.
  * Returns negative if error occurred.
  */
 static int write_enable(struct spi_nor *nor)
 {
 	return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
 }
 /*
  * Send write disable instruction to the chip.
  */
 static int write_disable(struct spi_nor *nor)
 {
 	return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
 }
 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
 {
 	return mtd->priv;
 }
 #ifndef CONFIG_SPI_FLASH_BAR
 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
 {
 	size_t i;
 	for (i = 0; i < size; i++)
 		if (table[i][0] == opcode)
 			return table[i][1];
 	/* No conversion found, keep input op code. */
 	return opcode;
 }
 static u8 spi_nor_convert_3to4_read(u8 opcode)
 {
 	static const u8 spi_nor_3to4_read[][2] = {
 		{ SPINOR_OP_READ,	SPINOR_OP_READ_4B },
 		{ SPINOR_OP_READ_FAST,	SPINOR_OP_READ_FAST_4B },
 		{ SPINOR_OP_READ_1_1_2,	SPINOR_OP_READ_1_1_2_4B },
 		{ SPINOR_OP_READ_1_2_2,	SPINOR_OP_READ_1_2_2_4B },
 		{ SPINOR_OP_READ_1_1_4,	SPINOR_OP_READ_1_1_4_4B },
 		{ SPINOR_OP_READ_1_4_4,	SPINOR_OP_READ_1_4_4_4B },
 		{ SPINOR_OP_READ_1_1_1_DTR,	SPINOR_OP_READ_1_1_1_DTR_4B },
 		{ SPINOR_OP_READ_1_2_2_DTR,	SPINOR_OP_READ_1_2_2_DTR_4B },
 		{ SPINOR_OP_READ_1_4_4_DTR,	SPINOR_OP_READ_1_4_4_DTR_4B },
 	};
 	return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
 				      ARRAY_SIZE(spi_nor_3to4_read));
 }
 static u8 spi_nor_convert_3to4_program(u8 opcode)
 {
 	static const u8 spi_nor_3to4_program[][2] = {
 		{ SPINOR_OP_PP,		SPINOR_OP_PP_4B },
 		{ SPINOR_OP_PP_1_1_4,	SPINOR_OP_PP_1_1_4_4B },
 		{ SPINOR_OP_PP_1_4_4,	SPINOR_OP_PP_1_4_4_4B },
 	};
 	return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
 				      ARRAY_SIZE(spi_nor_3to4_program));
 }
 static u8 spi_nor_convert_3to4_erase(u8 opcode)
 {
 	static const u8 spi_nor_3to4_erase[][2] = {
 		{ SPINOR_OP_BE_4K,	SPINOR_OP_BE_4K_4B },
 		{ SPINOR_OP_BE_32K,	SPINOR_OP_BE_32K_4B },
 		{ SPINOR_OP_SE,		SPINOR_OP_SE_4B },
 	};
 	return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
 				      ARRAY_SIZE(spi_nor_3to4_erase));
 }
 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
 				      const struct flash_info *info)
 {
 	/* Do some manufacturer fixups first */
 	switch (JEDEC_MFR(info)) {
 	case SNOR_MFR_SPANSION:
 		/* No small sector erase for 4-byte command set */
 		nor->erase_opcode = SPINOR_OP_SE;
 		nor->mtd.erasesize = info->sector_size;
 		break;
 	default:
 		break;
 	}
 	nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
 	nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
 	nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
 }
 #endif /* !CONFIG_SPI_FLASH_BAR */
 /* Enable/disable 4-byte addressing mode. */
 static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
 		     int enable)
 {
 	int status;
 	bool need_wren = false;
 	u8 cmd;
 	switch (JEDEC_MFR(info)) {
 	case SNOR_MFR_ST:
 	case SNOR_MFR_MICRON:
 		/* Some Micron need WREN command; all will accept it */
 		need_wren = true;
 	case SNOR_MFR_MACRONIX:
 	case SNOR_MFR_WINBOND:
 		if (need_wren)
 			write_enable(nor);
 		cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
 		status = nor->write_reg(nor, cmd, NULL, 0);
 		if (need_wren)
 			write_disable(nor);
 		if (!status && !enable &&
 		    JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
 			/*
 			 * On Winbond W25Q256FV, leaving 4byte mode causes
 			 * the Extended Address Register to be set to 1, so all
 			 * 3-byte-address reads come from the second 16M.
 			 * We must clear the register to enable normal behavior.
 			 */
 			write_enable(nor);
 			nor->cmd_buf[0] = 0;
 			nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1);
 			write_disable(nor);
 		}
 		return status;
 	default:
 		/* Spansion style */
 		nor->cmd_buf[0] = enable << 7;
 		return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
 	}
 }
 static int spi_nor_sr_ready(struct spi_nor *nor)
 {
 	int sr = read_sr(nor);
 	if (sr < 0)
 		return sr;
 	if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) {
 		if (sr & SR_E_ERR)
 			dev_dbg(nor->dev, "Erase Error occurred\n");
 		else
 			dev_dbg(nor->dev, "Programming Error occurred\n");
 		nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
 		return -EIO;
 	}
 	return !(sr & SR_WIP);
 }
 static int spi_nor_fsr_ready(struct spi_nor *nor)
 {
 	int fsr = read_fsr(nor);
 	if (fsr < 0)
 		return fsr;
 	if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
 		if (fsr & FSR_E_ERR)
 			dev_dbg(nor->dev, "Erase operation failed.\n");
 		else
 			dev_dbg(nor->dev, "Program operation failed.\n");
 		if (fsr & FSR_PT_ERR)
 			dev_dbg(nor->dev,
 				"Attempted to modify a protected sector.\n");
 		nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
 		return -EIO;
 	}
 	return fsr & FSR_READY;
 }
 static int spi_nor_ready(struct spi_nor *nor)
 {
 	int sr, fsr;
 	sr = spi_nor_sr_ready(nor);
 	if (sr < 0)
 		return sr;
 	fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
 	if (fsr < 0)
 		return fsr;
 	return sr && fsr;
 }
 /*
  * Service routine to read status register until ready, or timeout occurs.
  * Returns non-zero if error.
  */
 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
 						unsigned long timeout)
 {
 	unsigned long timebase;
 	int ret;
 	timebase = get_timer(0);
 	while (get_timer(timebase) < timeout) {
 		ret = spi_nor_ready(nor);
 		if (ret < 0)
 			return ret;
 		if (ret)
 			return 0;
 	}
 	dev_err(nor->dev, "flash operation timed out\n");
 	return -ETIMEDOUT;
 }
 static int spi_nor_wait_till_ready(struct spi_nor *nor)
 {
 	return spi_nor_wait_till_ready_with_timeout(nor,
 						    DEFAULT_READY_WAIT_JIFFIES);
 }
 #ifdef CONFIG_SPI_FLASH_BAR
 /*
  * This "clean_bar" is necessary in a situation when one was accessing
  * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit.
  *
  * After it the BA24 bit shall be cleared to allow access to correct
  * memory region after SW reset (by calling "reset" command).
  *
  * Otherwise, the BA24 bit may be left set and then after reset, the
  * ROM would read/write/erase SPL from 16 MiB * bank_sel address.
  */
 static int clean_bar(struct spi_nor *nor)
 {
 	u8 cmd, bank_sel = 0;
 	if (nor->bank_curr == 0)
 		return 0;
 	cmd = nor->bank_write_cmd;
 	nor->bank_curr = 0;
 	write_enable(nor);
 	return nor->write_reg(nor, cmd, &bank_sel, 1);
 }
 static int write_bar(struct spi_nor *nor, u32 offset)
 {
 	u8 cmd, bank_sel;
 	int ret;
 	bank_sel = offset / SZ_16M;
 	if (bank_sel == nor->bank_curr)
 		goto bar_end;
 	cmd = nor->bank_write_cmd;
 	write_enable(nor);
 	ret = nor->write_reg(nor, cmd, &bank_sel, 1);
 	if (ret < 0) {
 		debug("SF: fail to write bank register\n");
 		return ret;
 	}
 bar_end:
 	nor->bank_curr = bank_sel;
 	return nor->bank_curr;
 }
 static int read_bar(struct spi_nor *nor, const struct flash_info *info)
 {
 	u8 curr_bank = 0;
 	int ret;
 	switch (JEDEC_MFR(info)) {
 	case SNOR_MFR_SPANSION:
 		nor->bank_read_cmd = SPINOR_OP_BRRD;
 		nor->bank_write_cmd = SPINOR_OP_BRWR;
 		break;
 	default:
 		nor->bank_read_cmd = SPINOR_OP_RDEAR;
 		nor->bank_write_cmd = SPINOR_OP_WREAR;
 	}
 	ret = nor->read_reg(nor, nor->bank_read_cmd,
 				    &curr_bank, 1);
 	if (ret) {
 		debug("SF: fail to read bank addr register\n");
 		return ret;
 	}
 	nor->bank_curr = curr_bank;
 	return 0;
 }
 #endif
 /*
  * Initiate the erasure of a single sector
  */
 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)
 {
 	u8 buf[SPI_NOR_MAX_ADDR_WIDTH];
 	int i;
 	if (nor->erase)
 		return nor->erase(nor, addr);
 	/*
 	 * Default implementation, if driver doesn't have a specialized HW
 	 * control
 	 */
 	for (i = nor->addr_width - 1; i >= 0; i--) {
 		buf[i] = addr & 0xff;
 		addr >>= 8;
 	}
 	return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width);
 }
 /*
  * Erase an address range on the nor chip.  The address range may extend
  * one or more erase sectors.  Return an error is there is a problem erasing.
  */
 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
 {
 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
 	u32 addr, len, rem;
 	int ret;
 	dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
 		(long long)instr->len);
 	div_u64_rem(instr->len, mtd->erasesize, &rem);
 	if (rem)
 		return -EINVAL;
 	addr = instr->addr;
 	len = instr->len;
 	while (len) {
 #ifdef CONFIG_SPI_FLASH_BAR
 		ret = write_bar(nor, addr);
 		if (ret < 0)
 			return ret;
 #endif
 		write_enable(nor);
 		ret = spi_nor_erase_sector(nor, addr);
 		if (ret)
 			goto erase_err;
 		addr += mtd->erasesize;
 		len -= mtd->erasesize;
 		ret = spi_nor_wait_till_ready(nor);
 		if (ret)
 			goto erase_err;
 	}
 erase_err:
 #ifdef CONFIG_SPI_FLASH_BAR
 	ret = clean_bar(nor);
 #endif
 	write_disable(nor);
 	return ret;
 }
 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
 /* Write status register and ensure bits in mask match written values */
 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
 {
 	int ret;
 	write_enable(nor);
 	ret = write_sr(nor, status_new);
 	if (ret)
 		return ret;
 	ret = spi_nor_wait_till_ready(nor);
 	if (ret)
 		return ret;
 	ret = read_sr(nor);
 	if (ret < 0)
 		return ret;
 	return ((ret & mask) != (status_new & mask)) ? -EIO : 0;
 }
 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
 				 uint64_t *len)
 {
 	struct mtd_info *mtd = &nor->mtd;
 	u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
 	int shift = ffs(mask) - 1;
 	int pow;
 	if (!(sr & mask)) {
 		/* No protection */
 		*ofs = 0;
 		*len = 0;
 	} else {
 		pow = ((sr & mask) ^ mask) >> shift;
 		*len = mtd->size >> pow;
 		if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB)
 			*ofs = 0;
 		else
 			*ofs = mtd->size - *len;
 	}
 }
 /*
  * Return 1 if the entire region is locked (if @locked is true) or unlocked (if
  * @locked is false); 0 otherwise
  */
 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len,
 				    u8 sr, bool locked)
 {
 	loff_t lock_offs;
 	uint64_t lock_len;
 	if (!len)
 		return 1;
 	stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
 	if (locked)
 		/* Requested range is a sub-range of locked range */
 		return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
 	else
 		/* Requested range does not overlap with locked range */
 		return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs);
 }
 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
 			    u8 sr)
 {
 	return stm_check_lock_status_sr(nor, ofs, len, sr, true);
 }
 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
 			      u8 sr)
 {
 	return stm_check_lock_status_sr(nor, ofs, len, sr, false);
 }
 /*
  * Lock a region of the flash. Compatible with ST Micro and similar flash.
  * Supports the block protection bits BP{0,1,2} in the status register
  * (SR). Does not support these features found in newer SR bitfields:
  *   - SEC: sector/block protect - only handle SEC=0 (block protect)
  *   - CMP: complement protect - only support CMP=0 (range is not complemented)
  *
  * Support for the following is provided conditionally for some flash:
  *   - TB: top/bottom protect
  *
  * Sample table portion for 8MB flash (Winbond w25q64fw):
  *
  *   SEC  |  TB   |  BP2  |  BP1  |  BP0  |  Prot Length  | Protected Portion
  *  --------------------------------------------------------------------------
  *    X   |   X   |   0   |   0   |   0   |  NONE         | NONE
  *    0   |   0   |   0   |   0   |   1   |  128 KB       | Upper 1/64
  *    0   |   0   |   0   |   1   |   0   |  256 KB       | Upper 1/32
  *    0   |   0   |   0   |   1   |   1   |  512 KB       | Upper 1/16
  *    0   |   0   |   1   |   0   |   0   |  1 MB         | Upper 1/8
  *    0   |   0   |   1   |   0   |   1   |  2 MB         | Upper 1/4
  *    0   |   0   |   1   |   1   |   0   |  4 MB         | Upper 1/2
  *    X   |   X   |   1   |   1   |   1   |  8 MB         | ALL
  *  ------|-------|-------|-------|-------|---------------|-------------------
  *    0   |   1   |   0   |   0   |   1   |  128 KB       | Lower 1/64
  *    0   |   1   |   0   |   1   |   0   |  256 KB       | Lower 1/32
  *    0   |   1   |   0   |   1   |   1   |  512 KB       | Lower 1/16
  *    0   |   1   |   1   |   0   |   0   |  1 MB         | Lower 1/8
  *    0   |   1   |   1   |   0   |   1   |  2 MB         | Lower 1/4
  *    0   |   1   |   1   |   1   |   0   |  4 MB         | Lower 1/2
  *
  * Returns negative on errors, 0 on success.
  */
 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
 {
 	struct mtd_info *mtd = &nor->mtd;
 	int status_old, status_new;
 	u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
 	u8 shift = ffs(mask) - 1, pow, val;
 	loff_t lock_len;
 	bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
 	bool use_top;
 	status_old = read_sr(nor);
 	if (status_old < 0)
 		return status_old;
 	/* If nothing in our range is unlocked, we don't need to do anything */
 	if (stm_is_locked_sr(nor, ofs, len, status_old))
 		return 0;
 	/* If anything below us is unlocked, we can't use 'bottom' protection */
 	if (!stm_is_locked_sr(nor, 0, ofs, status_old))
 		can_be_bottom = false;
 	/* If anything above us is unlocked, we can't use 'top' protection */
 	if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len),
 			      status_old))
 		can_be_top = false;
 	if (!can_be_bottom && !can_be_top)
 		return -EINVAL;
 	/* Prefer top, if both are valid */
 	use_top = can_be_top;
 	/* lock_len: length of region that should end up locked */
 	if (use_top)
 		lock_len = mtd->size - ofs;
 	else
 		lock_len = ofs + len;
 	/*
 	 * Need smallest pow such that:
 	 *
 	 *   1 / (2^pow) <= (len / size)
 	 *
 	 * so (assuming power-of-2 size) we do:
 	 *
 	 *   pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
 	 */
 	pow = ilog2(mtd->size) - ilog2(lock_len);
 	val = mask - (pow << shift);
 	if (val & ~mask)
 		return -EINVAL;
 	/* Don't "lock" with no region! */
 	if (!(val & mask))
 		return -EINVAL;
 	status_new = (status_old & ~mask & ~SR_TB) | val;
 	/* Disallow further writes if WP pin is asserted */
 	status_new |= SR_SRWD;
 	if (!use_top)
 		status_new |= SR_TB;
 	/* Don't bother if they're the same */
 	if (status_new == status_old)
 		return 0;
 	/* Only modify protection if it will not unlock other areas */
 	if ((status_new & mask) < (status_old & mask))
 		return -EINVAL;
 	return write_sr_and_check(nor, status_new, mask);
 }
 /*
  * Unlock a region of the flash. See stm_lock() for more info
  *
  * Returns negative on errors, 0 on success.
  */
 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
 {
 	struct mtd_info *mtd = &nor->mtd;
 	int status_old, status_new;
 	u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
 	u8 shift = ffs(mask) - 1, pow, val;
 	loff_t lock_len;
 	bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
 	bool use_top;
 	status_old = read_sr(nor);
 	if (status_old < 0)
 		return status_old;
 	/* If nothing in our range is locked, we don't need to do anything */
 	if (stm_is_unlocked_sr(nor, ofs, len, status_old))
 		return 0;
 	/* If anything below us is locked, we can't use 'top' protection */
 	if (!stm_is_unlocked_sr(nor, 0, ofs, status_old))
 		can_be_top = false;
 	/* If anything above us is locked, we can't use 'bottom' protection */
 	if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len),
 				status_old))
 		can_be_bottom = false;
 	if (!can_be_bottom && !can_be_top)
 		return -EINVAL;
 	/* Prefer top, if both are valid */
 	use_top = can_be_top;
 	/* lock_len: length of region that should remain locked */
 	if (use_top)
 		lock_len = mtd->size - (ofs + len);
 	else
 		lock_len = ofs;
 	/*
 	 * Need largest pow such that:
 	 *
 	 *   1 / (2^pow) >= (len / size)
 	 *
 	 * so (assuming power-of-2 size) we do:
 	 *
 	 *   pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
 	 */
 	pow = ilog2(mtd->size) - order_base_2(lock_len);
 	if (lock_len == 0) {
 		val = 0; /* fully unlocked */
 	} else {
 		val = mask - (pow << shift);
 		/* Some power-of-two sizes are not supported */
 		if (val & ~mask)
 			return -EINVAL;
 	}
 	status_new = (status_old & ~mask & ~SR_TB) | val;
 	/* Don't protect status register if we're fully unlocked */
 	if (lock_len == 0)
 		status_new &= ~SR_SRWD;
 	if (!use_top)
 		status_new |= SR_TB;
 	/* Don't bother if they're the same */
 	if (status_new == status_old)
 		return 0;
 	/* Only modify protection if it will not lock other areas */
 	if ((status_new & mask) > (status_old & mask))
 		return -EINVAL;
 	return write_sr_and_check(nor, status_new, mask);
 }
 /*
  * Check if a region of the flash is (completely) locked. See stm_lock() for
  * more info.
  *
  * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
  * negative on errors.
  */
 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
 {
 	int status;
 	status = read_sr(nor);
 	if (status < 0)
 		return status;
 	return stm_is_locked_sr(nor, ofs, len, status);
 }
 #endif /* CONFIG_SPI_FLASH_STMICRO */
 /* Used when the "_ext_id" is two bytes at most */
 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)	\
 		.id = {							\
 			((_jedec_id) >> 16) & 0xff,			\
 			((_jedec_id) >> 8) & 0xff,			\
 			(_jedec_id) & 0xff,				\
 			((_ext_id) >> 8) & 0xff,			\
 			(_ext_id) & 0xff,				\
 			},						\
 		.id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),	\
 		.sector_size = (_sector_size),				\
 		.n_sectors = (_n_sectors),				\
 		.page_size = 256,					\
 		.flags = (_flags),
 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)	\
 		.id = {							\
 			((_jedec_id) >> 16) & 0xff,			\
 			((_jedec_id) >> 8) & 0xff,			\
 			(_jedec_id) & 0xff,				\
 			((_ext_id) >> 16) & 0xff,			\
 			((_ext_id) >> 8) & 0xff,			\
 			(_ext_id) & 0xff,				\
 			},						\
 		.id_len = 6,						\
 		.sector_size = (_sector_size),				\
 		.n_sectors = (_n_sectors),				\
 		.page_size = 256,					\
 		.flags = (_flags),
 /* NOTE: double check command sets and memory organization when you add
  * more nor chips.  This current list focusses on newer chips, which
  * have been converging on command sets which including JEDEC ID.
  *
  * All newly added entries should describe *hardware* and should use SECT_4K
  * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
  * scenarios excluding small sectors there is config option that can be
  * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
  * For historical (and compatibility) reasons (before we got above config) some
  * old entries may be missing 4K flag.
  */
 const struct flash_info spi_nor_ids[] = {
 #ifdef CONFIG_SPI_FLASH_ATMEL		/* ATMEL */
 	/* Atmel -- some are (confusingly) marketed as "DataFlash" */
 	{ "at26df321",  INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
 	{ "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
 	{ "at45db011d",	INFO(0x1f2200, 0, 64 * 1024,   4, SECT_4K) },
 	{ "at45db021d",	INFO(0x1f2300, 0, 64 * 1024,   8, SECT_4K) },
 	{ "at45db041d",	INFO(0x1f2400, 0, 64 * 1024,   8, SECT_4K) },
 	{ "at45db081d", INFO(0x1f2500, 0, 64 * 1024,  16, SECT_4K) },
 	{ "at45db161d",	INFO(0x1f2600, 0, 64 * 1024,  32, SECT_4K) },
 	{ "at45db321d",	INFO(0x1f2700, 0, 64 * 1024,  64, SECT_4K) },
 	{ "at45db641d",	INFO(0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
 	{ "at26df081a", INFO(0x1f4501, 0, 64 * 1024,  16, SECT_4K) },
 #endif
 #ifdef CONFIG_SPI_FLASH_EON		/* EON */
 	/* EON -- en25xxx */
 	{ "en25q32b",   INFO(0x1c3016, 0, 64 * 1024,   64, 0) },
 	{ "en25q64",    INFO(0x1c3017, 0, 64 * 1024,  128, SECT_4K) },
 	{ "en25qh128",  INFO(0x1c7018, 0, 64 * 1024,  256, 0) },
 	{ "en25s64",	INFO(0x1c3817, 0, 64 * 1024,  128, SECT_4K) },
 #endif
 #ifdef CONFIG_SPI_FLASH_GIGADEVICE	/* GIGADEVICE */
 	/* GigaDevice */
 	{
 		"gd25q16", INFO(0xc84015, 0, 64 * 1024,  32,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
 	{
 		"gd25q32", INFO(0xc84016, 0, 64 * 1024,  64,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
 	{
 		"gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
 	{
 		"gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
 #endif
 #ifdef CONFIG_SPI_FLASH_ISSI		/* ISSI */
 	/* ISSI */
 	{ "is25lq040b", INFO(0x9d4013, 0, 64 * 1024,   8,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "is25lp032",	INFO(0x9d6016, 0, 64 * 1024,  64, 0) },
 	{ "is25lp064",	INFO(0x9d6017, 0, 64 * 1024, 128, 0) },
 	{ "is25lp128",  INFO(0x9d6018, 0, 64 * 1024, 256,
 			SECT_4K | SPI_NOR_DUAL_READ) },
 	{ "is25lp256",  INFO(0x9d6019, 0, 64 * 1024, 512,
 			SECT_4K | SPI_NOR_DUAL_READ) },
 	{ "is25wp032",  INFO(0x9d7016, 0, 64 * 1024,  64,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "is25wp064",  INFO(0x9d7017, 0, 64 * 1024, 128,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "is25wp128",  INFO(0x9d7018, 0, 64 * 1024, 256,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 #endif
 #ifdef CONFIG_SPI_FLASH_MACRONIX	/* MACRONIX */
 	/* Macronix */
 	{ "mx25l2005a",  INFO(0xc22012, 0, 64 * 1024,   4, SECT_4K) },
 	{ "mx25l4005a",  INFO(0xc22013, 0, 64 * 1024,   8, SECT_4K) },
 	{ "mx25l8005",   INFO(0xc22014, 0, 64 * 1024,  16, 0) },
 	{ "mx25l1606e",  INFO(0xc22015, 0, 64 * 1024,  32, SECT_4K) },
 	{ "mx25l3205d",  INFO(0xc22016, 0, 64 * 1024,  64, SECT_4K) },
 	{ "mx25l6405d",  INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
 	{ "mx25u2033e",  INFO(0xc22532, 0, 64 * 1024,   4, SECT_4K) },
 	{ "mx25u1635e",  INFO(0xc22535, 0, 64 * 1024,  32, SECT_4K) },
 	{ "mx25u6435f",  INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
 	{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
 	{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
 	{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
 	{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
 	{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "mx25l1633e",	 INFO(0xc22415, 0, 64 * 1024,   32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
 #endif
 #ifdef CONFIG_SPI_FLASH_STMICRO		/* STMICRO */
 	/* Micron */
 	{ "n25q016a",	 INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ "n25q032",	 INFO(0x20ba16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
 	{ "n25q032a",	 INFO(0x20bb16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
 	{ "n25q064",     INFO(0x20ba17, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ "n25q064a",    INFO(0x20bb17, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "n25q256ax1",  INFO(0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
 	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
 	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ "mt25qu02g",   INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 #endif
 #ifdef CONFIG_SPI_FLASH_SPANSION	/* SPANSION */
 	/* Spansion/Cypress -- single (large) sector size only, at least
 	 * for the chips listed here (without boot sectors).
 	 */
 	{ "s25sl032p",  INFO(0x010215, 0x4d00,  64 * 1024,  64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "s25sl064p",  INFO(0x010216, 0x4d00,  64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },
 	{ "s25fl256s1", INFO(0x010219, 0x4d01,  64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
 	{ "s25fl512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
 	{ "s25fl512s_256k",  INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
 	{ "s25fl512s_64k",  INFO(0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
 	{ "s25fl512s_512k",  INFO(0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
 	{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024,  64, 0) },
 	{ "s25sl12801", INFO(0x012018, 0x0301,  64 * 1024, 256, 0) },
 	{ "s25fl128s",  INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
 	{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024,  64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
 	{ "s25fl129p1", INFO(0x012018, 0x4d01,  64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
 	{ "s25sl008a",  INFO(0x010213,      0,  64 * 1024,  16, 0) },
 	{ "s25sl016a",  INFO(0x010214,      0,  64 * 1024,  32, 0) },
 	{ "s25sl032a",  INFO(0x010215,      0,  64 * 1024,  64, 0) },
 	{ "s25sl064a",  INFO(0x010216,      0,  64 * 1024, 128, 0) },
 	{ "s25fl116k",  INFO(0x014015,      0,  64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "s25fl164k",  INFO(0x014017,      0,  64 * 1024, 128, SECT_4K) },
 	{ "s25fl208k",  INFO(0x014014,      0,  64 * 1024,  16, SECT_4K | SPI_NOR_DUAL_READ) },
 	{ "s25fl128l",  INFO(0x016018,      0,  64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 #endif
 #ifdef CONFIG_SPI_FLASH_SST		/* SST */
 	/* SST -- large erase sizes are "overlays", "sectors" are 4K */
 	{ "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024,  8, SECT_4K | SST_WRITE) },
 	{ "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
 	{ "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
 	{ "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
 	{ "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
 	{ "sst25wf512",  INFO(0xbf2501, 0, 64 * 1024,  1, SECT_4K | SST_WRITE) },
 	{ "sst25wf010",  INFO(0xbf2502, 0, 64 * 1024,  2, SECT_4K | SST_WRITE) },
 	{ "sst25wf020",  INFO(0xbf2503, 0, 64 * 1024,  4, SECT_4K | SST_WRITE) },
 	{ "sst25wf020a", INFO(0x621612, 0, 64 * 1024,  4, SECT_4K) },
 	{ "sst25wf040b", INFO(0x621613, 0, 64 * 1024,  8, SECT_4K) },
 	{ "sst25wf040",  INFO(0xbf2504, 0, 64 * 1024,  8, SECT_4K | SST_WRITE) },
 	{ "sst25wf080",  INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
 	{ "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "sst26wf016",  INFO(0xbf2651, 0, 64 * 1024,  32, SECT_4K) },
 	{ "sst26wf032",	 INFO(0xbf2622, 0, 64 * 1024,  64, SECT_4K) },
 	{ "sst26wf064",	 INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K) },
 #endif
 #ifdef CONFIG_SPI_FLASH_STMICRO		/* STMICRO */
 	/* ST Microelectronics -- newer production may have feature updates */
 	{ "m25p10",  INFO(0x202011,  0,  32 * 1024,   4, 0) },
 	{ "m25p20",  INFO(0x202012,  0,  64 * 1024,   4, 0) },
 	{ "m25p40",  INFO(0x202013,  0,  64 * 1024,   8, 0) },
 	{ "m25p80",  INFO(0x202014,  0,  64 * 1024,  16, 0) },
 	{ "m25p16",  INFO(0x202015,  0,  64 * 1024,  32, 0) },
 	{ "m25p32",  INFO(0x202016,  0,  64 * 1024,  64, 0) },
 	{ "m25p64",  INFO(0x202017,  0,  64 * 1024, 128, 0) },
 	{ "m25p128", INFO(0x202018,  0, 256 * 1024,  64, 0) },
 	{ "m25pe16", INFO(0x208015,  0, 64 * 1024, 32, SECT_4K) },
 	{ "m25px16",    INFO(0x207115,  0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "m25px64",    INFO(0x207117,  0, 64 * 1024, 128, 0) },
 #endif
 #ifdef CONFIG_SPI_FLASH_WINBOND		/* WINBOND */
 	/* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
 	{ "w25x05", INFO(0xef3010, 0, 64 * 1024,  1,  SECT_4K) },
 	{ "w25x10", INFO(0xef3011, 0, 64 * 1024,  2,  SECT_4K) },
 	{ "w25x20", INFO(0xef3012, 0, 64 * 1024,  4,  SECT_4K) },
 	{ "w25x40", INFO(0xef3013, 0, 64 * 1024,  8,  SECT_4K) },
 	{ "w25x80", INFO(0xef3014, 0, 64 * 1024,  16, SECT_4K) },
 	{ "w25x16", INFO(0xef3015, 0, 64 * 1024,  32, SECT_4K) },
 	{
 		"w25q16dw", INFO(0xef6015, 0, 64 * 1024,  32,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
 	{ "w25x32", INFO(0xef3016, 0, 64 * 1024,  64, SECT_4K) },
 	{ "w25q20cl", INFO(0xef4012, 0, 64 * 1024,  4, SECT_4K) },
 	{ "w25q20bw", INFO(0xef5012, 0, 64 * 1024,  4, SECT_4K) },
 	{ "w25q20ew", INFO(0xef6012, 0, 64 * 1024,  4, SECT_4K) },
 	{ "w25q32", INFO(0xef4016, 0, 64 * 1024,  64, SECT_4K) },
 	{
 		"w25q32dw", INFO(0xef6016, 0, 64 * 1024,  64,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
 	{
 		"w25q32jv", INFO(0xef7016, 0, 64 * 1024,  64,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
 	{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
 	{ "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
 	{
 		"w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
 	{
 		"w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
 	{ "w25q80", INFO(0xef5014, 0, 64 * 1024,  16, SECT_4K) },
 	{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024,  16, SECT_4K) },
 	{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
 	{ "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
 			SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },
 #endif
 #ifdef CONFIG_SPI_FLASH_XMC
 	/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
 	{ "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 #endif
 	{ },
 };
 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
 {
 	int			tmp;
 	u8			id[SPI_NOR_MAX_ID_LEN];
 	const struct flash_info	*info;
 	if (!ARRAY_SIZE(spi_nor_ids))
 		return ERR_PTR(-ENODEV);
 	tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
 	if (tmp < 0) {
 		dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
 		return ERR_PTR(tmp);
 	}
 	for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
 		info = &spi_nor_ids[tmp];
 		if (info->id_len) {
 			if (!memcmp(info->id, id, info->id_len))
 				return &spi_nor_ids[tmp];
 		}
 	}
 	dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
 		id[0], id[1], id[2]);
 	return ERR_PTR(-ENODEV);
 }
 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
 			size_t *retlen, u_char *buf)
 {
 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
 	int ret;
 	dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
 	while (len) {
 		loff_t addr = from;
 		size_t read_len = len;
 #ifdef CONFIG_SPI_FLASH_BAR
 		u32 remain_len;
 		ret = write_bar(nor, addr);
 		if (ret < 0)
 			return log_ret(ret);
 		remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr;
 		if (len < remain_len)
 			read_len = len;
 		else
 			read_len = remain_len;
 #endif
 		ret = nor->read(nor, addr, read_len, buf);
 		if (ret == 0) {
 			/* We shouldn't see 0-length reads */
 			ret = -EIO;
 			goto read_err;
 		}
 		if (ret < 0)
 			goto read_err;
 		*retlen += ret;
 		buf += ret;
 		from += ret;
 		len -= ret;
 	}
 	ret = 0;
 read_err:
 #ifdef CONFIG_SPI_FLASH_BAR
 	ret = clean_bar(nor);
 #endif
 	return ret;
 }
 #ifdef CONFIG_SPI_FLASH_SST
 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len,
 				 size_t *retlen, const u_char *buf)
 {
 	size_t actual;
 	int ret = 0;
 	for (actual = 0; actual < len; actual++) {
 		nor->program_opcode = SPINOR_OP_BP;
 		write_enable(nor);
 		/* write one byte. */
 		ret = nor->write(nor, to, 1, buf + actual);
 		if (ret < 0)
 			goto sst_write_err;
 		ret = spi_nor_wait_till_ready(nor);
 		if (ret)
 			goto sst_write_err;
 		to++;
 	}
 sst_write_err:
 	write_disable(nor);
 	return ret;
 }
 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
 		     size_t *retlen, const u_char *buf)
 {
 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
 	struct spi_slave *spi = nor->spi;
 	size_t actual;
 	int ret;
 	dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
 	if (spi->mode & SPI_TX_BYTE)
 		return sst_write_byteprogram(nor, to, len, retlen, buf);
 	write_enable(nor);
 	nor->sst_write_second = false;
 	actual = to % 2;
 	/* Start write from odd address. */
 	if (actual) {
 		nor->program_opcode = SPINOR_OP_BP;
 		/* write one byte. */
 		ret = nor->write(nor, to, 1, buf);
 		if (ret < 0)
 			goto sst_write_err;
 		ret = spi_nor_wait_till_ready(nor);
 		if (ret)
 			goto sst_write_err;
 	}
 	to += actual;
 	/* Write out most of the data here. */
 	for (; actual < len - 1; actual += 2) {
 		nor->program_opcode = SPINOR_OP_AAI_WP;
 		/* write two bytes. */
 		ret = nor->write(nor, to, 2, buf + actual);
 		if (ret < 0)
 			goto sst_write_err;
 		ret = spi_nor_wait_till_ready(nor);
 		if (ret)
 			goto sst_write_err;
 		to += 2;
 		nor->sst_write_second = true;
 	}
 	nor->sst_write_second = false;
 	write_disable(nor);
 	ret = spi_nor_wait_till_ready(nor);
 	if (ret)
 		goto sst_write_err;
 	/* Write out trailing byte if it exists. */
 	if (actual != len) {
 		write_enable(nor);
 		nor->program_opcode = SPINOR_OP_BP;
 		ret = nor->write(nor, to, 1, buf + actual);
 		if (ret < 0)
 			goto sst_write_err;
 		ret = spi_nor_wait_till_ready(nor);
 		if (ret)
 			goto sst_write_err;
 		write_disable(nor);
 		actual += 1;
 	}
 sst_write_err:
 	*retlen += actual;
 	return ret;
 }
 #endif
 /*
  * Write an address range to the nor chip.  Data must be written in
  * FLASH_PAGESIZE chunks.  The address range may be any size provided
  * it is within the physical boundaries.
  */
 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
 	size_t *retlen, const u_char *buf)
 {
 	struct spi_nor *nor = mtd_to_spi_nor(mtd);
 	size_t page_offset, page_remain, i;
 	ssize_t ret;
 	dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
 	for (i = 0; i < len; ) {
 		ssize_t written;
 		loff_t addr = to + i;
 		/*
 		 * If page_size is a power of two, the offset can be quickly
 		 * calculated with an AND operation. On the other cases we
 		 * need to do a modulus operation (more expensive).
 		 * Power of two numbers have only one bit set and we can use
 		 * the instruction hweight32 to detect if we need to do a
 		 * modulus (do_div()) or not.
 		 */
 		if (hweight32(nor->page_size) == 1) {
 			page_offset = addr & (nor->page_size - 1);
 		} else {
 			u64 aux = addr;
 			page_offset = do_div(aux, nor->page_size);
 		}
 		/* the size of data remaining on the first page */
 		page_remain = min_t(size_t,
 				    nor->page_size - page_offset, len - i);
 #ifdef CONFIG_SPI_FLASH_BAR
 		ret = write_bar(nor, addr);
 		if (ret < 0)
 			return ret;
 #endif
 		write_enable(nor);
 		ret = nor->write(nor, addr, page_remain, buf + i);
 		if (ret < 0)
 			goto write_err;
 		written = ret;
 		ret = spi_nor_wait_till_ready(nor);
 		if (ret)
 			goto write_err;
 		*retlen += written;
 		i += written;
 		if (written != page_remain) {
 			ret = -EIO;
 			goto write_err;
 		}
 	}
 write_err:
 #ifdef CONFIG_SPI_FLASH_BAR
 	ret = clean_bar(nor);
 #endif
 	return ret;
 }
 #ifdef CONFIG_SPI_FLASH_MACRONIX
 /**
  * macronix_quad_enable() - set QE bit in Status Register.
  * @nor:	pointer to a 'struct spi_nor'
  *
  * Set the Quad Enable (QE) bit in the Status Register.
  *
  * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories.
  *
  * Return: 0 on success, -errno otherwise.
  */
 static int macronix_quad_enable(struct spi_nor *nor)
 {
 	int ret, val;
 	val = read_sr(nor);
 	if (val < 0)
 		return val;
 	if (val & SR_QUAD_EN_MX)
 		return 0;
 	write_enable(nor);
 	write_sr(nor, val | SR_QUAD_EN_MX);
 	ret = spi_nor_wait_till_ready(nor);
 	if (ret)
 		return ret;
 	ret = read_sr(nor);
 	if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
 		dev_err(nor->dev, "Macronix Quad bit not set\n");
 		return -EINVAL;
 	}
 	return 0;
 }
 #endif
 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
 /*
  * Write status Register and configuration register with 2 bytes
  * The first byte will be written to the status register, while the
  * second byte will be written to the configuration register.
  * Return negative if error occurred.
  */
 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
 {
 	int ret;
 	write_enable(nor);
 	ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
 	if (ret < 0) {
 		dev_dbg(nor->dev,
 			"error while writing configuration register\n");
 		return -EINVAL;
 	}
 	ret = spi_nor_wait_till_ready(nor);
 	if (ret) {
 		dev_dbg(nor->dev,
 			"timeout while writing configuration register\n");
 		return ret;
 	}
 	return 0;
 }
 /**
  * spansion_read_cr_quad_enable() - set QE bit in Configuration Register.
  * @nor:	pointer to a 'struct spi_nor'
  *
  * Set the Quad Enable (QE) bit in the Configuration Register.
  * This function should be used with QSPI memories supporting the Read
  * Configuration Register (35h) instruction.
  *
  * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
  * memories.
  *
  * Return: 0 on success, -errno otherwise.
  */
 static int spansion_read_cr_quad_enable(struct spi_nor *nor)
 {
 	u8 sr_cr[2];
 	int ret;
 	/* Check current Quad Enable bit value. */
 	ret = read_cr(nor);
 	if (ret < 0) {
 		dev_dbg(dev, "error while reading configuration register\n");
 		return -EINVAL;
 	}
 	if (ret & CR_QUAD_EN_SPAN)
 		return 0;
 	sr_cr[1] = ret | CR_QUAD_EN_SPAN;
 	/* Keep the current value of the Status Register. */
 	ret = read_sr(nor);
 	if (ret < 0) {
 		dev_dbg(dev, "error while reading status register\n");
 		return -EINVAL;
 	}
 	sr_cr[0] = ret;
 	ret = write_sr_cr(nor, sr_cr);
 	if (ret)
 		return ret;
 	/* Read back and check it. */
 	ret = read_cr(nor);
 	if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
 		dev_dbg(nor->dev, "Spansion Quad bit not set\n");
 		return -EINVAL;
 	}
 	return 0;
 }
 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
 /**
  * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
  * @nor:	pointer to a 'struct spi_nor'
  *
  * Set the Quad Enable (QE) bit in the Configuration Register.
  * This function should be used with QSPI memories not supporting the Read
  * Configuration Register (35h) instruction.
  *
  * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI
  * memories.
  *
  * Return: 0 on success, -errno otherwise.
  */
 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
 {
 	u8 sr_cr[2];
 	int ret;
 	/* Keep the current value of the Status Register. */
 	ret = read_sr(nor);
 	if (ret < 0) {
 		dev_dbg(nor->dev, "error while reading status register\n");
 		return -EINVAL;
 	}
 	sr_cr[0] = ret;
 	sr_cr[1] = CR_QUAD_EN_SPAN;
 	return write_sr_cr(nor, sr_cr);
 }
 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
 #endif /* CONFIG_SPI_FLASH_SPANSION */
 struct spi_nor_read_command {
 	u8			num_mode_clocks;
 	u8			num_wait_states;
 	u8			opcode;
 	enum spi_nor_protocol	proto;
 };
 struct spi_nor_pp_command {
 	u8			opcode;
 	enum spi_nor_protocol	proto;
 };
 enum spi_nor_read_command_index {
 	SNOR_CMD_READ,
 	SNOR_CMD_READ_FAST,
 	SNOR_CMD_READ_1_1_1_DTR,
 	/* Dual SPI */
 	SNOR_CMD_READ_1_1_2,
 	SNOR_CMD_READ_1_2_2,
 	SNOR_CMD_READ_2_2_2,
 	SNOR_CMD_READ_1_2_2_DTR,
 	/* Quad SPI */
 	SNOR_CMD_READ_1_1_4,
 	SNOR_CMD_READ_1_4_4,
 	SNOR_CMD_READ_4_4_4,
 	SNOR_CMD_READ_1_4_4_DTR,
 	/* Octo SPI */
 	SNOR_CMD_READ_1_1_8,
 	SNOR_CMD_READ_1_8_8,
 	SNOR_CMD_READ_8_8_8,
 	SNOR_CMD_READ_1_8_8_DTR,
 	SNOR_CMD_READ_MAX
 };
 enum spi_nor_pp_command_index {
 	SNOR_CMD_PP,
 	/* Quad SPI */
 	SNOR_CMD_PP_1_1_4,
 	SNOR_CMD_PP_1_4_4,
 	SNOR_CMD_PP_4_4_4,
 	/* Octo SPI */
 	SNOR_CMD_PP_1_1_8,
 	SNOR_CMD_PP_1_8_8,
 	SNOR_CMD_PP_8_8_8,
 	SNOR_CMD_PP_MAX
 };
 struct spi_nor_flash_parameter {
 	u64				size;
 	u32				page_size;
 	struct spi_nor_hwcaps		hwcaps;
 	struct spi_nor_read_command	reads[SNOR_CMD_READ_MAX];
 	struct spi_nor_pp_command	page_programs[SNOR_CMD_PP_MAX];
 	int (*quad_enable)(struct spi_nor *nor);
 };
 static void
 spi_nor_set_read_settings(struct spi_nor_read_command *read,
 			  u8 num_mode_clocks,
 			  u8 num_wait_states,
 			  u8 opcode,
 			  enum spi_nor_protocol proto)
 {
 	read->num_mode_clocks = num_mode_clocks;
 	read->num_wait_states = num_wait_states;
 	read->opcode = opcode;
 	read->proto = proto;
 }
 static void
 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp,
 			u8 opcode,
 			enum spi_nor_protocol proto)
 {
 	pp->opcode = opcode;
 	pp->proto = proto;
 }
 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT)
 /*
  * Serial Flash Discoverable Parameters (SFDP) parsing.
  */
 /**
  * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters.
  * @nor:	pointer to a 'struct spi_nor'
  * @addr:	offset in the SFDP area to start reading data from
  * @len:	number of bytes to read
  * @buf:	buffer where the SFDP data are copied into (dma-safe memory)
  *
  * Whatever the actual numbers of bytes for address and dummy cycles are
  * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always
  * followed by a 3-byte address and 8 dummy clock cycles.
  *
  * Return: 0 on success, -errno otherwise.
  */
 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr,
 			     size_t len, void *buf)
 {
 	u8 addr_width, read_opcode, read_dummy;
 	int ret;
 	read_opcode = nor->read_opcode;
 	addr_width = nor->addr_width;
 	read_dummy = nor->read_dummy;
 	nor->read_opcode = SPINOR_OP_RDSFDP;
 	nor->addr_width = 3;
 	nor->read_dummy = 8;
 	while (len) {
 		ret = nor->read(nor, addr, len, (u8 *)buf);
 		if (!ret || ret > len) {
 			ret = -EIO;
 			goto read_err;
 		}
 		if (ret < 0)
 			goto read_err;
 		buf += ret;
 		addr += ret;
 		len -= ret;
 	}
 	ret = 0;
 read_err:
 	nor->read_opcode = read_opcode;
 	nor->addr_width = addr_width;
 	nor->read_dummy = read_dummy;
 	return ret;
 }
 struct sfdp_parameter_header {
 	u8		id_lsb;
 	u8		minor;
 	u8		major;
 	u8		length; /* in double words */
 	u8		parameter_table_pointer[3]; /* byte address */
 	u8		id_msb;
 };
 #define SFDP_PARAM_HEADER_ID(p)	(((p)->id_msb << 8) | (p)->id_lsb)
 #define SFDP_PARAM_HEADER_PTP(p) \
 	(((p)->parameter_table_pointer[2] << 16) | \
 	 ((p)->parameter_table_pointer[1] <<  8) | \
 	 ((p)->parameter_table_pointer[0] <<  0))
 #define SFDP_BFPT_ID		0xff00	/* Basic Flash Parameter Table */
 #define SFDP_SECTOR_MAP_ID	0xff81	/* Sector Map Table */
 #define SFDP_SIGNATURE		0x50444653U
 #define SFDP_JESD216_MAJOR	1
 #define SFDP_JESD216_MINOR	0
 #define SFDP_JESD216A_MINOR	5
 #define SFDP_JESD216B_MINOR	6
 struct sfdp_header {
 	u32		signature; /* Ox50444653U <=> "SFDP" */
 	u8		minor;
 	u8		major;
 	u8		nph; /* 0-base number of parameter headers */
 	u8		unused;
 	/* Basic Flash Parameter Table. */
 	struct sfdp_parameter_header	bfpt_header;
 };
 /* Basic Flash Parameter Table */
 /*
  * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
  * They are indexed from 1 but C arrays are indexed from 0.
  */
 #define BFPT_DWORD(i)		((i) - 1)
 #define BFPT_DWORD_MAX		16
 /* The first version of JESB216 defined only 9 DWORDs. */
 #define BFPT_DWORD_MAX_JESD216			9
 /* 1st DWORD. */
 #define BFPT_DWORD1_FAST_READ_1_1_2		BIT(16)
 #define BFPT_DWORD1_ADDRESS_BYTES_MASK		GENMASK(18, 17)
 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY	(0x0UL << 17)
 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4	(0x1UL << 17)
 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY	(0x2UL << 17)
 #define BFPT_DWORD1_DTR				BIT(19)
 #define BFPT_DWORD1_FAST_READ_1_2_2		BIT(20)
 #define BFPT_DWORD1_FAST_READ_1_4_4		BIT(21)
 #define BFPT_DWORD1_FAST_READ_1_1_4		BIT(22)
 /* 5th DWORD. */
 #define BFPT_DWORD5_FAST_READ_2_2_2		BIT(0)
 #define BFPT_DWORD5_FAST_READ_4_4_4		BIT(4)
 /* 11th DWORD. */
 #define BFPT_DWORD11_PAGE_SIZE_SHIFT		4
 #define BFPT_DWORD11_PAGE_SIZE_MASK		GENMASK(7, 4)
 /* 15th DWORD. */
 /*
  * (from JESD216 rev B)
  * Quad Enable Requirements (QER):
  * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
  *         reads based on instruction. DQ3/HOLD# functions are hold during
  *         instruction phase.
  * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
  *         two data bytes where bit 1 of the second byte is one.
  *         [...]
  *         Writing only one byte to the status register has the side-effect of
  *         clearing status register 2, including the QE bit. The 100b code is
  *         used if writing one byte to the status register does not modify
  *         status register 2.
  * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
  *         one data byte where bit 6 is one.
  *         [...]
  * - 011b: QE is bit 7 of status register 2. It is set via Write status
  *         register 2 instruction 3Eh with one data byte where bit 7 is one.
  *         [...]
  *         The status register 2 is read using instruction 3Fh.
  * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
  *         two data bytes where bit 1 of the second byte is one.
  *         [...]
  *         In contrast to the 001b code, writing one byte to the status
  *         register does not modify status register 2.
  * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
  *         Read Status instruction 05h. Status register2 is read using
  *         instruction 35h. QE is set via Writ Status instruction 01h with
  *         two data bytes where bit 1 of the second byte is one.
  *         [...]
  */
 #define BFPT_DWORD15_QER_MASK			GENMASK(22, 20)
 #define BFPT_DWORD15_QER_NONE			(0x0UL << 20) /* Micron */
 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY		(0x1UL << 20)
 #define BFPT_DWORD15_QER_SR1_BIT6		(0x2UL << 20) /* Macronix */
 #define BFPT_DWORD15_QER_SR2_BIT7		(0x3UL << 20)
 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD		(0x4UL << 20)
 #define BFPT_DWORD15_QER_SR2_BIT1		(0x5UL << 20) /* Spansion */
 struct sfdp_bfpt {
 	u32	dwords[BFPT_DWORD_MAX];
 };
 /* Fast Read settings. */
 static void
 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read,
 				    u16 half,
 				    enum spi_nor_protocol proto)
 {
 	read->num_mode_clocks = (half >> 5) & 0x07;
 	read->num_wait_states = (half >> 0) & 0x1f;
 	read->opcode = (half >> 8) & 0xff;
 	read->proto = proto;
 }
 struct sfdp_bfpt_read {
 	/* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */
 	u32			hwcaps;
 	/*
 	 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us
 	 * whether the Fast Read x-y-z command is supported.
 	 */
 	u32			supported_dword;
 	u32			supported_bit;
 	/*
 	 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD
 	 * encodes the op code, the number of mode clocks and the number of wait
 	 * states to be used by Fast Read x-y-z command.
 	 */
 	u32			settings_dword;
 	u32			settings_shift;
 	/* The SPI protocol for this Fast Read x-y-z command. */
 	enum spi_nor_protocol	proto;
 };
 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = {
 	/* Fast Read 1-1-2 */
 	{
 		SNOR_HWCAPS_READ_1_1_2,
 		BFPT_DWORD(1), BIT(16),	/* Supported bit */
 		BFPT_DWORD(4), 0,	/* Settings */
 		SNOR_PROTO_1_1_2,
 	},
 	/* Fast Read 1-2-2 */
 	{
 		SNOR_HWCAPS_READ_1_2_2,
 		BFPT_DWORD(1), BIT(20),	/* Supported bit */
 		BFPT_DWORD(4), 16,	/* Settings */
 		SNOR_PROTO_1_2_2,
 	},
 	/* Fast Read 2-2-2 */
 	{
 		SNOR_HWCAPS_READ_2_2_2,
 		BFPT_DWORD(5),  BIT(0),	/* Supported bit */
 		BFPT_DWORD(6), 16,	/* Settings */
 		SNOR_PROTO_2_2_2,
 	},
 	/* Fast Read 1-1-4 */
 	{
 		SNOR_HWCAPS_READ_1_1_4,
 		BFPT_DWORD(1), BIT(22),	/* Supported bit */
 		BFPT_DWORD(3), 16,	/* Settings */
 		SNOR_PROTO_1_1_4,
 	},
 	/* Fast Read 1-4-4 */
 	{
 		SNOR_HWCAPS_READ_1_4_4,
 		BFPT_DWORD(1), BIT(21),	/* Supported bit */
 		BFPT_DWORD(3), 0,	/* Settings */
 		SNOR_PROTO_1_4_4,
 	},
 	/* Fast Read 4-4-4 */
 	{
 		SNOR_HWCAPS_READ_4_4_4,
 		BFPT_DWORD(5), BIT(4),	/* Supported bit */
 		BFPT_DWORD(7), 16,	/* Settings */
 		SNOR_PROTO_4_4_4,
 	},
 };
 struct sfdp_bfpt_erase {
 	/*
 	 * The half-word at offset <shift> in DWORD <dwoard> encodes the
 	 * op code and erase sector size to be used by Sector Erase commands.
 	 */
 	u32			dword;
 	u32			shift;
 };
 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = {
 	/* Erase Type 1 in DWORD8 bits[15:0] */
 	{BFPT_DWORD(8), 0},
 	/* Erase Type 2 in DWORD8 bits[31:16] */
 	{BFPT_DWORD(8), 16},
 	/* Erase Type 3 in DWORD9 bits[15:0] */
 	{BFPT_DWORD(9), 0},
 	/* Erase Type 4 in DWORD9 bits[31:16] */
 	{BFPT_DWORD(9), 16},
 };
 static int spi_nor_hwcaps_read2cmd(u32 hwcaps);
 /**
  * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
  * @nor:		pointer to a 'struct spi_nor'
  * @bfpt_header:	pointer to the 'struct sfdp_parameter_header' describing
  *			the Basic Flash Parameter Table length and version
  * @params:		pointer to the 'struct spi_nor_flash_parameter' to be
  *			filled
  *
  * The Basic Flash Parameter Table is the main and only mandatory table as
  * defined by the SFDP (JESD216) specification.
  * It provides us with the total size (memory density) of the data array and
  * the number of address bytes for Fast Read, Page Program and Sector Erase
  * commands.
  * For Fast READ commands, it also gives the number of mode clock cycles and
  * wait states (regrouped in the number of dummy clock cycles) for each
  * supported instruction op code.
  * For Page Program, the page size is now available since JESD216 rev A, however
  * the supported instruction op codes are still not provided.
  * For Sector Erase commands, this table stores the supported instruction op
  * codes and the associated sector sizes.
  * Finally, the Quad Enable Requirements (QER) are also available since JESD216
  * rev A. The QER bits encode the manufacturer dependent procedure to be
  * executed to set the Quad Enable (QE) bit in some internal register of the
  * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
  * sending any Quad SPI command to the memory. Actually, setting the QE bit
  * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
  * and IO3 hence enabling 4 (Quad) I/O lines.
  *
  * Return: 0 on success, -errno otherwise.
  */
 static int spi_nor_parse_bfpt(struct spi_nor *nor,
 			      const struct sfdp_parameter_header *bfpt_header,
 			      struct spi_nor_flash_parameter *params)
 {
 	struct mtd_info *mtd = &nor->mtd;
 	struct sfdp_bfpt bfpt;
 	size_t len;
 	int i, cmd, err;
 	u32 addr;
 	u16 half;
 	/* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
 	if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
 		return -EINVAL;
 	/* Read the Basic Flash Parameter Table. */
 	len = min_t(size_t, sizeof(bfpt),
 		    bfpt_header->length * sizeof(u32));
 	addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
 	memset(&bfpt, 0, sizeof(bfpt));
 	err = spi_nor_read_sfdp(nor,  addr, len, &bfpt);
 	if (err < 0)
 		return err;
 	/* Fix endianness of the BFPT DWORDs. */
 	for (i = 0; i < BFPT_DWORD_MAX; i++)
 		bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
 	/* Number of address bytes. */
 	switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
 	case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
 		nor->addr_width = 3;
 		break;
 	case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
 		nor->addr_width = 4;
 		break;
 	default:
 		break;
 	}
 	/* Flash Memory Density (in bits). */
 	params->size = bfpt.dwords[BFPT_DWORD(2)];
 	if (params->size & BIT(31)) {
 		params->size &= ~BIT(31);
 		/*
 		 * Prevent overflows on params->size. Anyway, a NOR of 2^64
 		 * bits is unlikely to exist so this error probably means
 		 * the BFPT we are reading is corrupted/wrong.
 		 */
 		if (params->size > 63)
 			return -EINVAL;
 		params->size = 1ULL << params->size;
 	} else {
 		params->size++;
 	}
 	params->size >>= 3; /* Convert to bytes. */
 	/* Fast Read settings. */
 	for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
 		const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
 		struct spi_nor_read_command *read;
 		if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
 			params->hwcaps.mask &= ~rd->hwcaps;
 			continue;
 		}
 		params->hwcaps.mask |= rd->hwcaps;
 		cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
 		read = &params->reads[cmd];
 		half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
 		spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
 	}
 	/* Sector Erase settings. */
 	for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
 		const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
 		u32 erasesize;
 		u8 opcode;
 		half = bfpt.dwords[er->dword] >> er->shift;
 		erasesize = half & 0xff;
 		/* erasesize == 0 means this Erase Type is not supported. */
 		if (!erasesize)
 			continue;
 		erasesize = 1U << erasesize;
 		opcode = (half >> 8) & 0xff;
 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
 		if (erasesize == SZ_4K) {
 			nor->erase_opcode = opcode;
 			mtd->erasesize = erasesize;
 			break;
 		}
 #endif
 		if (!mtd->erasesize || mtd->erasesize < erasesize) {
 			nor->erase_opcode = opcode;
 			mtd->erasesize = erasesize;
 		}
 	}
 	/* Stop here if not JESD216 rev A or later. */
 	if (bfpt_header->length < BFPT_DWORD_MAX)
 		return 0;
 	/* Page size: this field specifies 'N' so the page size = 2^N bytes. */
 	params->page_size = bfpt.dwords[BFPT_DWORD(11)];
 	params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
 	params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
 	params->page_size = 1U << params->page_size;
 	/* Quad Enable Requirements. */
 	switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
 	case BFPT_DWORD15_QER_NONE:
 		params->quad_enable = NULL;
 		break;
 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
 	case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
 	case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
 		params->quad_enable = spansion_no_read_cr_quad_enable;
 		break;
 #endif
 #ifdef CONFIG_SPI_FLASH_MACRONIX
 	case BFPT_DWORD15_QER_SR1_BIT6:
 		params->quad_enable = macronix_quad_enable;
 		break;
 #endif
 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
 	case BFPT_DWORD15_QER_SR2_BIT1:
 		params->quad_enable = spansion_read_cr_quad_enable;
 		break;
 #endif
 	default:
 		return -EINVAL;
 	}
 	return 0;
 }
 /**
  * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
  * @nor:		pointer to a 'struct spi_nor'
  * @params:		pointer to the 'struct spi_nor_flash_parameter' to be
  *			filled
  *
  * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216
  * specification. This is a standard which tends to supported by almost all
  * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at
  * runtime the main parameters needed to perform basic SPI flash operations such
  * as Fast Read, Page Program or Sector Erase commands.
  *
  * Return: 0 on success, -errno otherwise.
  */
 static int spi_nor_parse_sfdp(struct spi_nor *nor,
 			      struct spi_nor_flash_parameter *params)
 {
 	const struct sfdp_parameter_header *param_header, *bfpt_header;
 	struct sfdp_parameter_header *param_headers = NULL;
 	struct sfdp_header header;
 	size_t psize;
 	int i, err;
 	/* Get the SFDP header. */
 	err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
 	if (err < 0)
 		return err;
 	/* Check the SFDP header version. */
 	if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
 	    header.major != SFDP_JESD216_MAJOR)
 		return -EINVAL;
 	/*
 	 * Verify that the first and only mandatory parameter header is a
 	 * Basic Flash Parameter Table header as specified in JESD216.
 	 */
 	bfpt_header = &header.bfpt_header;
 	if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
 	    bfpt_header->major != SFDP_JESD216_MAJOR)
 		return -EINVAL;
 	/*
 	 * Allocate memory then read all parameter headers with a single
 	 * Read SFDP command. These parameter headers will actually be parsed
 	 * twice: a first time to get the latest revision of the basic flash
 	 * parameter table, then a second time to handle the supported optional
 	 * tables.
 	 * Hence we read the parameter headers once for all to reduce the
 	 * processing time. Also we use kmalloc() instead of devm_kmalloc()
 	 * because we don't need to keep these parameter headers: the allocated
 	 * memory is always released with kfree() before exiting this function.
 	 */
 	if (header.nph) {
 		psize = header.nph * sizeof(*param_headers);
 		param_headers = kmalloc(psize, GFP_KERNEL);
 		if (!param_headers)
 			return -ENOMEM;
 		err = spi_nor_read_sfdp(nor, sizeof(header),
 					psize, param_headers);
 		if (err < 0) {
 			dev_err(dev, "failed to read SFDP parameter headers\n");
 			goto exit;
 		}
 	}
 	/*
 	 * Check other parameter headers to get the latest revision of
 	 * the basic flash parameter table.
 	 */
 	for (i = 0; i < header.nph; i++) {
 		param_header = &param_headers[i];
 		if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
 		    param_header->major == SFDP_JESD216_MAJOR &&
 		    (param_header->minor > bfpt_header->minor ||
 		     (param_header->minor == bfpt_header->minor &&
 		      param_header->length > bfpt_header->length)))
 			bfpt_header = param_header;
 	}
 	err = spi_nor_parse_bfpt(nor, bfpt_header, params);
 	if (err)
 		goto exit;
 	/* Parse other parameter headers. */
 	for (i = 0; i < header.nph; i++) {
 		param_header = &param_headers[i];
 		switch (SFDP_PARAM_HEADER_ID(param_header)) {
 		case SFDP_SECTOR_MAP_ID:
 			dev_info(dev, "non-uniform erase sector maps are not supported yet.\n");
 			break;
 		default:
 			break;
 		}
 		if (err)
 			goto exit;
 	}
 exit:
 	kfree(param_headers);
 	return err;
 }
 #else
 static int spi_nor_parse_sfdp(struct spi_nor *nor,
 			      struct spi_nor_flash_parameter *params)
 {
 	return -EINVAL;
 }
 #endif /* SPI_FLASH_SFDP_SUPPORT */
 static int spi_nor_init_params(struct spi_nor *nor,
 			       const struct flash_info *info,
 			       struct spi_nor_flash_parameter *params)
 {
 	/* Set legacy flash parameters as default. */
 	memset(params, 0, sizeof(*params));
 	/* Set SPI NOR sizes. */
 	params->size = info->sector_size * info->n_sectors;
 	params->page_size = info->page_size;
 	/* (Fast) Read settings. */
 	params->hwcaps.mask |= SNOR_HWCAPS_READ;
 	spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ],
 				  0, 0, SPINOR_OP_READ,
 				  SNOR_PROTO_1_1_1);
 	if (!(info->flags & SPI_NOR_NO_FR)) {
 		params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;
 		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST],
 					  0, 8, SPINOR_OP_READ_FAST,
 					  SNOR_PROTO_1_1_1);
 	}
 	if (info->flags & SPI_NOR_DUAL_READ) {
 		params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
 		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
 					  0, 8, SPINOR_OP_READ_1_1_2,
 					  SNOR_PROTO_1_1_2);
 	}
 	if (info->flags & SPI_NOR_QUAD_READ) {
 		params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
 		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
 					  0, 8, SPINOR_OP_READ_1_1_4,
 					  SNOR_PROTO_1_1_4);
 	}
 	/* Page Program settings. */
 	params->hwcaps.mask |= SNOR_HWCAPS_PP;
 	spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
 				SPINOR_OP_PP, SNOR_PROTO_1_1_1);
 	if (info->flags & SPI_NOR_QUAD_READ) {
 		params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
 		spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_1_4],
 					SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);
 	}
 	/* Select the procedure to set the Quad Enable bit. */
 	if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
 				   SNOR_HWCAPS_PP_QUAD)) {
 		switch (JEDEC_MFR(info)) {
 #ifdef CONFIG_SPI_FLASH_MACRONIX
 		case SNOR_MFR_MACRONIX:
 			params->quad_enable = macronix_quad_enable;
 			break;
 #endif
 		case SNOR_MFR_ST:
 		case SNOR_MFR_MICRON:
 			break;
 		default:
 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
 			/* Kept only for backward compatibility purpose. */
 			params->quad_enable = spansion_read_cr_quad_enable;
 #endif
 			break;
 		}
 	}
 	/* Override the parameters with data read from SFDP tables. */
 	nor->addr_width = 0;
 	nor->mtd.erasesize = 0;
 	if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) &&
 	    !(info->flags & SPI_NOR_SKIP_SFDP)) {
 		struct spi_nor_flash_parameter sfdp_params;
 		memcpy(&sfdp_params, params, sizeof(sfdp_params));
 		if (spi_nor_parse_sfdp(nor, &sfdp_params)) {
 			nor->addr_width = 0;
 			nor->mtd.erasesize = 0;
 		} else {
 			memcpy(params, &sfdp_params, sizeof(*params));
 		}
 	}
 	return 0;
 }
 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)
 {
 	size_t i;
 	for (i = 0; i < size; i++)
 		if (table[i][0] == (int)hwcaps)
 			return table[i][1];
 	return -EINVAL;
 }
 static int spi_nor_hwcaps_read2cmd(u32 hwcaps)
 {
 	static const int hwcaps_read2cmd[][2] = {
 		{ SNOR_HWCAPS_READ,		SNOR_CMD_READ },
 		{ SNOR_HWCAPS_READ_FAST,	SNOR_CMD_READ_FAST },
 		{ SNOR_HWCAPS_READ_1_1_1_DTR,	SNOR_CMD_READ_1_1_1_DTR },
 		{ SNOR_HWCAPS_READ_1_1_2,	SNOR_CMD_READ_1_1_2 },
 		{ SNOR_HWCAPS_READ_1_2_2,	SNOR_CMD_READ_1_2_2 },
 		{ SNOR_HWCAPS_READ_2_2_2,	SNOR_CMD_READ_2_2_2 },
 		{ SNOR_HWCAPS_READ_1_2_2_DTR,	SNOR_CMD_READ_1_2_2_DTR },
 		{ SNOR_HWCAPS_READ_1_1_4,	SNOR_CMD_READ_1_1_4 },
 		{ SNOR_HWCAPS_READ_1_4_4,	SNOR_CMD_READ_1_4_4 },
 		{ SNOR_HWCAPS_READ_4_4_4,	SNOR_CMD_READ_4_4_4 },
 		{ SNOR_HWCAPS_READ_1_4_4_DTR,	SNOR_CMD_READ_1_4_4_DTR },
 		{ SNOR_HWCAPS_READ_1_1_8,	SNOR_CMD_READ_1_1_8 },
 		{ SNOR_HWCAPS_READ_1_8_8,	SNOR_CMD_READ_1_8_8 },
 		{ SNOR_HWCAPS_READ_8_8_8,	SNOR_CMD_READ_8_8_8 },
 		{ SNOR_HWCAPS_READ_1_8_8_DTR,	SNOR_CMD_READ_1_8_8_DTR },
 	};
 	return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
 				  ARRAY_SIZE(hwcaps_read2cmd));
 }
 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
 {
 	static const int hwcaps_pp2cmd[][2] = {
 		{ SNOR_HWCAPS_PP,		SNOR_CMD_PP },
 		{ SNOR_HWCAPS_PP_1_1_4,		SNOR_CMD_PP_1_1_4 },
 		{ SNOR_HWCAPS_PP_1_4_4,		SNOR_CMD_PP_1_4_4 },
 		{ SNOR_HWCAPS_PP_4_4_4,		SNOR_CMD_PP_4_4_4 },
 		{ SNOR_HWCAPS_PP_1_1_8,		SNOR_CMD_PP_1_1_8 },
 		{ SNOR_HWCAPS_PP_1_8_8,		SNOR_CMD_PP_1_8_8 },
 		{ SNOR_HWCAPS_PP_8_8_8,		SNOR_CMD_PP_8_8_8 },
 	};
 	return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
 				  ARRAY_SIZE(hwcaps_pp2cmd));
 }
 static int spi_nor_select_read(struct spi_nor *nor,
 			       const struct spi_nor_flash_parameter *params,
 			       u32 shared_hwcaps)
 {
 	int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;
 	const struct spi_nor_read_command *read;
 	if (best_match < 0)
 		return -EINVAL;
 	cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
 	if (cmd < 0)
 		return -EINVAL;
 	read = &params->reads[cmd];
 	nor->read_opcode = read->opcode;
 	nor->read_proto = read->proto;
 	/*
 	 * In the spi-nor framework, we don't need to make the difference
 	 * between mode clock cycles and wait state clock cycles.
 	 * Indeed, the value of the mode clock cycles is used by a QSPI
 	 * flash memory to know whether it should enter or leave its 0-4-4
 	 * (Continuous Read / XIP) mode.
 	 * eXecution In Place is out of the scope of the mtd sub-system.
 	 * Hence we choose to merge both mode and wait state clock cycles
 	 * into the so called dummy clock cycles.
 	 */
 	nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
 	return 0;
 }
 static int spi_nor_select_pp(struct spi_nor *nor,
 			     const struct spi_nor_flash_parameter *params,
 			     u32 shared_hwcaps)
 {
 	int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;
 	const struct spi_nor_pp_command *pp;
 	if (best_match < 0)
 		return -EINVAL;
 	cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));
 	if (cmd < 0)
 		return -EINVAL;
 	pp = &params->page_programs[cmd];
 	nor->program_opcode = pp->opcode;
 	nor->write_proto = pp->proto;
 	return 0;
 }
 static int spi_nor_select_erase(struct spi_nor *nor,
 				const struct flash_info *info)
 {
 	struct mtd_info *mtd = &nor->mtd;
 	/* Do nothing if already configured from SFDP. */
 	if (mtd->erasesize)
 		return 0;
 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
 	/* prefer "small sector" erase if possible */
 	if (info->flags & SECT_4K) {
 		nor->erase_opcode = SPINOR_OP_BE_4K;
 		mtd->erasesize = 4096;
 	} else if (info->flags & SECT_4K_PMC) {
 		nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
 		mtd->erasesize = 4096;
 	} else
 #endif
 	{
 		nor->erase_opcode = SPINOR_OP_SE;
 		mtd->erasesize = info->sector_size;
 	}
 	return 0;
 }
 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
 			 const struct spi_nor_flash_parameter *params,
 			 const struct spi_nor_hwcaps *hwcaps)
 {
 	u32 ignored_mask, shared_mask;
 	bool enable_quad_io;
 	int err;
 	/*
 	 * Keep only the hardware capabilities supported by both the SPI
 	 * controller and the SPI flash memory.
 	 */
 	shared_mask = hwcaps->mask & params->hwcaps.mask;
 	/* SPI n-n-n protocols are not supported yet. */
 	ignored_mask = (SNOR_HWCAPS_READ_2_2_2 |
 			SNOR_HWCAPS_READ_4_4_4 |
 			SNOR_HWCAPS_READ_8_8_8 |
 			SNOR_HWCAPS_PP_4_4_4 |
 			SNOR_HWCAPS_PP_8_8_8);
 	if (shared_mask & ignored_mask) {
 		dev_dbg(nor->dev,
 			"SPI n-n-n protocols are not supported yet.\n");
 		shared_mask &= ~ignored_mask;
 	}
 	/* Select the (Fast) Read command. */
 	err = spi_nor_select_read(nor, params, shared_mask);
 	if (err) {
 		dev_dbg(nor->dev,
 			"can't select read settings supported by both the SPI controller and memory.\n");
 		return err;
 	}
 	/* Select the Page Program command. */
 	err = spi_nor_select_pp(nor, params, shared_mask);
 	if (err) {
 		dev_dbg(nor->dev,
 			"can't select write settings supported by both the SPI controller and memory.\n");
 		return err;
 	}
 	/* Select the Sector Erase command. */
 	err = spi_nor_select_erase(nor, info);
 	if (err) {
 		dev_dbg(nor->dev,
 			"can't select erase settings supported by both the SPI controller and memory.\n");
 		return err;
 	}
 	/* Enable Quad I/O if needed. */
 	enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 ||
 			  spi_nor_get_protocol_width(nor->write_proto) == 4);
 	if (enable_quad_io && params->quad_enable)
 		nor->quad_enable = params->quad_enable;
 	else
 		nor->quad_enable = NULL;
 	return 0;
 }
 static int spi_nor_init(struct spi_nor *nor)
 {
 	int err;
 	/*
 	 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
 	 * with the software protection bits set
 	 */
 	if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
 	    JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
 	    JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
 	    nor->info->flags & SPI_NOR_HAS_LOCK) {
 		write_enable(nor);
 		write_sr(nor, 0);
 		spi_nor_wait_till_ready(nor);
 	}
 	if (nor->quad_enable) {
 		err = nor->quad_enable(nor);
 		if (err) {
 			dev_dbg(nor->dev, "quad mode not supported\n");
 			return err;
 		}
 	}
 	if (nor->addr_width == 4 &&
 	    (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) &&
 	    !(nor->info->flags & SPI_NOR_4B_OPCODES)) {
 		/*
 		 * If the RESET# pin isn't hooked up properly, or the system
 		 * otherwise doesn't perform a reset command in the boot
 		 * sequence, it's impossible to 100% protect against unexpected
 		 * reboots (e.g., crashes). Warn the user (or hopefully, system
 		 * designer) that this is bad.
 		 */
 		if (nor->flags & SNOR_F_BROKEN_RESET)
 			printf("enabling reset hack; may not recover from unexpected reboots\n");
 		set_4byte(nor, nor->info, 1);
 	}
 	return 0;
 }
 int spi_nor_scan(struct spi_nor *nor)
 {
 	struct spi_nor_flash_parameter params;
 	const struct flash_info *info = NULL;
 	struct mtd_info *mtd = &nor->mtd;
 	struct spi_nor_hwcaps hwcaps = {
 		.mask = SNOR_HWCAPS_READ |
 			SNOR_HWCAPS_READ_FAST |
 			SNOR_HWCAPS_PP,
 	};
 	struct spi_slave *spi = nor->spi;
 	int ret;
 	/* Reset SPI protocol for all commands. */
 	nor->reg_proto = SNOR_PROTO_1_1_1;
 	nor->read_proto = SNOR_PROTO_1_1_1;
 	nor->write_proto = SNOR_PROTO_1_1_1;
 	nor->read = spi_nor_read_data;
 	nor->write = spi_nor_write_data;
 	nor->read_reg = spi_nor_read_reg;
 	nor->write_reg = spi_nor_write_reg;
 	if (spi->mode & SPI_RX_QUAD) {
 		hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
 		if (spi->mode & SPI_TX_QUAD)
 			hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 |
 					SNOR_HWCAPS_PP_1_1_4 |
 					SNOR_HWCAPS_PP_1_4_4);
 	} else if (spi->mode & SPI_RX_DUAL) {
 		hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
 		if (spi->mode & SPI_TX_DUAL)
 			hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2;
 	}
 	info = spi_nor_read_id(nor);
 	if (IS_ERR_OR_NULL(info))
 		return -ENOENT;
 	/* Parse the Serial Flash Discoverable Parameters table. */
 	ret = spi_nor_init_params(nor, info, &params);
 	if (ret)
 		return ret;
 	if (!mtd->name)
 		mtd->name = info->name;
 	mtd->priv = nor;
 	mtd->type = MTD_NORFLASH;
 	mtd->writesize = 1;
 	mtd->flags = MTD_CAP_NORFLASH;
 	mtd->size = params.size;
 	mtd->_erase = spi_nor_erase;
 	mtd->_read = spi_nor_read;
 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
 	/* NOR protection support for STmicro/Micron chips and similar */
 	if (JEDEC_MFR(info) == SNOR_MFR_ST ||
 	    JEDEC_MFR(info) == SNOR_MFR_MICRON ||
 	    JEDEC_MFR(info) == SNOR_MFR_SST ||
 			info->flags & SPI_NOR_HAS_LOCK) {
 		nor->flash_lock = stm_lock;
 		nor->flash_unlock = stm_unlock;
 		nor->flash_is_locked = stm_is_locked;
 	}
 #endif
 #ifdef CONFIG_SPI_FLASH_SST
 	/* sst nor chips use AAI word program */
 	if (info->flags & SST_WRITE)
 		mtd->_write = sst_write;
 	else
 #endif
 		mtd->_write = spi_nor_write;
 	if (info->flags & USE_FSR)
 		nor->flags |= SNOR_F_USE_FSR;
 	if (info->flags & SPI_NOR_HAS_TB)
 		nor->flags |= SNOR_F_HAS_SR_TB;
 	if (info->flags & NO_CHIP_ERASE)
 		nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
 	if (info->flags & USE_CLSR)
 		nor->flags |= SNOR_F_USE_CLSR;
 	if (info->flags & SPI_NOR_NO_ERASE)
 		mtd->flags |= MTD_NO_ERASE;
 	nor->page_size = params.page_size;
 	mtd->writebufsize = nor->page_size;
 	/* Some devices cannot do fast-read, no matter what DT tells us */
 	if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW))
 		params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST;
 	/*
 	 * Configure the SPI memory:
 	 * - select op codes for (Fast) Read, Page Program and Sector Erase.
 	 * - set the number of dummy cycles (mode cycles + wait states).
 	 * - set the SPI protocols for register and memory accesses.
 	 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
 	 */
 	ret = spi_nor_setup(nor, info, &params, &hwcaps);
 	if (ret)
 		return ret;
 	if (nor->addr_width) {
 		/* already configured from SFDP */
 	} else if (info->addr_width) {
 		nor->addr_width = info->addr_width;
 	} else if (mtd->size > SZ_16M) {
 #ifndef CONFIG_SPI_FLASH_BAR
 		/* enable 4-byte addressing if the device exceeds 16MiB */
 		nor->addr_width = 4;
 		if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
 		    info->flags & SPI_NOR_4B_OPCODES)
 			spi_nor_set_4byte_opcodes(nor, info);
 #else
 	/* Configure the BAR - discover bank cmds and read current bank */
 	nor->addr_width = 3;
 	ret = read_bar(nor, info);
 	if (ret < 0)
 		return ret;
 #endif
 	} else {
 		nor->addr_width = 3;
 	}
 	if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
 		dev_dbg(dev, "address width is too large: %u\n",
 			nor->addr_width);
 		return -EINVAL;
 	}
 	/* Send all the required SPI flash commands to initialize device */
 	nor->info = info;
 	ret = spi_nor_init(nor);
 	if (ret)
 		return ret;
 	nor->name = mtd->name;
 	nor->size = mtd->size;
 	nor->erase_size = mtd->erasesize;
 	nor->sector_size = mtd->erasesize;
 #ifndef CONFIG_SPL_BUILD
 	printf("SF: Detected %s with page size ", nor->name);
 	print_size(nor->page_size, ", erase size ");
 	print_size(nor->erase_size, ", total ");
 	print_size(nor->size, "");
 	puts("\n");
 #endif
 	return 0;
 }
 /* U-Boot specific functions, need to extend MTD to support these */
 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor)
 {
 	int sr = read_sr(nor);
 	if (sr < 0)
 		return sr;
 	return (sr >> 2) & 7;

drivers/spi/stm32_qspi.c

Diff comments View file @ c4e8862

1	// SPDX-License-Identifier: GPL-2.0+	1	// SPDX-License-Identifier: GPL-2.0+
2	/*	2	/*
3	* (C) Copyright 2016	3	* (C) Copyright 2016
4	*	4	*
5	* Michael Kurz, <michi.kurz@gmail.com>	5	* Michael Kurz, <michi.kurz@gmail.com>
6	*	6	*
7	* STM32 QSPI driver	7	* STM32 QSPI driver
8	*/	8	*/
9		9
10	#include <common.h>	10	#include <common.h>
11	#include <clk.h>	11	#include <clk.h>
12	#include <dm.h>	12	#include <dm.h>
13	#include <errno.h>	13	#include <errno.h>
14	#include <malloc.h>	14	#include <malloc.h>
15	#include <reset.h>	15	#include <reset.h>
16	#include <spi.h>	16	#include <spi.h>
17	#include <spi_flash.h>	17	#include <spi_flash.h>
18	#include <asm/io.h>	18	#include <asm/io.h>
19	#include <asm/arch/stm32.h>	19	#include <asm/arch/stm32.h>
20	#include <linux/ioport.h>	20	#include <linux/ioport.h>
21		21
22	struct stm32_qspi_regs {	22	struct stm32_qspi_regs {
23	u32 cr; /* 0x00 */	23	u32 cr; /* 0x00 */
24	u32 dcr; /* 0x04 */	24	u32 dcr; /* 0x04 */
25	u32 sr; /* 0x08 */	25	u32 sr; /* 0x08 */
26	u32 fcr; /* 0x0C */	26	u32 fcr; /* 0x0C */
27	u32 dlr; /* 0x10 */	27	u32 dlr; /* 0x10 */
28	u32 ccr; /* 0x14 */	28	u32 ccr; /* 0x14 */
29	u32 ar; /* 0x18 */	29	u32 ar; /* 0x18 */
30	u32 abr; /* 0x1C */	30	u32 abr; /* 0x1C */
31	u32 dr; /* 0x20 */	31	u32 dr; /* 0x20 */
32	u32 psmkr; /* 0x24 */	32	u32 psmkr; /* 0x24 */
33	u32 psmar; /* 0x28 */	33	u32 psmar; /* 0x28 */
34	u32 pir; /* 0x2C */	34	u32 pir; /* 0x2C */
35	u32 lptr; /* 0x30 */	35	u32 lptr; /* 0x30 */
36	};	36	};
37		37
38	/*	38	/*
39	* QUADSPI control register	39	* QUADSPI control register
40	*/	40	*/
41	#define STM32_QSPI_CR_EN BIT(0)	41	#define STM32_QSPI_CR_EN BIT(0)
42	#define STM32_QSPI_CR_ABORT BIT(1)	42	#define STM32_QSPI_CR_ABORT BIT(1)
43	#define STM32_QSPI_CR_DMAEN BIT(2)	43	#define STM32_QSPI_CR_DMAEN BIT(2)
44	#define STM32_QSPI_CR_TCEN BIT(3)	44	#define STM32_QSPI_CR_TCEN BIT(3)
45	#define STM32_QSPI_CR_SSHIFT BIT(4)	45	#define STM32_QSPI_CR_SSHIFT BIT(4)
46	#define STM32_QSPI_CR_DFM BIT(6)	46	#define STM32_QSPI_CR_DFM BIT(6)
47	#define STM32_QSPI_CR_FSEL BIT(7)	47	#define STM32_QSPI_CR_FSEL BIT(7)
48	#define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0)	48	#define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0)
49	#define STM32_QSPI_CR_FTHRES_SHIFT (8)	49	#define STM32_QSPI_CR_FTHRES_SHIFT (8)
50	#define STM32_QSPI_CR_TEIE BIT(16)	50	#define STM32_QSPI_CR_TEIE BIT(16)
51	#define STM32_QSPI_CR_TCIE BIT(17)	51	#define STM32_QSPI_CR_TCIE BIT(17)
52	#define STM32_QSPI_CR_FTIE BIT(18)	52	#define STM32_QSPI_CR_FTIE BIT(18)
53	#define STM32_QSPI_CR_SMIE BIT(19)	53	#define STM32_QSPI_CR_SMIE BIT(19)
54	#define STM32_QSPI_CR_TOIE BIT(20)	54	#define STM32_QSPI_CR_TOIE BIT(20)
55	#define STM32_QSPI_CR_APMS BIT(22)	55	#define STM32_QSPI_CR_APMS BIT(22)
56	#define STM32_QSPI_CR_PMM BIT(23)	56	#define STM32_QSPI_CR_PMM BIT(23)
57	#define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)	57	#define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
58	#define STM32_QSPI_CR_PRESCALER_SHIFT (24)	58	#define STM32_QSPI_CR_PRESCALER_SHIFT (24)
59		59
60	/*	60	/*
61	* QUADSPI device configuration register	61	* QUADSPI device configuration register
62	*/	62	*/
63	#define STM32_QSPI_DCR_CKMODE BIT(0)	63	#define STM32_QSPI_DCR_CKMODE BIT(0)
64	#define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)	64	#define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
65	#define STM32_QSPI_DCR_CSHT_SHIFT (8)	65	#define STM32_QSPI_DCR_CSHT_SHIFT (8)
66	#define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)	66	#define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
67	#define STM32_QSPI_DCR_FSIZE_SHIFT (16)	67	#define STM32_QSPI_DCR_FSIZE_SHIFT (16)
68		68
69	/*	69	/*
70	* QUADSPI status register	70	* QUADSPI status register
71	*/	71	*/
72	#define STM32_QSPI_SR_TEF BIT(0)	72	#define STM32_QSPI_SR_TEF BIT(0)
73	#define STM32_QSPI_SR_TCF BIT(1)	73	#define STM32_QSPI_SR_TCF BIT(1)
74	#define STM32_QSPI_SR_FTF BIT(2)	74	#define STM32_QSPI_SR_FTF BIT(2)
75	#define STM32_QSPI_SR_SMF BIT(3)	75	#define STM32_QSPI_SR_SMF BIT(3)
76	#define STM32_QSPI_SR_TOF BIT(4)	76	#define STM32_QSPI_SR_TOF BIT(4)
77	#define STM32_QSPI_SR_BUSY BIT(5)	77	#define STM32_QSPI_SR_BUSY BIT(5)
78	#define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0)	78	#define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0)
79	#define STM32_QSPI_SR_FLEVEL_SHIFT (8)	79	#define STM32_QSPI_SR_FLEVEL_SHIFT (8)
80		80
81	/*	81	/*
82	* QUADSPI flag clear register	82	* QUADSPI flag clear register
83	*/	83	*/
84	#define STM32_QSPI_FCR_CTEF BIT(0)	84	#define STM32_QSPI_FCR_CTEF BIT(0)
85	#define STM32_QSPI_FCR_CTCF BIT(1)	85	#define STM32_QSPI_FCR_CTCF BIT(1)
86	#define STM32_QSPI_FCR_CSMF BIT(3)	86	#define STM32_QSPI_FCR_CSMF BIT(3)
87	#define STM32_QSPI_FCR_CTOF BIT(4)	87	#define STM32_QSPI_FCR_CTOF BIT(4)
88		88
89	/*	89	/*
90	* QUADSPI communication configuration register	90	* QUADSPI communication configuration register
91	*/	91	*/
92	#define STM32_QSPI_CCR_DDRM BIT(31)	92	#define STM32_QSPI_CCR_DDRM BIT(31)
93	#define STM32_QSPI_CCR_DHHC BIT(30)	93	#define STM32_QSPI_CCR_DHHC BIT(30)
94	#define STM32_QSPI_CCR_SIOO BIT(28)	94	#define STM32_QSPI_CCR_SIOO BIT(28)
95	#define STM32_QSPI_CCR_FMODE_SHIFT (26)	95	#define STM32_QSPI_CCR_FMODE_SHIFT (26)
96	#define STM32_QSPI_CCR_DMODE_SHIFT (24)	96	#define STM32_QSPI_CCR_DMODE_SHIFT (24)
97	#define STM32_QSPI_CCR_DCYC_SHIFT (18)	97	#define STM32_QSPI_CCR_DCYC_SHIFT (18)
98	#define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0)	98	#define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0)
99	#define STM32_QSPI_CCR_ABSIZE_SHIFT (16)	99	#define STM32_QSPI_CCR_ABSIZE_SHIFT (16)
100	#define STM32_QSPI_CCR_ABMODE_SHIFT (14)	100	#define STM32_QSPI_CCR_ABMODE_SHIFT (14)
101	#define STM32_QSPI_CCR_ADSIZE_SHIFT (12)	101	#define STM32_QSPI_CCR_ADSIZE_SHIFT (12)
102	#define STM32_QSPI_CCR_ADMODE_SHIFT (10)	102	#define STM32_QSPI_CCR_ADMODE_SHIFT (10)
103	#define STM32_QSPI_CCR_IMODE_SHIFT (8)	103	#define STM32_QSPI_CCR_IMODE_SHIFT (8)
104	#define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0)	104	#define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0)
105		105
106	enum STM32_QSPI_CCR_IMODE {	106	enum STM32_QSPI_CCR_IMODE {
107	STM32_QSPI_CCR_IMODE_NONE = 0,	107	STM32_QSPI_CCR_IMODE_NONE = 0,
108	STM32_QSPI_CCR_IMODE_ONE_LINE = 1,	108	STM32_QSPI_CCR_IMODE_ONE_LINE = 1,
109	STM32_QSPI_CCR_IMODE_TWO_LINE = 2,	109	STM32_QSPI_CCR_IMODE_TWO_LINE = 2,
110	STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,	110	STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,
111	};	111	};
112		112
113	enum STM32_QSPI_CCR_ADMODE {	113	enum STM32_QSPI_CCR_ADMODE {
114	STM32_QSPI_CCR_ADMODE_NONE = 0,	114	STM32_QSPI_CCR_ADMODE_NONE = 0,
115	STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,	115	STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,
116	STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,	116	STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,
117	STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,	117	STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,
118	};	118	};
119		119
120	enum STM32_QSPI_CCR_ADSIZE {	120	enum STM32_QSPI_CCR_ADSIZE {
121	STM32_QSPI_CCR_ADSIZE_8BIT = 0,	121	STM32_QSPI_CCR_ADSIZE_8BIT = 0,
122	STM32_QSPI_CCR_ADSIZE_16BIT = 1,	122	STM32_QSPI_CCR_ADSIZE_16BIT = 1,
123	STM32_QSPI_CCR_ADSIZE_24BIT = 2,	123	STM32_QSPI_CCR_ADSIZE_24BIT = 2,
124	STM32_QSPI_CCR_ADSIZE_32BIT = 3,	124	STM32_QSPI_CCR_ADSIZE_32BIT = 3,
125	};	125	};
126		126
127	enum STM32_QSPI_CCR_ABMODE {	127	enum STM32_QSPI_CCR_ABMODE {
128	STM32_QSPI_CCR_ABMODE_NONE = 0,	128	STM32_QSPI_CCR_ABMODE_NONE = 0,
129	STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,	129	STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,
130	STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,	130	STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,
131	STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,	131	STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,
132	};	132	};
133		133
134	enum STM32_QSPI_CCR_ABSIZE {	134	enum STM32_QSPI_CCR_ABSIZE {
135	STM32_QSPI_CCR_ABSIZE_8BIT = 0,	135	STM32_QSPI_CCR_ABSIZE_8BIT = 0,
136	STM32_QSPI_CCR_ABSIZE_16BIT = 1,	136	STM32_QSPI_CCR_ABSIZE_16BIT = 1,
137	STM32_QSPI_CCR_ABSIZE_24BIT = 2,	137	STM32_QSPI_CCR_ABSIZE_24BIT = 2,
138	STM32_QSPI_CCR_ABSIZE_32BIT = 3,	138	STM32_QSPI_CCR_ABSIZE_32BIT = 3,
139	};	139	};
140		140
141	enum STM32_QSPI_CCR_DMODE {	141	enum STM32_QSPI_CCR_DMODE {
142	STM32_QSPI_CCR_DMODE_NONE = 0,	142	STM32_QSPI_CCR_DMODE_NONE = 0,
143	STM32_QSPI_CCR_DMODE_ONE_LINE = 1,	143	STM32_QSPI_CCR_DMODE_ONE_LINE = 1,
144	STM32_QSPI_CCR_DMODE_TWO_LINE = 2,	144	STM32_QSPI_CCR_DMODE_TWO_LINE = 2,
145	STM32_QSPI_CCR_DMODE_FOUR_LINE = 3,	145	STM32_QSPI_CCR_DMODE_FOUR_LINE = 3,
146	};	146	};
147		147
148	enum STM32_QSPI_CCR_FMODE {	148	enum STM32_QSPI_CCR_FMODE {
149	STM32_QSPI_CCR_IND_WRITE = 0,	149	STM32_QSPI_CCR_IND_WRITE = 0,
150	STM32_QSPI_CCR_IND_READ = 1,	150	STM32_QSPI_CCR_IND_READ = 1,
151	STM32_QSPI_CCR_AUTO_POLL = 2,	151	STM32_QSPI_CCR_AUTO_POLL = 2,
152	STM32_QSPI_CCR_MEM_MAP = 3,	152	STM32_QSPI_CCR_MEM_MAP = 3,
153	};	153	};
154		154
155	/* default SCK frequency, unit: HZ */	155	/* default SCK frequency, unit: HZ */
156	#define STM32_QSPI_DEFAULT_SCK_FREQ 108000000	156	#define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
157		157
158	#define STM32_MAX_NORCHIP 2	158	#define STM32_MAX_NORCHIP 2
159		159
160	struct stm32_qspi_platdata {	160	struct stm32_qspi_platdata {
161	u32 base;	161	u32 base;
162	u32 memory_map;	162	u32 memory_map;
163	u32 max_hz;	163	u32 max_hz;
164	};	164	};
165		165
166	struct stm32_qspi_priv {	166	struct stm32_qspi_priv {
167	struct stm32_qspi_regs *regs;	167	struct stm32_qspi_regs *regs;
168	ulong clock_rate;	168	ulong clock_rate;
169	u32 max_hz;	169	u32 max_hz;
170	u32 mode;	170	u32 mode;
171		171
172	u32 command;	172	u32 command;
173	u32 address;	173	u32 address;
174	u32 dummycycles;	174	u32 dummycycles;
175	#define CMD_HAS_ADR BIT(24)	175	#define CMD_HAS_ADR BIT(24)
176	#define CMD_HAS_DUMMY BIT(25)	176	#define CMD_HAS_DUMMY BIT(25)
177	#define CMD_HAS_DATA BIT(26)	177	#define CMD_HAS_DATA BIT(26)
178	};	178	};
179		179
180	static void _stm32_qspi_disable(struct stm32_qspi_priv *priv)	180	static void _stm32_qspi_disable(struct stm32_qspi_priv *priv)
181	{	181	{
182	clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);	182	clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
183	}	183	}
184		184
185	static void _stm32_qspi_enable(struct stm32_qspi_priv *priv)	185	static void _stm32_qspi_enable(struct stm32_qspi_priv *priv)
186	{	186	{
187	setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);	187	setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
188	}	188	}
189		189
190	static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)	190	static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
191	{	191	{
192	while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY)	192	while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY)
193	;	193	;
194	}	194	}
195		195
196	static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv)	196	static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv)
197	{	197	{
198	while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF))	198	while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF))
199	;	199	;
200	}	200	}
201		201
202	static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)	202	static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
203	{	203	{
204	while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF))	204	while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF))
205	;	205	;
206	}	206	}
207		207
208	static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)	208	static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
209	{	209	{
210	u32 fsize = fls(size) - 1;	210	u32 fsize = fls(size) - 1;
211		211
212	clrsetbits_le32(&priv->regs->dcr,	212	clrsetbits_le32(&priv->regs->dcr,
213	STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,	213	STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
214	fsize << STM32_QSPI_DCR_FSIZE_SHIFT);	214	fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
215	}	215	}
216		216
217	static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs)	217	static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs)
218	{	218	{
219	clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,	219	clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
220	cs ? STM32_QSPI_CR_FSEL : 0);	220	cs ? STM32_QSPI_CR_FSEL : 0);
221	}	221	}
222		222
223	static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv, u8 fmode)	223	static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv, u8 fmode)
224	{	224	{
225	unsigned int ccr_reg = 0;	225	unsigned int ccr_reg = 0;
226	u8 imode, admode, dmode;	226	u8 imode, admode, dmode;
227	u32 mode = priv->mode;	227	u32 mode = priv->mode;
228	u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);	228	u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);
229		229
230	imode = STM32_QSPI_CCR_IMODE_ONE_LINE;	230	imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
231	admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;	231	admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
232	dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;	232	dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
233		233
234	if ((priv->command & CMD_HAS_ADR) && (priv->command & CMD_HAS_DATA)) {	234	if ((priv->command & CMD_HAS_ADR) && (priv->command & CMD_HAS_DATA)) {
235	if (fmode == STM32_QSPI_CCR_IND_WRITE) {	235	if (fmode == STM32_QSPI_CCR_IND_WRITE) {
236	if (mode & SPI_TX_QUAD)	236	if (mode & SPI_TX_QUAD)
237	dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;	237	dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
238	else if (mode & SPI_TX_DUAL)	238	else if (mode & SPI_TX_DUAL)
239	dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;	239	dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
240	} else if ((fmode == STM32_QSPI_CCR_MEM_MAP) \|\|	240	} else if ((fmode == STM32_QSPI_CCR_MEM_MAP) \|\|
241	(fmode == STM32_QSPI_CCR_IND_READ)) {	241	(fmode == STM32_QSPI_CCR_IND_READ)) {
242	if (mode & SPI_RX_QUAD)	242	if (mode & SPI_RX_QUAD)
243	dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;	243	dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
244	else if (mode & SPI_RX_DUAL)	244	else if (mode & SPI_RX_DUAL)
245	dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;	245	dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
246	}	246	}
247	}	247	}
248		248
249	if (priv->command & CMD_HAS_DATA)	249	if (priv->command & CMD_HAS_DATA)
250	ccr_reg \|= (dmode << STM32_QSPI_CCR_DMODE_SHIFT);	250	ccr_reg \|= (dmode << STM32_QSPI_CCR_DMODE_SHIFT);
251		251
252	if (priv->command & CMD_HAS_DUMMY)	252	if (priv->command & CMD_HAS_DUMMY)
253	ccr_reg \|= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK)	253	ccr_reg \|= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK)
254	<< STM32_QSPI_CCR_DCYC_SHIFT);	254	<< STM32_QSPI_CCR_DCYC_SHIFT);
255		255
256	if (priv->command & CMD_HAS_ADR) {	256	if (priv->command & CMD_HAS_ADR) {
257	ccr_reg \|= (STM32_QSPI_CCR_ADSIZE_24BIT	257	ccr_reg \|= (STM32_QSPI_CCR_ADSIZE_24BIT
258	<< STM32_QSPI_CCR_ADSIZE_SHIFT);	258	<< STM32_QSPI_CCR_ADSIZE_SHIFT);
259	ccr_reg \|= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);	259	ccr_reg \|= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
260	}	260	}
261		261
262	ccr_reg \|= (fmode << STM32_QSPI_CCR_FMODE_SHIFT);	262	ccr_reg \|= (fmode << STM32_QSPI_CCR_FMODE_SHIFT);
263	ccr_reg \|= (imode << STM32_QSPI_CCR_IMODE_SHIFT);	263	ccr_reg \|= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
264	ccr_reg \|= cmd;	264	ccr_reg \|= cmd;
265		265
266	return ccr_reg;	266	return ccr_reg;
267	}	267	}
268		268
269	static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,	269	static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
270	struct spi_flash *flash)	270	struct spi_flash *flash)
271	{	271	{
272	unsigned int ccr_reg;	272	unsigned int ccr_reg;
273		273
274	priv->command = flash->read_cmd \| CMD_HAS_ADR \| CMD_HAS_DATA	274	priv->command = flash->read_opcode \| CMD_HAS_ADR \| CMD_HAS_DATA
275	\| CMD_HAS_DUMMY;	275	\| CMD_HAS_DUMMY;
276	priv->dummycycles = flash->dummy_byte * 8;	276	priv->dummycycles = flash->read_dummy;
277		277
278	ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_MEM_MAP);	278	ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_MEM_MAP);
279		279
280	_stm32_qspi_wait_for_not_busy(priv);	280	_stm32_qspi_wait_for_not_busy(priv);
281		281
282	writel(ccr_reg, &priv->regs->ccr);	282	writel(ccr_reg, &priv->regs->ccr);
283		283
284	priv->dummycycles = 0;	284	priv->dummycycles = 0;
285	}	285	}
286		286
287	static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv)	287	static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv)
288	{	288	{
289	setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);	289	setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
290	}	290	}
291		291
292	static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv,	292	static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv,
293	u32 length)	293	u32 length)
294	{	294	{
295	writel(length - 1, &priv->regs->dlr);	295	writel(length - 1, &priv->regs->dlr);
296	}	296	}
297		297
298	static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)	298	static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
299	{	299	{
300	writel(cr_reg, &priv->regs->ccr);	300	writel(cr_reg, &priv->regs->ccr);
301		301
302	if (priv->command & CMD_HAS_ADR)	302	if (priv->command & CMD_HAS_ADR)
303	writel(priv->address, &priv->regs->ar);	303	writel(priv->address, &priv->regs->ar);
304	}	304	}
305		305
306	static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,	306	static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
307	struct spi_flash *flash, unsigned int bitlen,	307	struct spi_flash *flash, unsigned int bitlen,
308	const u8 dout, u8 din, unsigned long flags)	308	const u8 dout, u8 din, unsigned long flags)
309	{	309	{
310	unsigned int words = bitlen / 8;	310	unsigned int words = bitlen / 8;
311	u32 ccr_reg;	311	u32 ccr_reg;
312	int i;	312	int i;
313		313
314	if (flags & SPI_XFER_MMAP) {	314	if (flags & SPI_XFER_MMAP) {
315	_stm32_qspi_enable_mmap(priv, flash);	315	_stm32_qspi_enable_mmap(priv, flash);
316	return 0;	316	return 0;
317	} else if (flags & SPI_XFER_MMAP_END) {	317	} else if (flags & SPI_XFER_MMAP_END) {
318	_stm32_qspi_disable_mmap(priv);	318	_stm32_qspi_disable_mmap(priv);
319	return 0;	319	return 0;
320	}	320	}
321		321
322	if (bitlen == 0)	322	if (bitlen == 0)
323	return -1;	323	return -1;
324		324
325	if (bitlen % 8) {	325	if (bitlen % 8) {
326	debug("spi_xfer: Non byte aligned SPI transfer\n");	326	debug("spi_xfer: Non byte aligned SPI transfer\n");
327	return -1;	327	return -1;
328	}	328	}
329		329
330	if (dout && din) {	330	if (dout && din) {
331	debug("spi_xfer: QSPI cannot have data in and data out set\n");	331	debug("spi_xfer: QSPI cannot have data in and data out set\n");
332	return -1;	332	return -1;
333	}	333	}
334		334
335	if (!dout && (flags & SPI_XFER_BEGIN)) {	335	if (!dout && (flags & SPI_XFER_BEGIN)) {
336	debug("spi_xfer: QSPI transfer must begin with command\n");	336	debug("spi_xfer: QSPI transfer must begin with command\n");
337	return -1;	337	return -1;
338	}	338	}
339		339
340	if (dout) {	340	if (dout) {
341	if (flags & SPI_XFER_BEGIN) {	341	if (flags & SPI_XFER_BEGIN) {
342	/* data is command */	342	/* data is command */
343	priv->command = dout[0] \| CMD_HAS_DATA;	343	priv->command = dout[0] \| CMD_HAS_DATA;
344	if (words >= 4) {	344	if (words >= 4) {
345	/* address is here too */	345	/* address is here too */
346	priv->address = (dout[1] << 16) \|	346	priv->address = (dout[1] << 16) \|
347	(dout[2] << 8) \| dout[3];	347	(dout[2] << 8) \| dout[3];
348	priv->command \|= CMD_HAS_ADR;	348	priv->command \|= CMD_HAS_ADR;
349	}	349	}
350		350
351	if (words > 4) {	351	if (words > 4) {
352	/* rest is dummy bytes */	352	/* rest is dummy bytes */
353	priv->dummycycles = (words - 4) * 8;	353	priv->dummycycles = (words - 4) * 8;
354	priv->command \|= CMD_HAS_DUMMY;	354	priv->command \|= CMD_HAS_DUMMY;
355	}	355	}
356		356
357	if (flags & SPI_XFER_END) {	357	if (flags & SPI_XFER_END) {
358	/* command without data */	358	/* command without data */
359	priv->command &= ~(CMD_HAS_DATA);	359	priv->command &= ~(CMD_HAS_DATA);
360	}	360	}
361	}	361	}
362		362
363	if (flags & SPI_XFER_END) {	363	if (flags & SPI_XFER_END) {
364	ccr_reg = _stm32_qspi_gen_ccr(priv,	364	ccr_reg = _stm32_qspi_gen_ccr(priv,
365	STM32_QSPI_CCR_IND_WRITE);	365	STM32_QSPI_CCR_IND_WRITE);
366		366
367	_stm32_qspi_wait_for_not_busy(priv);	367	_stm32_qspi_wait_for_not_busy(priv);
368		368
369	if (priv->command & CMD_HAS_DATA)	369	if (priv->command & CMD_HAS_DATA)
370	_stm32_qspi_set_xfer_length(priv, words);	370	_stm32_qspi_set_xfer_length(priv, words);
371		371
372	_stm32_qspi_start_xfer(priv, ccr_reg);	372	_stm32_qspi_start_xfer(priv, ccr_reg);
373		373
374	debug("%s: write: ccr:0x%08x adr:0x%08x\n",	374	debug("%s: write: ccr:0x%08x adr:0x%08x\n",
375	__func__, priv->regs->ccr, priv->regs->ar);	375	__func__, priv->regs->ccr, priv->regs->ar);
376		376
377	if (priv->command & CMD_HAS_DATA) {	377	if (priv->command & CMD_HAS_DATA) {
378	_stm32_qspi_wait_for_ftf(priv);	378	_stm32_qspi_wait_for_ftf(priv);
379		379
380	debug("%s: words:%d data:", __func__, words);	380	debug("%s: words:%d data:", __func__, words);
381		381
382	i = 0;	382	i = 0;
383	while (words > i) {	383	while (words > i) {
384	writeb(dout[i], &priv->regs->dr);	384	writeb(dout[i], &priv->regs->dr);
385	debug("%02x ", dout[i]);	385	debug("%02x ", dout[i]);
386	i++;	386	i++;
387	}	387	}
388	debug("\n");	388	debug("\n");
389		389
390	_stm32_qspi_wait_for_complete(priv);	390	_stm32_qspi_wait_for_complete(priv);
391	} else {	391	} else {
392	_stm32_qspi_wait_for_not_busy(priv);	392	_stm32_qspi_wait_for_not_busy(priv);
393	}	393	}
394	}	394	}
395	} else if (din) {	395	} else if (din) {
396	ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_IND_READ);	396	ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_IND_READ);
397		397
398	_stm32_qspi_wait_for_not_busy(priv);	398	_stm32_qspi_wait_for_not_busy(priv);
399		399
400	_stm32_qspi_set_xfer_length(priv, words);	400	_stm32_qspi_set_xfer_length(priv, words);
401		401
402	_stm32_qspi_start_xfer(priv, ccr_reg);	402	_stm32_qspi_start_xfer(priv, ccr_reg);
403		403
404	debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__,	404	debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__,
405	priv->regs->ccr, priv->regs->ar, priv->regs->dlr);	405	priv->regs->ccr, priv->regs->ar, priv->regs->dlr);
406		406
407	debug("%s: data:", __func__);	407	debug("%s: data:", __func__);
408		408
409	i = 0;	409	i = 0;
410	while (words > i) {	410	while (words > i) {
411	din[i] = readb(&priv->regs->dr);	411	din[i] = readb(&priv->regs->dr);
412	debug("%02x ", din[i]);	412	debug("%02x ", din[i]);
413	i++;	413	i++;
414	}	414	}
415	debug("\n");	415	debug("\n");
416	}	416	}
417		417
418	return 0;	418	return 0;
419	}	419	}
420		420
421	static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)	421	static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
422	{	422	{
423	struct resource res_regs, res_mem;	423	struct resource res_regs, res_mem;
424	struct stm32_qspi_platdata *plat = bus->platdata;	424	struct stm32_qspi_platdata *plat = bus->platdata;
425	int ret;	425	int ret;
426		426
427	ret = dev_read_resource_byname(bus, "qspi", &res_regs);	427	ret = dev_read_resource_byname(bus, "qspi", &res_regs);
428	if (ret) {	428	if (ret) {
429	debug("Error: can't get regs base addresses(ret = %d)!\n", ret);	429	debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
430	return -ENOMEM;	430	return -ENOMEM;
431	}	431	}
432	ret = dev_read_resource_byname(bus, "qspi_mm", &res_mem);	432	ret = dev_read_resource_byname(bus, "qspi_mm", &res_mem);
433	if (ret) {	433	if (ret) {
434	debug("Error: can't get mmap base address(ret = %d)!\n", ret);	434	debug("Error: can't get mmap base address(ret = %d)!\n", ret);
435	return -ENOMEM;	435	return -ENOMEM;
436	}	436	}
437		437
438	plat->max_hz = dev_read_u32_default(bus, "spi-max-frequency",	438	plat->max_hz = dev_read_u32_default(bus, "spi-max-frequency",
439	STM32_QSPI_DEFAULT_SCK_FREQ);	439	STM32_QSPI_DEFAULT_SCK_FREQ);
440		440
441	plat->base = res_regs.start;	441	plat->base = res_regs.start;
442	plat->memory_map = res_mem.start;	442	plat->memory_map = res_mem.start;
443		443
444	debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n",	444	debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n",
445	__func__,	445	__func__,
446	plat->base,	446	plat->base,
447	plat->memory_map,	447	plat->memory_map,
448	plat->max_hz	448	plat->max_hz
449	);	449	);
450		450
451	return 0;	451	return 0;
452	}	452	}
453		453
454	static int stm32_qspi_probe(struct udevice *bus)	454	static int stm32_qspi_probe(struct udevice *bus)
455	{	455	{
456	struct stm32_qspi_platdata *plat = dev_get_platdata(bus);	456	struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
457	struct stm32_qspi_priv *priv = dev_get_priv(bus);	457	struct stm32_qspi_priv *priv = dev_get_priv(bus);
458	struct dm_spi_bus *dm_spi_bus;	458	struct dm_spi_bus *dm_spi_bus;
459	struct clk clk;	459	struct clk clk;
460	struct reset_ctl reset_ctl;	460	struct reset_ctl reset_ctl;
461	int ret;	461	int ret;
462		462
463	dm_spi_bus = bus->uclass_priv;	463	dm_spi_bus = bus->uclass_priv;
464		464
465	dm_spi_bus->max_hz = plat->max_hz;	465	dm_spi_bus->max_hz = plat->max_hz;
466		466
467	priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base;	467	priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base;
468		468
469	priv->max_hz = plat->max_hz;	469	priv->max_hz = plat->max_hz;
470		470
471	ret = clk_get_by_index(bus, 0, &clk);	471	ret = clk_get_by_index(bus, 0, &clk);
472	if (ret < 0)	472	if (ret < 0)
473	return ret;	473	return ret;
474		474
475	ret = clk_enable(&clk);	475	ret = clk_enable(&clk);
476		476
477	if (ret) {	477	if (ret) {
478	dev_err(bus, "failed to enable clock\n");	478	dev_err(bus, "failed to enable clock\n");
479	return ret;	479	return ret;
480	}	480	}
481		481
482	priv->clock_rate = clk_get_rate(&clk);	482	priv->clock_rate = clk_get_rate(&clk);
483	if (priv->clock_rate < 0) {	483	if (priv->clock_rate < 0) {
484	clk_disable(&clk);	484	clk_disable(&clk);
485	return priv->clock_rate;	485	return priv->clock_rate;
486	}	486	}
487		487
488	ret = reset_get_by_index(bus, 0, &reset_ctl);	488	ret = reset_get_by_index(bus, 0, &reset_ctl);
489	if (ret) {	489	if (ret) {
490	if (ret != -ENOENT) {	490	if (ret != -ENOENT) {
491	dev_err(bus, "failed to get reset\n");	491	dev_err(bus, "failed to get reset\n");
492	clk_disable(&clk);	492	clk_disable(&clk);
493	return ret;	493	return ret;
494	}	494	}
495	} else {	495	} else {
496	/* Reset QSPI controller */	496	/* Reset QSPI controller */
497	reset_assert(&reset_ctl);	497	reset_assert(&reset_ctl);
498	udelay(2);	498	udelay(2);
499	reset_deassert(&reset_ctl);	499	reset_deassert(&reset_ctl);
500	}	500	}
501		501
502	setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);	502	setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
503		503
504	return 0;	504	return 0;
505	}	505	}
506		506
507	static int stm32_qspi_remove(struct udevice *bus)	507	static int stm32_qspi_remove(struct udevice *bus)
508	{	508	{
509	return 0;	509	return 0;
510	}	510	}
511		511
512	static int stm32_qspi_claim_bus(struct udevice *dev)	512	static int stm32_qspi_claim_bus(struct udevice *dev)
513	{	513	{
514	struct stm32_qspi_priv *priv;	514	struct stm32_qspi_priv *priv;
515	struct udevice *bus;	515	struct udevice *bus;
516	struct spi_flash *flash;	516	struct spi_flash *flash;
517	struct dm_spi_slave_platdata *slave_plat;	517	struct dm_spi_slave_platdata *slave_plat;
518		518
519	bus = dev->parent;	519	bus = dev->parent;
520	priv = dev_get_priv(bus);	520	priv = dev_get_priv(bus);
521	flash = dev_get_uclass_priv(dev);	521	flash = dev_get_uclass_priv(dev);
522	slave_plat = dev_get_parent_platdata(dev);	522	slave_plat = dev_get_parent_platdata(dev);
523		523
524	if (slave_plat->cs >= STM32_MAX_NORCHIP)	524	if (slave_plat->cs >= STM32_MAX_NORCHIP)
525	return -ENODEV;	525	return -ENODEV;
526		526
527	_stm32_qspi_set_cs(priv, slave_plat->cs);	527	_stm32_qspi_set_cs(priv, slave_plat->cs);
528		528
529	_stm32_qspi_set_flash_size(priv, flash->size);	529	_stm32_qspi_set_flash_size(priv, flash->size);
530		530
531	_stm32_qspi_enable(priv);	531	_stm32_qspi_enable(priv);
532		532
533	return 0;	533	return 0;
534	}	534	}
535		535
536	static int stm32_qspi_release_bus(struct udevice *dev)	536	static int stm32_qspi_release_bus(struct udevice *dev)
537	{	537	{
538	struct stm32_qspi_priv *priv;	538	struct stm32_qspi_priv *priv;
539	struct udevice *bus;	539	struct udevice *bus;
540		540
541	bus = dev->parent;	541	bus = dev->parent;
542	priv = dev_get_priv(bus);	542	priv = dev_get_priv(bus);
543		543
544	_stm32_qspi_disable(priv);	544	_stm32_qspi_disable(priv);
545		545
546	return 0;	546	return 0;
547	}	547	}
548		548
549	static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,	549	static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
550	const void dout, void din, unsigned long flags)	550	const void dout, void din, unsigned long flags)
551	{	551	{
552	struct stm32_qspi_priv *priv;	552	struct stm32_qspi_priv *priv;
553	struct udevice *bus;	553	struct udevice *bus;
554	struct spi_flash *flash;	554	struct spi_flash *flash;
555		555
556	bus = dev->parent;	556	bus = dev->parent;
557	priv = dev_get_priv(bus);	557	priv = dev_get_priv(bus);
558	flash = dev_get_uclass_priv(dev);	558	flash = dev_get_uclass_priv(dev);
559		559
560	return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout,	560	return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout,
561	(u8 *)din, flags);	561	(u8 *)din, flags);
562	}	562	}
563		563
564	static int stm32_qspi_set_speed(struct udevice *bus, uint speed)	564	static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
565	{	565	{
566	struct stm32_qspi_platdata *plat = bus->platdata;	566	struct stm32_qspi_platdata *plat = bus->platdata;
567	struct stm32_qspi_priv *priv = dev_get_priv(bus);	567	struct stm32_qspi_priv *priv = dev_get_priv(bus);
568	u32 qspi_clk = priv->clock_rate;	568	u32 qspi_clk = priv->clock_rate;
569	u32 prescaler = 255;	569	u32 prescaler = 255;
570	u32 csht;	570	u32 csht;
571		571
572	if (speed > plat->max_hz)	572	if (speed > plat->max_hz)
573	speed = plat->max_hz;	573	speed = plat->max_hz;
574		574
575	if (speed > 0) {	575	if (speed > 0) {
576	prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;	576	prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
577	if (prescaler > 255)	577	if (prescaler > 255)
578	prescaler = 255;	578	prescaler = 255;
579	else if (prescaler < 0)	579	else if (prescaler < 0)
580	prescaler = 0;	580	prescaler = 0;
581	}	581	}
582		582
583	csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);	583	csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
584	csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;	584	csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
585		585
586	_stm32_qspi_wait_for_not_busy(priv);	586	_stm32_qspi_wait_for_not_busy(priv);
587		587
588	clrsetbits_le32(&priv->regs->cr,	588	clrsetbits_le32(&priv->regs->cr,
589	STM32_QSPI_CR_PRESCALER_MASK <<	589	STM32_QSPI_CR_PRESCALER_MASK <<
590	STM32_QSPI_CR_PRESCALER_SHIFT,	590	STM32_QSPI_CR_PRESCALER_SHIFT,
591	prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);	591	prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
592		592
593	clrsetbits_le32(&priv->regs->dcr,	593	clrsetbits_le32(&priv->regs->dcr,
594	STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,	594	STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
595	csht << STM32_QSPI_DCR_CSHT_SHIFT);	595	csht << STM32_QSPI_DCR_CSHT_SHIFT);
596		596
597	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,	597	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
598	(qspi_clk / (prescaler + 1)));	598	(qspi_clk / (prescaler + 1)));
599		599
600	return 0;	600	return 0;
601	}	601	}
602		602
603	static int stm32_qspi_set_mode(struct udevice *bus, uint mode)	603	static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
604	{	604	{
605	struct stm32_qspi_priv *priv = dev_get_priv(bus);	605	struct stm32_qspi_priv *priv = dev_get_priv(bus);
606		606
607	_stm32_qspi_wait_for_not_busy(priv);	607	_stm32_qspi_wait_for_not_busy(priv);
608		608
609	if ((mode & SPI_CPHA) && (mode & SPI_CPOL))	609	if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
610	setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);	610	setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
611	else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))	611	else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
612	clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);	612	clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
613	else	613	else
614	return -ENODEV;	614	return -ENODEV;
615		615
616	if (mode & SPI_CS_HIGH)	616	if (mode & SPI_CS_HIGH)
617	return -ENODEV;	617	return -ENODEV;
618		618
619	if (mode & SPI_RX_QUAD)	619	if (mode & SPI_RX_QUAD)
620	priv->mode \|= SPI_RX_QUAD;	620	priv->mode \|= SPI_RX_QUAD;
621	else if (mode & SPI_RX_DUAL)	621	else if (mode & SPI_RX_DUAL)
622	priv->mode \|= SPI_RX_DUAL;	622	priv->mode \|= SPI_RX_DUAL;
623	else	623	else
624	priv->mode &= ~(SPI_RX_QUAD \| SPI_RX_DUAL);	624	priv->mode &= ~(SPI_RX_QUAD \| SPI_RX_DUAL);
625		625
626	if (mode & SPI_TX_QUAD)	626	if (mode & SPI_TX_QUAD)
627	priv->mode \|= SPI_TX_QUAD;	627	priv->mode \|= SPI_TX_QUAD;
628	else if (mode & SPI_TX_DUAL)	628	else if (mode & SPI_TX_DUAL)
629	priv->mode \|= SPI_TX_DUAL;	629	priv->mode \|= SPI_TX_DUAL;
630	else	630	else
631	priv->mode &= ~(SPI_TX_QUAD \| SPI_TX_DUAL);	631	priv->mode &= ~(SPI_TX_QUAD \| SPI_TX_DUAL);
632		632
633	debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);	633	debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
634		634
635	if (mode & SPI_RX_QUAD)	635	if (mode & SPI_RX_QUAD)
636	debug("quad, tx: ");	636	debug("quad, tx: ");
637	else if (mode & SPI_RX_DUAL)	637	else if (mode & SPI_RX_DUAL)
638	debug("dual, tx: ");	638	debug("dual, tx: ");
639	else	639	else
640	debug("single, tx: ");	640	debug("single, tx: ");
641		641
642	if (mode & SPI_TX_QUAD)	642	if (mode & SPI_TX_QUAD)
643	debug("quad\n");	643	debug("quad\n");
644	else if (mode & SPI_TX_DUAL)	644	else if (mode & SPI_TX_DUAL)
645	debug("dual\n");	645	debug("dual\n");
646	else	646	else
647	debug("single\n");	647	debug("single\n");
648		648
649	return 0;	649	return 0;
650	}	650	}
651		651
652	static const struct dm_spi_ops stm32_qspi_ops = {	652	static const struct dm_spi_ops stm32_qspi_ops = {
653	.claim_bus = stm32_qspi_claim_bus,	653	.claim_bus = stm32_qspi_claim_bus,
654	.release_bus = stm32_qspi_release_bus,	654	.release_bus = stm32_qspi_release_bus,
655	.xfer = stm32_qspi_xfer,	655	.xfer = stm32_qspi_xfer,
656	.set_speed = stm32_qspi_set_speed,	656	.set_speed = stm32_qspi_set_speed,
657	.set_mode = stm32_qspi_set_mode,	657	.set_mode = stm32_qspi_set_mode,
658	};	658	};
659		659
660	static const struct udevice_id stm32_qspi_ids[] = {	660	static const struct udevice_id stm32_qspi_ids[] = {
661	{ .compatible = "st,stm32-qspi" },	661	{ .compatible = "st,stm32-qspi" },
662	{ .compatible = "st,stm32f469-qspi" },	662	{ .compatible = "st,stm32f469-qspi" },
663	{ }	663	{ }
664	};	664	};
665		665
666	U_BOOT_DRIVER(stm32_qspi) = {	666	U_BOOT_DRIVER(stm32_qspi) = {
667	.name = "stm32_qspi",	667	.name = "stm32_qspi",
668	.id = UCLASS_SPI,	668	.id = UCLASS_SPI,
669	.of_match = stm32_qspi_ids,	669	.of_match = stm32_qspi_ids,
670	.ops = &stm32_qspi_ops,	670	.ops = &stm32_qspi_ops,
671	.ofdata_to_platdata = stm32_qspi_ofdata_to_platdata,	671	.ofdata_to_platdata = stm32_qspi_ofdata_to_platdata,
672	.platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata),	672	.platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata),
673	.priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),	673	.priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
674	.probe = stm32_qspi_probe,	674	.probe = stm32_qspi_probe,
675	.remove = stm32_qspi_remove,	675	.remove = stm32_qspi_remove,
676	};	676	};
677		677

include/spi_flash.h

Diff comments View file @ c4e8862

 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Common SPI flash Interface
  *
  * Copyright (C) 2008 Atmel Corporation
  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
  */
 #ifndef _SPI_FLASH_H_
 #define _SPI_FLASH_H_
 #include <dm.h>	/* Because we dereference struct udevice here */
 #include <linux/types.h>
+#include <linux/mtd/spi-nor.h>
 #ifndef CONFIG_SF_DEFAULT_SPEED
 # define CONFIG_SF_DEFAULT_SPEED	1000000
 #endif
 #ifndef CONFIG_SF_DEFAULT_MODE
 # define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
 #endif
 #ifndef CONFIG_SF_DEFAULT_CS
 # define CONFIG_SF_DEFAULT_CS		0
 #endif
 #ifndef CONFIG_SF_DEFAULT_BUS
 # define CONFIG_SF_DEFAULT_BUS		0
 #endif
 struct spi_slave;
-/**
- * struct spi_flash - SPI flash structure
- *
- * @spi:		SPI slave
- * @dev:		SPI flash device
- * @name:		Name of SPI flash
- * @dual_flash:		Indicates dual flash memories - dual stacked, parallel
- * @shift:		Flash shift useful in dual parallel
- * @flags:		Indication of spi flash flags
- * @size:		Total flash size
- * @page_size:		Write (page) size
- * @sector_size:	Sector size
- * @erase_size:		Erase size
- * @bank_read_cmd:	Bank read cmd
- * @bank_write_cmd:	Bank write cmd
- * @bank_curr:		Current flash bank
- * @erase_cmd:		Erase cmd 4K, 32K, 64K
- * @read_cmd:		Read cmd - Array Fast, Extn read and quad read.
- * @write_cmd:		Write cmd - page and quad program.
- * @dummy_byte:		Dummy cycles for read operation.
- * @memory_map:		Address of read-only SPI flash access
- * @flash_lock:		lock a region of the SPI Flash
- * @flash_unlock:	unlock a region of the SPI Flash
- * @flash_is_locked:	check if a region of the SPI Flash is completely locked
- * @read:		Flash read ops: Read len bytes at offset into buf
- *			Supported cmds: Fast Array Read
- * @write:		Flash write ops: Write len bytes from buf into offset
- *			Supported cmds: Page Program
- * @erase:		Flash erase ops: Erase len bytes from offset
- *			Supported cmds: Sector erase 4K, 32K, 64K
- * return 0 - Success, 1 - Failure
- */
-struct spi_flash {
-	struct spi_slave *spi;
-#ifdef CONFIG_DM_SPI_FLASH
-	struct udevice *dev;
-#endif
-	const char *name;
-	u8 dual_flash;
-	u8 shift;
-	u16 flags;
-	u32 size;
-	u32 page_size;
-	u32 sector_size;
-	u32 erase_size;
-#ifdef CONFIG_SPI_FLASH_BAR
-	u8 bank_read_cmd;
-	u8 bank_write_cmd;
-	u8 bank_curr;
-#endif
-	u8 erase_cmd;
-	u8 read_cmd;
-	u8 write_cmd;
-	u8 dummy_byte;
-	void *memory_map;
-	int (*flash_lock)(struct spi_flash *flash, u32 ofs, size_t len);
-	int (*flash_unlock)(struct spi_flash *flash, u32 ofs, size_t len);
-	int (*flash_is_locked)(struct spi_flash *flash, u32 ofs, size_t len);
-#ifndef CONFIG_DM_SPI_FLASH
-	/*
-	 * These are not strictly needed for driver model, but keep them here
-	 * while the transition is in progress.
-	 *
-	 * Normally each driver would provide its own operations, but for
-	 * SPI flash most chips use the same algorithms. One approach is
-	 * to create a 'common' SPI flash device which knows how to talk
-	 * to most devices, and then allow other drivers to be used instead
-	 * if required, perhaps with a way of scanning through the list to
-	 * find the driver that matches the device.
-	 */
-	int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
-	int (*write)(struct spi_flash *flash, u32 offset, size_t len,
-			const void *buf);
-	int (*erase)(struct spi_flash *flash, u32 offset, size_t len);
-#endif
-};
 struct dm_spi_flash_ops {
 	int (*read)(struct udevice *dev, u32 offset, size_t len, void *buf);
 	int (*write)(struct udevice *dev, u32 offset, size_t len,
 		     const void *buf);
 	int (*erase)(struct udevice *dev, u32 offset, size_t len);
 	/**
 	 * get_sw_write_prot() - Check state of software write-protect feature
 	 *
 	 * SPI flash chips can lock a region of the flash defined by a
 	 * 'protected area'. This function checks if this protected area is
 	 * defined.
 	 *
 	 * @dev:	SPI flash device
 	 * @return 0 if no region is write-protected, 1 if a region is
 	 *	write-protected, -ENOSYS if the driver does not implement this,
 	 *	other -ve value on error
 	 */
 	int (*get_sw_write_prot)(struct udevice *dev);
 };
 /* Access the serial operations for a device */
 #define sf_get_ops(dev) ((struct dm_spi_flash_ops *)(dev)->driver->ops)
 #ifdef CONFIG_DM_SPI_FLASH
 /**
  * spi_flash_read_dm() - Read data from SPI flash
  *
  * @dev:	SPI flash device
  * @offset:	Offset into device in bytes to read from
  * @len:	Number of bytes to read
  * @buf:	Buffer to put the data that is read
  * @return 0 if OK, -ve on error
  */
 int spi_flash_read_dm(struct udevice *dev, u32 offset, size_t len, void *buf);
 /**
  * spi_flash_write_dm() - Write data to SPI flash
  *
  * @dev:	SPI flash device
  * @offset:	Offset into device in bytes to write to
  * @len:	Number of bytes to write
  * @buf:	Buffer containing bytes to write
  * @return 0 if OK, -ve on error
  */
 int spi_flash_write_dm(struct udevice *dev, u32 offset, size_t len,
 		       const void *buf);
 /**
  * spi_flash_erase_dm() - Erase blocks of the SPI flash
  *
  * Note that @len must be a muiltiple of the flash sector size.
  *
  * @dev:	SPI flash device
  * @offset:	Offset into device in bytes to start erasing
  * @len:	Number of bytes to erase
  * @return 0 if OK, -ve on error
  */
 int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len);
 /**
  * spl_flash_get_sw_write_prot() - Check state of software write-protect feature
  *
  * SPI flash chips can lock a region of the flash defined by a
  * 'protected area'. This function checks if this protected area is
  * defined.
  *
  * @dev:	SPI flash device
  * @return 0 if no region is write-protected, 1 if a region is
  *	write-protected, -ENOSYS if the driver does not implement this,
  *	other -ve value on error
  */
 int spl_flash_get_sw_write_prot(struct udevice *dev);
 int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
 			   unsigned int max_hz, unsigned int spi_mode,
 			   struct udevice **devp);
 /* Compatibility function - this is the old U-Boot API */
 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 				  unsigned int max_hz, unsigned int spi_mode);
 /* Compatibility function - this is the old U-Boot API */
 void spi_flash_free(struct spi_flash *flash);
 static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
 				 size_t len, void *buf)
 {
 	return spi_flash_read_dm(flash->dev, offset, len, buf);
 }
 static inline int spi_flash_write(struct spi_flash *flash, u32 offset,
 				  size_t len, const void *buf)
 {
 	return spi_flash_write_dm(flash->dev, offset, len, buf);
 }
 static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
 				  size_t len)
 {
 	return spi_flash_erase_dm(flash->dev, offset, len);
 }
 struct sandbox_state;
 int sandbox_sf_bind_emul(struct sandbox_state *state, int busnum, int cs,
 			 struct udevice *bus, ofnode node, const char *spec);
 void sandbox_sf_unbind_emul(struct sandbox_state *state, int busnum, int cs);
 #else
 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 		unsigned int max_hz, unsigned int spi_mode);
 void spi_flash_free(struct spi_flash *flash);
 static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
 		size_t len, void *buf)
 {
-	return flash->read(flash, offset, len, buf);
+	struct mtd_info *mtd = &flash->mtd;
+	size_t retlen;
+	return mtd->_read(mtd, offset, len, &retlen, buf);
 }
 static inline int spi_flash_write(struct spi_flash *flash, u32 offset,
 		size_t len, const void *buf)
 {
-	return flash->write(flash, offset, len, buf);
+	struct mtd_info *mtd = &flash->mtd;
+	size_t retlen;
+	return mtd->_write(mtd, offset, len, &retlen, buf);
 }
 static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
 		size_t len)
 {
-	return flash->erase(flash, offset, len);
+	struct mtd_info *mtd = &flash->mtd;
+	struct erase_info instr;
+	if (offset % mtd->erasesize || len % mtd->erasesize) {
+		printf("SF: Erase offset/length not multiple of erase size\n");
+		return -EINVAL;
+	}
+	memset(&instr, 0, sizeof(instr));
+	instr.addr = offset;
+	instr.len = len;

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