Eric Lee / smarc-uboot

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Commit c4e8862308d420e85c227498797c32410d9e47a8

Authored by Vignesh R
Committed by Jagan Teki
1 parent 2ee6705be0
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

mtd: spi: Switch to new SPI NOR framework 

Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/definitions

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

Showing 9 changed files with 113 additions and 365 deletions Side-by-side Diff

drivers/mtd/spi/Kconfig
Diff comments   View file @ c4e8862
... ... @@ -27,6 +27,8 @@
27 27  
28 28 config SPI_FLASH
29 29 bool "Legacy SPI Flash Interface support"
  30 + depends on SPI
  31 + select SPI_MEM
30 32 help
31 33 Enable the legacy SPI flash support. This will include basic
32 34 standard support for things like probing, read / write, and
drivers/mtd/spi/Makefile
Diff comments   View file @ c4e8862
... ... @@ -9,8 +9,8 @@
9 9 obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
10 10 endif
11 11  
12   -obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o spi_flash_ids.o sf.o
13   -obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
  12 +obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi-nor-core.o
  13 +obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o sf.o
14 14 obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
15 15 obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
drivers/mtd/spi/sandbox.c
Diff comments   View file @ c4e8862
... ... @@ -92,7 +92,7 @@
92 92 /* The current flash status (see STAT_XXX defines above) */
93 93 u16 status;
94 94 /* Data describing the flash we're emulating */
95   - const struct spi_flash_info *data;
  95 + const struct flash_info *data;
96 96 /* The file on disk to serv up data from */
97 97 int fd;
98 98 };
... ... @@ -122,7 +122,7 @@
122 122 /* spec = idcode:file */
123 123 struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
124 124 size_t len, idname_len;
125   - const struct spi_flash_info *data;
  125 + const struct flash_info *data;
126 126 struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
127 127 struct sandbox_state *state = state_get_current();
128 128 struct dm_spi_slave_platdata *slave_plat;
... ... @@ -155,7 +155,7 @@
155 155 idname_len = strlen(spec);
156 156 debug("%s: device='%s'\n", __func__, spec);
157 157  
158   - for (data = spi_flash_ids; data->name; data++) {
  158 + for (data = spi_nor_ids; data->name; data++) {
159 159 len = strlen(data->name);
160 160 if (idname_len != len)
161 161 continue;
162 162  
163 163  
164 164  
165 165  
166 166  
167 167  
168 168  
169 169  
170 170  
171 171  
... ... @@ -243,43 +243,43 @@
243 243  
244 244 sbsf->cmd = rx[0];
245 245 switch (sbsf->cmd) {
246   - case CMD_READ_ID:
  246 + case SPINOR_OP_RDID:
247 247 sbsf->state = SF_ID;
248 248 sbsf->cmd = SF_ID;
249 249 break;
250   - case CMD_READ_ARRAY_FAST:
  250 + case SPINOR_OP_READ_FAST:
251 251 sbsf->pad_addr_bytes = 1;
252   - case CMD_READ_ARRAY_SLOW:
253   - case CMD_PAGE_PROGRAM:
  252 + case SPINOR_OP_READ:
  253 + case SPINOR_OP_PP:
254 254 sbsf->state = SF_ADDR;
255 255 break;
256   - case CMD_WRITE_DISABLE:
  256 + case SPINOR_OP_WRDI:
257 257 debug(" write disabled\n");
258 258 sbsf->status &= ~STAT_WEL;
259 259 break;
260   - case CMD_READ_STATUS:
  260 + case SPINOR_OP_RDSR:
261 261 sbsf->state = SF_READ_STATUS;
262 262 break;
263   - case CMD_READ_STATUS1:
  263 + case SPINOR_OP_RDSR2:
264 264 sbsf->state = SF_READ_STATUS1;
265 265 break;
266   - case CMD_WRITE_ENABLE:
  266 + case SPINOR_OP_WREN:
267 267 debug(" write enabled\n");
268 268 sbsf->status |= STAT_WEL;
269 269 break;
270   - case CMD_WRITE_STATUS:
  270 + case SPINOR_OP_WRSR:
271 271 sbsf->state = SF_WRITE_STATUS;
272 272 break;
273 273 default: {
274 274 int flags = sbsf->data->flags;
275 275  
276 276 /* we only support erase here */
277   - if (sbsf->cmd == CMD_ERASE_CHIP) {
  277 + if (sbsf->cmd == SPINOR_OP_CHIP_ERASE) {
278 278 sbsf->erase_size = sbsf->data->sector_size *
279 279 sbsf->data->n_sectors;
280   - } else if (sbsf->cmd == CMD_ERASE_4K && (flags & SECT_4K)) {
  280 + } else if (sbsf->cmd == SPINOR_OP_BE_4K && (flags & SECT_4K)) {
281 281 sbsf->erase_size = 4 << 10;
282   - } else if (sbsf->cmd == CMD_ERASE_64K && !(flags & SECT_4K)) {
  282 + } else if (sbsf->cmd == SPINOR_OP_SE && !(flags & SECT_4K)) {
283 283 sbsf->erase_size = 64 << 10;
284 284 } else {
285 285 debug(" cmd unknown: %#x\n", sbsf->cmd);
286 286  
... ... @@ -380,11 +380,11 @@
380 380 return -EIO;
381 381 }
382 382 switch (sbsf->cmd) {
383   - case CMD_READ_ARRAY_FAST:
384   - case CMD_READ_ARRAY_SLOW:
  383 + case SPINOR_OP_READ_FAST:
  384 + case SPINOR_OP_READ:
385 385 sbsf->state = SF_READ;
386 386 break;
387   - case CMD_PAGE_PROGRAM:
  387 + case SPINOR_OP_PP:
388 388 sbsf->state = SF_WRITE;
389 389 break;
390 390 default:
drivers/mtd/spi/sf_dataflash.c
Diff comments   View file @ c4e8862
... ... @@ -18,6 +18,7 @@
18 18  
19 19 #include "sf_internal.h"
20 20  
  21 +#define CMD_READ_ID 0x9f
21 22 /* reads can bypass the buffers */
22 23 #define OP_READ_CONTINUOUS 0xE8
23 24 #define OP_READ_PAGE 0xD2
... ... @@ -441,7 +442,7 @@
441 442 return 0;
442 443 }
443 444  
444   -struct flash_info {
  445 +struct data_flash_info {
445 446 char *name;
446 447  
447 448 /*
... ... @@ -460,7 +461,7 @@
460 461 #define IS_POW2PS 0x0001 /* uses 2^N byte pages */
461 462 };
462 463  
463   -static struct flash_info dataflash_data[] = {
  464 +static struct data_flash_info dataflash_data[] = {
464 465 /*
465 466 * NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
466 467 * one with IS_POW2PS and the other without. The entry with the
467 468  
... ... @@ -501,12 +502,12 @@
501 502 { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
502 503 };
503 504  
504   -static struct flash_info *jedec_probe(struct spi_slave *spi)
  505 +static struct data_flash_info *jedec_probe(struct spi_slave *spi)
505 506 {
506 507 int tmp;
507 508 uint8_t id[5];
508 509 uint32_t jedec;
509   - struct flash_info *info;
  510 + struct data_flash_info *info;
510 511 int status;
511 512  
512 513 /*
... ... @@ -583,7 +584,7 @@
583 584 {
584 585 struct spi_slave *spi = dev_get_parent_priv(dev);
585 586 struct spi_flash *spi_flash;
586   - struct flash_info *info;
  587 + struct data_flash_info *info;
587 588 int status;
588 589  
589 590 spi_flash = dev_get_uclass_priv(dev);
drivers/mtd/spi/sf_internal.h
Diff comments   View file @ c4e8862
... ... @@ -12,143 +12,64 @@
12 12 #include <linux/types.h>
13 13 #include <linux/compiler.h>
14 14  
15   -/* Dual SPI flash memories - see SPI_COMM_DUAL_... */
16   -enum spi_dual_flash {
17   - SF_SINGLE_FLASH = 0,
18   - SF_DUAL_STACKED_FLASH = BIT(0),
19   - SF_DUAL_PARALLEL_FLASH = BIT(1),
20   -};
  15 +#define SPI_NOR_MAX_ID_LEN 6
  16 +#define SPI_NOR_MAX_ADDR_WIDTH 4
21 17  
22   -enum spi_nor_option_flags {
23   - SNOR_F_SST_WR = BIT(0),
24   - SNOR_F_USE_FSR = BIT(1),
25   - SNOR_F_USE_UPAGE = BIT(3),
26   -};
  18 +struct flash_info {
  19 + char *name;
27 20  
28   -#define SPI_FLASH_3B_ADDR_LEN 3
29   -#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
30   -#define SPI_FLASH_16MB_BOUN 0x1000000
31   -
32   -/* CFI Manufacture ID's */
33   -#define SPI_FLASH_CFI_MFR_SPANSION 0x01
34   -#define SPI_FLASH_CFI_MFR_STMICRO 0x20
35   -#define SPI_FLASH_CFI_MFR_MICRON 0x2C
36   -#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
37   -#define SPI_FLASH_CFI_MFR_SST 0xbf
38   -#define SPI_FLASH_CFI_MFR_WINBOND 0xef
39   -#define SPI_FLASH_CFI_MFR_ATMEL 0x1f
40   -
41   -/* Erase commands */
42   -#define CMD_ERASE_4K 0x20
43   -#define CMD_ERASE_CHIP 0xc7
44   -#define CMD_ERASE_64K 0xd8
45   -
46   -/* Write commands */
47   -#define CMD_WRITE_STATUS 0x01
48   -#define CMD_PAGE_PROGRAM 0x02
49   -#define CMD_WRITE_DISABLE 0x04
50   -#define CMD_WRITE_ENABLE 0x06
51   -#define CMD_QUAD_PAGE_PROGRAM 0x32
52   -
53   -/* Read commands */
54   -#define CMD_READ_ARRAY_SLOW 0x03
55   -#define CMD_READ_ARRAY_FAST 0x0b
56   -#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
57   -#define CMD_READ_DUAL_IO_FAST 0xbb
58   -#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
59   -#define CMD_READ_QUAD_IO_FAST 0xeb
60   -#define CMD_READ_ID 0x9f
61   -#define CMD_READ_STATUS 0x05
62   -#define CMD_READ_STATUS1 0x35
63   -#define CMD_READ_CONFIG 0x35
64   -#define CMD_FLAG_STATUS 0x70
65   -
66   -/* Bank addr access commands */
67   -#ifdef CONFIG_SPI_FLASH_BAR
68   -# define CMD_BANKADDR_BRWR 0x17
69   -# define CMD_BANKADDR_BRRD 0x16
70   -# define CMD_EXTNADDR_WREAR 0xC5
71   -# define CMD_EXTNADDR_RDEAR 0xC8
72   -#endif
73   -
74   -/* Common status */
75   -#define STATUS_WIP BIT(0)
76   -#define STATUS_QEB_WINSPAN BIT(1)
77   -#define STATUS_QEB_MXIC BIT(6)
78   -#define STATUS_PEC BIT(7)
79   -#define SR_BP0 BIT(2) /* Block protect 0 */
80   -#define SR_BP1 BIT(3) /* Block protect 1 */
81   -#define SR_BP2 BIT(4) /* Block protect 2 */
82   -
83   -/* Flash timeout values */
84   -#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
85   -#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
86   -#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
87   -
88   -/* SST specific */
89   -#ifdef CONFIG_SPI_FLASH_SST
90   -#define SST26_CMD_READ_BPR 0x72
91   -#define SST26_CMD_WRITE_BPR 0x42
92   -
93   -#define SST26_BPR_8K_NUM 4
94   -#define SST26_MAX_BPR_REG_LEN (18 + 1)
95   -#define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
96   -
97   -enum lock_ctl {
98   - SST26_CTL_LOCK,
99   - SST26_CTL_UNLOCK,
100   - SST26_CTL_CHECK
101   -};
102   -
103   -# define CMD_SST_BP 0x02 /* Byte Program */
104   -# define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
105   -
106   -int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
107   - const void *buf);
108   -int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
109   - const void *buf);
110   -#endif
111   -
112   -#define JEDEC_MFR(info) ((info)->id[0])
113   -#define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
114   -#define JEDEC_EXT(info) (((info)->id[3]) << 8 | ((info)->id[4]))
115   -#define SPI_FLASH_MAX_ID_LEN 6
116   -
117   -struct spi_flash_info {
118   - /* Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) */
119   - const char *name;
120   -
121 21 /*
122 22 * This array stores the ID bytes.
123 23 * The first three bytes are the JEDIC ID.
124 24 * JEDEC ID zero means "no ID" (mostly older chips).
125 25 */
126   - u8 id[SPI_FLASH_MAX_ID_LEN];
  26 + u8 id[SPI_NOR_MAX_ID_LEN];
127 27 u8 id_len;
128 28  
129   - /*
130   - * The size listed here is what works with SPINOR_OP_SE, which isn't
  29 + /* The size listed here is what works with SPINOR_OP_SE, which isn't
131 30 * necessarily called a "sector" by the vendor.
132 31 */
133   - u32 sector_size;
134   - u32 n_sectors;
  32 + unsigned int sector_size;
  33 + u16 n_sectors;
135 34  
136 35 u16 page_size;
  36 + u16 addr_width;
137 37  
138 38 u16 flags;
139   -#define SECT_4K BIT(0) /* CMD_ERASE_4K works uniformly */
140   -#define E_FSR BIT(1) /* use flag status register for */
141   -#define SST_WR BIT(2) /* use SST byte/word programming */
142   -#define WR_QPP BIT(3) /* use Quad Page Program */
143   -#define RD_QUAD BIT(4) /* use Quad Read */
144   -#define RD_DUAL BIT(5) /* use Dual Read */
145   -#define RD_QUADIO BIT(6) /* use Quad IO Read */
146   -#define RD_DUALIO BIT(7) /* use Dual IO Read */
147   -#define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO)
  39 +#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
  40 +#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
  41 +#define SST_WRITE BIT(2) /* use SST byte programming */
  42 +#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
  43 +#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
  44 +#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
  45 +#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
  46 +#define USE_FSR BIT(7) /* use flag status register */
  47 +#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
  48 +#define SPI_NOR_HAS_TB BIT(9) /*
  49 + * Flash SR has Top/Bottom (TB) protect
  50 + * bit. Must be used with
  51 + * SPI_NOR_HAS_LOCK.
  52 + */
  53 +#define SPI_S3AN BIT(10) /*
  54 + * Xilinx Spartan 3AN In-System Flash
  55 + * (MFR cannot be used for probing
  56 + * because it has the same value as
  57 + * ATMEL flashes)
  58 + */
  59 +#define SPI_NOR_4B_OPCODES BIT(11) /*
  60 + * Use dedicated 4byte address op codes
  61 + * to support memory size above 128Mib.
  62 + */
  63 +#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
  64 +#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
  65 +#define USE_CLSR BIT(14) /* use CLSR command */
148 66 };
149 67  
150   -extern const struct spi_flash_info spi_flash_ids[];
  68 +extern const struct flash_info spi_nor_ids[];
151 69  
  70 +#define JEDEC_MFR(info) ((info)->id[0])
  71 +#define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
  72 +
152 73 /* Send a single-byte command to the device and read the response */
153 74 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
154 75  
155 76  
156 77  
157 78  
... ... @@ -167,79 +88,13 @@
167 88 const void *data, size_t data_len);
168 89  
169 90  
170   -/* Flash erase(sectors) operation, support all possible erase commands */
171   -int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
172   -
173 91 /* Get software write-protect value (BP bits) */
174 92 int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash);
175 93  
176   -/* Lock stmicro spi flash region */
177   -int stm_lock(struct spi_flash *flash, u32 ofs, size_t len);
178 94  
179   -/* Unlock stmicro spi flash region */
180   -int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len);
181   -
182   -/* Check if a stmicro spi flash region is completely locked */
183   -int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len);
184   -
185   -/* Enable writing on the SPI flash */
186   -static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
187   -{
188   - return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
189   -}
190   -
191   -/* Disable writing on the SPI flash */
192   -static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
193   -{
194   - return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
195   -}
196   -
197   -/*
198   - * Used for spi_flash write operation
199   - * - SPI claim
200   - * - spi_flash_cmd_write_enable
201   - * - spi_flash_cmd_write
202   - * - spi_flash_wait_till_ready
203   - * - SPI release
204   - */
205   -int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
206   - size_t cmd_len, const void *buf, size_t buf_len);
207   -
208   -/*
209   - * Flash write operation, support all possible write commands.
210   - * Write the requested data out breaking it up into multiple write
211   - * commands as needed per the write size.
212   - */
213   -int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
214   - size_t len, const void *buf);
215   -
216   -/*
217   - * Same as spi_flash_cmd_read() except it also claims/releases the SPI
218   - * bus. Used as common part of the ->read() operation.
219   - */
220   -int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
221   - size_t cmd_len, void *data, size_t data_len);
222   -
223   -/* Flash read operation, support all possible read commands */
224   -int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
225   - size_t len, void *data);
226   -
227 95 #ifdef CONFIG_SPI_FLASH_MTD
228 96 int spi_flash_mtd_register(struct spi_flash *flash);
229 97 void spi_flash_mtd_unregister(void);
230 98 #endif
231   -
232   -/**
233   - * spi_flash_scan - scan the SPI FLASH
234   - * @flash: the spi flash structure
235   - *
236   - * The drivers can use this fuction to scan the SPI FLASH.
237   - * In the scanning, it will try to get all the necessary information to
238   - * fill the spi_flash{}.
239   - *
240   - * Return: 0 for success, others for failure.
241   - */
242   -int spi_flash_scan(struct spi_flash *flash);
243   -
244 99 #endif /* _SF_INTERNAL_H_ */
drivers/mtd/spi/sf_probe.c
Diff comments   View file @ c4e8862
... ... @@ -40,7 +40,7 @@
40 40 return ret;
41 41 }
42 42  
43   - ret = spi_flash_scan(flash);
  43 + ret = spi_nor_scan(flash);
44 44 if (ret)
45 45 goto err_read_id;
46 46  
47 47  
48 48  
49 49  
50 50  
51 51  
... ... @@ -96,32 +96,38 @@
96 96 void *buf)
97 97 {
98 98 struct spi_flash *flash = dev_get_uclass_priv(dev);
  99 + struct mtd_info *mtd = &flash->mtd;
  100 + size_t retlen;
99 101  
100   - return log_ret(spi_flash_cmd_read_ops(flash, offset, len, buf));
  102 + return log_ret(mtd->_read(mtd, offset, len, &retlen, buf));
101 103 }
102 104  
103 105 static int spi_flash_std_write(struct udevice *dev, u32 offset, size_t len,
104 106 const void *buf)
105 107 {
106 108 struct spi_flash *flash = dev_get_uclass_priv(dev);
  109 + struct mtd_info *mtd = &flash->mtd;
  110 + size_t retlen;
107 111  
108   -#if defined(CONFIG_SPI_FLASH_SST)
109   - if (flash->flags & SNOR_F_SST_WR) {
110   - if (flash->spi->mode & SPI_TX_BYTE)
111   - return sst_write_bp(flash, offset, len, buf);
112   - else
113   - return sst_write_wp(flash, offset, len, buf);
114   - }
115   -#endif
116   -
117   - return spi_flash_cmd_write_ops(flash, offset, len, buf);
  112 + return mtd->_write(mtd, offset, len, &retlen, buf);
118 113 }
119 114  
120 115 static int spi_flash_std_erase(struct udevice *dev, u32 offset, size_t len)
121 116 {
122 117 struct spi_flash *flash = dev_get_uclass_priv(dev);
  118 + struct mtd_info *mtd = &flash->mtd;
  119 + struct erase_info instr;
123 120  
124   - return spi_flash_cmd_erase_ops(flash, offset, len);
  121 + if (offset % mtd->erasesize || len % mtd->erasesize) {
  122 + printf("SF: Erase offset/length not multiple of erase size\n");
  123 + return -EINVAL;
  124 + }
  125 +
  126 + memset(&instr, 0, sizeof(instr));
  127 + instr.addr = offset;
  128 + instr.len = len;
  129 +
  130 + return mtd->_erase(mtd, &instr);
125 131 }
126 132  
127 133 static int spi_flash_std_get_sw_write_prot(struct udevice *dev)
drivers/mtd/spi/spi-nor-core.c
Diff comments   View file @ c4e8862
... ... @@ -21,6 +21,8 @@
21 21 #include <spi-mem.h>
22 22 #include <spi.h>
23 23  
  24 +#include "sf_internal.h"
  25 +
24 26 /* Define max times to check status register before we give up. */
25 27  
26 28 /*
... ... @@ -31,63 +33,6 @@
31 33 #define HZ CONFIG_SYS_HZ
32 34  
33 35 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
34   -
35   -#define SPI_NOR_MAX_ID_LEN 6
36   -#define SPI_NOR_MAX_ADDR_WIDTH 4
37   -
38   -struct flash_info {
39   - char *name;
40   -
41   - /*
42   - * This array stores the ID bytes.
43   - * The first three bytes are the JEDIC ID.
44   - * JEDEC ID zero means "no ID" (mostly older chips).
45   - */
46   - u8 id[SPI_NOR_MAX_ID_LEN];
47   - u8 id_len;
48   -
49   - /* The size listed here is what works with SPINOR_OP_SE, which isn't
50   - * necessarily called a "sector" by the vendor.
51   - */
52   - unsigned int sector_size;
53   - u16 n_sectors;
54   -
55   - u16 page_size;
56   - u16 addr_width;
57   -
58   - u16 flags;
59   -#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
60   -#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
61   -#define SST_WRITE BIT(2) /* use SST byte programming */
62   -#define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */
63   -#define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
64   -#define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
65   -#define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
66   -#define USE_FSR BIT(7) /* use flag status register */
67   -#define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
68   -#define SPI_NOR_HAS_TB BIT(9) /*
69   - * Flash SR has Top/Bottom (TB) protect
70   - * bit. Must be used with
71   - * SPI_NOR_HAS_LOCK.
72   - */
73   -#define SPI_S3AN BIT(10) /*
74   - * Xilinx Spartan 3AN In-System Flash
75   - * (MFR cannot be used for probing
76   - * because it has the same value as
77   - * ATMEL flashes)
78   - */
79   -#define SPI_NOR_4B_OPCODES BIT(11) /*
80   - * Use dedicated 4byte address op codes
81   - * to support memory size above 128Mib.
82   - */
83   -#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
84   -#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
85   -#define USE_CLSR BIT(14) /* use CLSR command */
86   -
87   - int (*quad_enable)(struct spi_nor *nor);
88   -};
89   -
90   -#define JEDEC_MFR(info) ((info)->id[0])
91 36  
92 37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
93 38 *op, void *buf)
drivers/spi/stm32_qspi.c
Diff comments   View file @ c4e8862
... ... @@ -271,9 +271,9 @@
271 271 {
272 272 unsigned int ccr_reg;
273 273  
274   - priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA
  274 + priv->command = flash->read_opcode | CMD_HAS_ADR | CMD_HAS_DATA
275 275 | CMD_HAS_DUMMY;
276   - priv->dummycycles = flash->dummy_byte * 8;
  276 + priv->dummycycles = flash->read_dummy;
277 277  
278 278 ccr_reg = _stm32_qspi_gen_ccr(priv, STM32_QSPI_CCR_MEM_MAP);
279 279  
... ... @@ -11,6 +11,7 @@
11 11  
12 12 #include <dm.h> /* Because we dereference struct udevice here */
13 13 #include <linux/types.h>
  14 +#include <linux/mtd/spi-nor.h>
14 15  
15 16 #ifndef CONFIG_SF_DEFAULT_SPEED
16 17 # define CONFIG_SF_DEFAULT_SPEED 1000000
... ... @@ -27,86 +28,6 @@
27 28  
28 29 struct spi_slave;
29 30  
30   -/**
31   - * struct spi_flash - SPI flash structure
32   - *
33   - * @spi: SPI slave
34   - * @dev: SPI flash device
35   - * @name: Name of SPI flash
36   - * @dual_flash: Indicates dual flash memories - dual stacked, parallel
37   - * @shift: Flash shift useful in dual parallel
38   - * @flags: Indication of spi flash flags
39   - * @size: Total flash size
40   - * @page_size: Write (page) size
41   - * @sector_size: Sector size
42   - * @erase_size: Erase size
43   - * @bank_read_cmd: Bank read cmd
44   - * @bank_write_cmd: Bank write cmd
45   - * @bank_curr: Current flash bank
46   - * @erase_cmd: Erase cmd 4K, 32K, 64K
47   - * @read_cmd: Read cmd - Array Fast, Extn read and quad read.
48   - * @write_cmd: Write cmd - page and quad program.
49   - * @dummy_byte: Dummy cycles for read operation.
50   - * @memory_map: Address of read-only SPI flash access
51   - * @flash_lock: lock a region of the SPI Flash
52   - * @flash_unlock: unlock a region of the SPI Flash
53   - * @flash_is_locked: check if a region of the SPI Flash is completely locked
54   - * @read: Flash read ops: Read len bytes at offset into buf
55   - * Supported cmds: Fast Array Read
56   - * @write: Flash write ops: Write len bytes from buf into offset
57   - * Supported cmds: Page Program
58   - * @erase: Flash erase ops: Erase len bytes from offset
59   - * Supported cmds: Sector erase 4K, 32K, 64K
60   - * return 0 - Success, 1 - Failure
61   - */
62   -struct spi_flash {
63   - struct spi_slave *spi;
64   -#ifdef CONFIG_DM_SPI_FLASH
65   - struct udevice *dev;
66   -#endif
67   - const char *name;
68   - u8 dual_flash;
69   - u8 shift;
70   - u16 flags;
71   -
72   - u32 size;
73   - u32 page_size;
74   - u32 sector_size;
75   - u32 erase_size;
76   -#ifdef CONFIG_SPI_FLASH_BAR
77   - u8 bank_read_cmd;
78   - u8 bank_write_cmd;
79   - u8 bank_curr;
80   -#endif
81   - u8 erase_cmd;
82   - u8 read_cmd;
83   - u8 write_cmd;
84   - u8 dummy_byte;
85   -
86   - void *memory_map;
87   -
88   - int (*flash_lock)(struct spi_flash *flash, u32 ofs, size_t len);
89   - int (*flash_unlock)(struct spi_flash *flash, u32 ofs, size_t len);
90   - int (*flash_is_locked)(struct spi_flash *flash, u32 ofs, size_t len);
91   -#ifndef CONFIG_DM_SPI_FLASH
92   - /*
93   - * These are not strictly needed for driver model, but keep them here
94   - * while the transition is in progress.
95   - *
96   - * Normally each driver would provide its own operations, but for
97   - * SPI flash most chips use the same algorithms. One approach is
98   - * to create a 'common' SPI flash device which knows how to talk
99   - * to most devices, and then allow other drivers to be used instead
100   - * if required, perhaps with a way of scanning through the list to
101   - * find the driver that matches the device.
102   - */
103   - int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
104   - int (*write)(struct spi_flash *flash, u32 offset, size_t len,
105   - const void *buf);
106   - int (*erase)(struct spi_flash *flash, u32 offset, size_t len);
107   -#endif
108   -};
109   -
110 31 struct dm_spi_flash_ops {
111 32 int (*read)(struct udevice *dev, u32 offset, size_t len, void *buf);
112 33 int (*write)(struct udevice *dev, u32 offset, size_t len,
113 34  
114 35  
... ... @@ -225,19 +146,37 @@
225 146 static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
226 147 size_t len, void *buf)
227 148 {
228   - return flash->read(flash, offset, len, buf);
  149 + struct mtd_info *mtd = &flash->mtd;
  150 + size_t retlen;
  151 +
  152 + return mtd->_read(mtd, offset, len, &retlen, buf);
229 153 }
230 154  
231 155 static inline int spi_flash_write(struct spi_flash *flash, u32 offset,
232 156 size_t len, const void *buf)
233 157 {
234   - return flash->write(flash, offset, len, buf);
  158 + struct mtd_info *mtd = &flash->mtd;
  159 + size_t retlen;
  160 +
  161 + return mtd->_write(mtd, offset, len, &retlen, buf);
235 162 }
236 163  
237 164 static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
238 165 size_t len)
239 166 {
240   - return flash->erase(flash, offset, len);
  167 + struct mtd_info *mtd = &flash->mtd;
  168 + struct erase_info instr;
  169 +
  170 + if (offset % mtd->erasesize || len % mtd->erasesize) {
  171 + printf("SF: Erase offset/length not multiple of erase size\n");
  172 + return -EINVAL;
  173 + }
  174 +
  175 + memset(&instr, 0, sizeof(instr));
  176 + instr.addr = offset;
  177 + instr.len = len;
  178 +
  179 + return mtd->_erase(mtd, &instr);
241 180 }
242 181 #endif
243 182