Eric Lee / smarc-uboot

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Commit c534d2fdcf7aa80230a0f1ed54d5e3164ba595eb

Authored by Albert ARIBAUD
2 parents 10dc77716f 9f9d41bad1
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'

Showing 25 changed files Side-by-side Diff

... ... @@ -752,6 +752,9 @@
752 752 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
753 753 ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
754 754 ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin
  755 +ifeq ($(CONFIG_SPL_FRAMEWORK),y)
  756 +ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img
  757 +endif
755 758 ALL-$(CONFIG_OF_HOSTFILE) += u-boot.dtb
756 759 ifneq ($(CONFIG_SPL_TARGET),)
757 760 ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
... ... @@ -852,6 +855,11 @@
852 855 -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
853 856  
854 857 u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
  858 + $(call if_changed,mkimage)
  859 +
  860 +MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
  861 +
  862 +u-boot-dtb.img: u-boot-dtb.bin FORCE
855 863 $(call if_changed,mkimage)
856 864  
857 865 u-boot.sha1: u-boot.bin
arch/arm/cpu/armv7/zynq/cpu.c
Diff comments   View file @ c534d2f
... ... @@ -14,6 +14,9 @@
14 14 {
15 15 }
16 16  
  17 +#define ZYNQ_SILICON_VER_MASK 0xF0000000
  18 +#define ZYNQ_SILICON_VER_SHIFT 28
  19 +
17 20 int arch_cpu_init(void)
18 21 {
19 22 zynq_slcr_unlock();
... ... @@ -40,6 +43,16 @@
40 43 zynq_slcr_lock();
41 44  
42 45 return 0;
  46 +}
  47 +
  48 +unsigned int zynq_get_silicon_version(void)
  49 +{
  50 + unsigned int ver;
  51 +
  52 + ver = (readl(&devcfg_base->mctrl) &
  53 + ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT;
  54 +
  55 + return ver;
43 56 }
44 57  
45 58 void reset_cpu(ulong addr)
arch/arm/cpu/armv7/zynq/ddrc.c
Diff comments   View file @ c534d2f
... ... @@ -40,12 +40,9 @@
40 40 * first stage bootloader. To get ECC to work all memory has
41 41 * been initialized by writing any value.
42 42 */
43   - memset(0, 0, 1 * 1024 * 1024);
  43 + memset((void *)0, 0, 1 * 1024 * 1024);
44 44 } else {
45 45 puts("Memory: ECC disabled\n");
46 46 }
47   -
48   - if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)
49   - gd->ram_size /= 2;
50 47 }
arch/arm/cpu/armv7/zynq/slcr.c
Diff comments   View file @ c534d2f
... ... @@ -8,26 +8,75 @@
8 8 #include <asm/io.h>
9 9 #include <malloc.h>
10 10 #include <asm/arch/hardware.h>
  11 +#include <asm/arch/sys_proto.h>
11 12 #include <asm/arch/clk.h>
12 13  
13 14 #define SLCR_LOCK_MAGIC 0x767B
14 15 #define SLCR_UNLOCK_MAGIC 0xDF0D
15 16  
  17 +#define SLCR_USB_L1_SEL 0x04
  18 +
16 19 #define SLCR_IDCODE_MASK 0x1F000
17 20 #define SLCR_IDCODE_SHIFT 12
18 21  
  22 +/*
  23 + * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
  24 + *
  25 + * @peri_name: Name of the peripheral for checking MIO status
  26 + * @get_pins: Pointer to array of get pin for this peripheral
  27 + * @num_pins: Number of pins for this peripheral
  28 + * @mask: Mask value
  29 + * @check_val: Required check value to get the status of periph
  30 + */
  31 +struct zynq_slcr_mio_get_status {
  32 + const char *peri_name;
  33 + const int *get_pins;
  34 + int num_pins;
  35 + u32 mask;
  36 + u32 check_val;
  37 +};
  38 +
  39 +static const int usb0_pins[] = {
  40 + 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
  41 +};
  42 +
  43 +static const int usb1_pins[] = {
  44 + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
  45 +};
  46 +
  47 +static const struct zynq_slcr_mio_get_status mio_periphs[] = {
  48 + {
  49 + "usb0",
  50 + usb0_pins,
  51 + ARRAY_SIZE(usb0_pins),
  52 + SLCR_USB_L1_SEL,
  53 + SLCR_USB_L1_SEL,
  54 + },
  55 + {
  56 + "usb1",
  57 + usb1_pins,
  58 + ARRAY_SIZE(usb1_pins),
  59 + SLCR_USB_L1_SEL,
  60 + SLCR_USB_L1_SEL,
  61 + },
  62 +};
  63 +
19 64 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
20 65  
21 66 void zynq_slcr_lock(void)
22 67 {
23   - if (!slcr_lock)
  68 + if (!slcr_lock) {
24 69 writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
  70 + slcr_lock = 1;
  71 + }
25 72 }
26 73  
27 74 void zynq_slcr_unlock(void)
28 75 {
29   - if (slcr_lock)
  76 + if (slcr_lock) {
30 77 writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
  78 + slcr_lock = 0;
  79 + }
31 80 }
32 81  
33 82 /* Reset the entire system */
... ... @@ -82,7 +131,7 @@
82 131 {
83 132 zynq_slcr_unlock();
84 133  
85   - /* Disable AXI interface */
  134 + /* Disable AXI interface by asserting FPGA resets */
86 135 writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
87 136  
88 137 /* Set Level Shifters DT618760 */
... ... @@ -98,7 +147,7 @@
98 147 /* Set Level Shifters DT618760 */
99 148 writel(0xF, &slcr_base->lvl_shftr_en);
100 149  
101   - /* Disable AXI interface */
  150 + /* Enable AXI interface by de-asserting FPGA resets */
102 151 writel(0x0, &slcr_base->fpga_rst_ctrl);
103 152  
104 153 zynq_slcr_lock();
... ... @@ -114,5 +163,35 @@
114 163 {
115 164 return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
116 165 SLCR_IDCODE_SHIFT;
  166 +}
  167 +
  168 +/*
  169 + * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
  170 + *
  171 + * @periph: Name of the peripheral
  172 + *
  173 + * Returns count to indicate the number of pins configured for the
  174 + * given @periph.
  175 + */
  176 +int zynq_slcr_get_mio_pin_status(const char *periph)
  177 +{
  178 + const struct zynq_slcr_mio_get_status *mio_ptr;
  179 + int val, i, j;
  180 + int mio = 0;
  181 +
  182 + for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
  183 + if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
  184 + mio_ptr = &mio_periphs[i];
  185 + for (j = 0; j < mio_ptr->num_pins; j++) {
  186 + val = readl(&slcr_base->mio_pin
  187 + [mio_ptr->get_pins[j]]);
  188 + if ((val & mio_ptr->mask) == mio_ptr->check_val)
  189 + mio++;
  190 + }
  191 + break;
  192 + }
  193 + }
  194 +
  195 + return mio;
117 196 }
arch/arm/cpu/armv7/zynq/spl.c
Diff comments   View file @ c534d2f
... ... @@ -28,6 +28,13 @@
28 28 board_init_r(NULL, 0);
29 29 }
30 30  
  31 +#ifdef CONFIG_SPL_BOARD_INIT
  32 +void spl_board_init(void)
  33 +{
  34 + board_init();
  35 +}
  36 +#endif
  37 +
31 38 u32 spl_boot_device(void)
32 39 {
33 40 u32 mode;
... ... @@ -67,4 +74,12 @@
67 74 return 0;
68 75 }
69 76 #endif
  77 +
  78 +__weak void ps7_init(void)
  79 +{
  80 + /*
  81 + * This function is overridden by the one in
  82 + * board/xilinx/zynq/ps7_init.c, if it exists.
  83 + */
  84 +}
arch/arm/dts/zynq-7000.dtsi
Diff comments   View file @ c534d2f
... ... @@ -10,5 +10,199 @@
10 10  
11 11 / {
12 12 compatible = "xlnx,zynq-7000";
  13 +
  14 + cpus {
  15 + #address-cells = <1>;
  16 + #size-cells = <0>;
  17 +
  18 + cpu@0 {
  19 + compatible = "arm,cortex-a9";
  20 + device_type = "cpu";
  21 + reg = <0>;
  22 + clocks = <&clkc 3>;
  23 + clock-latency = <1000>;
  24 + operating-points = <
  25 + /* kHz uV */
  26 + 666667 1000000
  27 + 333334 1000000
  28 + 222223 1000000
  29 + >;
  30 + };
  31 +
  32 + cpu@1 {
  33 + compatible = "arm,cortex-a9";
  34 + device_type = "cpu";
  35 + reg = <1>;
  36 + clocks = <&clkc 3>;
  37 + };
  38 + };
  39 +
  40 + pmu {
  41 + compatible = "arm,cortex-a9-pmu";
  42 + interrupts = <0 5 4>, <0 6 4>;
  43 + interrupt-parent = <&intc>;
  44 + reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
  45 + };
  46 +
  47 + amba {
  48 + compatible = "simple-bus";
  49 + #address-cells = <1>;
  50 + #size-cells = <1>;
  51 + interrupt-parent = <&intc>;
  52 + ranges;
  53 +
  54 + i2c0: zynq-i2c@e0004000 {
  55 + compatible = "cdns,i2c-r1p10";
  56 + status = "disabled";
  57 + clocks = <&clkc 38>;
  58 + interrupt-parent = <&intc>;
  59 + interrupts = <0 25 4>;
  60 + reg = <0xe0004000 0x1000>;
  61 + #address-cells = <1>;
  62 + #size-cells = <0>;
  63 + };
  64 +
  65 + i2c1: zynq-i2c@e0005000 {
  66 + compatible = "cdns,i2c-r1p10";
  67 + status = "disabled";
  68 + clocks = <&clkc 39>;
  69 + interrupt-parent = <&intc>;
  70 + interrupts = <0 48 4>;
  71 + reg = <0xe0005000 0x1000>;
  72 + #address-cells = <1>;
  73 + #size-cells = <0>;
  74 + };
  75 +
  76 + intc: interrupt-controller@f8f01000 {
  77 + compatible = "arm,cortex-a9-gic";
  78 + #interrupt-cells = <3>;
  79 + #address-cells = <1>;
  80 + interrupt-controller;
  81 + reg = <0xF8F01000 0x1000>,
  82 + <0xF8F00100 0x100>;
  83 + };
  84 +
  85 + L2: cache-controller {
  86 + compatible = "arm,pl310-cache";
  87 + reg = <0xF8F02000 0x1000>;
  88 + arm,data-latency = <3 2 2>;
  89 + arm,tag-latency = <2 2 2>;
  90 + cache-unified;
  91 + cache-level = <2>;
  92 + };
  93 +
  94 + uart0: uart@e0000000 {
  95 + compatible = "xlnx,xuartps";
  96 + status = "disabled";
  97 + clocks = <&clkc 23>, <&clkc 40>;
  98 + clock-names = "ref_clk", "aper_clk";
  99 + reg = <0xE0000000 0x1000>;
  100 + interrupts = <0 27 4>;
  101 + };
  102 +
  103 + uart1: uart@e0001000 {
  104 + compatible = "xlnx,xuartps";
  105 + status = "disabled";
  106 + clocks = <&clkc 24>, <&clkc 41>;
  107 + clock-names = "ref_clk", "aper_clk";
  108 + reg = <0xE0001000 0x1000>;
  109 + interrupts = <0 50 4>;
  110 + };
  111 +
  112 + gem0: ethernet@e000b000 {
  113 + compatible = "cdns,gem";
  114 + reg = <0xe000b000 0x4000>;
  115 + status = "disabled";
  116 + interrupts = <0 22 4>;
  117 + clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
  118 + clock-names = "pclk", "hclk", "tx_clk";
  119 + };
  120 +
  121 + gem1: ethernet@e000c000 {
  122 + compatible = "cdns,gem";
  123 + reg = <0xe000c000 0x4000>;
  124 + status = "disabled";
  125 + interrupts = <0 45 4>;
  126 + clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
  127 + clock-names = "pclk", "hclk", "tx_clk";
  128 + };
  129 +
  130 + sdhci0: ps7-sdhci@e0100000 {
  131 + compatible = "arasan,sdhci-8.9a";
  132 + status = "disabled";
  133 + clock-names = "clk_xin", "clk_ahb";
  134 + clocks = <&clkc 21>, <&clkc 32>;
  135 + interrupt-parent = <&intc>;
  136 + interrupts = <0 24 4>;
  137 + reg = <0xe0100000 0x1000>;
  138 + } ;
  139 +
  140 + sdhci1: ps7-sdhci@e0101000 {
  141 + compatible = "arasan,sdhci-8.9a";
  142 + status = "disabled";
  143 + clock-names = "clk_xin", "clk_ahb";
  144 + clocks = <&clkc 22>, <&clkc 33>;
  145 + interrupt-parent = <&intc>;
  146 + interrupts = <0 47 4>;
  147 + reg = <0xe0101000 0x1000>;
  148 + } ;
  149 +
  150 + slcr: slcr@f8000000 {
  151 + #address-cells = <1>;
  152 + #size-cells = <1>;
  153 + compatible = "xlnx,zynq-slcr", "syscon";
  154 + reg = <0xF8000000 0x1000>;
  155 + ranges;
  156 + clkc: clkc@100 {
  157 + #clock-cells = <1>;
  158 + compatible = "xlnx,ps7-clkc";
  159 + ps-clk-frequency = <33333333>;
  160 + fclk-enable = <0>;
  161 + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
  162 + "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
  163 + "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
  164 + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
  165 + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
  166 + "dma", "usb0_aper", "usb1_aper", "gem0_aper",
  167 + "gem1_aper", "sdio0_aper", "sdio1_aper",
  168 + "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
  169 + "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
  170 + "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
  171 + "dbg_trc", "dbg_apb";
  172 + reg = <0x100 0x100>;
  173 + };
  174 + };
  175 +
  176 + global_timer: timer@f8f00200 {
  177 + compatible = "arm,cortex-a9-global-timer";
  178 + reg = <0xf8f00200 0x20>;
  179 + interrupts = <1 11 0x301>;
  180 + interrupt-parent = <&intc>;
  181 + clocks = <&clkc 4>;
  182 + };
  183 +
  184 + ttc0: ttc0@f8001000 {
  185 + interrupt-parent = <&intc>;
  186 + interrupts = < 0 10 4 0 11 4 0 12 4 >;
  187 + compatible = "cdns,ttc";
  188 + clocks = <&clkc 6>;
  189 + reg = <0xF8001000 0x1000>;
  190 + };
  191 +
  192 + ttc1: ttc1@f8002000 {
  193 + interrupt-parent = <&intc>;
  194 + interrupts = < 0 37 4 0 38 4 0 39 4 >;
  195 + compatible = "cdns,ttc";
  196 + clocks = <&clkc 6>;
  197 + reg = <0xF8002000 0x1000>;
  198 + };
  199 + scutimer: scutimer@f8f00600 {
  200 + interrupt-parent = <&intc>;
  201 + interrupts = < 1 13 0x301 >;
  202 + compatible = "arm,cortex-a9-twd-timer";
  203 + reg = < 0xf8f00600 0x20 >;
  204 + clocks = <&clkc 4>;
  205 + } ;
  206 + };
13 207 };
arch/arm/dts/zynq-microzed.dts
Diff comments   View file @ c534d2f
... ... @@ -11,5 +11,14 @@
11 11 / {
12 12 model = "Zynq MicroZED Board";
13 13 compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
  14 +
  15 + aliases {
  16 + serial0 = &uart1;
  17 + };
  18 +
  19 + memory {
  20 + device_type = "memory";
  21 + reg = <0 0x40000000>;
  22 + };
14 23 };
arch/arm/dts/zynq-zc702.dts
Diff comments   View file @ c534d2f
... ... @@ -11,5 +11,14 @@
11 11 / {
12 12 model = "Zynq ZC702 Board";
13 13 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
  14 +
  15 + aliases {
  16 + serial0 = &uart1;
  17 + };
  18 +
  19 + memory {
  20 + device_type = "memory";
  21 + reg = <0 0x40000000>;
  22 + };
14 23 };
arch/arm/dts/zynq-zc706.dts
Diff comments   View file @ c534d2f
... ... @@ -11,5 +11,14 @@
11 11 / {
12 12 model = "Zynq ZC706 Board";
13 13 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
  14 +
  15 + aliases {
  16 + serial0 = &uart1;
  17 + };
  18 +
  19 + memory {
  20 + device_type = "memory";
  21 + reg = <0 0x40000000>;
  22 + };
14 23 };
arch/arm/dts/zynq-zc770-xm010.dts
Diff comments   View file @ c534d2f
... ... @@ -11,5 +11,14 @@
11 11 / {
12 12 model = "Zynq ZC770 XM010 Board";
13 13 compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
  14 +
  15 + aliases {
  16 + serial0 = &uart1;
  17 + };
  18 +
  19 + memory {
  20 + device_type = "memory";
  21 + reg = <0 0x40000000>;
  22 + };
14 23 };
arch/arm/dts/zynq-zc770-xm012.dts
Diff comments   View file @ c534d2f
... ... @@ -11,5 +11,14 @@
11 11 / {
12 12 model = "Zynq ZC770 XM012 Board";
13 13 compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
  14 +
  15 + aliases {
  16 + serial0 = &uart1;
  17 + };
  18 +
  19 + memory {
  20 + device_type = "memory";
  21 + reg = <0 0x40000000>;
  22 + };
14 23 };
arch/arm/dts/zynq-zc770-xm013.dts
Diff comments   View file @ c534d2f
... ... @@ -11,5 +11,14 @@
11 11 / {
12 12 model = "Zynq ZC770 XM013 Board";
13 13 compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
  14 +
  15 + aliases {
  16 + serial0 = &uart0;
  17 + };
  18 +
  19 + memory {
  20 + device_type = "memory";
  21 + reg = <0 0x40000000>;
  22 + };
14 23 };
arch/arm/dts/zynq-zed.dts
Diff comments   View file @ c534d2f
... ... @@ -11,5 +11,14 @@
11 11 / {
12 12 model = "Zynq ZED Board";
13 13 compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
  14 +
  15 + aliases {
  16 + serial0 = &uart1;
  17 + };
  18 +
  19 + memory {
  20 + device_type = "memory";
  21 + reg = <0 0x20000000>;
  22 + };
14 23 };
arch/arm/include/asm/arch-zynq/hardware.h
Diff comments   View file @ c534d2f
... ... @@ -22,9 +22,12 @@
22 22 #define ZYNQ_SPI_BASEADDR0 0xE0006000
23 23 #define ZYNQ_SPI_BASEADDR1 0xE0007000
24 24 #define ZYNQ_DDRC_BASEADDR 0xF8006000
  25 +#define ZYNQ_EFUSE_BASEADDR 0xF800D000
  26 +#define ZYNQ_USB_BASEADDR0 0xE0002000
  27 +#define ZYNQ_USB_BASEADDR1 0xE0003000
25 28  
26 29 /* Bootmode setting values */
27   -#define ZYNQ_BM_MASK 0xF
  30 +#define ZYNQ_BM_MASK 0x7
28 31 #define ZYNQ_BM_NOR 0x2
29 32 #define ZYNQ_BM_SD 0x5
30 33 #define ZYNQ_BM_JTAG 0x0
... ... @@ -129,6 +132,14 @@
129 132 u32 ecc_scrub; /* 0xF4 */
130 133 };
131 134 #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
  135 +
  136 +struct efuse_reg {
  137 + u32 reserved1[4];
  138 + u32 status;
  139 + u32 reserved2[3];
  140 +};
  141 +
  142 +#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR)
132 143  
133 144 #endif /* _ASM_ARCH_HARDWARE_H */
arch/arm/include/asm/arch-zynq/sys_proto.h
Diff comments   View file @ c534d2f
... ... @@ -15,7 +15,9 @@
15 15 extern void zynq_slcr_devcfg_enable(void);
16 16 extern u32 zynq_slcr_get_boot_mode(void);
17 17 extern u32 zynq_slcr_get_idcode(void);
  18 +extern int zynq_slcr_get_mio_pin_status(const char *periph);
18 19 extern void zynq_ddrc_init(void);
  20 +extern unsigned int zynq_get_silicon_version(void);
19 21  
20 22 /* Driver extern functions */
21 23 extern int zynq_sdhci_init(u32 regbase);
board/xilinx/zynq/.gitignore
Diff comments   View file @ c534d2f
  1 +ps7_init.[ch]
board/xilinx/zynq/Makefile
Diff comments   View file @ c534d2f
... ... @@ -6,5 +6,8 @@
6 6 #
7 7  
8 8 obj-y := board.o
9   -obj-$(CONFIG_SPL_BUILD) += ps7_init.o
  9 +
  10 +# Please copy ps7_init.c/h from hw project to this directory
  11 +obj-$(CONFIG_SPL_BUILD) += \
  12 + $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o)
board/xilinx/zynq/board.c
Diff comments   View file @ c534d2f
... ... @@ -6,6 +6,8 @@
6 6  
7 7 #include <common.h>
8 8 #include <fdtdec.h>
  9 +#include <fpga.h>
  10 +#include <mmc.h>
9 11 #include <netdev.h>
10 12 #include <zynqpl.h>
11 13 #include <asm/arch/hardware.h>
12 14  
13 15  
... ... @@ -13,21 +15,23 @@
13 15  
14 16 DECLARE_GLOBAL_DATA_PTR;
15 17  
16   -#ifdef CONFIG_FPGA
17   -xilinx_desc fpga;
  18 +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  19 + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  20 +static xilinx_desc fpga;
18 21  
19 22 /* It can be done differently */
20   -xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
21   -xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
22   -xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
23   -xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
24   -xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
25   -xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
  23 +static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
  24 +static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
  25 +static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
  26 +static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
  27 +static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
  28 +static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
26 29 #endif
27 30  
28 31 int board_init(void)
29 32 {
30   -#ifdef CONFIG_FPGA
  33 +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  34 + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
31 35 u32 idcode;
32 36  
33 37 idcode = zynq_slcr_get_idcode();
... ... @@ -54,7 +58,8 @@
54 58 }
55 59 #endif
56 60  
57   -#ifdef CONFIG_FPGA
  61 +#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  62 + (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
58 63 fpga_init();
59 64 fpga_add(fpga_xilinx, &fpga);
60 65 #endif
board/xilinx/zynq/ps7_init.c
View file @ c534d2f
1   -/*
2   - * (C) Copyright 2014 Xilinx, Inc. Michal Simek
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -#include <common.h>
7   -#include <asm/arch/spl.h>
8   -
9   -__weak void ps7_init(void)
10   -{
11   - puts("Please copy ps7_init.c/h from hw project\n");
12   -}
board/xilinx/zynq/xil_io.h
Diff comments   View file @ c534d2f
  1 +/*
  2 + * SPDX-License-Identifier: GPL-2.0+
  3 + */
  4 +
  5 +#ifndef XIL_IO_H /* prevent circular inclusions */
  6 +#define XIL_IO_H
  7 +
  8 +/*
  9 + * This empty file is here because ps7_init.c exported by hw project
  10 + * has #include "xil_io.h" line.
  11 + */
  12 +
  13 +#endif /* XIL_IO_H */
drivers/usb/host/Makefile
Diff comments   View file @ c534d2f
... ... @@ -37,6 +37,7 @@
37 37 obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
38 38 obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
39 39 obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
  40 +obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
40 41  
41 42 # xhci
42 43 obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
drivers/usb/host/ehci-zynq.c
Diff comments   View file @ c534d2f
  1 +/*
  2 + * (C) Copyright 2014, Xilinx, Inc
  3 + *
  4 + * USB Low level initialization(Specific to zynq)
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <asm/arch/hardware.h>
  11 +#include <asm/arch/sys_proto.h>
  12 +#include <asm/io.h>
  13 +#include <usb.h>
  14 +#include <usb/ehci-fsl.h>
  15 +#include <usb/ulpi.h>
  16 +
  17 +#include "ehci.h"
  18 +
  19 +#define ZYNQ_USB_USBCMD_RST 0x0000002
  20 +#define ZYNQ_USB_USBCMD_STOP 0x0000000
  21 +#define ZYNQ_USB_NUM_MIO 12
  22 +
  23 +/*
  24 + * Create the appropriate control structures to manage
  25 + * a new EHCI host controller.
  26 + */
  27 +int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
  28 + struct ehci_hcor **hcor)
  29 +{
  30 + struct usb_ehci *ehci;
  31 + struct ulpi_viewport ulpi_vp;
  32 + int ret, mio_usb;
  33 + /* Used for writing the ULPI data address */
  34 + struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
  35 +
  36 + if (!index) {
  37 + mio_usb = zynq_slcr_get_mio_pin_status("usb0");
  38 + if (mio_usb != ZYNQ_USB_NUM_MIO) {
  39 + printf("usb0 wrong num MIO: %d, Index %d\n", mio_usb,
  40 + index);
  41 + return -1;
  42 + }
  43 + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0;
  44 + } else {
  45 + mio_usb = zynq_slcr_get_mio_pin_status("usb1");
  46 + if (mio_usb != ZYNQ_USB_NUM_MIO) {
  47 + printf("usb1 wrong num MIO: %d, Index %d\n", mio_usb,
  48 + index);
  49 + return -1;
  50 + }
  51 + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1;
  52 + }
  53 +
  54 + *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  55 + *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
  56 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  57 +
  58 + ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
  59 + ulpi_vp.port_num = 0;
  60 +
  61 + ret = ulpi_init(&ulpi_vp);
  62 + if (ret) {
  63 + puts("zynq ULPI viewport init failed\n");
  64 + return -1;
  65 + }
  66 +
  67 + /* ULPI set flags */
  68 + ulpi_write(&ulpi_vp, &ulpi->otg_ctrl,
  69 + ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN |
  70 + ULPI_OTG_EXTVBUSIND);
  71 + ulpi_write(&ulpi_vp, &ulpi->function_ctrl,
  72 + ULPI_FC_FULL_SPEED | ULPI_FC_OPMODE_NORMAL |
  73 + ULPI_FC_SUSPENDM);
  74 + ulpi_write(&ulpi_vp, &ulpi->iface_ctrl, 0);
  75 +
  76 + /* Set VBus */
  77 + ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set,
  78 + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
  79 +
  80 + return 0;
  81 +}
  82 +
  83 +/*
  84 + * Destroy the appropriate control structures corresponding
  85 + * the the EHCI host controller.
  86 + */
  87 +int ehci_hcd_stop(int index)
  88 +{
  89 + struct usb_ehci *ehci;
  90 +
  91 + if (!index)
  92 + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0;
  93 + else
  94 + ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1;
  95 +
  96 + /* Stop controller */
  97 + writel(ZYNQ_USB_USBCMD_STOP, &ehci->usbcmd);
  98 + udelay(1000);
  99 +
  100 + /* Initiate controller reset */
  101 + writel(ZYNQ_USB_USBCMD_RST, &ehci->usbcmd);
  102 +
  103 + return 0;
  104 +}
include/configs/zynq-common.h
Diff comments   View file @ c534d2f
... ... @@ -83,10 +83,27 @@
83 83 # define CONFIG_SDHCI
84 84 # define CONFIG_ZYNQ_SDHCI
85 85 # define CONFIG_CMD_MMC
86   -# define CONFIG_CMD_FAT
  86 +#endif
  87 +
  88 +#ifdef CONFIG_ZYNQ_USB
  89 +# define CONFIG_USB_EHCI
  90 +# define CONFIG_CMD_USB
  91 +# define CONFIG_USB_STORAGE
  92 +# define CONFIG_USB_EHCI_ZYNQ
  93 +# define CONFIG_USB_ULPI_VIEWPORT
  94 +# define CONFIG_USB_ULPI
  95 +# define CONFIG_EHCI_IS_TDI
  96 +# define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  97 +#endif
  98 +
  99 +#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQ_USB)
87 100 # define CONFIG_SUPPORT_VFAT
  101 +# define CONFIG_CMD_FAT
88 102 # define CONFIG_CMD_EXT2
  103 +# define CONFIG_FAT_WRITE
89 104 # define CONFIG_DOS_PARTITION
  105 +# define CONFIG_CMD_EXT4
  106 +# define CONFIG_CMD_EXT4_WRITE
90 107 #endif
91 108  
92 109 #define CONFIG_SYS_I2C_ZYNQ
... ... @@ -150,7 +167,13 @@
150 167 "bootm ${load_addr}\0" \
151 168 "jtagboot=echo TFTPing FIT to RAM... && " \
152 169 "tftpboot ${load_addr} ${fit_image} && " \
153   - "bootm ${load_addr}\0"
  170 + "bootm ${load_addr}\0" \
  171 + "usbboot=if usb start; then " \
  172 + "echo Copying FIT from USB to RAM... && " \
  173 + "fatload usb 0 ${load_addr} ${fit_image} && " \
  174 + "bootm ${load_addr}\0" \
  175 + "fi\0"
  176 +
154 177 #define CONFIG_BOOTCOMMAND "run $modeboot"
155 178 #define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */
156 179 #define CONFIG_SYS_LOAD_ADDR 0 /* default? */
... ... @@ -165,7 +188,7 @@
165 188 #define CONFIG_SYS_LONGHELP
166 189 #define CONFIG_CLOCKS
167 190 #define CONFIG_CMD_CLK
168   -#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
  191 +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
169 192 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
170 193 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
171 194 sizeof(CONFIG_SYS_PROMPT) + 16)
... ... @@ -213,7 +236,7 @@
213 236 #define CONFIG_RSA
214 237  
215 238 /* Extend size of kernel image for uncompression */
216   -#define CONFIG_SYS_BOOTM_LEN (20 * 1024 * 1024)
  239 +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
217 240  
218 241 /* Boot FreeBSD/vxWorks from an ELF image */
219 242 #if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
220 243  
... ... @@ -239,16 +262,10 @@
239 262 #define CONFIG_SPL_LIBCOMMON_SUPPORT
240 263 #define CONFIG_SPL_LIBGENERIC_SUPPORT
241 264 #define CONFIG_SPL_SERIAL_SUPPORT
  265 +#define CONFIG_SPL_BOARD_INIT
242 266  
243 267 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot-spl.lds"
244 268  
245   -/* Disable dcache for SPL just for sure */
246   -#ifdef CONFIG_SPL_BUILD
247   -#define CONFIG_SYS_DCACHE_OFF
248   -#undef CONFIG_FPGA
249   -#undef CONFIG_OF_CONTROL
250   -#endif
251   -
252 269 /* MMC support */
253 270 #ifdef CONFIG_ZYNQ_SDHCI0
254 271 #define CONFIG_SPL_MMC_SUPPORT
... ... @@ -257,7 +274,18 @@
257 274 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
258 275 #define CONFIG_SPL_LIBDISK_SUPPORT
259 276 #define CONFIG_SPL_FAT_SUPPORT
260   -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
  277 +#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_OF_SEPARATE)
  278 +# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
  279 +#else
  280 +# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
  281 +#endif
  282 +#endif
  283 +
  284 +/* Disable dcache for SPL just for sure */
  285 +#ifdef CONFIG_SPL_BUILD
  286 +#define CONFIG_SYS_DCACHE_OFF
  287 +#undef CONFIG_FPGA
  288 +#undef CONFIG_OF_CONTROL
261 289 #endif
262 290  
263 291 /* Address in RAM where the parameters must be copied by SPL. */
include/configs/zynq_zc70x.h
Diff comments   View file @ c534d2f
... ... @@ -19,6 +19,7 @@
19 19 #define CONFIG_SYS_NO_FLASH
20 20  
21 21 #define CONFIG_ZYNQ_SDHCI0
  22 +#define CONFIG_ZYNQ_USB
22 23 #define CONFIG_ZYNQ_I2C0
23 24 #define CONFIG_ZYNQ_EEPROM
24 25 #define CONFIG_ZYNQ_BOOT_FREEBSD
include/configs/zynq_zed.h
Diff comments   View file @ c534d2f
... ... @@ -18,6 +18,7 @@
18 18  
19 19 #define CONFIG_SYS_NO_FLASH
20 20  
  21 +#define CONFIG_ZYNQ_USB
21 22 #define CONFIG_ZYNQ_SDHCI0
22 23 #define CONFIG_ZYNQ_BOOT_FREEBSD
23 24 #define CONFIG_DEFAULT_DEVICE_TREE zynq-zed