Commit c57b953da923c6402afc1c890c21fdc7d5a2cc4a

Authored by Pavel Machek
Committed by Tom Rini
1 parent 4212098181

SPL: Add support for loading image from ram in SPL.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>

Showing 3 changed files with 26 additions and 0 deletions Side-by-side Diff

... ... @@ -2669,6 +2669,9 @@
2669 2669 CONFIG_SPL_SPI_SUPPORT
2670 2670 Support for drivers/spi/libspi.o in SPL binary
2671 2671  
  2672 + CONFIG_SPL_RAM_DEVICE
  2673 + Support for running image already present in ram, in SPL binary
  2674 +
2672 2675 CONFIG_SPL_LIBGENERIC_SUPPORT
2673 2676 Support for lib/libgeneric.o in SPL binary
2674 2677  
... ... @@ -128,6 +128,23 @@
128 128 image_entry((u32 *)boot_params_ptr_addr);
129 129 }
130 130  
  131 +#ifdef CONFIG_SPL_RAM_DEVICE
  132 +static void spl_ram_load_image(void)
  133 +{
  134 + const struct image_header *header;
  135 +
  136 + /*
  137 + * Get the header. It will point to an address defined by handoff
  138 + * which will tell where the image located inside the flash. For
  139 + * now, it will temporary fixed to address pointed by U-Boot.
  140 + */
  141 + header = (struct image_header *)
  142 + (CONFIG_SYS_TEXT_BASE - sizeof(struct image_header));
  143 +
  144 + spl_parse_image_header(header);
  145 +}
  146 +#endif
  147 +
131 148 void board_init_r(gd_t *dummy1, ulong dummy2)
132 149 {
133 150 u32 boot_device;
... ... @@ -145,6 +162,11 @@
145 162 boot_device = spl_boot_device();
146 163 debug("boot device - %d\n", boot_device);
147 164 switch (boot_device) {
  165 +#ifdef CONFIG_SPL_RAM_DEVICE
  166 + case BOOT_DEVICE_RAM:
  167 + spl_ram_load_image();
  168 + break;
  169 +#endif
148 170 #ifdef CONFIG_SPL_MMC_SUPPORT
149 171 case BOOT_DEVICE_MMC1:
150 172 case BOOT_DEVICE_MMC2:
... ... @@ -66,6 +66,7 @@
66 66 CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
67 67 CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
68 68 CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o)
  69 +CONFIG_SPL_RAM_DEVICE (common/spl/spl.c)
69 70  
70 71  
71 72 Normally CPU is assumed to be the same between the SPL and normal