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Commit c57fc28947e248fb03c49a28b467686299895055

Authored by Jason Jin
Committed by Scott Wood
1 parent 6fc110bd8a
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

NAND: Add NAND support for MPC8536DS board 

This patch defines 1M TLB&LAW size for NAND on MPC8536DS, assigns 0xffa00000
for CONFIG_SYS_NAND_BASE and adds other NAND supports in config file.
It also moves environment(CONFIG_ENV_ADDR) outside of u-boot image.

Singed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Showing 3 changed files with 60 additions and 2 deletions Side-by-side Diff

board/freescale/mpc8536ds/law.c
Diff comments   View file @ c57fc28
... ... @@ -38,6 +38,7 @@
38 38 SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
39 39 SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
40 40 SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
  41 + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
41 42 };
42 43  
43 44 int num_law_entries = ARRAY_SIZE(law_table);
board/freescale/mpc8536ds/tlb.c
Diff comments   View file @ c57fc28
... ... @@ -66,6 +66,11 @@
66 66 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
67 67 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
68 68 0, 3, BOOKE_PAGESZ_256K, 1),
  69 +
  70 + /* *I*G - NAND */
  71 + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  72 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  73 + 0, 4, BOOKE_PAGESZ_1M, 1),
69 74 };
70 75  
71 76 int num_tlb_entries = ARRAY_SIZE(tlb_table);
include/configs/MPC8536DS.h
Diff comments   View file @ c57fc28
... ... @@ -155,8 +155,9 @@
155 155 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
156 156 *
157 157 * Localbus non-cacheable
158   - * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
  158 + * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
159 159 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
  160 + * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
160 161 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
161 162 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
162 163 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
... ... @@ -243,6 +244,57 @@
243 244 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
244 245 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
245 246  
  247 +#define CONFIG_SYS_NAND_BASE 0xffa00000
  248 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  249 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
  250 + CONFIG_SYS_NAND_BASE + 0x40000, \
  251 + CONFIG_SYS_NAND_BASE + 0x80000, \
  252 + CONFIG_SYS_NAND_BASE + 0xC0000}
  253 +#define CONFIG_SYS_MAX_NAND_DEVICE 4
  254 +#define NAND_MAX_CHIPS 1
  255 +#define CONFIG_MTD_NAND_VERIFY_WRITE
  256 +#define CONFIG_CMD_NAND 1
  257 +#define CONFIG_NAND_FSL_ELBC 1
  258 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  259 +
  260 +/* NAND flash config */
  261 +#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
  262 + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  263 + | BR_PS_8 /* Port Size = 8 bit */ \
  264 + | BR_MS_FCM /* MSEL = FCM */ \
  265 + | BR_V) /* valid */
  266 +#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  267 + | OR_FCM_PGS /* Large Page*/ \
  268 + | OR_FCM_CSCT \
  269 + | OR_FCM_CST \
  270 + | OR_FCM_CHT \
  271 + | OR_FCM_SCY_1 \
  272 + | OR_FCM_TRLX \
  273 + | OR_FCM_EHTR)
  274 +
  275 +#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
  276 +#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  277 +
  278 +#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\
  279 + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  280 + | BR_PS_8 /* Port Size = 8 bit */ \
  281 + | BR_MS_FCM /* MSEL = FCM */ \
  282 + | BR_V) /* valid */
  283 +#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  284 +#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
  285 + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  286 + | BR_PS_8 /* Port Size = 8 bit */ \
  287 + | BR_MS_FCM /* MSEL = FCM */ \
  288 + | BR_V) /* valid */
  289 +#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  290 +
  291 +#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\
  292 + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  293 + | BR_PS_8 /* Port Size = 8 bit */ \
  294 + | BR_MS_FCM /* MSEL = FCM */ \
  295 + | BR_V) /* valid */
  296 +#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  297 +
246 298 /* Serial Port - controlled on board with jumper J8
247 299 * open - index 2
248 300 * shorted - index 1
... ... @@ -440,7 +492,7 @@
440 492 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
441 493 #define CONFIG_ENV_ADDR 0xfff80000
442 494 #else
443   -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
  495 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
444 496 #endif
445 497 #define CONFIG_ENV_SIZE 0x2000
446 498 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */