board/b4qds:Add support of 2 stage NAND boot-loader

Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>

board/b4qds:Add support of 2 stage NAND boot-loader
Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha · York Sun
1 parent 89ad7be8e7
Showing 7 changed files with 230 additions and 12 deletions Side-by-side Diff
board/freescale/b4860qds/Makefile
board/freescale/b4860qds/ddr.c
board/freescale/b4860qds/spl.c
board/freescale/b4860qds/tlb.c
boards.cfg
doc/README.b4860qds
include/configs/B4860QDS.h
@@ -4,10 +4,15 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
  
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-y	+= b4860qds.o
-obj-y	+= ddr.o
 obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o
-obj-$(CONFIG_PCI)	+= pci.o
+obj-$(CONFIG_PCI)      += pci.o
+endif
+
+obj-y	+= ddr.o
 obj-y	+= law.o
 obj-y	+= tlb.o
@@ -179,6 +179,7 @@
 {
 	phys_size_t dram_size;
  
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
  
 	dram_size = fsl_ddr_sdram();
@@ -186,7 +187,9 @@
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
  
-	puts("    DDR: ");
+#else
+	dram_size =  fsl_ddr_sdram_size();
+#endif
 	return dram_size;
 }
  
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/spl.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include "../common/qixis.h"
+#include "b4860qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch ((sysclk_conf & 0x0C) >> 2) {
+	case QIXIS_CLK_100:
+		return 100000000;
+	case QIXIS_CLK_125:
+		return 125000000;
+	case QIXIS_CLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (ddrclk_conf & 0x03) {
+	case QIXIS_CLK_100:
+		return 100000000;
+	case QIXIS_CLK_125:
+		return 125000000;
+	case QIXIS_CLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, sys_clk, uart_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+	/* Update GD pointer */
+	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+	/* compiler optimization barrier needed for GCC >= 3.4 */
+	__asm__ __volatile__("" : : : "memory");
+
+	console_init_f();
+
+	/* initialize selected port with appropriate baud rate */
+	sys_clk = get_board_sys_clk();
+	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+	uart_clk = sys_clk * plat_ratio / 2;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     uart_clk / 16 / CONFIG_BAUDRATE);
+
+	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	bd_t *bd;
+
+	bd = (bd_t *)(gd + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifndef CONFIG_SPL_NAND_BOOT
+	env_init();
+	env_relocate();
+#else
+	/* relocate environment function pointers etc. */
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+#endif
+
+	i2c_init_all();
+
+	puts("\n\n");
+
+	gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_boot();
+#endif
+}
@@ -62,6 +62,7 @@
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
  
+#ifndef CONFIG_SPL_BUILD
 	/* *I*G* - PCI */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -96,6 +97,7 @@
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 9, BOOKE_PAGESZ_16M, 1),
 #endif
+#endif
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -118,6 +120,7 @@
 	 * entry 14 and 15 has been used hard coded, they will be disabled
 	 * in cpu_init_f, so we use entry 16 for SRIO2.
 	 */
+#ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_SYS_SRIO1_MEM_PHYS
 	/* *I*G* - SRIO1 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
@@ -139,6 +142,13 @@
 		      CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		      0, 17, BOOKE_PAGESZ_1M, 1),
+#endif
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 17, BOOKE_PAGESZ_2G, 1)
 #endif
 };
  
@@ -741,11 +741,11 @@
 Active  powerpc     mpc85xx        -           -               socrates            socrates                             -                                                                                                                                 -
 Active  powerpc     mpc85xx        -           exmeritus       hww1u1a             HWW1U1A                              -                                                                                                                                 Kyle Moffett <Kyle.D.Moffett@boeing.com>
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS                             B4860QDS:PPC_B4420                                                                                                                -
-Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS_NAND                        B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
+Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS_NAND                        B4860QDS:PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND                                                                      -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS_SPIFLASH                    B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS                             B4860QDS:PPC_B4860                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SECURE_BOOT                 B4860QDS:PPC_B4860,SECURE_BOOT                                                                                                    Aneesh Bansal <aneesh.bansal@freescale.com>
-Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_NAND                        B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
+Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_NAND                        B4860QDS:PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SPIFLASH                    B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SRIO_PCIE_BOOT              B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       bsc9131rdb          BSC9131RDB_NAND                      BSC9131RDB:BSC9131RDB,NAND                                                                                                        Poonam Aggrwal <poonam.aggrwal@freescale.com>
@@ -328,4 +328,40 @@
    On Linux the interfaces are renamed as:
 	. eth2 -> fm1-gb2
 	. eth3 -> fm1-gb3
+
+NAND boot with 2 Stage boot loader
+----------------------------------
+PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
+SPL further initialise DDR using SPD and environment variables and copy
+u-boot(768 KB) from flash to DDR.
+Finally SPL transer control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+ Run time view of SPL framework during  boot :-
+ -----------------------------------------------
+ Area        | Address                         |
+-----------------------------------------------
+ Secure boot | 0xFFFC0000 (32KB)               |
+ headers     |                                 |
+ -----------------------------------------------
+ GD, BD      | 0xFFFC8000 (4KB)                |
+ -----------------------------------------------
+ ENV         | 0xFFFC9000 (8KB)                |
+ -----------------------------------------------
+ HEAP        | 0xFFFCB000 (30KB)               |
+ -----------------------------------------------
+ STACK       | 0xFFFD8000 (22KB)               |
+ -----------------------------------------------
+ U-boot SPL  | 0xFFFD8000 (160KB)              |
+ -----------------------------------------------
+
+NAND Flash memory Map on B4860 and B4420QDS
+------------------------------------------
+ Start		 End		Definition			Size
+0x000000	0x0FFFFF	u-boot                          1MB
+0x140000	0x15FFFF	u-boot env                      128KB
+0x1A0000	0x1BFFFF	FMAN Ucode                      128KB
@@ -14,11 +14,44 @@
 #define CONFIG_PHYS_64BIT
  
 #ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI	$(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW	$(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
+#ifndef CONFIG_NAND
 #define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
-#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/b4860qds/b4_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW	board/freescale/b4860qds/b4_rcw.cfg
+#else
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFD8000
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
 #endif
+#endif
+#endif
  
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
@@ -113,8 +146,8 @@
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_IN_REMOTE
 #define CONFIG_ENV_ADDR		0xffe20000
@@ -164,7 +197,16 @@
 /*
  *  Config the L3 Cache as L3 SRAM
  */
-#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		256 << 10
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_NAND
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(30 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
  
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_DCSRBAR		0xf0000000
  
@@ -193,7 +235,9 @@
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_SYS_FSL_DDR3
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_FSL_DDR_INTERACTIVE
+#endif
  
 #define CONFIG_SYS_SPD_BUS_NUM	0
 #define SPD_EEPROM_ADDRESS1	0x51
@@ -381,7 +425,11 @@
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
  
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
  
 #if defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_SYS_RAMBOOT
  
@@ -435,7 +483,9 @@
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
 #define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+#endif
  
  
 /* Use the HUSH parser */
@@ -607,7 +657,7 @@
 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1130)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR	(13 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
...	...	@@ -4,10 +4,15 @@
4	4	# SPDX-License-Identifier: GPL-2.0+
5	5	#
6	6
	7	+ifdef CONFIG_SPL_BUILD
	8	+obj-y += spl.o
	9	+else
7	10	obj-y += b4860qds.o
8		-obj-y += ddr.o
9	11	obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o
10		-obj-$(CONFIG_PCI) += pci.o
	12	+obj-$(CONFIG_PCI) += pci.o
	13	+endif
	14	+
	15	+obj-y += ddr.o
11	16	obj-y += law.o
12	17	obj-y += tlb.o
...	...	@@ -179,6 +179,7 @@
179	179	{
180	180	phys_size_t dram_size;
181	181
	182	+#if defined(CONFIG_SPL_BUILD) \|\| !defined(CONFIG_RAMBOOT_PBL)
182	183	puts("Initializing....using SPD\n");
183	184
184	185	dram_size = fsl_ddr_sdram();
...	...	@@ -186,7 +187,9 @@
186	187	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
187	188	dram_size *= 0x100000;
188	189
189		- puts(" DDR: ");
	190	+#else
	191	+ dram_size = fsl_ddr_sdram_size();
	192	+#endif
190	193	return dram_size;
191	194	}
192	195
	1	+/* Copyright 2013 Freescale Semiconductor, Inc.
	2	+ *
	3	+ * SPDX-License-Identifier: GPL-2.0+
	4	+ */
	5	+
	6	+#include <common.h>
	7	+#include <asm/spl.h>
	8	+#include <malloc.h>
	9	+#include <ns16550.h>
	10	+#include <nand.h>
	11	+#include <i2c.h>
	12	+#include "../common/qixis.h"
	13	+#include "b4860qds_qixis.h"
	14	+
	15	+DECLARE_GLOBAL_DATA_PTR;
	16	+
	17	+phys_size_t get_effective_memsize(void)
	18	+{
	19	+ return CONFIG_SYS_L3_SIZE;
	20	+}
	21	+
	22	+unsigned long get_board_sys_clk(void)
	23	+{
	24	+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	25	+
	26	+ switch ((sysclk_conf & 0x0C) >> 2) {
	27	+ case QIXIS_CLK_100:
	28	+ return 100000000;
	29	+ case QIXIS_CLK_125:
	30	+ return 125000000;
	31	+ case QIXIS_CLK_133:
	32	+ return 133333333;
	33	+ }
	34	+ return 66666666;
	35	+}
	36	+
	37	+unsigned long get_board_ddr_clk(void)
	38	+{
	39	+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
	40	+
	41	+ switch (ddrclk_conf & 0x03) {
	42	+ case QIXIS_CLK_100:
	43	+ return 100000000;
	44	+ case QIXIS_CLK_125:
	45	+ return 125000000;
	46	+ case QIXIS_CLK_133:
	47	+ return 133333333;
	48	+ }
	49	+ return 66666666;
	50	+}
	51	+
	52	+void board_init_f(ulong bootflag)
	53	+{
	54	+ u32 plat_ratio, sys_clk, uart_clk;
	55	+ ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	56	+
	57	+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
	58	+ memcpy((void )CONFIG_SPL_GD_ADDR, (void )gd, sizeof(gd_t));
	59	+
	60	+ /* Update GD pointer */
	61	+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
	62	+
	63	+ /* compiler optimization barrier needed for GCC >= 3.4 */
	64	+ __asm__ __volatile__("" : : : "memory");
	65	+
	66	+ console_init_f();
	67	+
	68	+ /* initialize selected port with appropriate baud rate */
	69	+ sys_clk = get_board_sys_clk();
	70	+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
	71	+ uart_clk = sys_clk * plat_ratio / 2;
	72	+
	73	+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
	74	+ uart_clk / 16 / CONFIG_BAUDRATE);
	75	+
	76	+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
	77	+}
	78	+
	79	+void board_init_r(gd_t *gd, ulong dest_addr)
	80	+{
	81	+ bd_t *bd;
	82	+
	83	+ bd = (bd_t *)(gd + sizeof(gd_t));
	84	+ memset(bd, 0, sizeof(bd_t));
	85	+ gd->bd = bd;
	86	+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
	87	+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
	88	+
	89	+ probecpu();
	90	+ get_clocks();
	91	+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
	92	+ CONFIG_SPL_RELOC_MALLOC_SIZE);
	93	+
	94	+#ifndef CONFIG_SPL_NAND_BOOT
	95	+ env_init();
	96	+ env_relocate();
	97	+#else
	98	+ /* relocate environment function pointers etc. */
	99	+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	100	+ (uchar *)CONFIG_ENV_ADDR);
	101	+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
	102	+ gd->env_valid = 1;
	103	+#endif
	104	+
	105	+ i2c_init_all();
	106	+
	107	+ puts("\n\n");
	108	+
	109	+ gd->ram_size = initdram(0);
	110	+
	111	+#ifdef CONFIG_SPL_NAND_BOOT
	112	+ nand_boot();
	113	+#endif
	114	+}
...	...	@@ -62,6 +62,7 @@
62	62	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,
63	63	0, 2, BOOKE_PAGESZ_256M, 1),
64	64
	65	+#ifndef CONFIG_SPL_BUILD
65	66	/* IG* - PCI */
66	67	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
67	68	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
...	...	@@ -96,6 +97,7 @@
96	97	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
97	98	0, 9, BOOKE_PAGESZ_16M, 1),
98	99	#endif
	100	+#endif
99	101	#ifdef CONFIG_SYS_DCSRBAR_PHYS
100	102	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
101	103	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
...	...	@@ -118,6 +120,7 @@
118	120	* entry 14 and 15 has been used hard coded, they will be disabled
119	121	* in cpu_init_f, so we use entry 16 for SRIO2.
120	122	*/
	123	+#ifndef CONFIG_SPL_BUILD
121	124	#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
122	125	/* IG* - SRIO1 */
123	126	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
...	...	@@ -139,6 +142,13 @@
139	142	CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
140	143	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_G,
141	144	0, 17, BOOKE_PAGESZ_1M, 1),
	145	+#endif
	146	+#endif
	147	+
	148	+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
	149	+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
	150	+ MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	151	+ 0, 17, BOOKE_PAGESZ_2G, 1)
142	152	#endif
143	153	};
144	154
...	...	@@ -741,11 +741,11 @@
741	741	Active powerpc mpc85xx - - socrates socrates - -
742	742	Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
743	743	Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 -
744		-Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
	744	+Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
745	745	Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
746	746	Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 -
747	747	Active powerpc mpc85xx - freescale b4860qds B4860QDS_SECURE_BOOT B4860QDS:PPC_B4860,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
748		-Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
	748	+Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND
749	749	Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
750	750	Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
751	751	Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal <poonam.aggrwal@freescale.com>
...	...	@@ -328,4 +328,40 @@
328	328	On Linux the interfaces are renamed as:
329	329	. eth2 -> fm1-gb2
330	330	. eth3 -> fm1-gb3
	331	+
	332	+NAND boot with 2 Stage boot loader
	333	+----------------------------------
	334	+PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
	335	+SPL further initialise DDR using SPD and environment variables and copy
	336	+u-boot(768 KB) from flash to DDR.
	337	+Finally SPL transer control to u-boot for futher booting.
	338	+
	339	+SPL has following features:
	340	+ - Executes within 256K
	341	+ - No relocation required
	342	+
	343	+ Run time view of SPL framework during boot :-
	344	+ -----------------------------------------------
	345	+ Area \| Address \|
	346	+-----------------------------------------------
	347	+ Secure boot \| 0xFFFC0000 (32KB) \|
	348	+ headers \| \|
	349	+ -----------------------------------------------
	350	+ GD, BD \| 0xFFFC8000 (4KB) \|
	351	+ -----------------------------------------------
	352	+ ENV \| 0xFFFC9000 (8KB) \|
	353	+ -----------------------------------------------
	354	+ HEAP \| 0xFFFCB000 (30KB) \|
	355	+ -----------------------------------------------
	356	+ STACK \| 0xFFFD8000 (22KB) \|
	357	+ -----------------------------------------------
	358	+ U-boot SPL \| 0xFFFD8000 (160KB) \|
	359	+ -----------------------------------------------
	360	+
	361	+NAND Flash memory Map on B4860 and B4420QDS
	362	+------------------------------------------
	363	+ Start End Definition Size
	364	+0x000000 0x0FFFFF u-boot 1MB
	365	+0x140000 0x15FFFF u-boot env 128KB
	366	+0x1A0000 0x1BFFFF FMAN Ucode 128KB
...	...	@@ -14,11 +14,44 @@
14	14	#define CONFIG_PHYS_64BIT
15	15
16	16	#ifdef CONFIG_RAMBOOT_PBL
	17	+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
	18	+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
	19	+#ifndef CONFIG_NAND
17	20	#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18	21	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
19		-#define CONFIG_SYS_FSL_PBL_PBI board/freescale/b4860qds/b4_pbi.cfg
20		-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/b4860qds/b4_rcw.cfg
	22	+#else
	23	+#define CONFIG_SPL
	24	+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	25	+#define CONFIG_SPL_ENV_SUPPORT
	26	+#define CONFIG_SPL_SERIAL_SUPPORT
	27	+#define CONFIG_SPL_FLUSH_IMAGE
	28	+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	29	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	30	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	31	+#define CONFIG_SPL_I2C_SUPPORT
	32	+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
	33	+#define CONFIG_FSL_LAW /* Use common FSL init code */
	34	+#define CONFIG_SYS_TEXT_BASE 0x00201000
	35	+#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
	36	+#define CONFIG_SPL_PAD_TO 0x40000
	37	+#define CONFIG_SPL_MAX_SIZE 0x28000
	38	+#define RESET_VECTOR_OFFSET 0x27FFC
	39	+#define BOOT_PAGE_OFFSET 0x27000
	40	+#define CONFIG_SPL_NAND_SUPPORT
	41	+#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
	42	+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
	43	+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
	44	+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
	45	+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
	46	+#define CONFIG_SPL_NAND_BOOT
	47	+#ifdef CONFIG_SPL_BUILD
	48	+#define CONFIG_SPL_SKIP_RELOCATE
	49	+#define CONFIG_SPL_COMMON_INIT_DDR
	50	+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
	51	+#define CONFIG_SYS_NO_FLASH
21	52	#endif
	53	+#endif
	54	+#endif
22	55
23	56	#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
24	57	/* Set 1M boot space */
...	...	@@ -113,8 +146,8 @@
113	146	#elif defined(CONFIG_NAND)
114	147	#define CONFIG_SYS_EXTRA_ENV_RELOC
115	148	#define CONFIG_ENV_IS_IN_NAND
116		-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
117		-#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
	149	+#define CONFIG_ENV_SIZE 0x2000
	150	+#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
118	151	#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
119	152	#define CONFIG_ENV_IS_IN_REMOTE
120	153	#define CONFIG_ENV_ADDR 0xffe20000
...	...	@@ -164,7 +197,16 @@
164	197	/*
165	198	* Config the L3 Cache as L3 SRAM
166	199	*/
167		-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
	200	+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
	201	+#define CONFIG_SYS_L3_SIZE 256 << 10
	202	+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
	203	+#ifdef CONFIG_NAND
	204	+#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
	205	+#endif
	206	+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
	207	+#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
	208	+#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
	209	+#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
168	210
169	211	#ifdef CONFIG_PHYS_64BIT
170	212	#define CONFIG_SYS_DCSRBAR 0xf0000000
171	213
...	...	@@ -193,7 +235,9 @@
193	235	#define CONFIG_DDR_SPD
194	236	#define CONFIG_SYS_DDR_RAW_TIMING
195	237	#define CONFIG_SYS_FSL_DDR3
	238	+#ifndef CONFIG_SPL_BUILD
196	239	#define CONFIG_FSL_DDR_INTERACTIVE
	240	+#endif
197	241
198	242	#define CONFIG_SYS_SPD_BUS_NUM 0
199	243	#define SPD_EEPROM_ADDRESS1 0x51
...	...	@@ -381,7 +425,11 @@
381	425	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
382	426	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
383	427
384		-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	428	+#ifdef CONFIG_SPL_BUILD
	429	+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	430	+#else
	431	+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	432	+#endif
385	433
386	434	#if defined(CONFIG_RAMBOOT_PBL)
387	435	#define CONFIG_SYS_RAMBOOT
388	436
...	...	@@ -435,7 +483,9 @@
435	483	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
436	484	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
437	485	#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
	486	+#ifndef CONFIG_SPL_BUILD
438	487	#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
	488	+#endif
439	489
440	490
441	491	/* Use the HUSH parser */
...	...	@@ -607,7 +657,7 @@
607	657	#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
608	658	#elif defined(CONFIG_NAND)
609	659	#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
610		-#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
	660	+#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
611	661	#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
612	662	/*
613	663	* Slave has no ucode locally, it can fetch this from remote. When implementing