Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit c5f3ebc2b4a3d01f2a923776450661787dd0aee3

Authored by Anson Huang
1 parent 772af34b12
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-12658 imx: adjust POR_B setting on i.MX6ULL 

Adjust POR_B settings on i.MX6ULL according to design
team's suggestion:

2'b00 :  always PUP100K
2'b01 :  PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL
2'b10 :  always disable PUP100K
2'b11 :  PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Showing 1 changed file with 14 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ c5f3ebc
... ... @@ -490,6 +490,20 @@
490 490 }
491 491 }
492 492  
  493 + if (is_cpu_type(MXC_CPU_MX6ULL)) {
  494 + /*
  495 + * GPBIT[1:0] is suggested to set to 2'b11:
  496 + * 2'b00 : always PUP100K
  497 + * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL
  498 + * 2'b10 : always disable PUP100K
  499 + * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL
  500 + * register offset is different from i.MX6UL, since
  501 + * i.MX6UL is fixed by ECO.
  502 + */
  503 + writel(readl(MX6UL_SNVS_LP_BASE_ADDR) |
  504 + 0x3, MX6UL_SNVS_LP_BASE_ADDR);
  505 + }
  506 +
493 507 /* Set perclk to source from OSC 24MHz */
494 508 #if defined(CONFIG_MX6SL)
495 509 set_preclk_from_osc();