Commit c60560c34cb0393747e9a9461ecc9c8286eb7074
1 parent
261192baf2
Exists in
smarc-n7.1.2_2.0.0-ga
and in
4 other branches
MLK-14776 imx6sl: add enet phy reset to i.MX6SL EVK board
For some i.MX6SL evk board, enet phy need reset. Add phy reset before phy clock enable and init the pinctrl earlier. Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Showing 1 changed file with 8 additions and 7 deletions Side-by-side Diff
board/freescale/mx6slevk/mx6slevk.c
| ... | ... | @@ -74,7 +74,7 @@ |
| 74 | 74 | #define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ |
| 75 | 75 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
| 76 | 76 | |
| 77 | -#define ETH_PHY_POWER IMX_GPIO_NR(4, 21) | |
| 77 | +#define ETH_PHY_RESET IMX_GPIO_NR(4, 21) | |
| 78 | 78 | |
| 79 | 79 | int dram_init(void) |
| 80 | 80 | { |
| ... | ... | @@ -223,10 +223,12 @@ |
| 223 | 223 | { |
| 224 | 224 | imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); |
| 225 | 225 | |
| 226 | - /* Power up LAN8720 PHY */ | |
| 227 | - gpio_request(ETH_PHY_POWER, "LAN8720 PHY PWR"); | |
| 228 | - gpio_direction_output(ETH_PHY_POWER , 1); | |
| 229 | - udelay(15000); | |
| 226 | + gpio_request(ETH_PHY_RESET, "LAN8720 PHY RST"); | |
| 227 | + | |
| 228 | + /* Reset LAN8720 PHY */ | |
| 229 | + gpio_direction_output(ETH_PHY_RESET , 0); | |
| 230 | + udelay(500); | |
| 231 | + gpio_set_value(ETH_PHY_RESET, 1); | |
| 230 | 232 | } |
| 231 | 233 | |
| 232 | 234 | #define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) |
| ... | ... | @@ -555,8 +557,6 @@ |
| 555 | 557 | #ifdef CONFIG_FEC_MXC |
| 556 | 558 | int board_eth_init(bd_t *bis) |
| 557 | 559 | { |
| 558 | - setup_iomux_fec(); | |
| 559 | - | |
| 560 | 560 | return cpu_eth_init(bis); |
| 561 | 561 | } |
| 562 | 562 | |
| ... | ... | @@ -564,6 +564,7 @@ |
| 564 | 564 | { |
| 565 | 565 | struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 566 | 566 | |
| 567 | + setup_iomux_fec(); | |
| 567 | 568 | /* clear gpr1[14], gpr1[18:17] to select anatop clock */ |
| 568 | 569 | clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); |
| 569 | 570 |