Eric Lee / smarc-uboot

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Commit c620c01e96814558470698ed5cab1bf2f504d1b5

Authored by Graeme Russ
Committed by Wolfgang Denk
1 parent 0c0ccf401e
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Added initial eNET board support 

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>

Showing 10 changed files with 766 additions and 0 deletions Side-by-side Diff

... ... @@ -659,6 +659,7 @@
659 659  
660 660 LIST_I486=" \
661 661 sc520_cdp \
  662 + sc520_eNET \
662 663 sc520_spunk \
663 664 sc520_spunk_rel \
664 665 "
... ... @@ -2996,6 +2996,9 @@
2996 2996 sc520_cdp_config : unconfig
2997 2997 @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp
2998 2998  
  2999 +eNET_config : unconfig
  3000 + @$(MKCONFIG) $(@:_config=) i386 i386 eNET
  3001 +
2999 3002 sc520_spunk_config : unconfig
3000 3003 @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk
3001 3004  
  1 +#
  2 +# (C) Copyright 2008
  3 +# Graeme Russ, graeme.russ@gmail.com.
  4 +#
  5 +# (C) Copyright 2006
  6 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7 +#
  8 +# (C) Copyright 2002
  9 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
  10 +#
  11 +# See file CREDITS for list of people who contributed to this
  12 +# project.
  13 +#
  14 +# This program is free software; you can redistribute it and/or
  15 +# modify it under the terms of the GNU General Public License as
  16 +# published by the Free Software Foundation; either version 2 of
  17 +# the License, or (at your option) any later version.
  18 +#
  19 +# This program is distributed in the hope that it will be useful,
  20 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  21 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22 +# GNU General Public License for more details.
  23 +#
  24 +# You should have received a copy of the GNU General Public License
  25 +# along with this program; if not, write to the Free Software
  26 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27 +# MA 02111-1307 USA
  28 +#
  29 +
  30 +include $(TOPDIR)/config.mk
  31 +
  32 +LIB = $(obj)lib$(BOARD).a
  33 +
  34 +COBJS := eNET.o
  35 +SOBJS := eNET_start16.o eNET_start.o
  36 +
  37 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  38 +OBJS := $(addprefix $(obj),$(COBJS))
  39 +SOBJS := $(addprefix $(obj),$(SOBJS))
  40 +
  41 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
  42 + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
  43 +
  44 +clean:
  45 + rm -f $(SOBJS) $(OBJS)
  46 +
  47 +distclean: clean
  48 + rm -f $(LIB) core *.bak $(obj).depend
  49 +
  50 +#########################################################################
  51 +
  52 +# defines $(obj).depend target
  53 +include $(SRCTREE)/rules.mk
  54 +
  55 +sinclude $(obj).depend
  56 +
  57 +#########################################################################
board/eNET/config.mk
Diff comments   View file @ c620c01
  1 +#
  2 +# (C) Copyright 2002
  3 +# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +TEXT_BASE = 0x38040000
  1 +/*
  2 + * (C) Copyright 2008
  3 + * Graeme Russ, graeme.russ@gmail.com.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <asm/io.h>
  26 +#include <asm/ic/sc520.h>
  27 +
  28 +#ifdef CONFIG_HW_WATCHDOG
  29 +#include <watchdog.h>
  30 +#endif
  31 +
  32 +#include "hardware.h"
  33 +
  34 +DECLARE_GLOBAL_DATA_PTR;
  35 +
  36 +#undef SC520_CDP_DEBUG
  37 +
  38 +#ifdef SC520_CDP_DEBUG
  39 +#define PRINTF(fmt,args...) printf (fmt ,##args)
  40 +#else
  41 +#define PRINTF(fmt,args...)
  42 +#endif
  43 +
  44 +unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
  45 +
  46 +void init_sc520_enet (void)
  47 +{
  48 + /* Set CPU Speed to 100MHz */
  49 + write_mmcr_byte(SC520_CPUCTL, 1);
  50 + gd->cpu_clk = 100000000;
  51 +
  52 + /* wait at least one millisecond */
  53 + asm("movl $0x2000,%%ecx\n"
  54 + "wait_loop: pushl %%ecx\n"
  55 + "popl %%ecx\n"
  56 + "loop wait_loop\n": : : "ecx");
  57 +
  58 + /* turn on the SDRAM write buffer */
  59 + write_mmcr_byte(SC520_DBCTL, 0x11);
  60 +
  61 + /* turn on the cache and disable write through */
  62 + asm("movl %%cr0, %%eax\n"
  63 + "andl $0x9fffffff, %%eax\n"
  64 + "movl %%eax, %%cr0\n" : : : "eax");
  65 +}
  66 +
  67 +/*
  68 + * Miscellaneous platform dependent initializations
  69 + */
  70 +int board_init(void)
  71 +{
  72 + init_sc520_enet();
  73 +
  74 + write_mmcr_byte(SC520_GPCSRT, 0x01); /* GP Chip Select Recovery Time */
  75 + write_mmcr_byte(SC520_GPCSPW, 0x07); /* GP Chip Select Pulse Width */
  76 + write_mmcr_byte(SC520_GPCSOFF, 0x00); /* GP Chip Select Offset */
  77 + write_mmcr_byte(SC520_GPRDW, 0x05); /* GP Read pulse width */
  78 + write_mmcr_byte(SC520_GPRDOFF, 0x01); /* GP Read offset */
  79 + write_mmcr_byte(SC520_GPWRW, 0x05); /* GP Write pulse width */
  80 + write_mmcr_byte(SC520_GPWROFF, 0x01); /* GP Write offset */
  81 +
  82 + write_mmcr_word(SC520_PIODATA15_0, 0x0630); /* PIO15_PIO0 Data */
  83 + write_mmcr_word(SC520_PIODATA31_16, 0x2000); /* PIO31_PIO16 Data */
  84 + write_mmcr_word(SC520_PIODIR31_16, 0x2000); /* GPIO Direction */
  85 + write_mmcr_word(SC520_PIODIR15_0, 0x87b5); /* GPIO Direction */
  86 + write_mmcr_word(SC520_PIOPFS31_16, 0x0dfe); /* GPIO pin function 31-16 reg */
  87 + write_mmcr_word(SC520_PIOPFS15_0, 0x200a); /* GPIO pin function 15-0 reg */
  88 + write_mmcr_byte(SC520_CSPFS, 0x00f8); /* Chip Select Pin Function Select */
  89 +
  90 + write_mmcr_long(SC520_PAR2, 0x200713f8); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
  91 + write_mmcr_long(SC520_PAR3, 0x2c0712f8); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
  92 + write_mmcr_long(SC520_PAR4, 0x300711f8); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
  93 + write_mmcr_long(SC520_PAR5, 0x340710f8); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
  94 + write_mmcr_long(SC520_PAR6, 0xe3ffc000); /* SDRAM (0x00000000, 128MB) */
  95 + write_mmcr_long(SC520_PAR7, 0xaa3fd000); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
  96 + write_mmcr_long(SC520_PAR8, 0xca3fd100); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
  97 + write_mmcr_long(SC520_PAR9, 0x4203d900); /* SRAM (GPCS0, 0x19000000, 1MB) */
  98 + write_mmcr_long(SC520_PAR10, 0x4e03d910); /* SRAM (GPCS3, 0x19100000, 1MB) */
  99 + write_mmcr_long(SC520_PAR11, 0x50018100); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
  100 + write_mmcr_long(SC520_PAR12, 0x54020000); /* CFLASH1 (0x200000000, 4kB) */
  101 + write_mmcr_long(SC520_PAR13, 0x5c020001); /* CFLASH2 (0x200010000, 4kB) */
  102 +/* write_mmcr_long(SC520_PAR14, 0x8bfff800); */ /* BOOTCS at 0x18000000 */
  103 +/* write_mmcr_long(SC520_PAR15, 0x38201000); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
  104 +
  105 + /* Disable Watchdog */
  106 + write_mmcr_word(0x0cb0, 0x3333);
  107 + write_mmcr_word(0x0cb0, 0xcccc);
  108 + write_mmcr_word(0x0cb0, 0x0000);
  109 +
  110 + /* Chip Select Configuration */
  111 + write_mmcr_word(SC520_BOOTCSCTL, 0x0033);
  112 + write_mmcr_word(SC520_ROMCS1CTL, 0x0615);
  113 + write_mmcr_word(SC520_ROMCS2CTL, 0x0615);
  114 +
  115 + write_mmcr_byte(SC520_ADDDECCTL, 0x02);
  116 + write_mmcr_byte(SC520_UART1CTL, 0x07);
  117 + write_mmcr_byte(SC520_SYSARBCTL,0x06);
  118 + write_mmcr_word(SC520_SYSARBMENB, 0x0003);
  119 +
  120 + /* Crystal is 33.000MHz */
  121 + gd->bus_clk = 33000000;
  122 +
  123 + return 0;
  124 +}
  125 +
  126 +int dram_init(void)
  127 +{
  128 + init_sc520_dram();
  129 + return 0;
  130 +}
  131 +
  132 +void show_boot_progress(int val)
  133 +{
  134 + uchar led_mask;
  135 +
  136 + led_mask = 0x00;
  137 +
  138 + if (val < 0)
  139 + led_mask |= LED_ERR_BITMASK;
  140 +
  141 + led_mask |= (uchar)(val & 0x001f);
  142 + outb(led_mask, LED_LATCH_ADDRESS);
  143 +}
  144 +
  145 +
  146 +int last_stage_init(void)
  147 +{
  148 + int minor;
  149 + int major;
  150 +
  151 + major = minor = 0;
  152 +
  153 + printf("Serck Controls eNET\n");
  154 +
  155 + return 0;
  156 +}
  157 +
  158 +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
  159 +{
  160 + if (banknum == 0) { /* non-CFI boot flash */
  161 + info->portwidth = FLASH_CFI_8BIT;
  162 + info->chipwidth = FLASH_CFI_BY8;
  163 + info->interface = FLASH_CFI_X8;
  164 + return 1;
  165 + } else
  166 + return 0;
  167 +}
board/eNET/eNET_start.S
Diff comments   View file @ c620c01
  1 +/*
  2 + * (C) Copyright 2008
  3 + * Graeme Russ, graeme.russ@gmail.com.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include "hardware.h"
  25 +
  26 +/* board early intialization */
  27 +.globl early_board_init
  28 +early_board_init:
  29 + /* No 32-bit board specific initialisation */
  30 + jmp *%ebp /* return to caller */
  31 +
  32 +.globl show_boot_progress_asm
  33 +show_boot_progress_asm:
  34 +
  35 + movb %al, %dl /* Create Working Copy */
  36 + andb $0x80, %dl /* Mask in only Error bit */
  37 + shrb $0x02, %dl /* Shift Error bit to Error LED */
  38 + andb $0x0f, %al /* Mask out 'Error' bit */
  39 + orb %dl, %al /* Mask in ERR LED */
  40 + movw $LED_LATCH_ADDRESS, %dx
  41 + outb %al, %dx
  42 + jmp *%ebp /* return to caller */
  43 +
  44 +.globl cpu_halt_asm
  45 +cpu_halt_asm:
  46 + movb $0x0f, %al
  47 + movw $LED_LATCH_ADDRESS, %dx
  48 + outb %al, %dx
  49 + hlt
  50 + jmp cpu_halt_asm
board/eNET/eNET_start16.S
Diff comments   View file @ c620c01
  1 +/*
  2 + * (C) Copyright 2008
  3 + * Graeme Russ, graeme.russ@gmail.com.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * 16bit initialization code.
  26 + * This code have to map the area of the boot flash
  27 + * that is used by U-boot to its final destination.
  28 + */
  29 +
  30 +/* #include <asm/ic/sc520_defs.h> */
  31 +
  32 +#include "hardware.h"
  33 +
  34 +.text
  35 +.section .start16, "ax"
  36 +.code16
  37 +.globl board_init16
  38 +board_init16:
  39 + /* Alias MMCR to 0xdf000 */
  40 + movw $0xfffc, %dx
  41 + movl $0x800df0cb, %eax
  42 + outl %eax, %dx
  43 +
  44 + /* Set ds to point to MMCR alias */
  45 + movw $0xdf00, %ax
  46 + movw %ax, %ds
  47 +
  48 + /* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
  49 + movl $0x00c0, %edi /* SC520_PAR14 */
  50 + movl $0x8bfff800, %eax /* TODO: Check this */
  51 + movl %eax, (%di)
  52 +
  53 + /* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
  54 + movl $0x00c4, %edi /* SC520_PAR15 */
  55 + movl $0x38201000, %eax
  56 + movl %eax, (%di)
  57 +
  58 + /* Disable SDRAM write buffer */
  59 + movw $0x0040, %di /* SC520_DBCTL */
  60 + xorw %ax, %ax
  61 + movb %al, (%di)
  62 +
  63 + /* Disabe MMCR alias */
  64 + movw $0xfffc, %dx
  65 + movl $0x000000cb, %eax
  66 + outl %eax, %dx
  67 +
  68 + /* the return address is stored in bp */
  69 + jmp *%bp
  70 +
  71 +.section .bios, "ax"
  72 +.code16
  73 +.globl realmode_reset
  74 +realmode_reset:
  75 + /* Alias MMCR to 0xdf000 */
  76 + movw $0xfffc, %dx
  77 + movl $0x800df0cb, %eax
  78 + outl %eax, %dx
  79 +
  80 + /* Set ds to point to MMCR alias */
  81 + movw $0xdf00, %ax
  82 + movw %ax, %ds
  83 +
  84 + /* issue software reset thorugh MMCR */
  85 + movl $0xd72, %edi
  86 + movb $0x01, %al
  87 + movb %al, (%di)
  88 +
  89 +1: hlt
  90 + jmp 1
board/eNET/hardware.h
Diff comments   View file @ c620c01
  1 +/*
  2 + * (C) Copyright 2008
  3 + * Graeme Russ, graeme.russ@gmail.com.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef HARDWARE_H_
  25 +#define HARDWARE_H_
  26 +
  27 +#define LED_LATCH_ADDRESS 0x1002
  28 +#define LED_RUN_BITMASK 0x01
  29 +#define LED_1_BITMASK 0x02
  30 +#define LED_2_BITMASK 0x04
  31 +#define LED_RX_BITMASK 0x08
  32 +#define LED_TX_BITMASK 0x10
  33 +#define LED_ERR_BITMASK 0x20
  34 +
  35 +#endif /* HARDWARE_H_ */
board/eNET/u-boot.lds
Diff comments   View file @ c620c01
  1 +/*
  2 + * (C) Copyright 2002
  3 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
  25 +OUTPUT_ARCH(i386)
  26 +ENTRY(_start)
  27 +
  28 +SECTIONS
  29 +{
  30 + . = 0x38040000; /* Location of bootcode in flash */
  31 + .text : { *(.text); }
  32 +
  33 + . = ALIGN(4);
  34 + .rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) }
  35 +
  36 + _i386boot_text_size = SIZEOF(.text) + SIZEOF(.rodata);
  37 +
  38 + . = 0x03FF0000; /* Ram data segment to use */
  39 + _i386boot_romdata_dest = ABSOLUTE(.);
  40 + .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
  41 + _i386boot_romdata_start = LOADADDR(.data);
  42 +
  43 + . = ALIGN(4);
  44 + .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) }
  45 +
  46 + . = ALIGN(4);
  47 + __u_boot_cmd_start = .;
  48 + .u_boot_cmd : { *(.u_boot_cmd) }
  49 + __u_boot_cmd_end = .;
  50 + _i386boot_cmd_start = LOADADDR(.u_boot_cmd);
  51 +
  52 + _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got) + SIZEOF(.u_boot_cmd);
  53 +
  54 + . = ALIGN(4);
  55 + _i386boot_bss_start = ABSOLUTE(.);
  56 + .bss (NOLOAD) : { *(.bss) }
  57 + _i386boot_bss_size = SIZEOF(.bss);
  58 +
  59 + /* 16bit realmode trampoline code */
  60 + .realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) + SIZEOF(.u_boot_cmd)) { *(.realmode) }
  61 +
  62 + _i386boot_realmode = LOADADDR(.realmode);
  63 + _i386boot_realmode_size = SIZEOF(.realmode);
  64 +
  65 + /* 16bit BIOS emulation code (just enough to boot Linux) */
  66 + .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) }
  67 +
  68 + _i386boot_bios = LOADADDR(.bios);
  69 + _i386boot_bios_size = SIZEOF(.bios);
  70 +
  71 + /* The load addresses below assumes that the flash
  72 + * will be mapped so that 0x387f0000 == 0xffff0000
  73 + * at reset time
  74 + *
  75 + * The fe00 and ff00 offsets of the start32 and start16
  76 + * segments are arbitrary, the just have to be mapped
  77 + * at reset and the code have to fit.
  78 + * The fff0 offset of reset is important, however.
  79 + */
  80 +
  81 + . = 0xfffffe00;
  82 + .start32 : AT (0x3807fe00) { *(.start32); }
  83 +
  84 + . = 0xf800;
  85 + .start16 : AT (0x3807f800) { *(.start16); }
  86 +
  87 + . = 0xfff0;
  88 + .reset : AT (0x3807fff0) { *(.reset); }
  89 + _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) );
  90 +}
include/configs/eNET.h
Diff comments   View file @ c620c01
  1 +/*
  2 + * (C) Copyright 2008
  3 + * Graeme Russ, graeme.russ@gmail.com.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * board/config.h - configuration options, board specific
  26 + */
  27 +
  28 +#ifndef __CONFIG_H
  29 +#define __CONFIG_H
  30 +
  31 +/*
  32 + * Stuff still to be dealt with -
  33 + */
  34 +#define CONFIG_RTC_MC146818
  35 +
  36 +/*
  37 + * High Level Configuration Options
  38 + * (easy to change)
  39 + */
  40 +#define DEBUG_PARSER
  41 +
  42 +#define CONFIG_X86 1 /* Intel X86 CPU */
  43 +#define CONFIG_SC520 1 /* AMD SC520 */
  44 +#define CONFIG_SC520_SSI
  45 +#define CONFIG_SHOW_BOOT_PROGRESS 1
  46 +#define CONFIG_LAST_STAGE_INIT 1
  47 +
  48 +/*
  49 + * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the
  50 + * bottom (processor) board MUST be removed!
  51 + */
  52 +#undef CONFIG_WATCHDOG
  53 +#undef CONFIG_HW_WATCHDOG
  54 +
  55 + /*-----------------------------------------------------------------------
  56 + * Video Configuration
  57 + */
  58 +#undef CONFIG_VIDEO /* No Video Hardware */
  59 +#undef CONFIG_CFB_CONSOLE
  60 +
  61 +/*
  62 + * Size of malloc() pool
  63 + */
  64 +#define CONFIG_MALLOC_SIZE (CONFIG_SYS_ENV_SIZE + 128*1024)
  65 +
  66 +#define CONFIG_BAUDRATE 9600
  67 +
  68 +/*-----------------------------------------------------------------------
  69 + * Command line configuration.
  70 + */
  71 +#include <config_cmd_default.h>
  72 +
  73 +#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */
  74 +#define CONFIG_CMD_BDI /* bdinfo */
  75 +#define CONFIG_CMD_BOOTD /* bootd */
  76 +#define CONFIG_CMD_CONSOLE /* coninfo */
  77 +#define CONFIG_CMD_ECHO /* echo arguments */
  78 +#define CONFIG_CMD_ENV /* saveenv */
  79 +#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
  80 +#define CONFIG_CMD_FPGA /* FPGA configuration Support */
  81 +#define CONFIG_CMD_IMI /* iminfo */
  82 +#define CONFIG_CMD_IMLS /* List all found images */
  83 +#define CONFIG_CMD_ITEST /* Integer (and string) test */
  84 +#define CONFIG_CMD_LOADB /* loadb */
  85 +#define CONFIG_CMD_LOADS /* loads */
  86 +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
  87 +#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
  88 +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
  89 +#undef CONFIG_CMD_NFS /* NFS support */
  90 +#define CONFIG_CMD_RUN /* run command in env variable */
  91 +#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
  92 +#define CONFIG_CMD_XIMG /* Load part of Multi Image */
  93 +#undef CONFIG_CMD_IRQ /* IRQ Information */
  94 +
  95 +#define CONFIG_BOOTDELAY 15
  96 +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
  97 +/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
  98 +
  99 +#if defined(CONFIG_CMD_KGDB)
  100 +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
  101 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  102 +#endif
  103 +
  104 +/*
  105 + * Miscellaneous configurable options
  106 + */
  107 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  108 +#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
  109 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  110 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  111 + sizeof(CONFIG_SYS_PROMPT) + \
  112 + 16) /* Print Buffer Size */
  113 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  114 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  115 +
  116 +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
  117 +#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
  118 +
  119 +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
  120 +
  121 +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  122 +
  123 +#define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */
  124 +
  125 + /* valid baudrates */
  126 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  127 +
  128 +/*-----------------------------------------------------------------------
  129 + * SDRAM Configuration
  130 + */
  131 +#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
  132 +#define CONFIG_NR_DRAM_BANKS 4
  133 +
  134 +/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
  135 +#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
  136 +#undef CONFIG_SYS_SDRAM_REFRESH_RATE
  137 +#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
  138 +#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
  139 +#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
  140 +
  141 +/*-----------------------------------------------------------------------
  142 + * CPU Features
  143 + */
  144 +#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
  145 +#define CONFIG_SYS_RESET_GENERIC /* use triple-fault to reset cpu */
  146 +#undef CONFIG_SYS_RESET_SC520 /* use SC520 MMCR's to reset cpu */
  147 +#define CONFIG_SYS_TIMER_SC520 /* use SC520 swtimers */
  148 +#undef CONFIG_SYS_TIMER_GENERIC /* use the i8254 PIT timers */
  149 +#undef CONFIG_SYS_TIMER_TSC /* use the Pentium TSC timers */
  150 +#define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
  151 + * in the SC520 on the CDP */
  152 +
  153 +/*-----------------------------------------------------------------------
  154 + * Memory organization
  155 + */
  156 +#define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */
  157 +#define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */
  158 +#define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */
  159 +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
  160 +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  161 +#define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */
  162 +#define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */
  163 +#define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */
  164 +
  165 +/* timeout values are in ticks */
  166 +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
  167 +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
  168 +
  169 +/* allow to overwrite serial and ethaddr */
  170 +#define CONFIG_ENV_OVERWRITE
  171 +
  172 + /*-----------------------------------------------------------------------
  173 + * FLASH configuration
  174 + */
  175 +#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
  176 +#define CONFIG_FLASH_CFI_LEGACY
  177 +#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */
  178 +#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
  179 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
  180 + CONFIG_SYS_FLASH_BASE_1, \
  181 + CONFIG_SYS_FLASH_BASE_2}
  182 +#define CONFIG_SYS_FLASH_EMPTY_INFO
  183 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  184 +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
  185 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
  186 +#define CONFIG_SYS_FLASH_LEGACY_512Kx8
  187 +
  188 + /*-----------------------------------------------------------------------
  189 + * Environment configuration
  190 + */
  191 +#define CONFIG_ENV_IS_IN_FLASH 1
  192 +#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
  193 +#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
  194 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
  195 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE_1 + \
  196 + CONFIG_ENV_OFFSET)
  197 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
  198 + CONFIG_ENV_SECT_SIZE)
  199 +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  200 +
  201 +
  202 + /*-----------------------------------------------------------------------
  203 + * PCI configuration
  204 + */
  205 +#undef CONFIG_PCI /* include pci support */
  206 +#undef CONFIG_PCI_PNP /* pci plug-and-play */
  207 +#undef CONFIG_PCI_SCAN_SHOW
  208 +#undef CONFIG_SYS_FIRST_PCI_IRQ
  209 +#undef CONFIG_SYS_SECOND_PCI_IRQ
  210 +#undef CONFIG_SYS_THIRD_PCI_IRQ
  211 +#undef CONFIG_SYS_FORTH_PCI_IRQ
  212 +
  213 +/*-----------------------------------------------------------------------
  214 + * Hardware watchdog configuration
  215 + */
  216 +#define CONFIG_SYS_WATCHDOG_PIO_BIT 0x8000
  217 +#define CONFIG_SYS_WATCHDIG_PIO_DATA SC520_PIODATA15_0
  218 +#define CONFIG_SYS_WATCHDIG_PIO_CLR SC520_PIOCLR15_0
  219 +#define CONFIG_SYS_WATCHDIG_PIO_SET SC520_PIOSET15_0
  220 +
  221 +/*-----------------------------------------------------------------------
  222 + * FPGA configuration
  223 + */
  224 +#define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000
  225 +#define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000
  226 +#define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000
  227 +#define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16
  228 +#define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16
  229 +#define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16
  230 +#define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16
  231 +#define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */
  232 +#define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */
  233 +#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */
  234 +#define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */
  235 +
  236 +#ifndef __ASSEMBLER__
  237 +extern unsigned long ip;
  238 +
  239 +#define PRINTIP asm ("call next_line\n" \
  240 + "next_line:\n" \
  241 + "pop %%eax\n" \
  242 + "movl %%eax, %0\n" \
  243 + :"=r"(ip) \
  244 + : /* No Input Registers */ \
  245 + :"%eax"); \
  246 + printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__);
  247 +
  248 +#endif
  249 +#endif /* __CONFIG_H */