Eric Lee / smarc-uboot

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Commit c6d48700754bc3245ec03c38b9c32d58fda17288

Authored by Ye Li
1 parent f0c57ffd95
Exists in smarc_8mq-imx_v2020.04_5.4.24_2.1.0 and in 1 other branch smarc_8mm-imx_v2020.04_5.4.24_2.1.0

MLK-23964-23 imx7ulp_evk: Enable the rm68200 mipi panel for splash screen 

Update DTS for LCDIF, MIPI DSI and panel relevant nodes.
Enable the video drivers and splash screen in board codse

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 52d4c7c3e98d573f1c3e4e67e02dd4b08be6bee7)

Showing 11 changed files with 196 additions and 21 deletions Side-by-side Diff

arch/arm/dts/imx7ulp-evk.dts
Diff comments   View file @ c6d4870
... ... @@ -31,7 +31,7 @@
31 31 reg = <0x60000000 0x40000000>;
32 32 };
33 33  
34   - backlight {
  34 + backlight: backlight {
35 35 compatible = "gpio-backlight";
36 36 pinctrl-names = "default";
37 37 pinctrl-0 = <&pinctrl_backlight>;
... ... @@ -47,6 +47,24 @@
47 47 #reset-cells = <0>;
48 48 };
49 49  
  50 + dsi_host: dsi-host {
  51 + compatible = "northwest,mipi-dsi";
  52 + status = "okay";
  53 + };
  54 +
  55 + rm68200_panel {
  56 + compatible = "raydium,rm68200";
  57 + reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
  58 + backlight = <&backlight>;
  59 + status = "okay";
  60 +
  61 + port {
  62 + rm68200_from_dsim: endpoint {
  63 + remote-endpoint = <&dsim_to_rm68200>;
  64 + };
  65 + };
  66 + };
  67 +
50 68 regulators {
51 69 compatible = "simple-bus";
52 70 #address-cells = <1>;
53 71  
54 72  
55 73  
56 74  
57 75  
... ... @@ -285,32 +303,21 @@
285 303 };
286 304  
287 305 &lcdif {
  306 + #address-cells = <1>;
  307 + #size-cells = <0>;
288 308 status = "okay";
289   - disp-dev = "mipi_dsi_northwest";
290 309 display = <&display0>;
291 310  
292 311 display0: display@0 {
293   - bits-per-pixel = <16>;
  312 + bits-per-pixel = <24>;
294 313 bus-width = <24>;
  314 + };
295 315  
296   - display-timings {
297   - native-mode = <&timing0>;
298   - timing0: timing0 {
299   - clock-frequency = <9200000>;
300   - hactive = <480>;
301   - vactive = <272>;
302   - hfront-porch = <8>;
303   - hback-porch = <4>;
304   - hsync-len = <41>;
305   - vback-porch = <2>;
306   - vfront-porch = <4>;
307   - vsync-len = <10>;
  316 + lcdif_disp0: port@0 {
  317 + reg = <0>;
308 318  
309   - hsync-active = <0>;
310   - vsync-active = <0>;
311   - de-active = <1>;
312   - pixelclk-active = <0>;
313   - };
  319 + lcdif_to_dsim: endpoint {
  320 + remote-endpoint = <&dsim_from_lcdif>;
314 321 };
315 322 };
316 323 };
317 324  
... ... @@ -345,11 +352,25 @@
345 352 };
346 353  
347 354 &mipi_dsi {
  355 + #address-cells = <1>;
  356 + #size-cells = <0>;
348 357 pinctrl-names = "default";
349 358 pinctrl-0 = <&pinctrl_mipi_dsi_reset>;
350 359 lcd_panel = "TRULY-WVGA-TFT3P5581E";
351 360 resets = <&mipi_dsi_reset>;
352 361 status = "okay";
  362 +
  363 + port@0 {
  364 + dsim_from_lcdif: endpoint {
  365 + remote-endpoint = <&lcdif_to_dsim>;
  366 + };
  367 + };
  368 +
  369 + port@1 {
  370 + dsim_to_rm68200: endpoint {
  371 + remote-endpoint = <&rm68200_from_dsim>;
  372 + };
  373 + };
353 374 };
354 375  
355 376 &lpuart4 { /* console */
arch/arm/dts/imx7ulp.dtsi
Diff comments   View file @ c6d4870
... ... @@ -488,6 +488,9 @@
488 488 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
489 489 clocks = <&clks IMX7ULP_CLK_DSI>;
490 490 clock-names = "mipi_dsi_clk";
  491 + data-lanes-num = <2>;
  492 + phy-ref-clkfreq = <24000000>;
  493 + max-data-rate = <800000000>;
491 494 sim = <&sim>;
492 495 status = "disabled";
493 496 };
arch/arm/include/asm/arch-mx7ulp/clock.h
Diff comments   View file @ c6d4870
... ... @@ -36,6 +36,8 @@
36 36 #ifdef CONFIG_USB_EHCI_HCD
37 37 void enable_usboh3_clk(unsigned char enable);
38 38 #endif
  39 +void enable_mipi_dsi_clk(unsigned char enable);
  40 +void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq_in_khz);
39 41 void init_clk_usdhc(u32 index);
40 42 void clock_init(void);
41 43 void hab_caam_clock_enable(unsigned char enable);
arch/arm/include/asm/arch-mx7ulp/imx-regs.h
Diff comments   View file @ c6d4870
... ... @@ -67,6 +67,8 @@
67 67 #define SIM1_PCC1_SLOT (48)
68 68 #define MMDC0_AIPS3_SLOT (43)
69 69 #define IOMUXC_DDR_AIPS3_SLOT (45)
  70 +#define DSI_AIPS3_SLOT (41)
  71 +#define LCDIF_AIPS3_SLOT (42)
70 72  
71 73 #define LPI2C0_AIPS0_SLOT (51)
72 74 #define LPI2C1_AIPS0_SLOT (52)
... ... @@ -183,6 +185,10 @@
183 185 #define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT)))
184 186 #define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT)))
185 187  
  188 +#define LCDIF_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LCDIF_AIPS3_SLOT)))
  189 +#define MXS_LCDIF_BASE LCDIF_RBASE
  190 +
  191 +
186 192 #define SNVS_BASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT)))
187 193 #define SNVS_LP_LPCR (SNVS_BASE + 0x38)
188 194  
... ... @@ -966,6 +972,7 @@
966 972 #define IOMUXC_BASE_ADDR IOMUXC1_RBASE
967 973  
968 974 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  975 +#include <asm/mach-imx/regs-lcdif.h>
969 976  
970 977 #include <asm/types.h>
971 978  
arch/arm/mach-imx/mx7ulp/clock.c
Diff comments   View file @ c6d4870
... ... @@ -326,6 +326,88 @@
326 326 }
327 327 #endif
328 328  
  329 +void enable_mipi_dsi_clk(unsigned char enable)
  330 +{
  331 + if (enable) {
  332 + pcc_clock_enable(PER_CLK_DSI, false);
  333 +
  334 + /* mipi dsi escape clock range is 40-80Mhz, we expect to set it to about 60 Mhz
  335 + * To avoid PCD issue, we select parent clock with lowest frequency
  336 + * NIC1_CLK = 1584000khz, frac = 1, div = 5, output = 63.360Mhz
  337 + */
  338 + pcc_clock_sel(PER_CLK_DSI, SCG_NIC1_CLK);
  339 + pcc_clock_div_config(PER_CLK_DSI, 1, 5);
  340 +
  341 + pcc_clock_enable(PER_CLK_DSI, true);
  342 + } else {
  343 + pcc_clock_enable(PER_CLK_DSI, false);
  344 + }
  345 +}
  346 +
  347 +void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq_in_khz)
  348 +{
  349 + /* Scan the parent clock to find best fit clock, whose generate actual frequence <= freq
  350 + * Otherwise, the higher actual freq may introduce some problem
  351 + * 1. The real frequency exceeds max framerate that screen supports
  352 + * 2. The DSI PHY clock depends on the lcdif clock, so the higher lcdif clock may violate
  353 + * DSI PHY clock requirement
  354 + */
  355 + u8 pcd, best_pcd = 0;
  356 + u32 parent, frac, rate, parent_rate;
  357 + u32 best_parent = 0, best_frac = 0, best = 0;
  358 +
  359 + static enum scg_clk clksrc_plat[] = {
  360 + SCG_NIC1_BUS_CLK,
  361 + SCG_NIC1_CLK,
  362 + SCG_DDR_CLK,
  363 + SCG_APLL_PFD2_CLK,
  364 + SCG_APLL_PFD1_CLK,
  365 + SCG_APLL_PFD0_CLK,
  366 + USB_PLL_OUT,
  367 + };
  368 +
  369 + pcc_clock_enable(PER_CLK_LCDIF, false);
  370 +
  371 + for (parent = 0; parent < ARRAY_SIZE(clksrc_plat); parent++) {
  372 + parent_rate = scg_clk_get_rate(clksrc_plat[parent]);
  373 + if (!parent_rate)
  374 + continue;
  375 +
  376 + parent_rate = parent_rate / 1000; /* Change to khz*/
  377 +
  378 + for (pcd = 0; pcd < 8; pcd++) {
  379 + for (frac = 0; frac < 2; frac++) {
  380 + if (pcd == 0 && frac == 1)
  381 + continue;
  382 +
  383 + rate = parent_rate * (frac + 1) / (pcd + 1);
  384 + if (rate > freq_in_khz)
  385 + continue;
  386 +
  387 + if (best == 0 || rate > best) {
  388 + best = rate;
  389 + best_parent = parent;
  390 + best_frac = frac;
  391 + best_pcd = pcd;
  392 + }
  393 + }
  394 + }
  395 + }
  396 +
  397 + if (best == 0) {
  398 + printf("Can't find parent clock for LCDIF, target freq: %u\n", freq_in_khz);
  399 + return;
  400 + }
  401 +
  402 + debug("LCD target rate %ukhz, best rate %ukhz, frac %u, pcd %u, best_parent %u\n",
  403 + freq_in_khz, best, best_frac, best_pcd, best_parent);
  404 +
  405 + pcc_clock_sel(PER_CLK_LCDIF, clksrc_plat[best_parent]);
  406 + pcc_clock_div_config(PER_CLK_LCDIF, best_frac, best_pcd + 1);
  407 + pcc_clock_enable(PER_CLK_LCDIF, true);
  408 +}
  409 +
  410 +
329 411 #ifndef CONFIG_SPL_BUILD
330 412 /*
331 413 * Dump some core clockes.
configs/mx7ulp_evk_defconfig
Diff comments   View file @ c6d4870
... ... @@ -81,4 +81,13 @@
81 81 CONFIG_FASTBOOT_BUF_SIZE=0x20000000
82 82 CONFIG_FASTBOOT_FLASH=y
83 83 CONFIG_EFI_PARTITION=y
  84 +
  85 +CONFIG_REGMAP=y
  86 +CONFIG_SYSCON=y
  87 +CONFIG_VIDEO_IMX_NW_DSI=y
  88 +CONFIG_DM_VIDEO=y
  89 +CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
  90 +CONFIG_BACKLIGHT_GPIO=y
  91 +CONFIG_SYS_WHITE_ON_BLACK=y
  92 +CONFIG_CMD_DM=y
configs/mx7ulp_evk_emmc_defconfig
Diff comments   View file @ c6d4870
... ... @@ -80,4 +80,13 @@
80 80 CONFIG_FASTBOOT_BUF_SIZE=0x20000000
81 81 CONFIG_FASTBOOT_FLASH=y
82 82 CONFIG_EFI_PARTITION=y
  83 +
  84 +CONFIG_REGMAP=y
  85 +CONFIG_SYSCON=y
  86 +CONFIG_VIDEO_IMX_NW_DSI=y
  87 +CONFIG_DM_VIDEO=y
  88 +CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
  89 +CONFIG_BACKLIGHT_GPIO=y
  90 +CONFIG_SYS_WHITE_ON_BLACK=y
  91 +CONFIG_CMD_DM=y
configs/mx7ulp_evk_m4boot_defconfig
Diff comments   View file @ c6d4870
... ... @@ -80,4 +80,13 @@
80 80 CONFIG_FASTBOOT_BUF_SIZE=0x20000000
81 81 CONFIG_FASTBOOT_FLASH=y
82 82 CONFIG_EFI_PARTITION=y
  83 +
  84 +CONFIG_REGMAP=y
  85 +CONFIG_SYSCON=y
  86 +CONFIG_VIDEO_IMX_NW_DSI=y
  87 +CONFIG_DM_VIDEO=y
  88 +CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
  89 +CONFIG_BACKLIGHT_GPIO=y
  90 +CONFIG_SYS_WHITE_ON_BLACK=y
  91 +CONFIG_CMD_DM=y
configs/mx7ulp_evk_optee_defconfig
Diff comments   View file @ c6d4870
... ... @@ -82,4 +82,13 @@
82 82 CONFIG_FASTBOOT_BUF_SIZE=0x20000000
83 83 CONFIG_FASTBOOT_FLASH=y
84 84 CONFIG_EFI_PARTITION=y
  85 +
  86 +CONFIG_REGMAP=y
  87 +CONFIG_SYSCON=y
  88 +CONFIG_VIDEO_IMX_NW_DSI=y
  89 +CONFIG_DM_VIDEO=y
  90 +CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
  91 +CONFIG_BACKLIGHT_GPIO=y
  92 +CONFIG_SYS_WHITE_ON_BLACK=y
  93 +CONFIG_CMD_DM=y
configs/mx7ulp_evk_plugin_defconfig
Diff comments   View file @ c6d4870
... ... @@ -80,4 +80,13 @@
80 80 CONFIG_FASTBOOT_BUF_SIZE=0x20000000
81 81 CONFIG_FASTBOOT_FLASH=y
82 82 CONFIG_EFI_PARTITION=y
  83 +
  84 +CONFIG_REGMAP=y
  85 +CONFIG_SYSCON=y
  86 +CONFIG_VIDEO_IMX_NW_DSI=y
  87 +CONFIG_DM_VIDEO=y
  88 +CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
  89 +CONFIG_BACKLIGHT_GPIO=y
  90 +CONFIG_SYS_WHITE_ON_BLACK=y
  91 +CONFIG_CMD_DM=y
include/configs/mx7ulp_evk.h
Diff comments   View file @ c6d4870
... ... @@ -74,6 +74,7 @@
74 74 "script=boot.scr\0" \
75 75 "image=zImage\0" \
76 76 "console=ttyLP0\0" \
  77 + "splashimage=0x78000000\0" \
77 78 "fdt_high=0xffffffff\0" \
78 79 "initrd_high=0xffffffff\0" \
79 80 "fdt_file=" CONFIG_DEFAULT_FDT_FILE ".dtb\0" \
... ... @@ -191,5 +192,19 @@
191 192 #else
192 193 #define TEE_ENV "tee=no\0"
193 194 #endif
  195 +
  196 +#ifdef CONFIG_DM_VIDEO
  197 +#define CONFIG_VIDEO_MXS
  198 +#define CONFIG_VIDEO_LOGO
  199 +#define CONFIG_SPLASH_SCREEN
  200 +#define CONFIG_SPLASH_SCREEN_ALIGN
  201 +#define CONFIG_CMD_BMP
  202 +#define CONFIG_BMP_16BPP
  203 +#define CONFIG_BMP_24BPP
  204 +#define CONFIG_BMP_32BPP
  205 +#define CONFIG_VIDEO_BMP_RLE8
  206 +#define CONFIG_VIDEO_BMP_LOGO
  207 +#endif
  208 +
194 209 #endif /* __CONFIG_H */