Eric Lee / smarc-uboot

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Commit c7219c08b71bf19056c3e02b83ee9a831e084f5e

Authored by Ye Li
1 parent 1b60a63576
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-18591-12 android: iot: Add board support imx6ul nxpu board 

Porting the board support for imx6ul nxpu iopb board from v2017.03

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 11 changed files with 1318 additions and 0 deletions Side-by-side Diff

arch/arm/mach-imx/mx6/Kconfig
Diff comments   View file @ c7219c0
... ... @@ -428,6 +428,13 @@
428 428 select DM
429 429 select DM_THERMAL
430 430  
  431 +config TARGET_MX6UL_NXPU_IOPB
  432 + bool "Support mx6ul_nxpu_iopb"
  433 + select BOARD_LATE_INIT
  434 + select MX6UL
  435 + select DM
  436 + select DM_THERMAL
  437 +
431 438 config TARGET_MX6UL_ENGICAM
432 439 bool "Support Engicam GEAM6UL/Is.IoT"
433 440 select BOARD_LATE_INIT
... ... @@ -628,6 +635,7 @@
628 635 source "board/freescale/mx6sxsabreauto/Kconfig"
629 636 source "board/freescale/mx6sx_17x17_arm2/Kconfig"
630 637 source "board/freescale/mx6sx_19x19_arm2/Kconfig"
  638 +source "board/freescale/mx6ul_nxpu_iopb/Kconfig"
631 639 source "board/freescale/mx6ul_14x14_evk/Kconfig"
632 640 source "board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig"
633 641 source "board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig"
board/freescale/mx6ul_nxpu_iopb/Kconfig
Diff comments   View file @ c7219c0
  1 +if TARGET_MX6UL_NXPU_IOPB
  2 +
  3 +config SYS_BOARD
  4 + default "mx6ul_nxpu_iopb"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_SOC
  10 + default "mx6"
  11 +
  12 +config SYS_CONFIG_NAME
  13 + default "mx6ul_nxpu_iopb"
  14 +
  15 +endif
board/freescale/mx6ul_nxpu_iopb/MAINTAINERS
Diff comments   View file @ c7219c0
  1 +MX6ULIOPB BOARD
  2 +M: Fang Hui <hui.fang@nxp.com>
  3 +S: Maintained
  4 +F: board/freescale/mx6ul_nxpu_iopb/
  5 +F: include/configs/mx6ul_nxpu_iopb.h
  6 +F: configs/mx6ul_nxpu_iopb_defconfig
board/freescale/mx6ul_nxpu_iopb/Makefile
Diff comments   View file @ c7219c0
  1 +# (C) Copyright 2016 Freescale Semiconductor, Inc.
  2 +#
  3 +# SPDX-License-Identifier: GPL-2.0+
  4 +#
  5 +
  6 +obj-y := mx6ul_nxpu_iopb.o
board/freescale/mx6ul_nxpu_iopb/imximage.cfg
Diff comments   View file @ c7219c0
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + * Copyright 2018 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + *
  7 + * Refer docs/README.imxmage for more details about how-to configure
  8 + * and create imximage boot image
  9 + *
  10 + * The syntax is taken as close as possible with the kwbimage
  11 + */
  12 +
  13 +#define __ASSEMBLY__
  14 +#include <config.h>
  15 +
  16 +/* image version */
  17 +
  18 +IMAGE_VERSION 2
  19 +
  20 +/*
  21 + * Boot Device : one of
  22 + * spi/sd/nand/onenand, qspi/nor
  23 + */
  24 +
  25 +#ifdef CONFIG_QSPI_BOOT
  26 +BOOT_FROM qspi
  27 +#elif defined(CONFIG_NOR_BOOT)
  28 +BOOT_FROM nor
  29 +#else
  30 +BOOT_FROM sd
  31 +#endif
  32 +
  33 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  34 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  35 +PLUGIN board/freescale/mx6ul_nxpu_iopb/plugin.bin 0x00907000
  36 +#else
  37 +
  38 +#ifdef CONFIG_SECURE_BOOT
  39 +CSF CONFIG_CSF_SIZE
  40 +#endif
  41 +
  42 +/*
  43 + * Device Configuration Data (DCD)
  44 + *
  45 + * Each entry must have the format:
  46 + * Addr-type Address Value
  47 + *
  48 + * where:
  49 + * Addr-type register length (1,2 or 4 bytes)
  50 + * Address absolute address of the register
  51 + * value value to be stored in the register
  52 + */
  53 +
  54 +#ifdef CONFIG_DDR3L_MT41K256M16HA
  55 +
  56 +/* DDR type MT41K256M16HA-125 which is EOL */
  57 +
  58 +/* Enable all clocks */
  59 +DATA 4 0x020c4068 0xffffffff
  60 +DATA 4 0x020c406c 0xffffffff
  61 +DATA 4 0x020c4070 0xffffffff
  62 +DATA 4 0x020c4074 0xffffffff
  63 +DATA 4 0x020c4078 0xffffffff
  64 +DATA 4 0x020c407c 0xffffffff
  65 +DATA 4 0x020c4080 0xffffffff
  66 +
  67 +DATA 4 0x020E04B4 0x000C0000
  68 +DATA 4 0x020E04AC 0x00000000
  69 +DATA 4 0x020E027C 0x00000030
  70 +DATA 4 0x020E0250 0x00000030
  71 +DATA 4 0x020E024C 0x00000030
  72 +DATA 4 0x020E0490 0x00000030
  73 +DATA 4 0x020E0288 0x00000030
  74 +DATA 4 0x020E0270 0x00000000
  75 +DATA 4 0x020E0260 0x00000030
  76 +DATA 4 0x020E0264 0x00000030
  77 +DATA 4 0x020E04A0 0x00000030
  78 +DATA 4 0x020E0494 0x00020000
  79 +DATA 4 0x020E0280 0x00000030
  80 +DATA 4 0x020E0284 0x00000030
  81 +DATA 4 0x020E04B0 0x00020000
  82 +DATA 4 0x020E0498 0x00000030
  83 +DATA 4 0x020E04A4 0x00000030
  84 +DATA 4 0x020E0244 0x00000030
  85 +DATA 4 0x020E0248 0x00000030
  86 +DATA 4 0x021B001C 0x00008000
  87 +DATA 4 0x021B0800 0xA1390003
  88 +DATA 4 0x021B080C 0x00000000
  89 +DATA 4 0x021B083C 0x41490145
  90 +DATA 4 0x021B0848 0x40404546
  91 +DATA 4 0x021B0850 0x4040524D
  92 +DATA 4 0x021B081C 0x33333333
  93 +DATA 4 0x021B0820 0x33333333
  94 +DATA 4 0x021B082C 0xf3333333
  95 +DATA 4 0x021B0830 0xf3333333
  96 +DATA 4 0x021B08C0 0x00921012
  97 +DATA 4 0x021B08b8 0x00000800
  98 +DATA 4 0x021B0004 0x0002002D
  99 +DATA 4 0x021B0008 0x00333030
  100 +DATA 4 0x021B000C 0x676B52F3
  101 +DATA 4 0x021B0010 0xB66D8B63
  102 +DATA 4 0x021B0014 0x01FF00DB
  103 +DATA 4 0x021B0018 0x00201740
  104 +DATA 4 0x021B001C 0x00008000
  105 +DATA 4 0x021B002C 0x000026D2
  106 +DATA 4 0x021B0030 0x006B1023
  107 +DATA 4 0x021B0040 0x0000004F
  108 +DATA 4 0x021B0000 0x84180000
  109 +DATA 4 0x021B001C 0x02008032
  110 +DATA 4 0x021B001C 0x00008033
  111 +DATA 4 0x021B001C 0x00048031
  112 +DATA 4 0x021B001C 0x15208030
  113 +DATA 4 0x021B001C 0x04008040
  114 +DATA 4 0x021B0020 0x00000800
  115 +DATA 4 0x021B0818 0x00000227
  116 +DATA 4 0x021B0004 0x0002552D
  117 +DATA 4 0x021B0404 0x00011006
  118 +DATA 4 0x021B001C 0x00000000
  119 +
  120 +#else
  121 +
  122 +/* New DDR type MT41K256M16TW-107 */
  123 +
  124 +/* Enable all clocks */
  125 +DATA 4 0x020c4068 0xffffffff
  126 +DATA 4 0x020c406c 0xffffffff
  127 +DATA 4 0x020c4070 0xffffffff
  128 +DATA 4 0x020c4074 0xffffffff
  129 +DATA 4 0x020c4078 0xffffffff
  130 +DATA 4 0x020c407c 0xffffffff
  131 +DATA 4 0x020c4080 0xffffffff
  132 +
  133 +DATA 4 0x020E04B4 0x000C0000
  134 +DATA 4 0x020E04AC 0x00000000
  135 +DATA 4 0x020E027C 0x00000030
  136 +DATA 4 0x020E0250 0x00000030
  137 +DATA 4 0x020E024C 0x00000030
  138 +DATA 4 0x020E0490 0x00000030
  139 +DATA 4 0x020E0288 0x00000030
  140 +DATA 4 0x020E0270 0x00000000
  141 +DATA 4 0x020E0260 0x00000030
  142 +DATA 4 0x020E0264 0x00000030
  143 +DATA 4 0x020E04A0 0x00000030
  144 +DATA 4 0x020E0494 0x00020000
  145 +DATA 4 0x020E0280 0x00000030
  146 +DATA 4 0x020E0284 0x00000030
  147 +DATA 4 0x020E04B0 0x00020000
  148 +DATA 4 0x020E0498 0x00000030
  149 +DATA 4 0x020E04A4 0x00000030
  150 +DATA 4 0x020E0244 0x00000030
  151 +DATA 4 0x020E0248 0x00000030
  152 +DATA 4 0x021B001C 0x00008000
  153 +DATA 4 0x021B0800 0xA1390003
  154 +DATA 4 0x021B080C 0x00000000
  155 +DATA 4 0x021B083C 0x41570155
  156 +DATA 4 0x021B0848 0x4040474A
  157 +DATA 4 0x021B0850 0x40405550
  158 +DATA 4 0x021B081C 0x33333333
  159 +DATA 4 0x021B0820 0x33333333
  160 +DATA 4 0x021B082C 0xf3333333
  161 +DATA 4 0x021B0830 0xf3333333
  162 +DATA 4 0x021B08C0 0x00921012
  163 +DATA 4 0x021B08b8 0x00000800
  164 +DATA 4 0x021B0004 0x0002002D
  165 +DATA 4 0x021B0008 0x1B333030
  166 +DATA 4 0x021B000C 0x676B52F3
  167 +DATA 4 0x021B0010 0xB66D0B63
  168 +DATA 4 0x021B0014 0x01FF00DB
  169 +DATA 4 0x021B0018 0x00201740
  170 +DATA 4 0x021B001C 0x00008000
  171 +DATA 4 0x021B002C 0x000026D2
  172 +DATA 4 0x021B0030 0x006B1023
  173 +DATA 4 0x021B0040 0x0000004F
  174 +DATA 4 0x021B0000 0x84180000
  175 +DATA 4 0x021B0890 0x23400A38
  176 +DATA 4 0x021B001C 0x02008032
  177 +DATA 4 0x021B001C 0x00008033
  178 +DATA 4 0x021B001C 0x00048031
  179 +DATA 4 0x021B001C 0x15208030
  180 +DATA 4 0x021B001C 0x04008040
  181 +DATA 4 0x021B0020 0x00000800
  182 +DATA 4 0x021B0818 0x00000227
  183 +DATA 4 0x021B0004 0x0002552D
  184 +DATA 4 0x021B0404 0x00011006
  185 +DATA 4 0x021B001C 0x00000000
  186 +#endif
  187 +
  188 +#endif
board/freescale/mx6ul_nxpu_iopb/mx6ul_nxpu_iopb.c
Diff comments   View file @ c7219c0
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <asm/arch/clock.h>
  8 +#include <asm/arch/iomux.h>
  9 +#include <asm/arch/imx-regs.h>
  10 +#include <asm/arch/crm_regs.h>
  11 +#include <asm/arch/mx6-pins.h>
  12 +#include <asm/arch/sys_proto.h>
  13 +#include <asm/gpio.h>
  14 +#include <asm/mach-imx/iomux-v3.h>
  15 +#include <asm/mach-imx/boot_mode.h>
  16 +#include <asm/mach-imx/mxc_i2c.h>
  17 +#include <asm/io.h>
  18 +#include <common.h>
  19 +#include <fsl_esdhc.h>
  20 +#include <i2c.h>
  21 +#include <linux/sizes.h>
  22 +#include <linux/fb.h>
  23 +#include <miiphy.h>
  24 +#include <mmc.h>
  25 +#include <mxsfb.h>
  26 +#include <netdev.h>
  27 +#include <usb.h>
  28 +#include <usb/ehci-ci.h>
  29 +
  30 +#ifdef CONFIG_POWER
  31 +#include <power/pmic.h>
  32 +#include <power/pfuze3000_pmic.h>
  33 +#include "../common/pfuze.h"
  34 +#endif
  35 +
  36 +#ifdef CONFIG_FSL_FASTBOOT
  37 +#include <fsl_fastboot.h>
  38 +#ifdef CONFIG_ANDROID_RECOVERY
  39 +#include <recovery.h>
  40 +#endif
  41 +#endif /*CONFIG_FSL_FASTBOOT*/
  42 +
  43 +
  44 +DECLARE_GLOBAL_DATA_PTR;
  45 +
  46 +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  47 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  48 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  49 +
  50 +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  51 + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  52 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  53 +
  54 +#define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  55 + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
  56 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  57 +
  58 +
  59 +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  60 + PAD_CTL_SPEED_HIGH | \
  61 + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  62 +
  63 +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  64 + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  65 +
  66 +
  67 +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  68 +
  69 +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  70 + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  71 +
  72 +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  73 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  74 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  75 + PAD_CTL_ODE)
  76 +
  77 +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  78 + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  79 +
  80 +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  81 +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  82 + PAD_CTL_SRE_FAST)
  83 +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  84 +
  85 +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  86 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  87 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  88 +
  89 +#define SPI_PAD_CTRL (PAD_CTL_HYS | \
  90 + PAD_CTL_SPEED_MED | \
  91 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  92 +
  93 +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  94 + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  95 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  96 +
  97 +#ifdef CONFIG_SYS_I2C_MXC
  98 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  99 +/* I2C1 for PMIC and EEPROM */
  100 +struct i2c_pads_info i2c_pad_info1 = {
  101 + .scl = {
  102 + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
  103 + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
  104 + .gp = IMX_GPIO_NR(1, 2),
  105 + },
  106 + .sda = {
  107 + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
  108 + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
  109 + .gp = IMX_GPIO_NR(1, 3),
  110 + },
  111 +};
  112 +#endif
  113 +
  114 +int dram_init(void)
  115 +{
  116 +#ifdef CONFIG_IMX_TRUSTY_OS
  117 + gd->ram_size = PHYS_SDRAM_SIZE - TRUSTY_OS_RAM_SIZE;
  118 +#else
  119 + gd->ram_size = PHYS_SDRAM_SIZE;
  120 +#endif
  121 + return 0;
  122 +}
  123 +
  124 +static iomux_v3_cfg_t const uart3_pads[] = {
  125 + MX6_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  126 + MX6_PAD_UART3_RX_DATA__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  127 +};
  128 +
  129 +static iomux_v3_cfg_t const usdhc1_pads[] = {
  130 + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  131 + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  132 +
  133 + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  134 + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  135 + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  136 + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  137 +
  138 + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  139 + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  140 + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  141 + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  142 +
  143 + /* RST_B */
  144 + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  145 +};
  146 +
  147 +static iomux_v3_cfg_t const usdhc2_pads[] = {
  148 + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  149 + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  150 + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  151 + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  152 + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  153 + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  154 + /* CD */
  155 + MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
  156 +};
  157 +
  158 +#ifdef CONFIG_FEC_MXC
  159 +/*
  160 + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
  161 + * be used for ENET1 or ENET2, cannot be used for both.
  162 + */
  163 +static iomux_v3_cfg_t const fec1_pads[] = {
  164 + MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), /* MDIO */
  165 + MX6_PAD_ENET2_RX_DATA1__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), /* MDC */
  166 +
  167 + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  168 + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  169 + MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  170 + MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  171 + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  172 + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  173 +
  174 + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  175 + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  176 + MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  177 + MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  178 + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  179 + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  180 + MX6_PAD_UART1_CTS_B__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  181 +
  182 + MX6_PAD_LCD_HSYNC__GPIO3_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
  183 + MX6_PAD_UART2_CTS_B__ENET1_CRS | MUX_PAD_CTRL(NO_PAD_CTRL),
  184 + MX6_PAD_UART2_RTS_B__ENET1_COL | MUX_PAD_CTRL(NO_PAD_CTRL),
  185 +};
  186 +
  187 +static void setup_iomux_fec(int fec_id)
  188 +{
  189 + if (fec_id == 0)
  190 + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
  191 + else
  192 + printf("Warning: fec_id %d, should be 0\n", fec_id);
  193 +}
  194 +#endif
  195 +
  196 +static void setup_iomux_uart(void)
  197 +{
  198 + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  199 +}
  200 +
  201 +#ifdef CONFIG_FSL_ESDHC
  202 +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  203 + {USDHC1_BASE_ADDR, 0, 8},
  204 + {USDHC2_BASE_ADDR, 0, 4},
  205 +};
  206 +
  207 +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 17)
  208 +
  209 +int board_mmc_get_env_dev(int devno)
  210 +{
  211 + return devno;
  212 +}
  213 +
  214 +int mmc_map_to_kernel_blk(int dev_no)
  215 +{
  216 + if (dev_no == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR))
  217 + dev_no = 1;
  218 +
  219 + return dev_no;
  220 +}
  221 +
  222 +int board_mmc_getcd(struct mmc *mmc)
  223 +{
  224 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  225 + int ret = 0;
  226 +
  227 + switch (cfg->esdhc_base) {
  228 + case USDHC1_BASE_ADDR:
  229 + ret = 1;
  230 + break;
  231 + case USDHC2_BASE_ADDR:
  232 + ret = !gpio_get_value(USDHC2_CD_GPIO);
  233 + break;
  234 + }
  235 +
  236 + return ret;
  237 +}
  238 +
  239 +int board_mmc_init(bd_t *bis)
  240 +{
  241 + int i, ret;
  242 +
  243 + /*
  244 + * According to the board_mmc_init() the following map is done:
  245 + * (U-boot device node) (Physical Port)
  246 + * mmc0 USDHC1
  247 + * mmc1 USDHC2
  248 + */
  249 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  250 + switch (i) {
  251 + case 0:
  252 + imx_iomux_v3_setup_multiple_pads(
  253 + usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  254 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  255 + break;
  256 + case 1:
  257 + imx_iomux_v3_setup_multiple_pads(
  258 + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  259 + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
  260 + gpio_direction_input(USDHC2_CD_GPIO);
  261 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  262 + break;
  263 + default:
  264 + printf("Warning: you configured more USDHC controllers"
  265 + "(%d) than supported by the board\n", i + 1);
  266 + return -EINVAL;
  267 + }
  268 +
  269 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  270 + if (ret) {
  271 + printf("Warning: failed to initialize mmc dev %d\n", i);
  272 + }
  273 + }
  274 +
  275 + return 0;
  276 +}
  277 +
  278 +#endif
  279 +
  280 +#ifdef CONFIG_FEC_MXC
  281 +int board_eth_init(bd_t *bis)
  282 +{
  283 + int ret;
  284 +
  285 + setup_iomux_fec(CONFIG_FEC_ENET_DEV);
  286 +
  287 + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
  288 + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  289 + if (ret)
  290 + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
  291 +
  292 + return 0;
  293 +}
  294 +
  295 +static int setup_fec(int fec_id)
  296 +{
  297 + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  298 + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
  299 + int ret;
  300 +
  301 + if (0 == fec_id) {
  302 + if (check_module_fused(MX6_MODULE_ENET1))
  303 + return -1;
  304 +
  305 + /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[17](ENET1_TX_CLK),
  306 + set gpr1[13](ENET1_CLK_SEL) */
  307 + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  308 + IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK);
  309 + } else {
  310 + if (check_module_fused(MX6_MODULE_ENET2))
  311 + return -1;
  312 +
  313 + /* Use 50M anatop loopback REF_CLK2 for ENET2, clear gpr1[14], set gpr1[18]*/
  314 + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
  315 + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
  316 + }
  317 +
  318 + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
  319 + if (ret)
  320 + return ret;
  321 +
  322 + enable_enet_clk(1);
  323 +
  324 + return 0;
  325 +}
  326 +
  327 +int board_phy_config(struct phy_device *phydev)
  328 +{
  329 +
  330 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  331 +
  332 + if (phydev->drv->config)
  333 + phydev->drv->config(phydev);
  334 +
  335 + return 0;
  336 +}
  337 +#endif
  338 +
  339 +#ifdef CONFIG_USB_EHCI_MX6
  340 +#define USB_OTHERREGS_OFFSET 0x800
  341 +#define UCTRL_PWR_POL (1 << 9)
  342 +
  343 +iomux_v3_cfg_t const usb_otg1_pads[] = {
  344 + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  345 + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
  346 +};
  347 +
  348 +/*
  349 + * Leave it here, but default configuration only supports 1 port now,
  350 + * because we need sd1 and i2c1
  351 + */
  352 +iomux_v3_cfg_t const usb_otg2_pads[] = {
  353 + MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  354 +};
  355 +
  356 +/* At default the 3v3 enables the MIC2026 for VBUS power */
  357 +static void setup_usb(void)
  358 +{
  359 + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
  360 + ARRAY_SIZE(usb_otg1_pads));
  361 +
  362 + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
  363 + ARRAY_SIZE(usb_otg2_pads));
  364 +}
  365 +
  366 +int board_usb_phy_mode(int port)
  367 +{
  368 + if (port == 1)
  369 + return USB_INIT_HOST;
  370 + else
  371 + return usb_phy_mode(port);
  372 +}
  373 +
  374 +int board_ehci_hcd_init(int port)
  375 +{
  376 + u32 *usbnc_usb_ctrl;
  377 +
  378 + if (port > 1)
  379 + return -EINVAL;
  380 +
  381 + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
  382 + port * 4);
  383 +
  384 + /* Set Power polarity */
  385 + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
  386 +
  387 + return 0;
  388 +}
  389 +#endif
  390 +
  391 +int board_early_init_f(void)
  392 +{
  393 + setup_iomux_uart();
  394 +
  395 + return 0;
  396 +}
  397 +
  398 +#ifdef CONFIG_POWER
  399 +#define I2C_PMIC 0
  400 +static struct pmic *pfuze;
  401 +int power_init_board(void)
  402 +{
  403 + int ret;
  404 + unsigned int reg, rev_id;
  405 +
  406 + ret = power_pfuze3000_init(I2C_PMIC);
  407 + if (ret)
  408 + return ret;
  409 +
  410 + pfuze = pmic_get("PFUZE3000");
  411 + ret = pmic_probe(pfuze);
  412 + if (ret)
  413 + return ret;
  414 +
  415 + pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
  416 + pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
  417 + printf("PMIC: PFUZE300 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
  418 +
  419 + /* disable Low Power Mode during standby mode */
  420 + pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
  421 + reg |= 0x1;
  422 + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
  423 +
  424 + /* SW1B step ramp up time from 2us to 4us/25mV */
  425 + reg = 0x40;
  426 + pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg);
  427 +
  428 + /* SW1B mode to APS/PFM */
  429 + reg = 0xc;
  430 + pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg);
  431 +
  432 + /* SW1B standby voltage set to 0.975V */
  433 + reg = 0xb;
  434 + pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg);
  435 +
  436 + return 0;
  437 +}
  438 +
  439 +#ifdef CONFIG_LDO_BYPASS_CHECK
  440 +void ldo_mode_set(int ldo_bypass)
  441 +{
  442 + unsigned int value;
  443 + u32 vddarm;
  444 +
  445 + struct pmic *p = pfuze;
  446 +
  447 + if (!p) {
  448 + printf("No PMIC found!\n");
  449 + return;
  450 + }
  451 +
  452 + /* switch to ldo_bypass mode */
  453 + if (ldo_bypass) {
  454 + prep_anatop_bypass();
  455 + /* decrease VDDARM to 1.275V */
  456 + pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
  457 + value &= ~0x1f;
  458 + value |= PFUZE300_SW1AB_SETP(1275);
  459 + pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
  460 +
  461 + set_anatop_bypass(1);
  462 + vddarm = PFUZE300_SW1AB_SETP(1175);
  463 +
  464 + pmic_reg_read(pfuze, PFUZE300_SW1BVOLT, &value);
  465 + value &= ~0x1f;
  466 + value |= vddarm;
  467 + pmic_reg_write(pfuze, PFUZE300_SW1BVOLT, value);
  468 +
  469 + finish_anatop_bypass();
  470 +
  471 + printf("switch to ldo_bypass mode!\n");
  472 + }
  473 +}
  474 +#endif
  475 +#endif
  476 +
  477 +int board_init(void)
  478 +{
  479 + /* Address of boot parameters */
  480 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  481 +
  482 + gpio_request(IMX_GPIO_NR(3, 2), "reset_gpio");
  483 + gpio_direction_output(IMX_GPIO_NR(3, 2) , 0);
  484 + udelay(500);
  485 + gpio_direction_output(IMX_GPIO_NR(3, 2) , 1);
  486 +
  487 +#ifdef CONFIG_SYS_I2C_MXC
  488 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  489 +#endif
  490 +
  491 +#ifdef CONFIG_FEC_MXC
  492 + setup_fec(CONFIG_FEC_ENET_DEV);
  493 +#endif
  494 +
  495 +#ifdef CONFIG_USB_EHCI_MX6
  496 + setup_usb();
  497 +#endif
  498 +
  499 + return 0;
  500 +}
  501 +
  502 +#ifdef CONFIG_CMD_BMODE
  503 +static const struct boot_mode board_boot_modes[] = {
  504 + /* 4 bit bus width */
  505 + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
  506 + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  507 + {NULL, 0},
  508 +};
  509 +#endif
  510 +
  511 +int board_late_init(void)
  512 +{
  513 +#ifdef CONFIG_CMD_BMODE
  514 + add_board_boot_modes(board_boot_modes);
  515 +#endif
  516 +
  517 +#ifdef CONFIG_ENV_IS_IN_MMC
  518 + board_late_mmc_env_init();
  519 +#endif
  520 +
  521 + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
  522 +
  523 + return 0;
  524 +}
  525 +
  526 +u32 get_board_rev(void)
  527 +{
  528 + return get_cpu_rev();
  529 +}
  530 +
  531 +int checkboard(void)
  532 +{
  533 + puts("Board: MX6UL NXPU IOPB\n");
  534 +
  535 + return 0;
  536 +}
  537 +
  538 +#ifdef CONFIG_FSL_FASTBOOT
  539 +#ifdef CONFIG_ANDROID_RECOVERY
  540 +int is_recovery_key_pressing(void)
  541 +{
  542 + /* No key defined for this board */
  543 + return 0;
  544 +}
  545 +#endif /*CONFIG_ANDROID_RECOVERY*/
  546 +#endif /*CONFIG_FSL_FASTBOOT*/
board/freescale/mx6ul_nxpu_iopb/plugin.S
Diff comments   View file @ c7219c0
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <config.h>
  8 +
  9 +/* DDR script */
  10 +.macro imx6ul_ddr3_iopb_setting
  11 + ldr r0, =IOMUXC_BASE_ADDR
  12 + ldr r1, =0x000C0000
  13 + str r1, [r0, #0x4B4]
  14 + ldr r1, =0x00000000
  15 + str r1, [r0, #0x4AC]
  16 + ldr r1, =0x00000030
  17 + str r1, [r0, #0x27C]
  18 + ldr r1, =0x00000030
  19 + str r1, [r0, #0x250]
  20 + str r1, [r0, #0x24C]
  21 + str r1, [r0, #0x490]
  22 + str r1, [r0, #0x288]
  23 +
  24 + ldr r1, =0x00000000
  25 + str r1, [r0, #0x270]
  26 +
  27 + ldr r1, =0x00000030
  28 + str r1, [r0, #0x260]
  29 + str r1, [r0, #0x264]
  30 + str r1, [r0, #0x4A0]
  31 +
  32 + ldr r1, =0x00020000
  33 + str r1, [r0, #0x494]
  34 +
  35 + ldr r1, =0x00000030
  36 + str r1, [r0, #0x280]
  37 + ldr r1, =0x00000030
  38 + str r1, [r0, #0x284]
  39 +
  40 + ldr r1, =0x00020000
  41 + str r1, [r0, #0x4B0]
  42 +
  43 + ldr r1, =0x00000030
  44 + str r1, [r0, #0x498]
  45 + str r1, [r0, #0x4A4]
  46 + str r1, [r0, #0x244]
  47 + str r1, [r0, #0x248]
  48 +
  49 + ldr r0, =MMDC_P0_BASE_ADDR
  50 + ldr r1, =0x00008000
  51 + str r1, [r0, #0x1C]
  52 + ldr r1, =0xA1390003
  53 + str r1, [r0, #0x800]
  54 + ldr r1, =0x00000000
  55 + str r1, [r0, #0x80C]
  56 + ldr r1, =0x41570155
  57 + str r1, [r0, #0x83C]
  58 + ldr r1, =0x4040474A
  59 + str r1, [r0, #0x848]
  60 + ldr r1, =0x40405550
  61 + str r1, [r0, #0x850]
  62 + ldr r1, =0x33333333
  63 + str r1, [r0, #0x81C]
  64 + str r1, [r0, #0x820]
  65 + ldr r1, =0xF3333333
  66 + str r1, [r0, #0x82C]
  67 + str r1, [r0, #0x830]
  68 + ldr r1, =0x00921012
  69 + str r1, [r0, #0x8C0]
  70 + ldr r1, =0x00000800
  71 + str r1, [r0, #0x8B8]
  72 + ldr r1, =0x0002002D
  73 + str r1, [r0, #0x004]
  74 + ldr r1, =0x1B333030
  75 + str r1, [r0, #0x008]
  76 + ldr r1, =0x676B52F3
  77 + str r1, [r0, #0x00C]
  78 + ldr r1, =0xB66D0B63
  79 + str r1, [r0, #0x010]
  80 + ldr r1, =0x01FF00DB
  81 + str r1, [r0, #0x014]
  82 + ldr r1, =0x00201740
  83 + str r1, [r0, #0x018]
  84 + ldr r1, =0x00008000
  85 + str r1, [r0, #0x01C]
  86 + ldr r1, =0x000026D2
  87 + str r1, [r0, #0x02C]
  88 + ldr r1, =0x006B1023
  89 + str r1, [r0, #0x030]
  90 + ldr r1, =0x0000004F
  91 + str r1, [r0, #0x040]
  92 + ldr r1, =0x84180000
  93 + str r1, [r0, #0x000]
  94 + ldr r1, =0x23400A38
  95 + str r1, [r0, #0x890]
  96 + ldr r1, =0x02008032
  97 + str r1, [r0, #0x01C]
  98 + ldr r1, =0x00008033
  99 + str r1, [r0, #0x01C]
  100 + ldr r1, =0x00048031
  101 + str r1, [r0, #0x01C]
  102 + ldr r1, =0x15208030
  103 + str r1, [r0, #0x01C]
  104 + ldr r1, =0x04008040
  105 + str r1, [r0, #0x01C]
  106 + ldr r1, =0x00000800
  107 + str r1, [r0, #0x020]
  108 + ldr r1, =0x00000227
  109 + str r1, [r0, #0x818]
  110 + ldr r1, =0x0002552D
  111 + str r1, [r0, #0x004]
  112 + ldr r1, =0x00011006
  113 + str r1, [r0, #0x404]
  114 + ldr r1, =0x00000000
  115 + str r1, [r0, #0x01C]
  116 +.endm
  117 +
  118 +.macro imx6_clock_gating
  119 + ldr r0, =CCM_BASE_ADDR
  120 + ldr r1, =0xFFFFFFFF
  121 + str r1, [r0, #0x68]
  122 + str r1, [r0, #0x6C]
  123 + str r1, [r0, #0x70]
  124 + str r1, [r0, #0x74]
  125 + str r1, [r0, #0x78]
  126 + str r1, [r0, #0x7C]
  127 + str r1, [r0, #0x80]
  128 +.endm
  129 +
  130 +.macro imx6_qos_setting
  131 +.endm
  132 +
  133 +.macro imx6_ddr_setting
  134 + imx6ul_ddr3_iopb_setting
  135 +.endm
  136 +
  137 +/* include the common plugin code here */
  138 +#include <asm/arch/mx6_plugin.S>
configs/mx6ul_nxpu_iopb_defconfig
Diff comments   View file @ c7219c0
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_nxpu_iopb/imximage.cfg,ANDROID_THINGS_SUPPORT"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX6=y
  4 +CONFIG_SYS_TEXT_BASE=0x87800000
  5 +CONFIG_TARGET_MX6UL_NXPU_IOPB=y
  6 +CONFIG_ANDROID_BOOT_IMAGE=y
  7 +CONFIG_BOOTDELAY=-2
  8 +CONFIG_EFI_PARTITION=y
  9 +# CONFIG_CONSOLE_MUX is not set
  10 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  11 +CONFIG_ENV_IS_IN_MMC=y
  12 +CONFIG_BOARD_EARLY_INIT_F=y
  13 +CONFIG_HUSH_PARSER=y
  14 +CONFIG_CMD_BOOTZ=y
  15 +# CONFIG_CMD_IMLS is not set
  16 +CONFIG_CMD_MEMTEST=y
  17 +# CONFIG_CMD_FLASH is not set
  18 +CONFIG_CMD_MMC=y
  19 +CONFIG_CMD_USB=y
  20 +CONFIG_CMD_GPIO=y
  21 +CONFIG_CMD_DHCP=y
  22 +CONFIG_CMD_MII=y
  23 +CONFIG_CMD_PING=y
  24 +CONFIG_CMD_CACHE=y
  25 +CONFIG_CMD_EXT2=y
  26 +CONFIG_CMD_EXT4=y
  27 +CONFIG_CMD_EXT4_WRITE=y
  28 +CONFIG_CMD_FAT=y
  29 +CONFIG_CMD_FS_GENERIC=y
  30 +CONFIG_USB=y
  31 +CONFIG_USB_STORAGE=y
  32 +CONFIG_OF_LIBFDT=y
  33 +CONFIG_AVB_ATX=y
configs/mx6ul_nxpu_iopb_trusty_defconfig
Diff comments   View file @ c7219c0
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_nxpu_iopb/imximage.cfg,ANDROID_THINGS_SUPPORT,ARMV7_NONSEC"
  2 +CONFIG_ARM=y
  3 +CONFIG_ARCH_MX6=y
  4 +CONFIG_SYS_TEXT_BASE=0x87800000
  5 +CONFIG_IMX_TRUSTY_OS=y
  6 +CONFIG_AVB_ATX=y
  7 +CONFIG_TARGET_MX6UL_NXPU_IOPB=y
  8 +CONFIG_ANDROID_BOOT_IMAGE=y
  9 +CONFIG_BOOTDELAY=-2
  10 +CONFIG_EFI_PARTITION=y
  11 +# CONFIG_CONSOLE_MUX is not set
  12 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  13 +CONFIG_ENV_IS_IN_MMC=y
  14 +CONFIG_BOARD_EARLY_INIT_F=y
  15 +CONFIG_HUSH_PARSER=y
  16 +CONFIG_CMD_BOOTZ=y
  17 +# CONFIG_CMD_IMLS is not set
  18 +CONFIG_CMD_MEMTEST=y
  19 +# CONFIG_CMD_FLASH is not set
  20 +CONFIG_CMD_MMC=y
  21 +CONFIG_CMD_USB=y
  22 +CONFIG_CMD_GPIO=y
  23 +CONFIG_CMD_DHCP=y
  24 +CONFIG_CMD_MII=y
  25 +CONFIG_CMD_PING=y
  26 +CONFIG_CMD_CACHE=y
  27 +CONFIG_CMD_EXT2=y
  28 +CONFIG_CMD_EXT4=y
  29 +CONFIG_CMD_EXT4_WRITE=y
  30 +CONFIG_CMD_FAT=y
  31 +CONFIG_CMD_FS_GENERIC=y
  32 +CONFIG_USB=y
  33 +CONFIG_USB_STORAGE=y
  34 +CONFIG_OF_LIBFDT=y
include/configs/mx6ul_nxpu_iopb.h
Diff comments   View file @ c7219c0
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * Configuration settings for the Freescale i.MX6UL NXPU IOPB board.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +#ifndef __MX6UL_NXPU_IOPB_CONFIG_H
  9 +#define __MX6UL_NXPU_IOPB_CONFIG_H
  10 +
  11 +#include "mx6_common.h"
  12 +
  13 +#if !defined(CONFIG_MX6UL_9X9_LPDDR2)
  14 +/* DCDC used on 14x14 EVK, no PMIC */
  15 +#undef CONFIG_LDO_BYPASS_CHECK
  16 +#endif
  17 +
  18 +/* Size of malloc() pool */
  19 +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
  20 +
  21 +#define CONFIG_MXC_UART
  22 +#define CONFIG_MXC_UART_BASE UART3_BASE
  23 +
  24 +/* MMC Configs */
  25 +#define CONFIG_FSL_USDHC
  26 +#ifdef CONFIG_FSL_USDHC
  27 +#define CONFIG_FSL_ESDHC
  28 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
  29 +
  30 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  31 +
  32 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
  33 +#endif
  34 +
  35 +#ifdef CONFIG_CMD_NET
  36 +#define CONFIG_FEC_MXC
  37 +#define CONFIG_MII
  38 +#define CONFIG_FEC_ENET_DEV 0
  39 +#define IMX_FEC_BASE ENET_BASE_ADDR
  40 +#define CONFIG_FEC_MXC_PHYADDR 0x1
  41 +#define CONFIG_FEC_XCV_TYPE MII100
  42 +#define CONFIG_ETHPRIME "FEC"
  43 +#define CONFIG_PHYLIB
  44 +#endif
  45 +
  46 +/* allow to overwrite serial and ethaddr */
  47 +#define CONFIG_ENV_OVERWRITE
  48 +#define CONFIG_CONS_INDEX 1
  49 +
  50 +/* I2C configs */
  51 +#define CONFIG_CMD_I2C
  52 +#ifdef CONFIG_CMD_I2C
  53 +#define CONFIG_SYS_I2C
  54 +#define CONFIG_SYS_I2C_MXC
  55 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  56 +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  57 +#define CONFIG_SYS_I2C_SPEED 100000
  58 +#endif
  59 +
  60 +#define PHYS_SDRAM_SIZE SZ_512M
  61 +
  62 +/* PMIC */
  63 +#define CONFIG_POWER
  64 +#define CONFIG_POWER_I2C
  65 +#define CONFIG_POWER_PFUZE3000
  66 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
  67 +
  68 +
  69 +
  70 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  71 +
  72 +#define CONFIG_MFG_ENV_SETTINGS \
  73 + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  74 + "rdinit=/linuxrc " \
  75 + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  76 + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \
  77 + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  78 + "g_mass_storage.iSerialNumber=\"\" "\
  79 + "clk_ignore_unused "\
  80 + "\0" \
  81 + "initrd_addr=0x83800000\0" \
  82 + "initrd_high=0xffffffff\0" \
  83 + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  84 +
  85 +#if defined(CONFIG_NAND_BOOT)
  86 +#define CONFIG_EXTRA_ENV_SETTINGS \
  87 + CONFIG_MFG_ENV_SETTINGS \
  88 + "panel=TFT43AB\0" \
  89 + "fdt_addr=0x83000000\0" \
  90 + "fdt_high=0xffffffff\0" \
  91 + "console=ttymxc0\0" \
  92 + "bootargs=console=ttymxc0,115200 ubi.mtd=3 " \
  93 + "root=ubi0:rootfs rootfstype=ubifs " \
  94 + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),-(rootfs)\0"\
  95 + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
  96 + "nand read ${fdt_addr} 0x5000000 0x100000;"\
  97 + "bootz ${loadaddr} - ${fdt_addr}\0"
  98 +
  99 +#else
  100 +#define CONFIG_EXTRA_ENV_SETTINGS \
  101 + CONFIG_MFG_ENV_SETTINGS \
  102 + "panel=TFT43AB\0" \
  103 + "script=boot.scr\0" \
  104 + "image=zImage\0" \
  105 + "console=ttymxc2\0" \
  106 + "fdt_high=0xffffffff\0" \
  107 + "initrd_high=0xffffffff\0" \
  108 + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
  109 + "fdt_addr=0x83000000\0" \
  110 + "boot_fdt=try\0" \
  111 + "ip_dyn=yes\0" \
  112 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  113 + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  114 + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  115 + "mmcautodetect=yes\0" \
  116 + "mmcargs=setenv bootargs console=${console},${baudrate} " \
  117 + "root=${mmcroot}\0" \
  118 + "loadbootscript=" \
  119 + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  120 + "bootscript=echo Running bootscript from mmc ...; " \
  121 + "source\0" \
  122 + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  123 + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  124 + "mmcboot=echo Booting from mmc ...; " \
  125 + "run mmcargs; " \
  126 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  127 + "if run loadfdt; then " \
  128 + "bootz ${loadaddr} - ${fdt_addr}; " \
  129 + "else " \
  130 + "if test ${boot_fdt} = try; then " \
  131 + "bootz; " \
  132 + "else " \
  133 + "echo WARN: Cannot load the DT; " \
  134 + "fi; " \
  135 + "fi; " \
  136 + "else " \
  137 + "bootz; " \
  138 + "fi;\0" \
  139 + "netargs=setenv bootargs console=${console},${baudrate} " \
  140 + "root=/dev/nfs " \
  141 + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  142 + "netboot=echo Booting from net ...; " \
  143 + "run netargs; " \
  144 + "if test ${ip_dyn} = yes; then " \
  145 + "setenv get_cmd dhcp; " \
  146 + "else " \
  147 + "setenv get_cmd tftp; " \
  148 + "fi; " \
  149 + "${get_cmd} ${image}; " \
  150 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  151 + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  152 + "bootz ${loadaddr} - ${fdt_addr}; " \
  153 + "else " \
  154 + "if test ${boot_fdt} = try; then " \
  155 + "bootz; " \
  156 + "else " \
  157 + "echo WARN: Cannot load the DT; " \
  158 + "fi; " \
  159 + "fi; " \
  160 + "else " \
  161 + "bootz; " \
  162 + "fi;\0"
  163 +
  164 +#define CONFIG_BOOTCOMMAND \
  165 + "mmc dev ${mmcdev};" \
  166 + "mmc dev ${mmcdev}; if mmc rescan; then " \
  167 + "if run loadbootscript; then " \
  168 + "run bootscript; " \
  169 + "else " \
  170 + "if run loadimage; then " \
  171 + "run mmcboot; " \
  172 + "else run netboot; " \
  173 + "fi; " \
  174 + "fi; " \
  175 + "else run netboot; fi"
  176 +#endif
  177 +
  178 +#define CONFIG_SYS_MEMTEST_START 0x80000000
  179 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
  180 +
  181 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  182 +#define CONFIG_SYS_HZ 1000
  183 +
  184 +/* Physical Memory Map */
  185 +#define CONFIG_NR_DRAM_BANKS 1
  186 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
  187 +
  188 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
  189 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
  190 +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
  191 +
  192 +#define CONFIG_SYS_INIT_SP_OFFSET \
  193 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  194 +#define CONFIG_SYS_INIT_SP_ADDR \
  195 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  196 +
  197 +/* FLASH and environment organization */
  198 +
  199 +#define CONFIG_ENV_SIZE SZ_8K
  200 +
  201 +#ifdef CONFIG_CMD_NAND
  202 +#define CONFIG_CMD_NAND_TRIMFFS
  203 +
  204 +/* NAND stuff */
  205 +#define CONFIG_NAND_MXS
  206 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  207 +#define CONFIG_SYS_NAND_BASE 0x40000000
  208 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  209 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  210 +
  211 +/* DMA stuff, needed for GPMI/MXS NAND support */
  212 +#define CONFIG_APBH_DMA
  213 +#define CONFIG_APBH_DMA_BURST
  214 +#define CONFIG_APBH_DMA_BURST8
  215 +#endif
  216 +
  217 +#ifdef CONFIG_FSL_QSPI
  218 +#define CONFIG_QSPI_BASE QSPI1_BASE_ADDR
  219 +#define CONFIG_QSPI_MEMMAP_BASE QSPI1_ARB_BASE_ADDR
  220 +
  221 +#define CONFIG_CMD_SF
  222 +#define CONFIG_SPI_FLASH
  223 +#define CONFIG_SPI_FLASH_STMICRO
  224 +#define CONFIG_SPI_FLASH_BAR
  225 +#define CONFIG_SF_DEFAULT_BUS 0
  226 +#define CONFIG_SF_DEFAULT_CS 0
  227 +#define CONFIG_SF_DEFAULT_SPEED 40000000
  228 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  229 +#endif
  230 +
  231 +#if defined(CONFIG_ENV_IS_IN_MMC)
  232 +#define CONFIG_ENV_OFFSET (13 * SZ_64K)
  233 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  234 +#define CONFIG_ENV_OFFSET (768 * 1024)
  235 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
  236 +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
  237 +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  238 +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
  239 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  240 +#elif defined(CONFIG_ENV_IS_IN_NAND)
  241 +#undef CONFIG_ENV_SIZE
  242 +#define CONFIG_ENV_OFFSET (60 << 20)
  243 +#define CONFIG_ENV_SECT_SIZE (128 << 10)
  244 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  245 +#endif
  246 +
  247 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
  248 +#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 area */
  249 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  250 +
  251 +#ifdef CONFIG_VIDEO
  252 +#define CONFIG_VIDEO_MXS
  253 +#define CONFIG_VIDEO_LOGO
  254 +#define CONFIG_SPLASH_SCREEN
  255 +#define CONFIG_SPLASH_SCREEN_ALIGN
  256 +#define CONFIG_BMP_16BPP
  257 +#define CONFIG_VIDEO_BMP_RLE8
  258 +#define CONFIG_VIDEO_BMP_LOGO
  259 +#define CONFIG_IMX_VIDEO_SKIP
  260 +#endif
  261 +
  262 +/* USB Configs */
  263 +#ifdef CONFIG_CMD_USB
  264 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  265 +#define CONFIG_USB_HOST_ETHER
  266 +#define CONFIG_USB_ETHER_ASIX
  267 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  268 +#define CONFIG_MXC_USB_FLAGS 0
  269 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  270 +#endif
  271 +
  272 +#define CONFIG_MODULE_FUSE
  273 +#define CONFIG_OF_SYSTEM_SETUP
  274 +
  275 +#if defined(CONFIG_ANDROID_THINGS_SUPPORT)
  276 +#include "mx6ul_nxpu_iopb_android_things.h"
  277 +#endif
  278 +
  279 +
  280 +#define PRODUCT_NAME "imx6ul"
  281 +#define VARIANT_NAME "imx6ul_iopb"
  282 +
  283 +#endif
include/configs/mx6ul_nxpu_iopb_android_things.h
Diff comments   View file @ c7219c0
  1 +
  2 +/*
  3 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  4 + * Copyright 2017 NXP
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __MX6UL_NXPU_IOPB_ANDROID_THINGS_H
  10 +#define __MX6UL_NXPU_IOPB_ANDROID_THINGS_H
  11 +#include "mx_android_common.h"
  12 +#define TRUSTY_OS_ENTRY 0x9e000000
  13 +#define TRUSTY_OS_RAM_SIZE 0x2000000
  14 +#define TRUSTY_OS_MMC_BLKS 0xFFF
  15 +#define TEE_HWPARTITION_ID 2
  16 +
  17 +#define AVB_RPMB
  18 +#ifdef AVB_RPMB
  19 +#define KEYSLOT_BLKS 0xFFF
  20 +#define KEYSLOT_HWPARTITION_ID 2
  21 +#endif
  22 +
  23 +#ifdef CONFIG_AVB_ATX
  24 +#define PERMANENT_ATTRIBUTE_HASH_OFFSET 32
  25 +#endif
  26 +
  27 +#ifdef CONFIG_IMX_TRUSTY_OS
  28 +#define NON_SECURE_FASTBOOT
  29 +#define TRUSTY_KEYSLOT_PACKAGE
  30 +#endif
  31 +
  32 +/* For NAND we don't support lock/unlock */
  33 +#ifndef CONFIG_NAND_BOOT
  34 +#define CONFIG_FASTBOOT_LOCK
  35 +#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT
  36 +#define FSL_FASTBOOT_FB_DEV "mmc"
  37 +#endif
  38 +
  39 +#define CONFIG_ANDROID_AB_SUPPORT
  40 +#define CONFIG_SYSTEM_RAMDISK_SUPPORT
  41 +#define CONFIG_FSL_CAAM_KB
  42 +#define CONFIG_CMD_FSL_CAAM_KB
  43 +#define CONFIG_SHA1
  44 +#define CONFIG_SHA256
  45 +
  46 +#define CONFIG_AVB_SUPPORT
  47 +#ifdef CONFIG_AVB_SUPPORT
  48 +#ifdef CONFIG_SYS_MALLOC_LEN
  49 +#undef CONFIG_SYS_MALLOC_LEN
  50 +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
  51 +#endif
  52 +#define CONFIG_SUPPORT_EMMC_RPMB
  53 +/* fuse bank size in word */
  54 +#define CONFIG_AVB_FUSE_BANK_SIZEW 8
  55 +#define CONFIG_AVB_FUSE_BANK_START 10
  56 +#define CONFIG_AVB_FUSE_BANK_END 15
  57 +#endif
  58 +
  59 +#endif
  60 +/* __MX6UL_NXPU_IOPB_ANDROID_THINGS_H */