MLK-23964-17 imx8mm_evk: Enable video splash screen on DDR4 and LPDDR4 EVK

Update board codes and DTS files to add display relevant nodes and configurations. Support two video links with MIPI DSI: 1. MIPI DSI to HDMI convertor, this is default 2. RM67191 panel Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 05498bdd53c77c5d6ead68da82cd34afde0ba17a)

MLK-23964-17 imx8mm_evk: Enable video splash screen on DDR4 and LPDDR4 EVK
Update board codes and DTS files to add display relevant nodes and configurations. Support two video links with MIPI DSI: 1. MIPI DSI to HDMI convertor, this is default 2. RM67191 panel Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 05498bdd53c77c5d6ead68da82cd34afde0ba17a)
Ye Li · Eric Lee
1 parent b7fe5ca10c
Showing 9 changed files with 155 additions and 1 deletions Side-by-side Diff
arch/arm/dts/imx8mm-evk-u-boot.dtsi
arch/arm/dts/imx8mm-evk.dts
arch/arm/dts/imx8mm.dtsi
board/freescale/imx8mm_evk/imx8mm_evk.c
configs/imx8mm_ddr4_evk_defconfig
configs/imx8mm_ddr4_evk_nand_defconfig
configs/imx8mm_evk_defconfig
configs/imx8mm_evk_fspi_defconfig
include/configs/imx8mm_evk.h
@@ -169,4 +169,17 @@
 	assigned-clocks = <&clk IMX8MM_CLK_QSPI>;
 	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
 };
+
+&lcdif {
+	enable_polarity_low;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
+
+&mipi_dsi {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
@@ -71,6 +71,32 @@
 			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
 		};
 	};
+
+	dsi_host: dsi-host {
+		compatible = "samsung,sec-mipi-dsi";
+		status = "okay";
+	};
+
+	rm67191_panel {
+		compatible = "raydium,rm67191";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_mipi_dsi_en>;
+		reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
+		dsi-lanes = <4>;
+		video-mode = <2>;	/* 0: burst mode
+					 * 1: non-burst mode with sync event
+					 * 2: non-burst mode with sync pulse
+					 */
+		panel-width-mm = <68>;
+		panel-height-mm = <121>;
+		status = "okay";
+
+		port {
+			rm67191_from_dsim: endpoint {
+				remote-endpoint = <&dsim_to_rm67191>;
+			};
+		};
+	};
 };
  
 &A53_0 {
@@ -237,6 +263,20 @@
 	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
 	status = "okay";
  
+	adv_bridge: adv7535@3d {
+		compatible = "adi,adv7533";
+		reg = <0x3d>;
+		adi,addr-cec = <0x3c>;
+		adi,dsi-lanes = <4>;
+		status = "okay";
+
+		port {
+			adv7535_from_dsim: endpoint {
+				remote-endpoint = <&dsim_to_adv7535>;
+			};
+		};
+	};
+
 	ptn5110: tcpc@50 {
 		compatible = "nxp,ptn5110";
 		pinctrl-names = "default";
@@ -354,6 +394,32 @@
 	status = "okay";
 };
  
+&lcdif {
+	display = <&display0>;
+	status = "okay";
+
+	display0: display@0 {
+		bits-per-pixel = <24>;
+		bus-width = <24>;
+	};
+};
+
+&mipi_dsi {
+	status = "okay";
+
+	port@1 {
+		dsim_to_adv7535: endpoint {
+			remote-endpoint = <&adv7535_from_dsim>;
+		};
+	};
+
+	port@2 {
+		dsim_to_rm67191: endpoint {
+			remote-endpoint = <&rm67191_from_dsim>;
+		};
+	};
+};
+
 &iomuxc {
 	pinctrl-names = "default";
  
@@ -569,6 +635,12 @@
 	pinctrl_wdog: wdoggrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
+		>;
+	};
+
+	pinctrl_mipi_dsi_en: mipi_dsi_en {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x19
 		>;
 	};
 };
@@ -40,6 +40,7 @@
 		spi0 = &flexspi;
 		usb0 = &usbotg1;
 		usb1 = &usbotg2;
+		video0 = &lcdif;
 	};
  
 	cpus {
@@ -1030,7 +1031,7 @@
 				assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
 							 <&clk IMX8MM_SYS_PLL2_1000M>,
 							 <&clk IMX8MM_SYS_PLL1_800M>;
-				assigned-clock-rate = <594000000>, <500000000>, <200000000>;
+				assigned-clock-rates = <594000000>, <500000000>, <200000000>;
 				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 				lcdif-gpr = <&dispmix_gpr>;
 				resets = <&lcdif_resets>;
@@ -1278,6 +1279,11 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		#reset-cells = <0>;
+
+		lcdif-soft-resetn {
+			compatible = "lcdif,soft-resetn";
+			resets = <&dispmix_sft_rstn IMX8MM_BUS_RSTN_BLK_SYNC>;
+		};
  
 		lcdif-clk-enable {
 			compatible = "lcdif,clk-enable";
@@ -287,6 +287,11 @@
  
 #endif
  
+#define FSL_SIP_GPC			0xC2000000
+#define FSL_SIP_CONFIG_GPC_PM_DOMAIN	0x3
+#define DISPMIX				9
+#define MIPI				10
+
 int board_init(void)
 {
 #ifdef CONFIG_USB_TCPC
@@ -295,6 +300,9 @@
  
 	if (IS_ENABLED(CONFIG_FEC_MXC))
 		setup_fec();
+
+	call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0);
+	call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0);
  
 	return 0;
 }
@@ -124,4 +124,14 @@
 CONFIG_NAND_MXS_DT=y
  
 CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
@@ -127,4 +127,14 @@
 CONFIG_NAND_MXS_DT=y
  
 CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
@@ -129,4 +129,14 @@
 CONFIG_SDP_LOADADDR=0x40400000
  
 CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
@@ -130,4 +130,14 @@
 CONFIG_SDP_LOADADDR=0x40400000
  
 CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
@@ -97,6 +97,7 @@
 #if defined(CONFIG_NAND_BOOT)
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	CONFIG_MFG_ENV_SETTINGS \
+	"splashimage=0x50000000\0" \
 	"fdt_addr=0x43000000\0"			\
 	"fdt_high=0xffffffffffffffff\0" \
 	"mtdparts=" MFG_NAND_PARTITION "\0" \
@@ -115,6 +116,7 @@
 	JAILHOUSE_ENV \
 	"script=boot.scr\0" \
 	"image=Image\0" \
+	"splashimage=0x50000000\0" \
 	"console=ttymxc1,115200\0" \
 	"fdt_addr=0x43000000\0"			\
 	"fdt_high=0xffffffffffffffff\0"		\
@@ -272,6 +274,19 @@
  
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
+
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
  
 #endif
...	...	@@ -169,4 +169,17 @@
169	169	assigned-clocks = <&clk IMX8MM_CLK_QSPI>;
170	170	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
171	171	};
	172	+
	173	+&lcdif {
	174	+ enable_polarity_low;
	175	+ /delete-property/ assigned-clocks;
	176	+ /delete-property/ assigned-clock-parents;
	177	+ /delete-property/ assigned-clock-rates;
	178	+};
	179	+
	180	+&mipi_dsi {
	181	+ /delete-property/ assigned-clocks;
	182	+ /delete-property/ assigned-clock-parents;
	183	+ /delete-property/ assigned-clock-rates;
	184	+};
...	...	@@ -71,6 +71,32 @@
71	71	clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
72	72	};
73	73	};
	74	+
	75	+ dsi_host: dsi-host {
	76	+ compatible = "samsung,sec-mipi-dsi";
	77	+ status = "okay";
	78	+ };
	79	+
	80	+ rm67191_panel {
	81	+ compatible = "raydium,rm67191";
	82	+ pinctrl-names = "default";
	83	+ pinctrl-0 = <&pinctrl_mipi_dsi_en>;
	84	+ reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
	85	+ dsi-lanes = <4>;
	86	+ video-mode = <2>; /* 0: burst mode
	87	+ * 1: non-burst mode with sync event
	88	+ * 2: non-burst mode with sync pulse
	89	+ */
	90	+ panel-width-mm = <68>;
	91	+ panel-height-mm = <121>;
	92	+ status = "okay";
	93	+
	94	+ port {
	95	+ rm67191_from_dsim: endpoint {
	96	+ remote-endpoint = <&dsim_to_rm67191>;
	97	+ };
	98	+ };
	99	+ };
74	100	};
75	101
76	102	&A53_0 {
...	...	@@ -237,6 +263,20 @@
237	263	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
238	264	status = "okay";
239	265
	266	+ adv_bridge: adv7535@3d {
	267	+ compatible = "adi,adv7533";
	268	+ reg = <0x3d>;
	269	+ adi,addr-cec = <0x3c>;
	270	+ adi,dsi-lanes = <4>;
	271	+ status = "okay";
	272	+
	273	+ port {
	274	+ adv7535_from_dsim: endpoint {
	275	+ remote-endpoint = <&dsim_to_adv7535>;
	276	+ };
	277	+ };
	278	+ };
	279	+
240	280	ptn5110: tcpc@50 {
241	281	compatible = "nxp,ptn5110";
242	282	pinctrl-names = "default";
...	...	@@ -354,6 +394,32 @@
354	394	status = "okay";
355	395	};
356	396
	397	+&lcdif {
	398	+ display = <&display0>;
	399	+ status = "okay";
	400	+
	401	+ display0: display@0 {
	402	+ bits-per-pixel = <24>;
	403	+ bus-width = <24>;
	404	+ };
	405	+};
	406	+
	407	+&mipi_dsi {
	408	+ status = "okay";
	409	+
	410	+ port@1 {
	411	+ dsim_to_adv7535: endpoint {
	412	+ remote-endpoint = <&adv7535_from_dsim>;
	413	+ };
	414	+ };
	415	+
	416	+ port@2 {
	417	+ dsim_to_rm67191: endpoint {
	418	+ remote-endpoint = <&rm67191_from_dsim>;
	419	+ };
	420	+ };
	421	+};
	422	+
357	423	&iomuxc {
358	424	pinctrl-names = "default";
359	425
...	...	@@ -569,6 +635,12 @@
569	635	pinctrl_wdog: wdoggrp {
570	636	fsl,pins = <
571	637	MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
	638	+ >;
	639	+ };
	640	+
	641	+ pinctrl_mipi_dsi_en: mipi_dsi_en {
	642	+ fsl,pins = <
	643	+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
572	644	>;
573	645	};
574	646	};
...	...	@@ -40,6 +40,7 @@
40	40	spi0 = &flexspi;
41	41	usb0 = &usbotg1;
42	42	usb1 = &usbotg2;
	43	+ video0 = &lcdif;
43	44	};
44	45
45	46	cpus {
...	...	@@ -1030,7 +1031,7 @@
1030	1031	assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
1031	1032	<&clk IMX8MM_SYS_PLL2_1000M>,
1032	1033	<&clk IMX8MM_SYS_PLL1_800M>;
1033		- assigned-clock-rate = <594000000>, <500000000>, <200000000>;
	1034	+ assigned-clock-rates = <594000000>, <500000000>, <200000000>;
1034	1035	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1035	1036	lcdif-gpr = <&dispmix_gpr>;
1036	1037	resets = <&lcdif_resets>;
...	...	@@ -1278,6 +1279,11 @@
1278	1279	#address-cells = <1>;
1279	1280	#size-cells = <0>;
1280	1281	#reset-cells = <0>;
	1282	+
	1283	+ lcdif-soft-resetn {
	1284	+ compatible = "lcdif,soft-resetn";
	1285	+ resets = <&dispmix_sft_rstn IMX8MM_BUS_RSTN_BLK_SYNC>;
	1286	+ };
1281	1287
1282	1288	lcdif-clk-enable {
1283	1289	compatible = "lcdif,clk-enable";
...	...	@@ -287,6 +287,11 @@
287	287
288	288	#endif
289	289
	290	+#define FSL_SIP_GPC 0xC2000000
	291	+#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x3
	292	+#define DISPMIX 9
	293	+#define MIPI 10
	294	+
290	295	int board_init(void)
291	296	{
292	297	#ifdef CONFIG_USB_TCPC
...	...	@@ -295,6 +300,9 @@
295	300
296	301	if (IS_ENABLED(CONFIG_FEC_MXC))
297	302	setup_fec();
	303	+
	304	+ call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0);
	305	+ call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0);
298	306
299	307	return 0;
300	308	}
...	...	@@ -124,4 +124,14 @@
124	124	CONFIG_NAND_MXS_DT=y
125	125
126	126	CONFIG_OF_LIBFDT_OVERLAY=y
	127	+
	128	+CONFIG_REGMAP=y
	129	+CONFIG_SYSCON=y
	130	+CONFIG_DM_RESET=y
	131	+CONFIG_RESET_DISPMIX=y
	132	+CONFIG_VIDEO_IMX_SEC_DSI=y
	133	+CONFIG_DM_VIDEO=y
	134	+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
	135	+CONFIG_VIDEO_ADV7535=y
	136	+CONFIG_SYS_WHITE_ON_BLACK=y
...	...	@@ -127,4 +127,14 @@
127	127	CONFIG_NAND_MXS_DT=y
128	128
129	129	CONFIG_OF_LIBFDT_OVERLAY=y
	130	+
	131	+CONFIG_REGMAP=y
	132	+CONFIG_SYSCON=y
	133	+CONFIG_DM_RESET=y
	134	+CONFIG_RESET_DISPMIX=y
	135	+CONFIG_VIDEO_IMX_SEC_DSI=y
	136	+CONFIG_DM_VIDEO=y
	137	+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
	138	+CONFIG_VIDEO_ADV7535=y
	139	+CONFIG_SYS_WHITE_ON_BLACK=y
...	...	@@ -129,4 +129,14 @@
129	129	CONFIG_SDP_LOADADDR=0x40400000
130	130
131	131	CONFIG_OF_LIBFDT_OVERLAY=y
	132	+
	133	+CONFIG_REGMAP=y
	134	+CONFIG_SYSCON=y
	135	+CONFIG_DM_RESET=y
	136	+CONFIG_RESET_DISPMIX=y
	137	+CONFIG_VIDEO_IMX_SEC_DSI=y
	138	+CONFIG_DM_VIDEO=y
	139	+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
	140	+CONFIG_VIDEO_ADV7535=y
	141	+CONFIG_SYS_WHITE_ON_BLACK=y
...	...	@@ -130,4 +130,14 @@
130	130	CONFIG_SDP_LOADADDR=0x40400000
131	131
132	132	CONFIG_OF_LIBFDT_OVERLAY=y
	133	+
	134	+CONFIG_REGMAP=y
	135	+CONFIG_SYSCON=y
	136	+CONFIG_DM_RESET=y
	137	+CONFIG_RESET_DISPMIX=y
	138	+CONFIG_VIDEO_IMX_SEC_DSI=y
	139	+CONFIG_DM_VIDEO=y
	140	+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
	141	+CONFIG_VIDEO_ADV7535=y
	142	+CONFIG_SYS_WHITE_ON_BLACK=y
...	...	@@ -97,6 +97,7 @@
97	97	#if defined(CONFIG_NAND_BOOT)
98	98	#define CONFIG_EXTRA_ENV_SETTINGS \
99	99	CONFIG_MFG_ENV_SETTINGS \
	100	+ "splashimage=0x50000000\0" \
100	101	"fdt_addr=0x43000000\0" \
101	102	"fdt_high=0xffffffffffffffff\0" \
102	103	"mtdparts=" MFG_NAND_PARTITION "\0" \
...	...	@@ -115,6 +116,7 @@
115	116	JAILHOUSE_ENV \
116	117	"script=boot.scr\0" \
117	118	"image=Image\0" \
	119	+ "splashimage=0x50000000\0" \
118	120	"console=ttymxc1,115200\0" \
119	121	"fdt_addr=0x43000000\0" \
120	122	"fdt_high=0xffffffffffffffff\0" \
...	...	@@ -272,6 +274,19 @@
272	274
273	275	#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
274	276	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	277	+
	278	+#ifdef CONFIG_DM_VIDEO
	279	+#define CONFIG_VIDEO_MXS
	280	+#define CONFIG_VIDEO_LOGO
	281	+#define CONFIG_SPLASH_SCREEN
	282	+#define CONFIG_SPLASH_SCREEN_ALIGN
	283	+#define CONFIG_CMD_BMP
	284	+#define CONFIG_BMP_16BPP
	285	+#define CONFIG_BMP_24BPP
	286	+#define CONFIG_BMP_32BPP
	287	+#define CONFIG_VIDEO_BMP_RLE8
	288	+#define CONFIG_VIDEO_BMP_LOGO
	289	+#endif
275	290
276	291	#endif