Eric Lee / smarc-uboot

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Commit c8123f5004f7563085eaa0f122e45d7575e66ad6

Authored by Lokesh Vutla
1 parent cc1c95f414
Exists in v2015.07-smarct4x and in 3 other branches ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc

ARM: DRA7: emif: Fix disabling/enabling of refreshes 

clrsetbits_le32/clrbits_le32 takes mask of the bits as input that
are needed to be set/clear. But emif driver passes the shift of the bits.
Fixing it here.

Reported-by: Mark Mckeown <m-mckeown@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Showing 1 changed file with 3 additions and 3 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap-common/emif-common.c
Diff comments   View file @ c8123f5
... ... @@ -294,8 +294,8 @@
294 294 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
295 295  
296 296 /* Disable refreshed before leveling */
297   - clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT,
298   - EMIF_REG_INITREF_DIS_SHIFT);
  297 + clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
  298 + EMIF_REG_INITREF_DIS_MASK);
299 299  
300 300 /* Start Full leveling */
301 301 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
... ... @@ -309,7 +309,7 @@
309 309 }
310 310  
311 311 /* Enable refreshes after leveling */
312   - clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT);
  312 + clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
313 313  
314 314 debug("HW leveling success\n");
315 315 /*