ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling

This patch (Part 1 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>

ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling
This patch (Part 1 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
Grant Erickson · Stefan Roese
1 parent a439680019
Showing 12 changed files with 723 additions and 274 deletions Side-by-side Diff
cpu/ppc4xx/44x_spd_ddr.c
cpu/ppc4xx/44x_spd_ddr2.c
cpu/ppc4xx/Makefile
cpu/ppc4xx/cpu_init.c
cpu/ppc4xx/ecc.c
cpu/ppc4xx/ecc.h
cpu/ppc4xx/sdram.c
cpu/ppc4xx/start.S
cpu/ppc4xx/traps.c
include/asm-ppc/processor.h
include/ppc405.h
include/ppc4xx.h
@@ -53,6 +53,8 @@
 #include <ppc4xx.h>
 #include <asm/mmu.h>
  
+#include "ecc.h"
+
 #if defined(CONFIG_SPD_EEPROM) &&					\
 	(defined(CONFIG_440GP) || defined(CONFIG_440GX) ||		\
 	 defined(CONFIG_440EP) || defined(CONFIG_440GR))
@@ -296,10 +298,6 @@
 			unsigned long num_dimm_banks);
 static void program_tr1(void);
  
-#ifdef CONFIG_DDR_ECC
-static void program_ecc(unsigned long num_bytes);
-#endif
-
 static unsigned long program_bxcr(unsigned long *dimm_populated,
 				  unsigned char *iic0_dimm_addr,
 				  unsigned long num_dimm_banks);
@@ -418,7 +416,7 @@
 	/*
 	 * If ecc is enabled, initialize the parity bits.
 	 */
-	program_ecc(total_size);
+	ecc_init(CFG_SDRAM_BASE, total_size);
 #endif
  
 	return total_size;
@@ -1402,46 +1400,5 @@
  
 	return(bank_base_addr);
 }
-
-#ifdef CONFIG_DDR_ECC
-static void program_ecc(unsigned long num_bytes)
-{
-	unsigned long bank_base_addr;
-	unsigned long current_address;
-	unsigned long end_address;
-	unsigned long address_increment;
-	unsigned long cfg0;
-
-	/*
-	 * get Memory Controller Options 0 data
-	 */
-	mfsdram(mem_cfg0, cfg0);
-
-	/*
-	 * reset the bank_base address
-	 */
-	bank_base_addr = CFG_SDRAM_BASE;
-
-	if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
-		mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN);
-
-		if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32)
-			address_increment = 4;
-		else
-			address_increment = 8;
-
-		current_address = (unsigned long)(bank_base_addr);
-		end_address = (unsigned long)(bank_base_addr) + num_bytes;
-
-		while (current_address < end_address) {
-			*((unsigned long*)current_address) = 0x00000000;
-			current_address += address_increment;
-		}
-
-		mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
-			SDRAM_CFG0_MCHK_CHK);
-	}
-}
-#endif /* CONFIG_DDR_ECC */
 #endif /* CONFIG_SPD_EEPROM */
@@ -3,9 +3,12 @@
  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
  * DDR2 controller (non Denali Core). Those currently are:
  *
- * 405:		405EX
+ * 405:		405EX(r)
  * 440/460:	440SP/440SPe/460EX/460GT
  *
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ *   Grant Erickson <gerickson@nuovations.com>
+
  * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
@@ -45,6 +48,8 @@
 #include <asm/mmu.h>
 #include <asm/cache.h>
  
+#include "ecc.h"
+
 #if defined(CONFIG_SPD_EEPROM) &&				\
 	(defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
 	 defined(CONFIG_460EX) || defined(CONFIG_460GT))
  
@@ -3064,10 +3069,117 @@
 	dcr_data = mfdcr(SDRAM_R3BAS);
 	printf("        MQ3_B0BAS       = 0x%08X\n", dcr_data);
 }
-#else
+#else /* !defined(DEBUG) */
 static void ppc440sp_sdram_register_dump(void)
 {
 }
-#endif
-#endif /* CONFIG_SPD_EEPROM */
+#endif /* defined(DEBUG) */
+#elif defined(CONFIG_405EX)
+/*-----------------------------------------------------------------------------
+ * Function:	initdram
+ * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
+ * 		banks. The configuration is performed using static, compile-
+ *		time parameters.
+ *---------------------------------------------------------------------------*/
+long initdram(int board_type)
+{
+	unsigned long val;
+
+	/* Set Memory Bank Configuration Registers */
+
+	mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
+	mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
+	mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
+	mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
+
+	/* Set Memory Clock Timing Register */
+
+	mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
+
+	/* Set Refresh Time Register */
+
+	mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
+
+	/* Set SDRAM Timing Registers */
+
+	mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
+	mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
+	mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
+
+	/* Set Mode and Extended Mode Registers */
+
+	mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
+	mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
+
+	/* Set Memory Controller Options 1 Register */
+
+	mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
+
+	/* Set Manual Initialization Control Registers */
+
+	mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
+	mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
+	mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
+	mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
+	mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
+	mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
+	mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
+	mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
+	mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
+	mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
+	mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
+	mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
+	mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
+	mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
+	mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
+	mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
+
+	/* Set On-Die Termination Registers */
+
+	mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
+	mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
+	mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
+
+	/* Set Write Timing Register */
+
+	mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
+
+	/*
+	 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
+	 * SDRAM0_MCOPT2[IPTR] = 1
+	 */
+
+	mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
+			       SDRAM_MCOPT2_IPTR_EXECUTE));
+
+	/*
+	 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
+	 * completion of initialization.
+	 */
+
+	do {
+		mfsdram(SDRAM_MCSTAT, val);
+	} while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
+
+	/* Set Delay Control Registers */
+
+	mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
+	mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
+	mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
+	mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
+
+	/*
+	 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
+	 */
+
+	mfsdram(SDRAM_MCOPT2, val);
+	mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
+
+#if defined(CONFIG_DDR_ECC)
+	ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
+#endif /* defined(CONFIG_DDR_ECC) */
+
+	return (CFG_MBYTES_SDRAM << 20);
+}
+#endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) || ... */
@@ -45,6 +45,7 @@
 COBJS	+= cpu_init.o
 COBJS	+= denali_data_eye.o
 COBJS	+= denali_spd_ddr2.o
+COBJS	+= ecc.o
 COBJS	+= fdt.o
 COBJS	+= gpio.o
 COBJS	+= i2c.o
@@ -32,73 +32,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
  
-#ifdef CFG_INIT_DCACHE_CS
-# if (CFG_INIT_DCACHE_CS == 0)
-#  define PBxAP pb0ap
-#  define PBxCR pb0cr
-#  if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
-#   define PBxAP_VAL CFG_EBC_PB0AP
-#   define PBxCR_VAL CFG_EBC_PB0CR
-#  endif
-# endif
-# if (CFG_INIT_DCACHE_CS == 1)
-#  define PBxAP pb1ap
-#  define PBxCR pb1cr
-#  if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
-#   define PBxAP_VAL CFG_EBC_PB1AP
-#   define PBxCR_VAL CFG_EBC_PB1CR
-#  endif
-# endif
-# if (CFG_INIT_DCACHE_CS == 2)
-#  define PBxAP pb2ap
-#  define PBxCR pb2cr
-#  if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
-#   define PBxAP_VAL CFG_EBC_PB2AP
-#   define PBxCR_VAL CFG_EBC_PB2CR
-#  endif
-# endif
-# if (CFG_INIT_DCACHE_CS == 3)
-#  define PBxAP pb3ap
-#  define PBxCR pb3cr
-#  if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
-#   define PBxAP_VAL CFG_EBC_PB3AP
-#   define PBxCR_VAL CFG_EBC_PB3CR
-#  endif
-# endif
-# if (CFG_INIT_DCACHE_CS == 4)
-#  define PBxAP pb4ap
-#  define PBxCR pb4cr
-#  if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
-#   define PBxAP_VAL CFG_EBC_PB4AP
-#   define PBxCR_VAL CFG_EBC_PB4CR
-#  endif
-# endif
-# if (CFG_INIT_DCACHE_CS == 5)
-#  define PBxAP pb5ap
-#  define PBxCR pb5cr
-#  if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
-#   define PBxAP_VAL CFG_EBC_PB5AP
-#   define PBxCR_VAL CFG_EBC_PB5CR
-#  endif
-# endif
-# if (CFG_INIT_DCACHE_CS == 6)
-#  define PBxAP pb6ap
-#  define PBxCR pb6cr
-#  if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
-#   define PBxAP_VAL CFG_EBC_PB6AP
-#   define PBxCR_VAL CFG_EBC_PB6CR
-#  endif
-# endif
-# if (CFG_INIT_DCACHE_CS == 7)
-#  define PBxAP pb7ap
-#  define PBxCR pb7cr
-#  if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
-#   define PBxAP_VAL CFG_EBC_PB7AP
-#   define PBxCR_VAL CFG_EBC_PB7CR
-#  endif
-# endif
-#endif /* CFG_INIT_DCACHE_CS */
-
 #ifndef CFG_PLL_RECONFIG
 #define CFG_PLL_RECONFIG	0
 #endif
@@ -352,24 +285,6 @@
 #if defined(CONFIG_405GP)
 	uint pvr = get_pvr();
 #endif
-
-#ifdef CFG_INIT_DCACHE_CS
-	/*
-	 * Flush and invalidate dcache, then disable CS for temporary stack.
-	 * Afterwards, this CS can be used for other purposes
-	 */
-	dcache_disable();   /* flush and invalidate dcache */
-	mtebc(PBxAP, 0);
-	mtebc(PBxCR, 0);    /* disable CS for temporary stack */
-
-#if (defined(PBxAP_VAL) && defined(PBxCR_VAL))
-	/*
-	 * Write new value into CS register
-	 */
-	mtebc(PBxAP, PBxAP_VAL);
-	mtebc(PBxCR, PBxCR_VAL);
-#endif
-#endif /* CFG_INIT_DCACHE_CS */
  
 	/*
 	 * Write Ethernetaddress into on-chip register
+/*
+ *    Copyright (c) 2008 Nuovation System Designs, LLC
+ *      Grant Erickson <gerickson@nuovations.com>
+ *
+ *    (C) Copyright 2005-2007
+ *    Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ *    (C) Copyright 2002
+ *    Jun Gu, Artesyn Technology, jung@artesyncp.com
+ *
+ *    (C) Copyright 2001
+ *    Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
+ *
+ *    See file CREDITS for list of people who contributed to this
+ *    project.
+ *
+ *    This program is free software; you can redistribute it and/or
+ *    modify it under the terms of the GNU General Public License as
+ *    published by the Free Software Foundation; either version 2 of
+ *    the License, or (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will abe useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ *    MA 02111-1307 USA
+ *
+ *    Description:
+ *	This file implements generic DRAM ECC initialization for
+ *	PowerPC processors using a SDRAM DDR/DDR2 controller,
+ *	including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and
+ *	460EX/GT.
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#include "ecc.h"
+
+#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
+#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)
+/*
+ *  void ecc_init()
+ *
+ *  Description:
+ *    This routine initializes a range of DRAM ECC memory with known
+ *    data and enables ECC checking.
+ *
+ *  TO DO:
+ *    - Improve performance by utilizing cache.
+ *    - Further generalize to make usable by other 4xx variants (e.g.
+ *      440EPx, et al).
+ *
+ *  Input(s):
+ *    start - A pointer to the start of memory covered by ECC requiring
+ *	      initialization.
+ *    size  - The size, in bytes, of the memory covered by ECC requiring
+ *	      initialization.
+ *
+ *  Output(s):
+ *    start - A pointer to the start of memory covered by ECC with
+ *	      CFG_ECC_PATTERN written to all locations and ECC data
+ *	      primed.
+ *
+ *  Returns:
+ *    N/A
+ */
+void ecc_init(unsigned long * const start, unsigned long size)
+{
+	const unsigned long pattern = CFG_ECC_PATTERN;
+	unsigned * const end = (unsigned long * const)((long)start + size);
+	unsigned long * current = start;
+	unsigned long mcopt1;
+	long increment;
+
+	if (start >= end)
+		return;
+
+	mfsdram(SDRAM_MCOPT1, mcopt1);
+
+	/* Enable ECC generation without checking or reporting */
+
+	mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) |
+			       SDRAM_MCOPT1_MCHK_GEN));
+
+	increment = sizeof(u32);
+
+#if defined(CONFIG_440)
+	/*
+	 * Look at the geometry of SDRAM (data width) to determine whether we
+	 * can skip words when writing.
+	 */
+
+	if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) != SDRAM_MCOPT1_DMWD_32)
+		increment = sizeof(u64);
+#endif /* defined(CONFIG_440) */
+
+	while (current < end) {
+		*current = pattern;
+		 current = (unsigned long *)((long)current + increment);
+	}
+
+	/* Wait until the writes are finished. */
+
+	sync();
+
+	/* Enable ECC generation with checking and no reporting */
+
+	mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) |
+			       SDRAM_MCOPT1_MCHK_CHK));
+}
+#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
+#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
+/*
+ *    Copyright (c) 2008 Nuovation System Designs, LLC
+ *	Grant Erickson <gerickson@nuovations.com>
+ *
+ *    Copyright (c) 2007 DENX Software Engineering, GmbH
+ *	Stefan Roese <sr@denx.de>
+ *
+ *    See file CREDITS for list of people who contributed to this
+ *    project.
+ *
+ *    This program is free software; you can redistribute it and/or
+ *    modify it under the terms of the GNU General Public License as
+ *    published by the Free Software Foundation; either version 2 of
+ *    the License, or (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will abe useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ *    MA 02111-1307 USA
+ *
+ *    Description:
+ *	This file implements ECC initialization for PowerPC processors
+ *	using the SDRAM DDR2 controller, including the 405EX(r),
+ *	440SP(E), 460EX and 460GT.
+ *
+ */
+
+#ifndef _ECC_H_
+#define _ECC_H_
+
+#if !defined(CFG_ECC_PATTERN)
+#define	CFG_ECC_PATTERN	0x00000000
+#endif /* !defined(CFG_ECC_PATTERN) */
+
+extern void ecc_init(unsigned long * const start, unsigned long size);
+
+#endif /* _ECC_H_ */
@@ -31,6 +31,7 @@
 #include <ppc4xx.h>
 #include <asm/processor.h>
 #include "sdram.h"
+#include "ecc.h"
  
 #ifdef CONFIG_SDRAM_BANK0
  
@@ -331,49 +332,6 @@
 	/* return the current value for TR1 */
 	*tr1_value = (first_good + last_bad) / 2;
 }
-
-#ifdef CONFIG_SDRAM_ECC
-static void ecc_init(ulong start, ulong size)
-{
-	ulong	current_addr;		/* current byte address */
-	ulong	end_addr;		/* end of memory region */
-	ulong	addr_inc;		/* address skip between writes */
-	ulong	cfg0_reg;		/* for restoring ECC state */
-
-	/*
-	 * TODO: Enable dcache before running this test (speedup)
-	 */
-
-	mfsdram(mem_cfg0, cfg0_reg);
-	mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_GEN);
-
-	/*
-	 * look at geometry of SDRAM (data width) to determine whether we
-	 * can skip words when writing
-	 */
-	if ((cfg0_reg & SDRAM_CFG0_DRAMWDTH) == SDRAM_CFG0_DRAMWDTH_32)
-		addr_inc = 4;
-	else
-		addr_inc = 8;
-
-	current_addr = start;
-	end_addr = start + size;
-
-	while (current_addr < end_addr) {
-		*((ulong *)current_addr) = 0x00000000;
-		current_addr += addr_inc;
-	}
-
-	/*
-	 * TODO: Flush dcache and disable it again
-	 */
-
-	/*
-	 * Enable ecc checking and parity errors
-	 */
-	mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_CHK);
-}
-#endif
  
 /*
  * Autodetect onboard DDR SDRAM on 440 platforms
@@ -3,6 +3,8 @@
  *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
  *  Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *  Copyright (c) 2008 Nuovation System Designs, LLC
+ *    Grant Erickson <gerickson@nuovations.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  
  
  
  
  
  
  
  
  
@@ -79,41 +81,124 @@
 # if (CFG_INIT_DCACHE_CS == 0)
 #  define PBxAP pb0ap
 #  define PBxCR pb0cr
+#  if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
+#   define PBxAP_VAL CFG_EBC_PB0AP
+#   define PBxCR_VAL CFG_EBC_PB0CR
+#  endif
 # endif
 # if (CFG_INIT_DCACHE_CS == 1)
 #  define PBxAP pb1ap
 #  define PBxCR pb1cr
+#  if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
+#   define PBxAP_VAL CFG_EBC_PB1AP
+#   define PBxCR_VAL CFG_EBC_PB1CR
+#  endif
 # endif
 # if (CFG_INIT_DCACHE_CS == 2)
 #  define PBxAP pb2ap
 #  define PBxCR pb2cr
+#  if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
+#   define PBxAP_VAL CFG_EBC_PB2AP
+#   define PBxCR_VAL CFG_EBC_PB2CR
+#  endif
 # endif
 # if (CFG_INIT_DCACHE_CS == 3)
 #  define PBxAP pb3ap
 #  define PBxCR pb3cr
+#  if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
+#   define PBxAP_VAL CFG_EBC_PB3AP
+#   define PBxCR_VAL CFG_EBC_PB3CR
+#  endif
 # endif
 # if (CFG_INIT_DCACHE_CS == 4)
 #  define PBxAP pb4ap
 #  define PBxCR pb4cr
+#  if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
+#   define PBxAP_VAL CFG_EBC_PB4AP
+#   define PBxCR_VAL CFG_EBC_PB4CR
+#  endif
 # endif
 # if (CFG_INIT_DCACHE_CS == 5)
 #  define PBxAP pb5ap
 #  define PBxCR pb5cr
+#  if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
+#   define PBxAP_VAL CFG_EBC_PB5AP
+#   define PBxCR_VAL CFG_EBC_PB5CR
+#  endif
 # endif
 # if (CFG_INIT_DCACHE_CS == 6)
 #  define PBxAP pb6ap
 #  define PBxCR pb6cr
+#  if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
+#   define PBxAP_VAL CFG_EBC_PB6AP
+#   define PBxCR_VAL CFG_EBC_PB6CR
+#  endif
 # endif
 # if (CFG_INIT_DCACHE_CS == 7)
 #  define PBxAP pb7ap
 #  define PBxCR pb7cr
+#  if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
+#   define PBxAP_VAL CFG_EBC_PB7AP
+#   define PBxCR_VAL CFG_EBC_PB7CR
+#  endif
 # endif
+# ifndef PBxAP_VAL
+#  define PBxAP_VAL	0
+# endif
+# ifndef PBxCR_VAL
+#  define PBxCR_VAL	0
+# endif
+/*
+ * Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB
+ * used as temporary stack pointer for the primordial stack
+ */
+# ifndef CFG_INIT_DCACHE_PBxAR
+#  define CFG_INIT_DCACHE_PBxAR	(EBC_BXAP_BME_DISABLED			| \
+				 EBC_BXAP_TWT_ENCODE(7)			| \
+				 EBC_BXAP_BCE_DISABLE			| \
+				 EBC_BXAP_BCT_2TRANS			| \
+				 EBC_BXAP_CSN_ENCODE(0)			| \
+				 EBC_BXAP_OEN_ENCODE(0)			| \
+				 EBC_BXAP_WBN_ENCODE(0)			| \
+				 EBC_BXAP_WBF_ENCODE(0)			| \
+				 EBC_BXAP_TH_ENCODE(2)			| \
+				 EBC_BXAP_RE_DISABLED			| \
+				 EBC_BXAP_SOR_NONDELAYED		| \
+				 EBC_BXAP_BEM_WRITEONLY			| \
+				 EBC_BXAP_PEN_DISABLED)
+# endif /* CFG_INIT_DCACHE_PBxAR */
+# ifndef CFG_INIT_DCACHE_PBxCR
+#  define CFG_INIT_DCACHE_PBxCR	(EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR)	| \
+				 EBC_BXCR_BS_64MB			| \
+				 EBC_BXCR_BU_RW				| \
+				 EBC_BXCR_BW_16BIT)
+# endif /* CFG_INIT_DCACHE_PBxCR */
+# ifndef CFG_INIT_RAM_PATTERN
+#  define CFG_INIT_RAM_PATTERN	0xDEADDEAD
+# endif
 #endif /* CFG_INIT_DCACHE_CS */
  
 #if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10)))
 #error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END!
 #endif
  
+/*
+ * Unless otherwise overriden, enable two 128MB cachable instruction regions
+ * at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering
+ * NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions.
+ */
+#if !defined(CFG_ICACHE_SACR_VALUE)
+# define CFG_ICACHE_SACR_VALUE		\
+		(PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (  0 << 20)) | \
+		 PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (128 << 20)) | \
+		 PPC_128MB_SACR_VALUE(CFG_FLASH_BASE))
+#endif /* !defined(CFG_ICACHE_SACR_VALUE) */
+
+#if !defined(CFG_DCACHE_SACR_VALUE)
+# define CFG_DCACHE_SACR_VALUE		\
+		(0x00000000)
+#endif /* !defined(CFG_DCACHE_SACR_VALUE) */
+
 #define function_prolog(func_name)	.text; \
 					.align 2; \
 					.globl func_name; \
  
@@ -840,16 +925,16 @@
 	/* make sure above stores all comlete before going on */
 	sync
  
-	/*----------------------------------------------------------------------- */
-	/* Enable two 128MB cachable regions. */
-	/*----------------------------------------------------------------------- */
-	addis	r1,r0,0xc000
-	addi	r1,r1,0x0001
-	mticcr	r1			/* instruction cache */
+	/* Set-up icache cacheability. */
+	lis	r1, CFG_ICACHE_SACR_VALUE@h
+	ori	r1, r1, CFG_ICACHE_SACR_VALUE@l
+	mticcr	r1
+	isync
  
-	addis	r1,r0,0x0000
-	addi	r1,r1,0x0000
-	mtdccr	r1			/* data cache */
+	/* Set-up dcache cacheability. */
+	lis	r1, CFG_DCACHE_SACR_VALUE@h
+	ori	r1, r1, CFG_DCACHE_SACR_VALUE@l
+	mtdccr	r1
  
 	addis	r1,r0,CFG_INIT_RAM_ADDR@h
 	ori	r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
  
  
@@ -892,27 +977,20 @@
 					/* dbsr is cleared by setting bits to 1) */
 	mtdbsr	r4			/* clear/reset the dbsr */
  
-	/*----------------------------------------------------------------------- */
-	/* Invalidate I and D caches. Enable I cache for defined memory regions */
-	/* to speed things up. Leave the D cache disabled for now. It will be */
-	/* enabled/left disabled later based on user selected menu options. */
-	/* Be aware that the I cache may be disabled later based on the menu */
-	/* options as well. See miscLib/main.c. */
-	/*----------------------------------------------------------------------- */
+	/* Invalidate the i- and d-caches. */
 	bl	invalidate_icache
 	bl	invalidate_dcache
  
-	/*----------------------------------------------------------------------- */
-	/* Enable two 128MB cachable regions. */
-	/*----------------------------------------------------------------------- */
-	lis	r4,0xc000
-	ori	r4,r4,0x0001
-	mticcr	r4			/* instruction cache */
+	/* Set-up icache cacheability. */
+	lis	r4, CFG_ICACHE_SACR_VALUE@h
+	ori	r4, r4, CFG_ICACHE_SACR_VALUE@l
+	mticcr	r4
 	isync
  
-	lis	r4,0x0000
-	ori	r4,r4,0x0000
-	mtdccr	r4			/* data cache */
+	/* Set-up dcache cacheability. */
+	lis	r4, CFG_DCACHE_SACR_VALUE@h
+	ori	r4, r4, CFG_DCACHE_SACR_VALUE@l
+	mtdccr	r4
  
 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX)
 	/*----------------------------------------------------------------------- */
@@ -922,9 +1000,9 @@
 #endif
 #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
 	/*
-	 * Boards like the Kilauea (405EX) don't have OCM and can't use
-	 * DCache for init-ram. So setup stack here directly after the
-	 * SDRAM is initialized.
+	 * For boards that don't have OCM and can't use the data cache
+	 * for their primordial stack, setup stack here directly after the
+	 * SDRAM is initialized in ext_bus_cntlr_init.
 	 */
 	lis	r1, CFG_INIT_RAM_ADDR@h
 	ori	r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
  
  
  
  
  
  
  
  
  
  
@@ -1043,48 +1121,87 @@
 	/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
 	/*----------------------------------------------------------------------- */
 #ifdef CFG_INIT_DCACHE_CS
-	/*----------------------------------------------------------------------- */
-	/* Memory Bank x (nothingness) initialization 1GB+64MEG */
-	/* used as temporary stack pointer for stage0  */
-	/*----------------------------------------------------------------------- */
-	li	r4,PBxAP
-	mtdcr	ebccfga,r4
-	lis	r4,0x0380
-	ori	r4,r4,0x0480
-	mtdcr	ebccfgd,r4
+	li	r4, PBxAP
+	mtdcr	ebccfga, r4
+	lis	r4, CFG_INIT_DCACHE_PBxAR@h
+	ori	r4, r4, CFG_INIT_DCACHE_PBxAR@l
+	mtdcr	ebccfgd, r4
  
-	addi	r4,0,PBxCR
-	mtdcr	ebccfga,r4
-	lis	r4,0x400D
-	ori	r4,r4,0xa000
-	mtdcr	ebccfgd,r4
+	addi	r4, 0, PBxCR
+	mtdcr	ebccfga, r4
+	lis	r4, CFG_INIT_DCACHE_PBxCR@h
+	ori	r4, r4, CFG_INIT_DCACHE_PBxCR@l
+	mtdcr	ebccfgd, r4
  
-	/* turn on data cache for this region */
-	lis	r4,0x0080
+	/*
+	 * Enable the data cache for the 128MB storage access control region
+	 * at CFG_INIT_RAM_ADDR.
+	 */
+	mfdccr	r4
+	oris	r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
+	ori	r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
 	mtdccr	r4
  
-	/* set stack pointer and clear stack to known value */
+	/*
+	 * Preallocate data cache lines to be used to avoid a subsequent
+	 * cache miss and an ensuing machine check exception when exceptions
+	 * are enabled.
+	 */
+	li	r0, 0
  
-	lis	r1,CFG_INIT_RAM_ADDR@h
-	ori	r1,r1,CFG_INIT_SP_OFFSET@l
+	lis	r3, CFG_INIT_RAM_ADDR@h
+	ori	r3, r3, CFG_INIT_RAM_ADDR@l
  
-	li	r4,2048			/* we store 2048 words to stack */
+	lis	r4, CFG_INIT_RAM_END@h
+	ori	r4, r4, CFG_INIT_RAM_END@l
+
+	/*
+	 * Convert the size, in bytes, to the number of cache lines/blocks
+	 * to preallocate.
+	 */
+	clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
+	srwi	r5, r4, L1_CACHE_SHIFT
+	beq	..load_counter
+	addi	r5, r5, 0x0001
+..load_counter:
+	mtctr	r5
+
+	/* Preallocate the computed number of cache blocks. */
+..alloc_dcache_block:
+	dcba	r0, r3
+	addi	r3, r3, L1_CACHE_BYTES
+	bdnz	..alloc_dcache_block
+	sync
+
+	/*
+	 * Load the initial stack pointer and data area and convert the size,
+	 * in bytes, to the number of words to initialize to a known value.
+	 */
+	lis	r1, CFG_INIT_RAM_ADDR@h
+	ori	r1, r1, CFG_INIT_SP_OFFSET@l
+
+	lis	r4, (CFG_INIT_RAM_END >> 2)@h
+	ori	r4, r4, (CFG_INIT_RAM_END >> 2)@l
 	mtctr	r4
  
-	lis	r2,CFG_INIT_RAM_ADDR@h		/* we also clear data area */
-	ori	r2,r2,CFG_INIT_RAM_END@l	/* so cant copy value from r1 */
+	lis	r2, CFG_INIT_RAM_ADDR@h
+	ori	r2, r2, CFG_INIT_RAM_END@l
  
-	lis	r4,0xdead		/* we store 0xdeaddead in the stack */
-	ori	r4,r4,0xdead
+	lis	r4, CFG_INIT_RAM_PATTERN@h
+	ori	r4, r4, CFG_INIT_RAM_PATTERN@l
  
 ..stackloop:
-	stwu	r4,-4(r2)
+	stwu	r4, -4(r2)
 	bdnz	..stackloop
  
-	li	r0, 0			/* Make room for stack frame header and */
-	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
-	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
 	/*
+	 * Make room for stack frame header and clear final stack frame so
+	 * that stack backtraces terminate cleanly.
+	 */
+	stwu	r0, -4(r1)
+	stwu	r0, -4(r1)
+
+	/*
 	 * Set up a dummy frame to store reset vector as return address.
 	 * this causes stack underflow to reset board.
 	 */
  
  
  
  
  
  
@@ -1328,34 +1445,73 @@
  * This "function" does not return, instead it continues in RAM
  * after relocating the monitor code.
  *
- * r3 = dest
- * r4 = src
- * r5 = length in bytes
- * r6 = cachelinesize
+ * r3 = Relocated stack pointer
+ * r4 = Relocated global data pointer
+ * r5 = Relocated text pointer
  */
 	.globl	relocate_code
 relocate_code:
-#ifdef CONFIG_4xx_DCACHE
+#if defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS)
 	/*
-	 * We need to flush the Init Data before the dcache will be
-	 * invalidated
+	 * We need to flush the initial global data (gd_t) before the dcache
+	 * will be invalidated.
 	 */
  
-	/* save regs */
-	mr	r9,r3
-	mr	r10,r4
-	mr	r11,r5
+	/* Save registers */
+	mr	r9, r3
+	mr	r10, r4
+	mr	r11, r5
  
-	mr	r3,r4
-	addi	r4,r4,0x200	/* should be enough for init data */
+	/* Flush initial global data range */
+	mr	r3, r4
+	addi	r4, r4, CFG_GBL_DATA_SIZE@l
 	bl	flush_dcache_range
  
-	/* restore regs */
-	mr	r3,r9
-	mr	r4,r10
-	mr	r5,r11
-#endif
+#if defined(CFG_INIT_DCACHE_CS)
+	/*
+	 * Undo the earlier data cache set-up for the primordial stack and
+	 * data area. First, invalidate the data cache and then disable data
+	 * cacheability for that area. Finally, restore the EBC values, if
+	 * any.
+	 */
  
+	/* Invalidate the primordial stack and data area in cache */
+	lis	r3, CFG_INIT_RAM_ADDR@h
+	ori	r3, r3, CFG_INIT_RAM_ADDR@l
+
+	lis	r4, CFG_INIT_RAM_END@h
+	ori	r4, r4, CFG_INIT_RAM_END@l
+	add	r4, r4, r3
+
+	bl	invalidate_dcache_range
+
+	/* Disable cacheability for the region */
+	mfdccr	r3
+	lis     r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
+	ori     r4, r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
+	and     r3, r3, r4
+	mtdccr  r3
+
+	/* Restore the EBC parameters */
+	li	r3, PBxAP
+	mtdcr	ebccfga, r3
+	lis	r3, PBxAP_VAL@h
+	ori	r3, r3, PBxAP_VAL@l
+	mtdcr	ebccfgd, r3
+
+	li	r3, PBxCR
+	mtdcr	ebccfga, r3
+	lis	r3, PBxCR_VAL@h
+	ori	r3, r3, PBxCR_VAL@l
+	mtdcr	ebccfgd, r3
+#endif /* defined(CFG_INIT_DCACHE_CS) */
+
+	/* Restore registers */
+	mr	r3, r9
+	mr	r4, r10
+	mr	r5, r11
+#endif /* defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) */
+
 #ifdef CFG_INIT_RAM_DCACHE
 	/*
 	 * Unlock the previously locked d-cache
  
@@ -1396,13 +1552,13 @@
 	addi	r1,r0,CFG_TLB_FOR_BOOT_FLASH	/* Use defined TLB */
 #else
 	addi	r1,r0,0x0000		/* Default TLB entry is #0 */
-#endif
+#endif /* CFG_TLB_FOR_BOOT_FLASH */
 	tlbre	r0,r1,0x0002		/* Read contents */
 	ori	r0,r0,0x0c00		/* Or in the inhibit, write through bit */
 	tlbwe	r0,r1,0x0002		/* Save it out */
 	sync
 	isync
-#endif
+#endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */
 	mr	r1,  r3		/* Set new stack pointer		*/
 	mr	r9,  r4		/* Save copy of Init Data pointer	*/
 	mr	r10, r5		/* Save copy of Destination Address	*/
@@ -1425,7 +1581,7 @@
  
 	/* First our own GOT */
 	add	r14, r14, r15
-	/* the the one used by the C code */
+	/* then the one used by the C code */
 	add	r30, r30, r15
  
 	/*
@@ -170,7 +170,7 @@
  
 	val = get_esr();
  
-#if !defined(CONFIG_440)
+#if !defined(CONFIG_440) && !defined(CONFIG_405EX)
 	if (val& ESR_IMCP) {
 		printf("Instruction");
 		mtspr(ESR, val & ~ESR_IMCP);
@@ -179,7 +179,7 @@
 	}
 	printf(" machine check.\n");
  
-#elif defined(CONFIG_440)
+#elif defined(CONFIG_440) || defined(CONFIG_405EX)
 	if (val& ESR_IMCP){
 		printf("Instruction Synchronous Machine Check exception\n");
 		mtspr(SPRN_ESR, val & ~ESR_IMCP);
  
@@ -187,10 +187,15 @@
 		val = mfspr(MCSR);
 		if (val & MCSR_IB)
 			printf("Instruction Read PLB Error\n");
+#if defined(CONFIG_440)
 		if (val & MCSR_DRB)
 			printf("Data Read PLB Error\n");
 		if (val & MCSR_DWB)
 			printf("Data Write PLB Error\n");
+#else
+		if (val & MCSR_DB)
+			printf("Data PLB Error\n");
+#endif
 		if (val & MCSR_TLBP)
 			printf("TLB Parity Error\n");
 		if (val & MCSR_ICP){
@@ -460,17 +460,19 @@
 #define SPRN_PID2	0x27a	/* Process ID Register 2 */
 #define SPRN_MCSR	0x23c	/* Machine Check Syndrome register */
 #define SPRN_MCAR	0x23d	/* Machine Check Address register */
-#ifdef CONFIG_440
 #define MCSR_MCS	0x80000000	/* Machine Check Summary */
 #define MCSR_IB		0x40000000	/* Instruction PLB Error */
+#if defined(CONFIG_440)
 #define MCSR_DRB	0x20000000	/* Data Read PLB Error */
 #define MCSR_DWB	0x10000000	/* Data Write PLB Error */
+#else
+#define MCSR_DB		0x20000000	/* Data PLB Error */
+#endif /* defined(CONFIG_440) */
 #define MCSR_TLBP	0x08000000	/* TLB Parity Error */
 #define MCSR_ICP	0x04000000	/* I-Cache Parity Error */
 #define MCSR_DCSP	0x02000000	/* D-Cache Search Parity Error */
 #define MCSR_DCFP	0x01000000	/* D-Cache Flush Parity Error */
 #define MCSR_IMPE	0x00800000	/* Imprecise Machine Check Exception */
-#endif
 #define ESR_ST		0x00800000	/* Store Operation */
  
 #if defined(CONFIG_MPC86xx)
@@ -22,6 +22,10 @@
 #ifndef	__PPC405_H__
 #define __PPC405_H__
  
+/* Define bits and masks for real-mode storage attribute control registers */
+#define PPC_128MB_SACR_BIT(addr)	((addr) >> 27)
+#define PPC_128MB_SACR_VALUE(addr)	PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
+
 #ifndef CONFIG_IOP480
 #define CFG_DCACHE_SIZE		(16 << 10)	/* For AMCC 405 CPUs	*/
 #else
@@ -363,6 +367,120 @@
 #endif	/* defined(CONFIG_405EZ) */
  
 /******************************************************************************
+ * External Bus Controller (EBC)
+ *****************************************************************************/
+
+/* Bank Configuration Register */
+#define	EBC_BXCR_BAS_MASK	PPC_REG_VAL(11, 0xFFF)
+#define EBC_BXCR_BAS_ENCODE(n)	(((static_cast(unsigned long, n)) & \
+				  EBC_BXCR_BAS_MASK) << 0)
+#define EBC_BXCR_BS_MASK	PPC_REG_VAL(14, 0x7)
+#define EBC_BXCR_BS_1MB		PPC_REG_VAL(14, 0x0)
+#define EBC_BXCR_BS_2MB		PPC_REG_VAL(14, 0x1)
+#define EBC_BXCR_BS_4MB		PPC_REG_VAL(14, 0x2)
+#define EBC_BXCR_BS_8MB		PPC_REG_VAL(14, 0x3)
+#define EBC_BXCR_BS_16MB	PPC_REG_VAL(14, 0x4)
+#define EBC_BXCR_BS_32MB	PPC_REG_VAL(14, 0x5)
+#define EBC_BXCR_BS_64MB	PPC_REG_VAL(14, 0x6)
+#define EBC_BXCR_BS_128MB	PPC_REG_VAL(14, 0x7)
+#define EBC_BXCR_BU_MASK	PPC_REG_VAL(16, 0x3)
+#define	EBC_BXCR_BU_NONE	PPC_REG_VAL(16, 0x0)
+#define EBC_BXCR_BU_R		PPC_REG_VAL(16, 0x1)
+#define EBC_BXCR_BU_W		PPC_REG_VAL(16, 0x2)
+#define EBC_BXCR_BU_RW		PPC_REG_VAL(16, 0x3)
+#define EBC_BXCR_BW_MASK	PPC_REG_VAL(18, 0x3)
+#define EBC_BXCR_BW_8BIT	PPC_REG_VAL(18, 0x0)
+#define EBC_BXCR_BW_16BIT	PPC_REG_VAL(18, 0x1)
+#define EBC_BXCR_BW_32BIT	PPC_REG_VAL(18, 0x3)
+
+/* Bank Access Parameter Register */
+#define EBC_BXAP_BME_ENABLED	PPC_REG_VAL(0, 0x1)
+#define EBC_BXAP_BME_DISABLED	PPC_REG_VAL(0, 0x0)
+#define EBC_BXAP_TWT_ENCODE(n)	PPC_REG_VAL(8, \
+					    (static_cast(unsigned long, n)) \
+					    & 0xFF)
+#define	EBC_BXAP_FWT_ENCODE(n)	PPC_REG_VAL(5, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x1F)
+#define	EBC_BXAP_BWT_ENCODE(n)	PPC_REG_VAL(8, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x7)
+#define EBC_BXAP_BCE_DISABLE	PPC_REG_VAL(9, 0x0)
+#define EBC_BXAP_BCE_ENABLE	PPC_REG_VAL(9, 0x1)
+#define EBC_BXAP_BCT_MASK	PPC_REG_VAL(11, 0x3)
+#define EBC_BXAP_BCT_2TRANS	PPC_REG_VAL(11, 0x0)
+#define EBC_BXAP_BCT_4TRANS	PPC_REG_VAL(11, 0x1)
+#define EBC_BXAP_BCT_8TRANS	PPC_REG_VAL(11, 0x2)
+#define EBC_BXAP_BCT_16TRANS	PPC_REG_VAL(11, 0x3)
+#define EBC_BXAP_CSN_ENCODE(n)	PPC_REG_VAL(13, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x3)
+#define EBC_BXAP_OEN_ENCODE(n)	PPC_REG_VAL(15, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x3)
+#define EBC_BXAP_WBN_ENCODE(n)	PPC_REG_VAL(17, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x3)
+#define EBC_BXAP_WBF_ENCODE(n)	PPC_REG_VAL(19, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x3)
+#define EBC_BXAP_TH_ENCODE(n)	PPC_REG_VAL(22, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x7)
+#define EBC_BXAP_RE_ENABLED	PPC_REG_VAL(23, 0x1)
+#define EBC_BXAP_RE_DISABLED	PPC_REG_VAL(23, 0x0)
+#define EBC_BXAP_SOR_DELAYED	PPC_REG_VAL(24, 0x0)
+#define EBC_BXAP_SOR_NONDELAYED	PPC_REG_VAL(24, 0x1)
+#define EBC_BXAP_BEM_WRITEONLY	PPC_REG_VAL(25, 0x0)
+#define EBC_BXAP_BEM_RW		PPC_REG_VAL(25, 0x1)
+#define EBC_BXAP_PEN_DISABLED	PPC_REG_VAL(26, 0x0)
+#define EBC_BXAP_PEN_ENABLED	PPC_REG_VAL(26, 0x1)
+
+/* Configuration Register */
+#define EBC_CFG_LE_MASK		PPC_REG_VAL(0, 0x1)
+#define EBC_CFG_LE_UNLOCK	PPC_REG_VAL(0, 0x0)
+#define EBC_CFG_LE_LOCK		PPC_REG_VAL(0, 0x1)
+#define EBC_CFG_PTD_MASK	PPC_REG_VAL(1, 0x1)
+#define EBC_CFG_PTD_ENABLE	PPC_REG_VAL(1, 0x0)
+#define EBC_CFG_PTD_DISABLE	PPC_REG_VAL(1, 0x1)
+#define EBC_CFG_RTC_MASK	PPC_REG_VAL(4, 0x7)
+#define EBC_CFG_RTC_16PERCLK	PPC_REG_VAL(4, 0x0)
+#define EBC_CFG_RTC_32PERCLK	PPC_REG_VAL(4, 0x1)
+#define EBC_CFG_RTC_64PERCLK	PPC_REG_VAL(4, 0x2)
+#define EBC_CFG_RTC_128PERCLK	PPC_REG_VAL(4, 0x3)
+#define EBC_CFG_RTC_256PERCLK	PPC_REG_VAL(4, 0x4)
+#define EBC_CFG_RTC_512PERCLK	PPC_REG_VAL(4, 0x5)
+#define EBC_CFG_RTC_1024PERCLK	PPC_REG_VAL(4, 0x6)
+#define EBC_CFG_RTC_2048PERCLK	PPC_REG_VAL(4, 0x7)
+#define EBC_CFG_ATC_MASK	PPC_REG_VAL(5, 0x1)
+#define EBC_CFG_ATC_HI		PPC_REG_VAL(5, 0x0)
+#define EBC_CFG_ATC_PREVIOUS	PPC_REG_VAL(5, 0x1)
+#define EBC_CFG_DTC_MASK	PPC_REG_VAL(6, 0x1)
+#define EBC_CFG_DTC_HI		PPC_REG_VAL(6, 0x0)
+#define EBC_CFG_DTC_PREVIOUS	PPC_REG_VAL(6, 0x1)
+#define EBC_CFG_CTC_MASK	PPC_REG_VAL(7, 0x1)
+#define EBC_CFG_CTC_HI		PPC_REG_VAL(7, 0x0)
+#define EBC_CFG_CTC_PREVIOUS	PPC_REG_VAL(7, 0x1)
+#define EBC_CFG_OEO_MASK	PPC_REG_VAL(8, 0x1)
+#define EBC_CFG_OEO_DISABLE	PPC_REG_VAL(8, 0x0)
+#define EBC_CFG_OEO_ENABLE	PPC_REG_VAL(8, 0x1)
+#define EBC_CFG_EMC_MASK	PPC_REG_VAL(9, 0x1)
+#define EBC_CFG_EMC_NONDEFAULT	PPC_REG_VAL(9, 0x0)
+#define EBC_CFG_EMC_DEFAULT	PPC_REG_VAL(9, 0x1)
+#define EBC_CFG_PME_MASK	PPC_REG_VAL(14, 0x1)
+#define EBC_CFG_PME_DISABLE	PPC_REG_VAL(14, 0x0)
+#define EBC_CFG_PME_ENABLE	PPC_REG_VAL(14, 0x1)
+#define EBC_CFG_PMT_MASK	PPC_REG_VAL(19, 0x1F)
+#define EBC_CFG_PMT_ENCODE(n)	PPC_REG_VAL(19, \
+					    (static_cast(unsigned long, n)) \
+					    & 0x1F)
+#define EBC_CFG_PR_MASK		PPC_REG_VAL(21, 0x3)
+#define EBC_CFG_PR_16		PPC_REG_VAL(21, 0x0)
+#define EBC_CFG_PR_32		PPC_REG_VAL(21, 0x1)
+#define EBC_CFG_PR_64		PPC_REG_VAL(21, 0x2)
+#define EBC_CFG_PR_128		PPC_REG_VAL(21, 0x3)
+
+/******************************************************************************
  * SDRAM Controller
  ******************************************************************************/
   /* values for memcfga register - indirect addressing of these regs */
@@ -1218,19 +1336,43 @@
  
 /*-----------------------------------------------------------------------------+
 |  Memory Bank 0-7 configuration
-+-----------------------------------------------------------------------------*/
-#define SDRAM_RXBAS_SDSZ_4	   0x00000000	   /*	4M		      */
-#define SDRAM_RXBAS_SDSZ_8	   0x00001000	   /*	8M		      */
-#define SDRAM_RXBAS_SDSZ_16	   0x00002000	   /*  16M		      */
-#define SDRAM_RXBAS_SDSZ_32	   0x00003000	   /*  32M		      */
-#define SDRAM_RXBAS_SDSZ_64	   0x00004000	   /*  64M		      */
-#define SDRAM_RXBAS_SDSZ_128	   0x00005000	   /* 128M		      */
-#define SDRAM_RXBAS_SDSZ_256	   0x00006000	   /* 256M		      */
-#define SDRAM_RXBAS_SDSZ_512	   0x00007000	   /* 512M		      */
-#define SDRAM_RXBAS_SDSZ_1024	   0x00008000	   /* 1024M		      */
-#define SDRAM_RXBAS_SDSZ_2048	   0x00009000	   /* 2048M		      */
-#define SDRAM_RXBAS_SDSZ_4096	   0x0000a000	   /* 4096M		      */
-#define SDRAM_RXBAS_SDSZ_8192	   0x0000b000	   /* 8192M		      */
++----------------------------------------------------------------------------*/
+#define SDRAM_RXBAS_SDSZ_MASK		PPC_REG_VAL(19, 0xF)
+#define SDRAM_RXBAS_SDSZ_4MB	   	PPC_REG_VAL(19, 0x0)
+#define SDRAM_RXBAS_SDSZ_8MB	   	PPC_REG_VAL(19, 0x1)
+#define SDRAM_RXBAS_SDSZ_16MB	   	PPC_REG_VAL(19, 0x2)
+#define SDRAM_RXBAS_SDSZ_32MB	   	PPC_REG_VAL(19, 0x3)
+#define SDRAM_RXBAS_SDSZ_64MB	   	PPC_REG_VAL(19, 0x4)
+#define SDRAM_RXBAS_SDSZ_128MB	   	PPC_REG_VAL(19, 0x5)
+#define SDRAM_RXBAS_SDSZ_256MB	   	PPC_REG_VAL(19, 0x6)
+#define SDRAM_RXBAS_SDSZ_512MB	   	PPC_REG_VAL(19, 0x7)
+#define SDRAM_RXBAS_SDSZ_1024MB	   	PPC_REG_VAL(19, 0x8)
+#define SDRAM_RXBAS_SDSZ_2048MB	   	PPC_REG_VAL(19, 0x9)
+#define SDRAM_RXBAS_SDSZ_4096MB		PPC_REG_VAL(19, 0xA)
+#define SDRAM_RXBAS_SDSZ_8192MB		PPC_REG_VAL(19, 0xB)
+#define SDRAM_RXBAS_SDSZ_8      	SDRAM_RXBAS_SDSZ_8MB
+#define SDRAM_RXBAS_SDSZ_16     	SDRAM_RXBAS_SDSZ_16MB
+#define SDRAM_RXBAS_SDSZ_32     	SDRAM_RXBAS_SDSZ_32MB
+#define SDRAM_RXBAS_SDSZ_64     	SDRAM_RXBAS_SDSZ_64MB
+#define SDRAM_RXBAS_SDSZ_128    	SDRAM_RXBAS_SDSZ_128MB
+#define SDRAM_RXBAS_SDSZ_256    	SDRAM_RXBAS_SDSZ_256MB
+#define SDRAM_RXBAS_SDSZ_512    	SDRAM_RXBAS_SDSZ_512MB
+#define SDRAM_RXBAS_SDSZ_1024		SDRAM_RXBAS_SDSZ_1024MB
+#define SDRAM_RXBAS_SDSZ_2048		SDRAM_RXBAS_SDSZ_2048MB
+#define SDRAM_RXBAS_SDSZ_4096		SDRAM_RXBAS_SDSZ_4096MB
+#define SDRAM_RXBAS_SDSZ_8192		SDRAM_RXBAS_SDSZ_8192MB
+#define SDRAM_RXBAS_SDAM_MODE0		PPC_REG_VAL(23, 0x0)
+#define SDRAM_RXBAS_SDAM_MODE1		PPC_REG_VAL(23, 0x1)
+#define SDRAM_RXBAS_SDAM_MODE2		PPC_REG_VAL(23, 0x2)
+#define SDRAM_RXBAS_SDAM_MODE3		PPC_REG_VAL(23, 0x3)
+#define SDRAM_RXBAS_SDAM_MODE4		PPC_REG_VAL(23, 0x4)
+#define SDRAM_RXBAS_SDAM_MODE5		PPC_REG_VAL(23, 0x5)
+#define SDRAM_RXBAS_SDAM_MODE6		PPC_REG_VAL(23, 0x6)
+#define SDRAM_RXBAS_SDAM_MODE7		PPC_REG_VAL(23, 0x7)
+#define SDRAM_RXBAS_SDAM_MODE8		PPC_REG_VAL(23, 0x8)
+#define SDRAM_RXBAS_SDAM_MODE9		PPC_REG_VAL(23, 0x9)
+#define SDRAM_RXBAS_SDBE_DISABLE	PPC_REG_VAL(31, 0x0)
+#define SDRAM_RXBAS_SDBE_ENABLE		PPC_REG_VAL(31, 0x1)
  
 /*-----------------------------------------------------------------------------+
 |  Memory Controller Status
@@ -1611,6 +1753,29 @@
 #define SDR0_PFC1_USBBIGEN	0x00000010
 #define SDR0_PFC1_GPT_FREQ	0x0000000f
 #endif
+
+/* General Purpose Timer (GPT) Register Offsets */
+#define GPT0_TBC		0x00000000
+#define GPT0_IM			0x00000018
+#define GPT0_ISS		0x0000001C
+#define GPT0_ISC		0x00000020
+#define GPT0_IE			0x00000024
+#define GPT0_COMP0		0x00000080
+#define GPT0_COMP1		0x00000084
+#define GPT0_COMP2		0x00000088
+#define GPT0_COMP3		0x0000008C
+#define GPT0_COMP4		0x00000090
+#define GPT0_COMP5		0x00000094
+#define GPT0_COMP6		0x00000098
+#define GPT0_MASK0		0x000000C0
+#define GPT0_MASK1		0x000000C4
+#define GPT0_MASK2		0x000000C8
+#define GPT0_MASK3		0x000000CC
+#define GPT0_MASK4		0x000000D0
+#define GPT0_MASK5		0x000000D4
+#define GPT0_MASK6		0x000000D8
+#define GPT0_DCT0		0x00000110
+#define GPT0_DCIS		0x0000011C
  
 #endif	/* __PPC405_H__ */
@@ -29,6 +29,21 @@
 #endif
  
 /*
+ * Macro for generating register field mnemonics
+ */
+#define	PPC_REG_BITS		32
+#define	PPC_REG_VAL(bit, value)	((value) << ((PPC_REG_BITS - 1) - (bit)))
+
+/*
+ * Elide casts when assembling register mnemonics
+ */
+#ifndef __ASSEMBLY__
+#define	static_cast(type, val)	(type)(val)
+#else
+#define	static_cast(type, val)	(val)
+#endif
+
+/*
  * Common stuff for 4xx (405 and 440)
  */
...	...	@@ -53,6 +53,8 @@
53	53	#include <ppc4xx.h>
54	54	#include <asm/mmu.h>
55	55
	56	+#include "ecc.h"
	57	+
56	58	#if defined(CONFIG_SPD_EEPROM) && \
57	59	(defined(CONFIG_440GP) \|\| defined(CONFIG_440GX) \|\| \
58	60	defined(CONFIG_440EP) \|\| defined(CONFIG_440GR))
...	...	@@ -296,10 +298,6 @@
296	298	unsigned long num_dimm_banks);
297	299	static void program_tr1(void);
298	300
299		-#ifdef CONFIG_DDR_ECC
300		-static void program_ecc(unsigned long num_bytes);
301		-#endif
302		-
303	301	static unsigned long program_bxcr(unsigned long *dimm_populated,
304	302	unsigned char *iic0_dimm_addr,
305	303	unsigned long num_dimm_banks);
...	...	@@ -418,7 +416,7 @@
418	416	/*
419	417	* If ecc is enabled, initialize the parity bits.
420	418	*/
421		- program_ecc(total_size);
	419	+ ecc_init(CFG_SDRAM_BASE, total_size);
422	420	#endif
423	421
424	422	return total_size;
...	...	@@ -1402,46 +1400,5 @@
1402	1400
1403	1401	return(bank_base_addr);
1404	1402	}
1405		-
1406		-#ifdef CONFIG_DDR_ECC
1407		-static void program_ecc(unsigned long num_bytes)
1408		-{
1409		- unsigned long bank_base_addr;
1410		- unsigned long current_address;
1411		- unsigned long end_address;
1412		- unsigned long address_increment;
1413		- unsigned long cfg0;
1414		-
1415		- /*
1416		- * get Memory Controller Options 0 data
1417		- */
1418		- mfsdram(mem_cfg0, cfg0);
1419		-
1420		- /*
1421		- * reset the bank_base address
1422		- */
1423		- bank_base_addr = CFG_SDRAM_BASE;
1424		-
1425		- if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
1426		- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) \| SDRAM_CFG0_MCHK_GEN);
1427		-
1428		- if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32)
1429		- address_increment = 4;
1430		- else
1431		- address_increment = 8;
1432		-
1433		- current_address = (unsigned long)(bank_base_addr);
1434		- end_address = (unsigned long)(bank_base_addr) + num_bytes;
1435		-
1436		- while (current_address < end_address) {
1437		- ((unsigned long)current_address) = 0x00000000;
1438		- current_address += address_increment;
1439		- }
1440		-
1441		- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) \|
1442		- SDRAM_CFG0_MCHK_CHK);
1443		- }
1444		-}
1445		-#endif /* CONFIG_DDR_ECC */
1446	1403	#endif /* CONFIG_SPD_EEPROM */
...	...	@@ -3,9 +3,12 @@
3	3	* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4	4	* DDR2 controller (non Denali Core). Those currently are:
5	5	*
6		- * 405: 405EX
	6	+ * 405: 405EX(r)
7	7	* 440/460: 440SP/440SPe/460EX/460GT
8	8	*
	9	+ * Copyright (c) 2008 Nuovation System Designs, LLC
	10	+ * Grant Erickson <gerickson@nuovations.com>
	11	+
9	12	* (C) Copyright 2007-2008
10	13	* Stefan Roese, DENX Software Engineering, sr@denx.de.
11	14	*
...	...	@@ -45,6 +48,8 @@
45	48	#include <asm/mmu.h>
46	49	#include <asm/cache.h>
47	50
	51	+#include "ecc.h"
	52	+
48	53	#if defined(CONFIG_SPD_EEPROM) && \
49	54	(defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE) \|\| \
50	55	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT))
51	56
...	...	@@ -3064,10 +3069,117 @@
3064	3069	dcr_data = mfdcr(SDRAM_R3BAS);
3065	3070	printf(" MQ3_B0BAS = 0x%08X\n", dcr_data);
3066	3071	}
3067		-#else
	3072	+#else /* !defined(DEBUG) */
3068	3073	static void ppc440sp_sdram_register_dump(void)
3069	3074	{
3070	3075	}
3071		-#endif
3072		-#endif /* CONFIG_SPD_EEPROM */
	3076	+#endif /* defined(DEBUG) */
	3077	+#elif defined(CONFIG_405EX)
	3078	+/*-----------------------------------------------------------------------------
	3079	+ * Function: initdram
	3080	+ * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
	3081	+ * banks. The configuration is performed using static, compile-
	3082	+ * time parameters.
	3083	+ ---------------------------------------------------------------------------/
	3084	+long initdram(int board_type)
	3085	+{
	3086	+ unsigned long val;
	3087	+
	3088	+ /* Set Memory Bank Configuration Registers */
	3089	+
	3090	+ mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
	3091	+ mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
	3092	+ mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
	3093	+ mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
	3094	+
	3095	+ /* Set Memory Clock Timing Register */
	3096	+
	3097	+ mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
	3098	+
	3099	+ /* Set Refresh Time Register */
	3100	+
	3101	+ mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
	3102	+
	3103	+ /* Set SDRAM Timing Registers */
	3104	+
	3105	+ mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
	3106	+ mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
	3107	+ mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
	3108	+
	3109	+ /* Set Mode and Extended Mode Registers */
	3110	+
	3111	+ mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
	3112	+ mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
	3113	+
	3114	+ /* Set Memory Controller Options 1 Register */
	3115	+
	3116	+ mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
	3117	+
	3118	+ /* Set Manual Initialization Control Registers */
	3119	+
	3120	+ mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
	3121	+ mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
	3122	+ mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
	3123	+ mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
	3124	+ mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
	3125	+ mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
	3126	+ mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
	3127	+ mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
	3128	+ mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
	3129	+ mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
	3130	+ mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
	3131	+ mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
	3132	+ mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
	3133	+ mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
	3134	+ mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
	3135	+ mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
	3136	+
	3137	+ /* Set On-Die Termination Registers */
	3138	+
	3139	+ mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
	3140	+ mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
	3141	+ mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
	3142	+
	3143	+ /* Set Write Timing Register */
	3144	+
	3145	+ mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
	3146	+
	3147	+ /*
	3148	+ * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
	3149	+ * SDRAM0_MCOPT2[IPTR] = 1
	3150	+ */
	3151	+
	3152	+ mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT \|
	3153	+ SDRAM_MCOPT2_IPTR_EXECUTE));
	3154	+
	3155	+ /*
	3156	+ * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
	3157	+ * completion of initialization.
	3158	+ */
	3159	+
	3160	+ do {
	3161	+ mfsdram(SDRAM_MCSTAT, val);
	3162	+ } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
	3163	+
	3164	+ /* Set Delay Control Registers */
	3165	+
	3166	+ mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
	3167	+ mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
	3168	+ mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
	3169	+ mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
	3170	+
	3171	+ /*
	3172	+ * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
	3173	+ */
	3174	+
	3175	+ mfsdram(SDRAM_MCOPT2, val);
	3176	+ mtsdram(SDRAM_MCOPT2, val \| SDRAM_MCOPT2_DCEN_ENABLE);
	3177	+
	3178	+#if defined(CONFIG_DDR_ECC)
	3179	+ ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
	3180	+#endif /* defined(CONFIG_DDR_ECC) */
	3181	+
	3182	+ return (CFG_MBYTES_SDRAM << 20);
	3183	+}
	3184	+#endif /* defined(CONFIG_SPD_EEPROM) && defined(CONFIG_440SP) \|\| ... */
...	...	@@ -45,6 +45,7 @@
45	45	COBJS += cpu_init.o
46	46	COBJS += denali_data_eye.o
47	47	COBJS += denali_spd_ddr2.o
	48	+COBJS += ecc.o
48	49	COBJS += fdt.o
49	50	COBJS += gpio.o
50	51	COBJS += i2c.o
...	...	@@ -32,73 +32,6 @@
32	32	DECLARE_GLOBAL_DATA_PTR;
33	33	#endif
34	34
35		-#ifdef CFG_INIT_DCACHE_CS
36		-# if (CFG_INIT_DCACHE_CS == 0)
37		-# define PBxAP pb0ap
38		-# define PBxCR pb0cr
39		-# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
40		-# define PBxAP_VAL CFG_EBC_PB0AP
41		-# define PBxCR_VAL CFG_EBC_PB0CR
42		-# endif
43		-# endif
44		-# if (CFG_INIT_DCACHE_CS == 1)
45		-# define PBxAP pb1ap
46		-# define PBxCR pb1cr
47		-# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
48		-# define PBxAP_VAL CFG_EBC_PB1AP
49		-# define PBxCR_VAL CFG_EBC_PB1CR
50		-# endif
51		-# endif
52		-# if (CFG_INIT_DCACHE_CS == 2)
53		-# define PBxAP pb2ap
54		-# define PBxCR pb2cr
55		-# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
56		-# define PBxAP_VAL CFG_EBC_PB2AP
57		-# define PBxCR_VAL CFG_EBC_PB2CR
58		-# endif
59		-# endif
60		-# if (CFG_INIT_DCACHE_CS == 3)
61		-# define PBxAP pb3ap
62		-# define PBxCR pb3cr
63		-# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
64		-# define PBxAP_VAL CFG_EBC_PB3AP
65		-# define PBxCR_VAL CFG_EBC_PB3CR
66		-# endif
67		-# endif
68		-# if (CFG_INIT_DCACHE_CS == 4)
69		-# define PBxAP pb4ap
70		-# define PBxCR pb4cr
71		-# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
72		-# define PBxAP_VAL CFG_EBC_PB4AP
73		-# define PBxCR_VAL CFG_EBC_PB4CR
74		-# endif
75		-# endif
76		-# if (CFG_INIT_DCACHE_CS == 5)
77		-# define PBxAP pb5ap
78		-# define PBxCR pb5cr
79		-# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
80		-# define PBxAP_VAL CFG_EBC_PB5AP
81		-# define PBxCR_VAL CFG_EBC_PB5CR
82		-# endif
83		-# endif
84		-# if (CFG_INIT_DCACHE_CS == 6)
85		-# define PBxAP pb6ap
86		-# define PBxCR pb6cr
87		-# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
88		-# define PBxAP_VAL CFG_EBC_PB6AP
89		-# define PBxCR_VAL CFG_EBC_PB6CR
90		-# endif
91		-# endif
92		-# if (CFG_INIT_DCACHE_CS == 7)
93		-# define PBxAP pb7ap
94		-# define PBxCR pb7cr
95		-# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
96		-# define PBxAP_VAL CFG_EBC_PB7AP
97		-# define PBxCR_VAL CFG_EBC_PB7CR
98		-# endif
99		-# endif
100		-#endif /* CFG_INIT_DCACHE_CS */
101		-
102	35	#ifndef CFG_PLL_RECONFIG
103	36	#define CFG_PLL_RECONFIG 0
104	37	#endif
...	...	@@ -352,24 +285,6 @@
352	285	#if defined(CONFIG_405GP)
353	286	uint pvr = get_pvr();
354	287	#endif
355		-
356		-#ifdef CFG_INIT_DCACHE_CS
357		- /*
358		- * Flush and invalidate dcache, then disable CS for temporary stack.
359		- * Afterwards, this CS can be used for other purposes
360		- */
361		- dcache_disable(); /* flush and invalidate dcache */
362		- mtebc(PBxAP, 0);
363		- mtebc(PBxCR, 0); /* disable CS for temporary stack */
364		-
365		-#if (defined(PBxAP_VAL) && defined(PBxCR_VAL))
366		- /*
367		- * Write new value into CS register
368		- */
369		- mtebc(PBxAP, PBxAP_VAL);
370		- mtebc(PBxCR, PBxCR_VAL);
371		-#endif
372		-#endif /* CFG_INIT_DCACHE_CS */
373	288
374	289	/*
375	290	* Write Ethernetaddress into on-chip register
	1	+/*
	2	+ * Copyright (c) 2008 Nuovation System Designs, LLC
	3	+ * Grant Erickson <gerickson@nuovations.com>
	4	+ *
	5	+ * (C) Copyright 2005-2007
	6	+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
	7	+ *
	8	+ * (C) Copyright 2002
	9	+ * Jun Gu, Artesyn Technology, jung@artesyncp.com
	10	+ *
	11	+ * (C) Copyright 2001
	12	+ * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
	13	+ *
	14	+ * See file CREDITS for list of people who contributed to this
	15	+ * project.
	16	+ *
	17	+ * This program is free software; you can redistribute it and/or
	18	+ * modify it under the terms of the GNU General Public License as
	19	+ * published by the Free Software Foundation; either version 2 of
	20	+ * the License, or (at your option) any later version.
	21	+ *
	22	+ * This program is distributed in the hope that it will abe useful,
	23	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	+ * GNU General Public License for more details.
	26	+ *
	27	+ * You should have received a copy of the GNU General Public License
	28	+ * along with this program; if not, write to the Free Software
	29	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	30	+ * MA 02111-1307 USA
	31	+ *
	32	+ * Description:
	33	+ * This file implements generic DRAM ECC initialization for
	34	+ * PowerPC processors using a SDRAM DDR/DDR2 controller,
	35	+ * including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and
	36	+ * 460EX/GT.
	37	+ */
	38	+
	39	+#include <common.h>
	40	+#include <ppc4xx.h>
	41	+#include <ppc_asm.tmpl>
	42	+#include <ppc_defs.h>
	43	+#include <asm/processor.h>
	44	+#include <asm/io.h>
	45	+
	46	+#include "ecc.h"
	47	+
	48	+#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
	49	+#if defined(CONFIG_DDR_ECC) \|\| defined(CONFIG_SDRAM_ECC)
	50	+/*
	51	+ * void ecc_init()
	52	+ *
	53	+ * Description:
	54	+ * This routine initializes a range of DRAM ECC memory with known
	55	+ * data and enables ECC checking.
	56	+ *
	57	+ * TO DO:
	58	+ * - Improve performance by utilizing cache.
	59	+ * - Further generalize to make usable by other 4xx variants (e.g.
	60	+ * 440EPx, et al).
	61	+ *
	62	+ * Input(s):
	63	+ * start - A pointer to the start of memory covered by ECC requiring
	64	+ * initialization.
	65	+ * size - The size, in bytes, of the memory covered by ECC requiring
	66	+ * initialization.
	67	+ *
	68	+ * Output(s):
	69	+ * start - A pointer to the start of memory covered by ECC with
	70	+ * CFG_ECC_PATTERN written to all locations and ECC data
	71	+ * primed.
	72	+ *
	73	+ * Returns:
	74	+ * N/A
	75	+ */
	76	+void ecc_init(unsigned long * const start, unsigned long size)
	77	+{
	78	+ const unsigned long pattern = CFG_ECC_PATTERN;
	79	+ unsigned * const end = (unsigned long * const)((long)start + size);
	80	+ unsigned long * current = start;
	81	+ unsigned long mcopt1;
	82	+ long increment;
	83	+
	84	+ if (start >= end)
	85	+ return;
	86	+
	87	+ mfsdram(SDRAM_MCOPT1, mcopt1);
	88	+
	89	+ /* Enable ECC generation without checking or reporting */
	90	+
	91	+ mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) \|
	92	+ SDRAM_MCOPT1_MCHK_GEN));
	93	+
	94	+ increment = sizeof(u32);
	95	+
	96	+#if defined(CONFIG_440)
	97	+ /*
	98	+ * Look at the geometry of SDRAM (data width) to determine whether we
	99	+ * can skip words when writing.
	100	+ */
	101	+
	102	+ if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) != SDRAM_MCOPT1_DMWD_32)
	103	+ increment = sizeof(u64);
	104	+#endif /* defined(CONFIG_440) */
	105	+
	106	+ while (current < end) {
	107	+ *current = pattern;
	108	+ current = (unsigned long *)((long)current + increment);
	109	+ }
	110	+
	111	+ /* Wait until the writes are finished. */
	112	+
	113	+ sync();
	114	+
	115	+ /* Enable ECC generation with checking and no reporting */
	116	+
	117	+ mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) \|
	118	+ SDRAM_MCOPT1_MCHK_CHK));
	119	+}
	120	+#endif /* defined(CONFIG_DDR_ECC) \|\| defined(CONFIG_SDRAM_ECC) */
	121	+#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
	1	+/*
	2	+ * Copyright (c) 2008 Nuovation System Designs, LLC
	3	+ * Grant Erickson <gerickson@nuovations.com>
	4	+ *
	5	+ * Copyright (c) 2007 DENX Software Engineering, GmbH
	6	+ * Stefan Roese <sr@denx.de>
	7	+ *
	8	+ * See file CREDITS for list of people who contributed to this
	9	+ * project.
	10	+ *
	11	+ * This program is free software; you can redistribute it and/or
	12	+ * modify it under the terms of the GNU General Public License as
	13	+ * published by the Free Software Foundation; either version 2 of
	14	+ * the License, or (at your option) any later version.
	15	+ *
	16	+ * This program is distributed in the hope that it will abe useful,
	17	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	+ * GNU General Public License for more details.
	20	+ *
	21	+ * You should have received a copy of the GNU General Public License
	22	+ * along with this program; if not, write to the Free Software
	23	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	+ * MA 02111-1307 USA
	25	+ *
	26	+ * Description:
	27	+ * This file implements ECC initialization for PowerPC processors
	28	+ * using the SDRAM DDR2 controller, including the 405EX(r),
	29	+ * 440SP(E), 460EX and 460GT.
	30	+ *
	31	+ */
	32	+
	33	+#ifndef _ECC_H_
	34	+#define _ECC_H_
	35	+
	36	+#if !defined(CFG_ECC_PATTERN)
	37	+#define CFG_ECC_PATTERN 0x00000000
	38	+#endif /* !defined(CFG_ECC_PATTERN) */
	39	+
	40	+extern void ecc_init(unsigned long * const start, unsigned long size);
	41	+
	42	+#endif /* _ECC_H_ */
...	...	@@ -31,6 +31,7 @@
31	31	#include <ppc4xx.h>
32	32	#include <asm/processor.h>
33	33	#include "sdram.h"
	34	+#include "ecc.h"
34	35
35	36	#ifdef CONFIG_SDRAM_BANK0
36	37
...	...	@@ -331,49 +332,6 @@
331	332	/* return the current value for TR1 */
332	333	*tr1_value = (first_good + last_bad) / 2;
333	334	}
334		-
335		-#ifdef CONFIG_SDRAM_ECC
336		-static void ecc_init(ulong start, ulong size)
337		-{
338		- ulong current_addr; /* current byte address */
339		- ulong end_addr; /* end of memory region */
340		- ulong addr_inc; /* address skip between writes */
341		- ulong cfg0_reg; /* for restoring ECC state */
342		-
343		- /*
344		- * TODO: Enable dcache before running this test (speedup)
345		- */
346		-
347		- mfsdram(mem_cfg0, cfg0_reg);
348		- mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) \| SDRAM_CFG0_MEMCHK_GEN);
349		-
350		- /*
351		- * look at geometry of SDRAM (data width) to determine whether we
352		- * can skip words when writing
353		- */
354		- if ((cfg0_reg & SDRAM_CFG0_DRAMWDTH) == SDRAM_CFG0_DRAMWDTH_32)
355		- addr_inc = 4;
356		- else
357		- addr_inc = 8;
358		-
359		- current_addr = start;
360		- end_addr = start + size;
361		-
362		- while (current_addr < end_addr) {
363		- ((ulong )current_addr) = 0x00000000;
364		- current_addr += addr_inc;
365		- }
366		-
367		- /*
368		- * TODO: Flush dcache and disable it again
369		- */
370		-
371		- /*
372		- * Enable ecc checking and parity errors
373		- */
374		- mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) \| SDRAM_CFG0_MEMCHK_CHK);
375		-}
376		-#endif
377	335
378	336	/*
379	337	* Autodetect onboard DDR SDRAM on 440 platforms
...	...	@@ -3,6 +3,8 @@
3	3	* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4	4	* Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5	5	* Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
	6	+ * Copyright (c) 2008 Nuovation System Designs, LLC
	7	+ * Grant Erickson <gerickson@nuovations.com>
6	8	*
7	9	* See file CREDITS for list of people who contributed to this
8	10	* project.
9	11
10	12
11	13
12	14
13	15
14	16
15	17
16	18
17	19
...	...	@@ -79,41 +81,124 @@
79	81	# if (CFG_INIT_DCACHE_CS == 0)
80	82	# define PBxAP pb0ap
81	83	# define PBxCR pb0cr
	84	+# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
	85	+# define PBxAP_VAL CFG_EBC_PB0AP
	86	+# define PBxCR_VAL CFG_EBC_PB0CR
	87	+# endif
82	88	# endif
83	89	# if (CFG_INIT_DCACHE_CS == 1)
84	90	# define PBxAP pb1ap
85	91	# define PBxCR pb1cr
	92	+# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
	93	+# define PBxAP_VAL CFG_EBC_PB1AP
	94	+# define PBxCR_VAL CFG_EBC_PB1CR
	95	+# endif
86	96	# endif
87	97	# if (CFG_INIT_DCACHE_CS == 2)
88	98	# define PBxAP pb2ap
89	99	# define PBxCR pb2cr
	100	+# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
	101	+# define PBxAP_VAL CFG_EBC_PB2AP
	102	+# define PBxCR_VAL CFG_EBC_PB2CR
	103	+# endif
90	104	# endif
91	105	# if (CFG_INIT_DCACHE_CS == 3)
92	106	# define PBxAP pb3ap
93	107	# define PBxCR pb3cr
	108	+# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
	109	+# define PBxAP_VAL CFG_EBC_PB3AP
	110	+# define PBxCR_VAL CFG_EBC_PB3CR
	111	+# endif
94	112	# endif
95	113	# if (CFG_INIT_DCACHE_CS == 4)
96	114	# define PBxAP pb4ap
97	115	# define PBxCR pb4cr
	116	+# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
	117	+# define PBxAP_VAL CFG_EBC_PB4AP
	118	+# define PBxCR_VAL CFG_EBC_PB4CR
	119	+# endif
98	120	# endif
99	121	# if (CFG_INIT_DCACHE_CS == 5)
100	122	# define PBxAP pb5ap
101	123	# define PBxCR pb5cr
	124	+# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
	125	+# define PBxAP_VAL CFG_EBC_PB5AP
	126	+# define PBxCR_VAL CFG_EBC_PB5CR
	127	+# endif
102	128	# endif
103	129	# if (CFG_INIT_DCACHE_CS == 6)
104	130	# define PBxAP pb6ap
105	131	# define PBxCR pb6cr
	132	+# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
	133	+# define PBxAP_VAL CFG_EBC_PB6AP
	134	+# define PBxCR_VAL CFG_EBC_PB6CR
	135	+# endif
106	136	# endif
107	137	# if (CFG_INIT_DCACHE_CS == 7)
108	138	# define PBxAP pb7ap
109	139	# define PBxCR pb7cr
	140	+# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
	141	+# define PBxAP_VAL CFG_EBC_PB7AP
	142	+# define PBxCR_VAL CFG_EBC_PB7CR
	143	+# endif
110	144	# endif
	145	+# ifndef PBxAP_VAL
	146	+# define PBxAP_VAL 0
	147	+# endif
	148	+# ifndef PBxCR_VAL
	149	+# define PBxCR_VAL 0
	150	+# endif
	151	+/*
	152	+ * Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB
	153	+ * used as temporary stack pointer for the primordial stack
	154	+ */
	155	+# ifndef CFG_INIT_DCACHE_PBxAR
	156	+# define CFG_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED \| \
	157	+ EBC_BXAP_TWT_ENCODE(7) \| \
	158	+ EBC_BXAP_BCE_DISABLE \| \
	159	+ EBC_BXAP_BCT_2TRANS \| \
	160	+ EBC_BXAP_CSN_ENCODE(0) \| \
	161	+ EBC_BXAP_OEN_ENCODE(0) \| \
	162	+ EBC_BXAP_WBN_ENCODE(0) \| \
	163	+ EBC_BXAP_WBF_ENCODE(0) \| \
	164	+ EBC_BXAP_TH_ENCODE(2) \| \
	165	+ EBC_BXAP_RE_DISABLED \| \
	166	+ EBC_BXAP_SOR_NONDELAYED \| \
	167	+ EBC_BXAP_BEM_WRITEONLY \| \
	168	+ EBC_BXAP_PEN_DISABLED)
	169	+# endif /* CFG_INIT_DCACHE_PBxAR */
	170	+# ifndef CFG_INIT_DCACHE_PBxCR
	171	+# define CFG_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR) \| \
	172	+ EBC_BXCR_BS_64MB \| \
	173	+ EBC_BXCR_BU_RW \| \
	174	+ EBC_BXCR_BW_16BIT)
	175	+# endif /* CFG_INIT_DCACHE_PBxCR */
	176	+# ifndef CFG_INIT_RAM_PATTERN
	177	+# define CFG_INIT_RAM_PATTERN 0xDEADDEAD
	178	+# endif
111	179	#endif /* CFG_INIT_DCACHE_CS */
112	180
113	181	#if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10)))
114	182	#error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END!
115	183	#endif
116	184
	185	+/*
	186	+ * Unless otherwise overriden, enable two 128MB cachable instruction regions
	187	+ * at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering
	188	+ * NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions.
	189	+ */
	190	+#if !defined(CFG_ICACHE_SACR_VALUE)
	191	+# define CFG_ICACHE_SACR_VALUE \
	192	+ (PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + ( 0 << 20)) \| \
	193	+ PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (128 << 20)) \| \
	194	+ PPC_128MB_SACR_VALUE(CFG_FLASH_BASE))
	195	+#endif /* !defined(CFG_ICACHE_SACR_VALUE) */
	196	+
	197	+#if !defined(CFG_DCACHE_SACR_VALUE)
	198	+# define CFG_DCACHE_SACR_VALUE \
	199	+ (0x00000000)
	200	+#endif /* !defined(CFG_DCACHE_SACR_VALUE) */
	201	+
117	202	#define function_prolog(func_name) .text; \
118	203	.align 2; \
119	204	.globl func_name; \
120	205
...	...	@@ -840,16 +925,16 @@
840	925	/* make sure above stores all comlete before going on */
841	926	sync
842	927
843		- /----------------------------------------------------------------------- /
844		- /* Enable two 128MB cachable regions. */
845		- /----------------------------------------------------------------------- /
846		- addis r1,r0,0xc000
847		- addi r1,r1,0x0001
848		- mticcr r1 /* instruction cache */
	928	+ /* Set-up icache cacheability. */
	929	+ lis r1, CFG_ICACHE_SACR_VALUE@h
	930	+ ori r1, r1, CFG_ICACHE_SACR_VALUE@l
	931	+ mticcr r1
	932	+ isync
849	933
850		- addis r1,r0,0x0000
851		- addi r1,r1,0x0000
852		- mtdccr r1 /* data cache */
	934	+ /* Set-up dcache cacheability. */
	935	+ lis r1, CFG_DCACHE_SACR_VALUE@h
	936	+ ori r1, r1, CFG_DCACHE_SACR_VALUE@l
	937	+ mtdccr r1
853	938
854	939	addis r1,r0,CFG_INIT_RAM_ADDR@h
855	940	ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
856	941
857	942
...	...	@@ -892,27 +977,20 @@
892	977	/* dbsr is cleared by setting bits to 1) */
893	978	mtdbsr r4 /* clear/reset the dbsr */
894	979
895		- /----------------------------------------------------------------------- /
896		- /* Invalidate I and D caches. Enable I cache for defined memory regions */
897		- /* to speed things up. Leave the D cache disabled for now. It will be */
898		- /* enabled/left disabled later based on user selected menu options. */
899		- /* Be aware that the I cache may be disabled later based on the menu */
900		- /* options as well. See miscLib/main.c. */
901		- /----------------------------------------------------------------------- /
	980	+ /* Invalidate the i- and d-caches. */
902	981	bl invalidate_icache
903	982	bl invalidate_dcache
904	983
905		- /----------------------------------------------------------------------- /
906		- /* Enable two 128MB cachable regions. */
907		- /----------------------------------------------------------------------- /
908		- lis r4,0xc000
909		- ori r4,r4,0x0001
910		- mticcr r4 /* instruction cache */
	984	+ /* Set-up icache cacheability. */
	985	+ lis r4, CFG_ICACHE_SACR_VALUE@h
	986	+ ori r4, r4, CFG_ICACHE_SACR_VALUE@l
	987	+ mticcr r4
911	988	isync
912	989
913		- lis r4,0x0000
914		- ori r4,r4,0x0000
915		- mtdccr r4 /* data cache */
	990	+ /* Set-up dcache cacheability. */
	991	+ lis r4, CFG_DCACHE_SACR_VALUE@h
	992	+ ori r4, r4, CFG_DCACHE_SACR_VALUE@l
	993	+ mtdccr r4
916	994
917	995	#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) \|\| defined(CONFIG_405EX)
918	996	/----------------------------------------------------------------------- /
...	...	@@ -922,9 +1000,9 @@
922	1000	#endif
923	1001	#if !(defined(CFG_INIT_DCACHE_CS) \|\| defined(CFG_TEMP_STACK_OCM))
924	1002	/*
925		- * Boards like the Kilauea (405EX) don't have OCM and can't use
926		- * DCache for init-ram. So setup stack here directly after the
927		- * SDRAM is initialized.
	1003	+ * For boards that don't have OCM and can't use the data cache
	1004	+ * for their primordial stack, setup stack here directly after the
	1005	+ * SDRAM is initialized in ext_bus_cntlr_init.
928	1006	*/
929	1007	lis r1, CFG_INIT_RAM_ADDR@h
930	1008	ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
931	1009
932	1010
933	1011
934	1012
935	1013
936	1014
937	1015
938	1016
939	1017
940	1018
...	...	@@ -1043,48 +1121,87 @@
1043	1121	/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
1044	1122	/----------------------------------------------------------------------- /
1045	1123	#ifdef CFG_INIT_DCACHE_CS
1046		- /----------------------------------------------------------------------- /
1047		- /* Memory Bank x (nothingness) initialization 1GB+64MEG */
1048		- /* used as temporary stack pointer for stage0 */
1049		- /----------------------------------------------------------------------- /
1050		- li r4,PBxAP
1051		- mtdcr ebccfga,r4
1052		- lis r4,0x0380
1053		- ori r4,r4,0x0480
1054		- mtdcr ebccfgd,r4
	1124	+ li r4, PBxAP
	1125	+ mtdcr ebccfga, r4
	1126	+ lis r4, CFG_INIT_DCACHE_PBxAR@h
	1127	+ ori r4, r4, CFG_INIT_DCACHE_PBxAR@l
	1128	+ mtdcr ebccfgd, r4
1055	1129
1056		- addi r4,0,PBxCR
1057		- mtdcr ebccfga,r4
1058		- lis r4,0x400D
1059		- ori r4,r4,0xa000
1060		- mtdcr ebccfgd,r4
	1130	+ addi r4, 0, PBxCR
	1131	+ mtdcr ebccfga, r4
	1132	+ lis r4, CFG_INIT_DCACHE_PBxCR@h
	1133	+ ori r4, r4, CFG_INIT_DCACHE_PBxCR@l
	1134	+ mtdcr ebccfgd, r4
1061	1135
1062		- /* turn on data cache for this region */
1063		- lis r4,0x0080
	1136	+ /*
	1137	+ * Enable the data cache for the 128MB storage access control region
	1138	+ * at CFG_INIT_RAM_ADDR.
	1139	+ */
	1140	+ mfdccr r4
	1141	+ oris r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
	1142	+ ori r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
1064	1143	mtdccr r4
1065	1144
1066		- /* set stack pointer and clear stack to known value */
	1145	+ /*
	1146	+ * Preallocate data cache lines to be used to avoid a subsequent
	1147	+ * cache miss and an ensuing machine check exception when exceptions
	1148	+ * are enabled.
	1149	+ */
	1150	+ li r0, 0
1067	1151
1068		- lis r1,CFG_INIT_RAM_ADDR@h
1069		- ori r1,r1,CFG_INIT_SP_OFFSET@l
	1152	+ lis r3, CFG_INIT_RAM_ADDR@h
	1153	+ ori r3, r3, CFG_INIT_RAM_ADDR@l
1070	1154
1071		- li r4,2048 /* we store 2048 words to stack */
	1155	+ lis r4, CFG_INIT_RAM_END@h
	1156	+ ori r4, r4, CFG_INIT_RAM_END@l
	1157	+
	1158	+ /*
	1159	+ * Convert the size, in bytes, to the number of cache lines/blocks
	1160	+ * to preallocate.
	1161	+ */
	1162	+ clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
	1163	+ srwi r5, r4, L1_CACHE_SHIFT
	1164	+ beq ..load_counter
	1165	+ addi r5, r5, 0x0001
	1166	+..load_counter:
	1167	+ mtctr r5
	1168	+
	1169	+ /* Preallocate the computed number of cache blocks. */
	1170	+..alloc_dcache_block:
	1171	+ dcba r0, r3
	1172	+ addi r3, r3, L1_CACHE_BYTES
	1173	+ bdnz ..alloc_dcache_block
	1174	+ sync
	1175	+
	1176	+ /*
	1177	+ * Load the initial stack pointer and data area and convert the size,
	1178	+ * in bytes, to the number of words to initialize to a known value.
	1179	+ */
	1180	+ lis r1, CFG_INIT_RAM_ADDR@h
	1181	+ ori r1, r1, CFG_INIT_SP_OFFSET@l
	1182	+
	1183	+ lis r4, (CFG_INIT_RAM_END >> 2)@h
	1184	+ ori r4, r4, (CFG_INIT_RAM_END >> 2)@l
1072	1185	mtctr r4
1073	1186
1074		- lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */
1075		- ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */
	1187	+ lis r2, CFG_INIT_RAM_ADDR@h
	1188	+ ori r2, r2, CFG_INIT_RAM_END@l
1076	1189
1077		- lis r4,0xdead /* we store 0xdeaddead in the stack */
1078		- ori r4,r4,0xdead
	1190	+ lis r4, CFG_INIT_RAM_PATTERN@h
	1191	+ ori r4, r4, CFG_INIT_RAM_PATTERN@l
1079	1192
1080	1193	..stackloop:
1081		- stwu r4,-4(r2)
	1194	+ stwu r4, -4(r2)
1082	1195	bdnz ..stackloop
1083	1196
1084		- li r0, 0 /* Make room for stack frame header and */
1085		- stwu r0, -4(r1) /* clear final stack frame so that */
1086		- stwu r0, -4(r1) /* stack backtraces terminate cleanly */
1087	1197	/*
	1198	+ * Make room for stack frame header and clear final stack frame so
	1199	+ * that stack backtraces terminate cleanly.
	1200	+ */
	1201	+ stwu r0, -4(r1)
	1202	+ stwu r0, -4(r1)
	1203	+
	1204	+ /*
1088	1205	* Set up a dummy frame to store reset vector as return address.
1089	1206	* this causes stack underflow to reset board.
1090	1207	*/
1091	1208
1092	1209
1093	1210
1094	1211
1095	1212
1096	1213
...	...	@@ -1328,34 +1445,73 @@
1328	1445	* This "function" does not return, instead it continues in RAM
1329	1446	* after relocating the monitor code.
1330	1447	*
1331		- * r3 = dest
1332		- * r4 = src
1333		- * r5 = length in bytes
1334		- * r6 = cachelinesize
	1448	+ * r3 = Relocated stack pointer
	1449	+ * r4 = Relocated global data pointer
	1450	+ * r5 = Relocated text pointer
1335	1451	*/
1336	1452	.globl relocate_code
1337	1453	relocate_code:
1338		-#ifdef CONFIG_4xx_DCACHE
	1454	+#if defined(CONFIG_4xx_DCACHE) \|\| defined(CFG_INIT_DCACHE_CS)
1339	1455	/*
1340		- * We need to flush the Init Data before the dcache will be
1341		- * invalidated
	1456	+ * We need to flush the initial global data (gd_t) before the dcache
	1457	+ * will be invalidated.
1342	1458	*/
1343	1459
1344		- /* save regs */
1345		- mr r9,r3
1346		- mr r10,r4
1347		- mr r11,r5
	1460	+ /* Save registers */
	1461	+ mr r9, r3
	1462	+ mr r10, r4
	1463	+ mr r11, r5
1348	1464
1349		- mr r3,r4
1350		- addi r4,r4,0x200 /* should be enough for init data */
	1465	+ /* Flush initial global data range */
	1466	+ mr r3, r4
	1467	+ addi r4, r4, CFG_GBL_DATA_SIZE@l
1351	1468	bl flush_dcache_range
1352	1469
1353		- /* restore regs */
1354		- mr r3,r9
1355		- mr r4,r10
1356		- mr r5,r11
1357		-#endif
	1470	+#if defined(CFG_INIT_DCACHE_CS)
	1471	+ /*
	1472	+ * Undo the earlier data cache set-up for the primordial stack and
	1473	+ * data area. First, invalidate the data cache and then disable data
	1474	+ * cacheability for that area. Finally, restore the EBC values, if
	1475	+ * any.
	1476	+ */
1358	1477
	1478	+ /* Invalidate the primordial stack and data area in cache */
	1479	+ lis r3, CFG_INIT_RAM_ADDR@h
	1480	+ ori r3, r3, CFG_INIT_RAM_ADDR@l
	1481	+
	1482	+ lis r4, CFG_INIT_RAM_END@h
	1483	+ ori r4, r4, CFG_INIT_RAM_END@l
	1484	+ add r4, r4, r3
	1485	+
	1486	+ bl invalidate_dcache_range
	1487	+
	1488	+ /* Disable cacheability for the region */
	1489	+ mfdccr r3
	1490	+ lis r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h
	1491	+ ori r4, r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l
	1492	+ and r3, r3, r4
	1493	+ mtdccr r3
	1494	+
	1495	+ /* Restore the EBC parameters */
	1496	+ li r3, PBxAP
	1497	+ mtdcr ebccfga, r3
	1498	+ lis r3, PBxAP_VAL@h
	1499	+ ori r3, r3, PBxAP_VAL@l
	1500	+ mtdcr ebccfgd, r3
	1501	+
	1502	+ li r3, PBxCR
	1503	+ mtdcr ebccfga, r3
	1504	+ lis r3, PBxCR_VAL@h
	1505	+ ori r3, r3, PBxCR_VAL@l
	1506	+ mtdcr ebccfgd, r3
	1507	+#endif /* defined(CFG_INIT_DCACHE_CS) */
	1508	+
	1509	+ /* Restore registers */
	1510	+ mr r3, r9
	1511	+ mr r4, r10
	1512	+ mr r5, r11
	1513	+#endif /* defined(CONFIG_4xx_DCACHE) \|\| defined(CFG_INIT_DCACHE_CS) */
	1514	+
1359	1515	#ifdef CFG_INIT_RAM_DCACHE
1360	1516	/*
1361	1517	* Unlock the previously locked d-cache
1362	1518
...	...	@@ -1396,13 +1552,13 @@
1396	1552	addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1397	1553	#else
1398	1554	addi r1,r0,0x0000 /* Default TLB entry is #0 */
1399		-#endif
	1555	+#endif /* CFG_TLB_FOR_BOOT_FLASH */
1400	1556	tlbre r0,r1,0x0002 /* Read contents */
1401	1557	ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1402	1558	tlbwe r0,r1,0x0002 /* Save it out */
1403	1559	sync
1404	1560	isync
1405		-#endif
	1561	+#endif /* defined(CONFIG_440EP) \|\| ... \|\| defined(CONFIG_460GT) */
1406	1562	mr r1, r3 /* Set new stack pointer */
1407	1563	mr r9, r4 /* Save copy of Init Data pointer */
1408	1564	mr r10, r5 /* Save copy of Destination Address */
...	...	@@ -1425,7 +1581,7 @@
1425	1581
1426	1582	/* First our own GOT */
1427	1583	add r14, r14, r15
1428		- /* the the one used by the C code */
	1584	+ /* then the one used by the C code */
1429	1585	add r30, r30, r15
1430	1586
1431	1587	/*
...	...	@@ -170,7 +170,7 @@
170	170
171	171	val = get_esr();
172	172
173		-#if !defined(CONFIG_440)
	173	+#if !defined(CONFIG_440) && !defined(CONFIG_405EX)
174	174	if (val& ESR_IMCP) {
175	175	printf("Instruction");
176	176	mtspr(ESR, val & ~ESR_IMCP);
...	...	@@ -179,7 +179,7 @@
179	179	}
180	180	printf(" machine check.\n");
181	181
182		-#elif defined(CONFIG_440)
	182	+#elif defined(CONFIG_440) \|\| defined(CONFIG_405EX)
183	183	if (val& ESR_IMCP){
184	184	printf("Instruction Synchronous Machine Check exception\n");
185	185	mtspr(SPRN_ESR, val & ~ESR_IMCP);
186	186
...	...	@@ -187,10 +187,15 @@
187	187	val = mfspr(MCSR);
188	188	if (val & MCSR_IB)
189	189	printf("Instruction Read PLB Error\n");
	190	+#if defined(CONFIG_440)
190	191	if (val & MCSR_DRB)
191	192	printf("Data Read PLB Error\n");
192	193	if (val & MCSR_DWB)
193	194	printf("Data Write PLB Error\n");
	195	+#else
	196	+ if (val & MCSR_DB)
	197	+ printf("Data PLB Error\n");
	198	+#endif
194	199	if (val & MCSR_TLBP)
195	200	printf("TLB Parity Error\n");
196	201	if (val & MCSR_ICP){
...	...	@@ -460,17 +460,19 @@
460	460	#define SPRN_PID2 0x27a /* Process ID Register 2 */
461	461	#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
462	462	#define SPRN_MCAR 0x23d /* Machine Check Address register */
463		-#ifdef CONFIG_440
464	463	#define MCSR_MCS 0x80000000 /* Machine Check Summary */
465	464	#define MCSR_IB 0x40000000 /* Instruction PLB Error */
	465	+#if defined(CONFIG_440)
466	466	#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
467	467	#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
	468	+#else
	469	+#define MCSR_DB 0x20000000 /* Data PLB Error */
	470	+#endif /* defined(CONFIG_440) */
468	471	#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
469	472	#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
470	473	#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
471	474	#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
472	475	#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
473		-#endif
474	476	#define ESR_ST 0x00800000 /* Store Operation */
475	477
476	478	#if defined(CONFIG_MPC86xx)