Commit c83a35f65250a8bdb519cb26680437e5c93d133d
Committed by
Michal Simek
Michal Simek
1 parent
e141652b9c
Exists in
master
and in
49 other branches
fpga: zynq: Correct fpga load when buf is not aligned
When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is not aligned, new_buf address became greater then buf_start address and the load_word loop corrupts bit file data. A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data before buf but permits to load correctly. Signed-off-by: Stany MARCEL <smarcel@novasys-ingenierie.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Showing 1 changed file with 10 additions and 0 deletions Inline Diff
drivers/fpga/zynqpl.c
| 1 | /* | 1 | /* |
| 2 | * (C) Copyright 2012-2013, Xilinx, Michal Simek | 2 | * (C) Copyright 2012-2013, Xilinx, Michal Simek |
| 3 | * | 3 | * |
| 4 | * (C) Copyright 2012 | 4 | * (C) Copyright 2012 |
| 5 | * Joe Hershberger <joe.hershberger@ni.com> | 5 | * Joe Hershberger <joe.hershberger@ni.com> |
| 6 | * | 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ | 8 | */ |
| 9 | 9 | ||
| 10 | #include <common.h> | 10 | #include <common.h> |
| 11 | #include <asm/io.h> | 11 | #include <asm/io.h> |
| 12 | #include <zynqpl.h> | 12 | #include <zynqpl.h> |
| 13 | #include <asm/sizes.h> | 13 | #include <asm/sizes.h> |
| 14 | #include <asm/arch/hardware.h> | 14 | #include <asm/arch/hardware.h> |
| 15 | #include <asm/arch/sys_proto.h> | 15 | #include <asm/arch/sys_proto.h> |
| 16 | 16 | ||
| 17 | #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 | 17 | #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 |
| 18 | #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 | 18 | #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 |
| 19 | #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 | 19 | #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 |
| 20 | #define DEVCFG_ISR_RX_FIFO_OV 0x00040000 | 20 | #define DEVCFG_ISR_RX_FIFO_OV 0x00040000 |
| 21 | #define DEVCFG_ISR_DMA_DONE 0x00002000 | 21 | #define DEVCFG_ISR_DMA_DONE 0x00002000 |
| 22 | #define DEVCFG_ISR_PCFG_DONE 0x00000004 | 22 | #define DEVCFG_ISR_PCFG_DONE 0x00000004 |
| 23 | #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000 | 23 | #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000 |
| 24 | #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000 | 24 | #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000 |
| 25 | #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 | 25 | #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 |
| 26 | #define DEVCFG_STATUS_PCFG_INIT 0x00000010 | 26 | #define DEVCFG_STATUS_PCFG_INIT 0x00000010 |
| 27 | #define DEVCFG_MCTRL_PCAP_LPBK 0x00000010 | 27 | #define DEVCFG_MCTRL_PCAP_LPBK 0x00000010 |
| 28 | #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 | 28 | #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 |
| 29 | #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001 | 29 | #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001 |
| 30 | 30 | ||
| 31 | #ifndef CONFIG_SYS_FPGA_WAIT | 31 | #ifndef CONFIG_SYS_FPGA_WAIT |
| 32 | #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ | 32 | #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ |
| 33 | #endif | 33 | #endif |
| 34 | 34 | ||
| 35 | #ifndef CONFIG_SYS_FPGA_PROG_TIME | 35 | #ifndef CONFIG_SYS_FPGA_PROG_TIME |
| 36 | #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ | 36 | #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ |
| 37 | #endif | 37 | #endif |
| 38 | 38 | ||
| 39 | int zynq_info(Xilinx_desc *desc) | 39 | int zynq_info(Xilinx_desc *desc) |
| 40 | { | 40 | { |
| 41 | return FPGA_SUCCESS; | 41 | return FPGA_SUCCESS; |
| 42 | } | 42 | } |
| 43 | 43 | ||
| 44 | #define DUMMY_WORD 0xffffffff | 44 | #define DUMMY_WORD 0xffffffff |
| 45 | 45 | ||
| 46 | /* Xilinx binary format header */ | 46 | /* Xilinx binary format header */ |
| 47 | static const u32 bin_format[] = { | 47 | static const u32 bin_format[] = { |
| 48 | DUMMY_WORD, /* Dummy words */ | 48 | DUMMY_WORD, /* Dummy words */ |
| 49 | DUMMY_WORD, | 49 | DUMMY_WORD, |
| 50 | DUMMY_WORD, | 50 | DUMMY_WORD, |
| 51 | DUMMY_WORD, | 51 | DUMMY_WORD, |
| 52 | DUMMY_WORD, | 52 | DUMMY_WORD, |
| 53 | DUMMY_WORD, | 53 | DUMMY_WORD, |
| 54 | DUMMY_WORD, | 54 | DUMMY_WORD, |
| 55 | DUMMY_WORD, | 55 | DUMMY_WORD, |
| 56 | 0x000000bb, /* Sync word */ | 56 | 0x000000bb, /* Sync word */ |
| 57 | 0x11220044, /* Sync word */ | 57 | 0x11220044, /* Sync word */ |
| 58 | DUMMY_WORD, | 58 | DUMMY_WORD, |
| 59 | DUMMY_WORD, | 59 | DUMMY_WORD, |
| 60 | 0xaa995566, /* Sync word */ | 60 | 0xaa995566, /* Sync word */ |
| 61 | }; | 61 | }; |
| 62 | 62 | ||
| 63 | #define SWAP_NO 1 | 63 | #define SWAP_NO 1 |
| 64 | #define SWAP_DONE 2 | 64 | #define SWAP_DONE 2 |
| 65 | 65 | ||
| 66 | /* | 66 | /* |
| 67 | * Load the whole word from unaligned buffer | 67 | * Load the whole word from unaligned buffer |
| 68 | * Keep in your mind that it is byte loading on little-endian system | 68 | * Keep in your mind that it is byte loading on little-endian system |
| 69 | */ | 69 | */ |
| 70 | static u32 load_word(const void *buf, u32 swap) | 70 | static u32 load_word(const void *buf, u32 swap) |
| 71 | { | 71 | { |
| 72 | u32 word = 0; | 72 | u32 word = 0; |
| 73 | u8 *bitc = (u8 *)buf; | 73 | u8 *bitc = (u8 *)buf; |
| 74 | int p; | 74 | int p; |
| 75 | 75 | ||
| 76 | if (swap == SWAP_NO) { | 76 | if (swap == SWAP_NO) { |
| 77 | for (p = 0; p < 4; p++) { | 77 | for (p = 0; p < 4; p++) { |
| 78 | word <<= 8; | 78 | word <<= 8; |
| 79 | word |= bitc[p]; | 79 | word |= bitc[p]; |
| 80 | } | 80 | } |
| 81 | } else { | 81 | } else { |
| 82 | for (p = 3; p >= 0; p--) { | 82 | for (p = 3; p >= 0; p--) { |
| 83 | word <<= 8; | 83 | word <<= 8; |
| 84 | word |= bitc[p]; | 84 | word |= bitc[p]; |
| 85 | } | 85 | } |
| 86 | } | 86 | } |
| 87 | 87 | ||
| 88 | return word; | 88 | return word; |
| 89 | } | 89 | } |
| 90 | 90 | ||
| 91 | static u32 check_header(const void *buf) | 91 | static u32 check_header(const void *buf) |
| 92 | { | 92 | { |
| 93 | u32 i, pattern; | 93 | u32 i, pattern; |
| 94 | int swap = SWAP_NO; | 94 | int swap = SWAP_NO; |
| 95 | u32 *test = (u32 *)buf; | 95 | u32 *test = (u32 *)buf; |
| 96 | 96 | ||
| 97 | debug("%s: Let's check bitstream header\n", __func__); | 97 | debug("%s: Let's check bitstream header\n", __func__); |
| 98 | 98 | ||
| 99 | /* Checking that passing bin is not a bitstream */ | 99 | /* Checking that passing bin is not a bitstream */ |
| 100 | for (i = 0; i < ARRAY_SIZE(bin_format); i++) { | 100 | for (i = 0; i < ARRAY_SIZE(bin_format); i++) { |
| 101 | pattern = load_word(&test[i], swap); | 101 | pattern = load_word(&test[i], swap); |
| 102 | 102 | ||
| 103 | /* | 103 | /* |
| 104 | * Bitstreams in binary format are swapped | 104 | * Bitstreams in binary format are swapped |
| 105 | * compare to regular bistream. | 105 | * compare to regular bistream. |
| 106 | * Do not swap dummy word but if swap is done assume | 106 | * Do not swap dummy word but if swap is done assume |
| 107 | * that parsing buffer is binary format | 107 | * that parsing buffer is binary format |
| 108 | */ | 108 | */ |
| 109 | if ((__swab32(pattern) != DUMMY_WORD) && | 109 | if ((__swab32(pattern) != DUMMY_WORD) && |
| 110 | (__swab32(pattern) == bin_format[i])) { | 110 | (__swab32(pattern) == bin_format[i])) { |
| 111 | pattern = __swab32(pattern); | 111 | pattern = __swab32(pattern); |
| 112 | swap = SWAP_DONE; | 112 | swap = SWAP_DONE; |
| 113 | debug("%s: data swapped - let's swap\n", __func__); | 113 | debug("%s: data swapped - let's swap\n", __func__); |
| 114 | } | 114 | } |
| 115 | 115 | ||
| 116 | debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i, | 116 | debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i, |
| 117 | (u32)&test[i], pattern, bin_format[i]); | 117 | (u32)&test[i], pattern, bin_format[i]); |
| 118 | if (pattern != bin_format[i]) { | 118 | if (pattern != bin_format[i]) { |
| 119 | debug("%s: Bitstream is not recognized\n", __func__); | 119 | debug("%s: Bitstream is not recognized\n", __func__); |
| 120 | return 0; | 120 | return 0; |
| 121 | } | 121 | } |
| 122 | } | 122 | } |
| 123 | debug("%s: Found bitstream header at %x %s swapinng\n", __func__, | 123 | debug("%s: Found bitstream header at %x %s swapinng\n", __func__, |
| 124 | (u32)buf, swap == SWAP_NO ? "without" : "with"); | 124 | (u32)buf, swap == SWAP_NO ? "without" : "with"); |
| 125 | 125 | ||
| 126 | return swap; | 126 | return swap; |
| 127 | } | 127 | } |
| 128 | 128 | ||
| 129 | static void *check_data(u8 *buf, size_t bsize, u32 *swap) | 129 | static void *check_data(u8 *buf, size_t bsize, u32 *swap) |
| 130 | { | 130 | { |
| 131 | u32 word, p = 0; /* possition */ | 131 | u32 word, p = 0; /* possition */ |
| 132 | 132 | ||
| 133 | /* Because buf doesn't need to be aligned let's read it by chars */ | 133 | /* Because buf doesn't need to be aligned let's read it by chars */ |
| 134 | for (p = 0; p < bsize; p++) { | 134 | for (p = 0; p < bsize; p++) { |
| 135 | word = load_word(&buf[p], SWAP_NO); | 135 | word = load_word(&buf[p], SWAP_NO); |
| 136 | debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]); | 136 | debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]); |
| 137 | 137 | ||
| 138 | /* Find the first bitstream dummy word */ | 138 | /* Find the first bitstream dummy word */ |
| 139 | if (word == DUMMY_WORD) { | 139 | if (word == DUMMY_WORD) { |
| 140 | debug("%s: Found dummy word at position %x/%x\n", | 140 | debug("%s: Found dummy word at position %x/%x\n", |
| 141 | __func__, p, (u32)&buf[p]); | 141 | __func__, p, (u32)&buf[p]); |
| 142 | *swap = check_header(&buf[p]); | 142 | *swap = check_header(&buf[p]); |
| 143 | if (*swap) { | 143 | if (*swap) { |
| 144 | /* FIXME add full bitstream checking here */ | 144 | /* FIXME add full bitstream checking here */ |
| 145 | return &buf[p]; | 145 | return &buf[p]; |
| 146 | } | 146 | } |
| 147 | } | 147 | } |
| 148 | /* Loop can be huge - support CTRL + C */ | 148 | /* Loop can be huge - support CTRL + C */ |
| 149 | if (ctrlc()) | 149 | if (ctrlc()) |
| 150 | return 0; | 150 | return 0; |
| 151 | } | 151 | } |
| 152 | return 0; | 152 | return 0; |
| 153 | } | 153 | } |
| 154 | 154 | ||
| 155 | 155 | ||
| 156 | int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) | 156 | int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) |
| 157 | { | 157 | { |
| 158 | unsigned long ts; /* Timestamp */ | 158 | unsigned long ts; /* Timestamp */ |
| 159 | u32 partialbit = 0; | 159 | u32 partialbit = 0; |
| 160 | u32 i, control, isr_status, status, swap, diff; | 160 | u32 i, control, isr_status, status, swap, diff; |
| 161 | u32 *buf_start; | 161 | u32 *buf_start; |
| 162 | 162 | ||
| 163 | /* Detect if we are going working with partial or full bitstream */ | 163 | /* Detect if we are going working with partial or full bitstream */ |
| 164 | if (bsize != desc->size) { | 164 | if (bsize != desc->size) { |
| 165 | printf("%s: Working with partial bitstream\n", __func__); | 165 | printf("%s: Working with partial bitstream\n", __func__); |
| 166 | partialbit = 1; | 166 | partialbit = 1; |
| 167 | } | 167 | } |
| 168 | 168 | ||
| 169 | buf_start = check_data((u8 *)buf, bsize, &swap); | 169 | buf_start = check_data((u8 *)buf, bsize, &swap); |
| 170 | if (!buf_start) | 170 | if (!buf_start) |
| 171 | return FPGA_FAIL; | 171 | return FPGA_FAIL; |
| 172 | 172 | ||
| 173 | /* Check if data is postpone from start */ | 173 | /* Check if data is postpone from start */ |
| 174 | diff = (u32)buf_start - (u32)buf; | 174 | diff = (u32)buf_start - (u32)buf; |
| 175 | if (diff) { | 175 | if (diff) { |
| 176 | printf("%s: Bitstream is not validated yet (diff %x)\n", | 176 | printf("%s: Bitstream is not validated yet (diff %x)\n", |
| 177 | __func__, diff); | 177 | __func__, diff); |
| 178 | return FPGA_FAIL; | 178 | return FPGA_FAIL; |
| 179 | } | 179 | } |
| 180 | 180 | ||
| 181 | if ((u32)buf < SZ_1M) { | 181 | if ((u32)buf < SZ_1M) { |
| 182 | printf("%s: Bitstream has to be placed up to 1MB (%x)\n", | 182 | printf("%s: Bitstream has to be placed up to 1MB (%x)\n", |
| 183 | __func__, (u32)buf); | 183 | __func__, (u32)buf); |
| 184 | return FPGA_FAIL; | 184 | return FPGA_FAIL; |
| 185 | } | 185 | } |
| 186 | 186 | ||
| 187 | if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { | 187 | if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { |
| 188 | u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); | 188 | u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); |
| 189 | 189 | ||
| 190 | /* | ||
| 191 | * This might be dangerous but permits to flash if | ||
| 192 | * ARCH_DMA_MINALIGN is greater than header size | ||
| 193 | */ | ||
| 194 | if (new_buf > buf_start) { | ||
| 195 | debug("%s: Aligned buffer is after buffer start\n", | ||
| 196 | __func__); | ||
| 197 | new_buf -= ARCH_DMA_MINALIGN; | ||
| 198 | } | ||
| 199 | |||
| 190 | printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, | 200 | printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, |
| 191 | (u32)buf_start, (u32)new_buf, swap); | 201 | (u32)buf_start, (u32)new_buf, swap); |
| 192 | 202 | ||
| 193 | for (i = 0; i < (bsize/4); i++) | 203 | for (i = 0; i < (bsize/4); i++) |
| 194 | new_buf[i] = load_word(&buf_start[i], swap); | 204 | new_buf[i] = load_word(&buf_start[i], swap); |
| 195 | 205 | ||
| 196 | swap = SWAP_DONE; | 206 | swap = SWAP_DONE; |
| 197 | buf = new_buf; | 207 | buf = new_buf; |
| 198 | } else if (swap != SWAP_DONE) { | 208 | } else if (swap != SWAP_DONE) { |
| 199 | /* For bitstream which are aligned */ | 209 | /* For bitstream which are aligned */ |
| 200 | u32 *new_buf = (u32 *)buf; | 210 | u32 *new_buf = (u32 *)buf; |
| 201 | 211 | ||
| 202 | printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, | 212 | printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, |
| 203 | swap); | 213 | swap); |
| 204 | 214 | ||
| 205 | for (i = 0; i < (bsize/4); i++) | 215 | for (i = 0; i < (bsize/4); i++) |
| 206 | new_buf[i] = load_word(&buf_start[i], swap); | 216 | new_buf[i] = load_word(&buf_start[i], swap); |
| 207 | 217 | ||
| 208 | swap = SWAP_DONE; | 218 | swap = SWAP_DONE; |
| 209 | } | 219 | } |
| 210 | 220 | ||
| 211 | /* Clear loopback bit */ | 221 | /* Clear loopback bit */ |
| 212 | clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); | 222 | clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); |
| 213 | 223 | ||
| 214 | if (!partialbit) { | 224 | if (!partialbit) { |
| 215 | zynq_slcr_devcfg_disable(); | 225 | zynq_slcr_devcfg_disable(); |
| 216 | 226 | ||
| 217 | /* Setting PCFG_PROG_B signal to high */ | 227 | /* Setting PCFG_PROG_B signal to high */ |
| 218 | control = readl(&devcfg_base->ctrl); | 228 | control = readl(&devcfg_base->ctrl); |
| 219 | writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); | 229 | writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); |
| 220 | /* Setting PCFG_PROG_B signal to low */ | 230 | /* Setting PCFG_PROG_B signal to low */ |
| 221 | writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); | 231 | writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); |
| 222 | 232 | ||
| 223 | /* Polling the PCAP_INIT status for Reset */ | 233 | /* Polling the PCAP_INIT status for Reset */ |
| 224 | ts = get_timer(0); | 234 | ts = get_timer(0); |
| 225 | while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { | 235 | while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { |
| 226 | if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { | 236 | if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { |
| 227 | printf("%s: Timeout wait for INIT to clear\n", | 237 | printf("%s: Timeout wait for INIT to clear\n", |
| 228 | __func__); | 238 | __func__); |
| 229 | return FPGA_FAIL; | 239 | return FPGA_FAIL; |
| 230 | } | 240 | } |
| 231 | } | 241 | } |
| 232 | 242 | ||
| 233 | /* Setting PCFG_PROG_B signal to high */ | 243 | /* Setting PCFG_PROG_B signal to high */ |
| 234 | writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); | 244 | writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); |
| 235 | 245 | ||
| 236 | /* Polling the PCAP_INIT status for Set */ | 246 | /* Polling the PCAP_INIT status for Set */ |
| 237 | ts = get_timer(0); | 247 | ts = get_timer(0); |
| 238 | while (!(readl(&devcfg_base->status) & | 248 | while (!(readl(&devcfg_base->status) & |
| 239 | DEVCFG_STATUS_PCFG_INIT)) { | 249 | DEVCFG_STATUS_PCFG_INIT)) { |
| 240 | if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { | 250 | if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { |
| 241 | printf("%s: Timeout wait for INIT to set\n", | 251 | printf("%s: Timeout wait for INIT to set\n", |
| 242 | __func__); | 252 | __func__); |
| 243 | return FPGA_FAIL; | 253 | return FPGA_FAIL; |
| 244 | } | 254 | } |
| 245 | } | 255 | } |
| 246 | } | 256 | } |
| 247 | 257 | ||
| 248 | isr_status = readl(&devcfg_base->int_sts); | 258 | isr_status = readl(&devcfg_base->int_sts); |
| 249 | 259 | ||
| 250 | /* Clear it all, so if Boot ROM comes back, it can proceed */ | 260 | /* Clear it all, so if Boot ROM comes back, it can proceed */ |
| 251 | writel(0xFFFFFFFF, &devcfg_base->int_sts); | 261 | writel(0xFFFFFFFF, &devcfg_base->int_sts); |
| 252 | 262 | ||
| 253 | if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) { | 263 | if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) { |
| 254 | debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status); | 264 | debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status); |
| 255 | 265 | ||
| 256 | /* If RX FIFO overflow, need to flush RX FIFO first */ | 266 | /* If RX FIFO overflow, need to flush RX FIFO first */ |
| 257 | if (isr_status & DEVCFG_ISR_RX_FIFO_OV) { | 267 | if (isr_status & DEVCFG_ISR_RX_FIFO_OV) { |
| 258 | writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl); | 268 | writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl); |
| 259 | writel(0xFFFFFFFF, &devcfg_base->int_sts); | 269 | writel(0xFFFFFFFF, &devcfg_base->int_sts); |
| 260 | } | 270 | } |
| 261 | return FPGA_FAIL; | 271 | return FPGA_FAIL; |
| 262 | } | 272 | } |
| 263 | 273 | ||
| 264 | status = readl(&devcfg_base->status); | 274 | status = readl(&devcfg_base->status); |
| 265 | 275 | ||
| 266 | debug("%s: Status = 0x%08X\n", __func__, status); | 276 | debug("%s: Status = 0x%08X\n", __func__, status); |
| 267 | 277 | ||
| 268 | if (status & DEVCFG_STATUS_DMA_CMD_Q_F) { | 278 | if (status & DEVCFG_STATUS_DMA_CMD_Q_F) { |
| 269 | debug("%s: Error: device busy\n", __func__); | 279 | debug("%s: Error: device busy\n", __func__); |
| 270 | return FPGA_FAIL; | 280 | return FPGA_FAIL; |
| 271 | } | 281 | } |
| 272 | 282 | ||
| 273 | debug("%s: Device ready\n", __func__); | 283 | debug("%s: Device ready\n", __func__); |
| 274 | 284 | ||
| 275 | if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) { | 285 | if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) { |
| 276 | if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) { | 286 | if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) { |
| 277 | /* Error state, transfer cannot occur */ | 287 | /* Error state, transfer cannot occur */ |
| 278 | debug("%s: ISR indicates error\n", __func__); | 288 | debug("%s: ISR indicates error\n", __func__); |
| 279 | return FPGA_FAIL; | 289 | return FPGA_FAIL; |
| 280 | } else { | 290 | } else { |
| 281 | /* Clear out the status */ | 291 | /* Clear out the status */ |
| 282 | writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); | 292 | writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); |
| 283 | } | 293 | } |
| 284 | } | 294 | } |
| 285 | 295 | ||
| 286 | if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) { | 296 | if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) { |
| 287 | /* Clear the count of completed DMA transfers */ | 297 | /* Clear the count of completed DMA transfers */ |
| 288 | writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status); | 298 | writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status); |
| 289 | } | 299 | } |
| 290 | 300 | ||
| 291 | debug("%s: Source = 0x%08X\n", __func__, (u32)buf); | 301 | debug("%s: Source = 0x%08X\n", __func__, (u32)buf); |
| 292 | debug("%s: Size = %zu\n", __func__, bsize); | 302 | debug("%s: Size = %zu\n", __func__, bsize); |
| 293 | 303 | ||
| 294 | /* flush(clean & invalidate) d-cache range buf */ | 304 | /* flush(clean & invalidate) d-cache range buf */ |
| 295 | flush_dcache_range((u32)buf, (u32)buf + | 305 | flush_dcache_range((u32)buf, (u32)buf + |
| 296 | roundup(bsize, ARCH_DMA_MINALIGN)); | 306 | roundup(bsize, ARCH_DMA_MINALIGN)); |
| 297 | 307 | ||
| 298 | /* Set up the transfer */ | 308 | /* Set up the transfer */ |
| 299 | writel((u32)buf | 1, &devcfg_base->dma_src_addr); | 309 | writel((u32)buf | 1, &devcfg_base->dma_src_addr); |
| 300 | writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); | 310 | writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); |
| 301 | writel(bsize >> 2, &devcfg_base->dma_src_len); | 311 | writel(bsize >> 2, &devcfg_base->dma_src_len); |
| 302 | writel(0, &devcfg_base->dma_dst_len); | 312 | writel(0, &devcfg_base->dma_dst_len); |
| 303 | 313 | ||
| 304 | isr_status = readl(&devcfg_base->int_sts); | 314 | isr_status = readl(&devcfg_base->int_sts); |
| 305 | 315 | ||
| 306 | /* Polling the PCAP_INIT status for Set */ | 316 | /* Polling the PCAP_INIT status for Set */ |
| 307 | ts = get_timer(0); | 317 | ts = get_timer(0); |
| 308 | while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { | 318 | while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { |
| 309 | if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { | 319 | if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { |
| 310 | debug("%s: Error: isr = 0x%08X\n", __func__, | 320 | debug("%s: Error: isr = 0x%08X\n", __func__, |
| 311 | isr_status); | 321 | isr_status); |
| 312 | debug("%s: Write count = 0x%08X\n", __func__, | 322 | debug("%s: Write count = 0x%08X\n", __func__, |
| 313 | readl(&devcfg_base->write_count)); | 323 | readl(&devcfg_base->write_count)); |
| 314 | debug("%s: Read count = 0x%08X\n", __func__, | 324 | debug("%s: Read count = 0x%08X\n", __func__, |
| 315 | readl(&devcfg_base->read_count)); | 325 | readl(&devcfg_base->read_count)); |
| 316 | 326 | ||
| 317 | return FPGA_FAIL; | 327 | return FPGA_FAIL; |
| 318 | } | 328 | } |
| 319 | if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { | 329 | if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { |
| 320 | printf("%s: Timeout wait for DMA to complete\n", | 330 | printf("%s: Timeout wait for DMA to complete\n", |
| 321 | __func__); | 331 | __func__); |
| 322 | return FPGA_FAIL; | 332 | return FPGA_FAIL; |
| 323 | } | 333 | } |
| 324 | isr_status = readl(&devcfg_base->int_sts); | 334 | isr_status = readl(&devcfg_base->int_sts); |
| 325 | } | 335 | } |
| 326 | 336 | ||
| 327 | debug("%s: DMA transfer is done\n", __func__); | 337 | debug("%s: DMA transfer is done\n", __func__); |
| 328 | 338 | ||
| 329 | /* Check FPGA configuration completion */ | 339 | /* Check FPGA configuration completion */ |
| 330 | ts = get_timer(0); | 340 | ts = get_timer(0); |
| 331 | while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { | 341 | while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { |
| 332 | if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { | 342 | if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { |
| 333 | printf("%s: Timeout wait for FPGA to config\n", | 343 | printf("%s: Timeout wait for FPGA to config\n", |
| 334 | __func__); | 344 | __func__); |
| 335 | return FPGA_FAIL; | 345 | return FPGA_FAIL; |
| 336 | } | 346 | } |
| 337 | isr_status = readl(&devcfg_base->int_sts); | 347 | isr_status = readl(&devcfg_base->int_sts); |
| 338 | } | 348 | } |
| 339 | 349 | ||
| 340 | debug("%s: FPGA config done\n", __func__); | 350 | debug("%s: FPGA config done\n", __func__); |
| 341 | 351 | ||
| 342 | /* Clear out the DMA status */ | 352 | /* Clear out the DMA status */ |
| 343 | writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); | 353 | writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); |
| 344 | 354 | ||
| 345 | if (!partialbit) | 355 | if (!partialbit) |
| 346 | zynq_slcr_devcfg_enable(); | 356 | zynq_slcr_devcfg_enable(); |
| 347 | 357 | ||
| 348 | return FPGA_SUCCESS; | 358 | return FPGA_SUCCESS; |
| 349 | } | 359 | } |
| 350 | 360 | ||
| 351 | int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize) | 361 | int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize) |
| 352 | { | 362 | { |
| 353 | return FPGA_FAIL; | 363 | return FPGA_FAIL; |
| 354 | } | 364 | } |
| 355 | 365 |