Eric Lee / smarc-uboot | Embedian Git Server

Commit c887d48017b0ae671344d8af3ebee48854c66b59

Authored by Ley Foon Tan 2017-04-26 02:44:41 +0800

Committed by Marek Vasut 2017-05-18 17:33:18 +0800

arm: socfpga: Add sdram header file for Arria 10

Add sdram header file for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>

Showing 1 changed file with 380 additions and 0 deletions Side-by-side Diff

arch/arm/mach-socfpga/include/mach/sdram_arria10.h

arch/arm/mach-socfpga/include/mach/sdram_arria10.h

Diff comments View file @ c887d48

	1	+/*
	2	+ * Copyright (C) 2015-2017 Intel Corporation <www.intel.com>
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0
	5	+ */
	6	+
	7	+#ifndef _SOCFPGA_SDRAM_ARRIA10_H_
	8	+#define _SOCFPGA_SDRAM_ARRIA10_H_
	9	+
	10	+#ifndef __ASSEMBLY__
	11	+
	12	+struct socfpga_ecc_hmc {
	13	+ u32 ip_rev_id;
	14	+ u32 _pad_0x4_0x7;
	15	+ u32 ddrioctrl;
	16	+ u32 ddrcalstat;
	17	+ u32 mpr_0beat1;
	18	+ u32 mpr_1beat1;
	19	+ u32 mpr_2beat1;
	20	+ u32 mpr_3beat1;
	21	+ u32 mpr_4beat1;
	22	+ u32 mpr_5beat1;
	23	+ u32 mpr_6beat1;
	24	+ u32 mpr_7beat1;
	25	+ u32 mpr_8beat1;
	26	+ u32 mpr_0beat2;
	27	+ u32 mpr_1beat2;
	28	+ u32 mpr_2beat2;
	29	+ u32 mpr_3beat2;
	30	+ u32 mpr_4beat2;
	31	+ u32 mpr_5beat2;
	32	+ u32 mpr_6beat2;
	33	+ u32 mpr_7beat2;
	34	+ u32 mpr_8beat2;
	35	+ u32 _pad_0x58_0x5f[2];
	36	+ u32 auto_precharge;
	37	+ u32 _pad_0x64_0xff[39];
	38	+ u32 eccctrl;
	39	+ u32 eccctrl2;
	40	+ u32 _pad_0x108_0x10f[2];
	41	+ u32 errinten;
	42	+ u32 errintens;
	43	+ u32 errintenr;
	44	+ u32 intmode;
	45	+ u32 intstat;
	46	+ u32 diaginttest;
	47	+ u32 modstat;
	48	+ u32 derraddra;
	49	+ u32 serraddra;
	50	+ u32 _pad_0x134_0x137;
	51	+ u32 autowb_corraddr;
	52	+ u32 serrcntreg;
	53	+ u32 autowb_drop_cntreg;
	54	+ u32 _pad_0x144_0x147;
	55	+ u32 ecc_reg2wreccdatabus;
	56	+ u32 ecc_rdeccdata2regbus;
	57	+ u32 ecc_reg2rdeccdatabus;
	58	+ u32 _pad_0x154_0x15f[3];
	59	+ u32 ecc_diagon;
	60	+ u32 ecc_decstat;
	61	+ u32 _pad_0x168_0x16f[2];
	62	+ u32 ecc_errgenaddr_0;
	63	+ u32 ecc_errgenaddr_1;
	64	+ u32 ecc_errgenaddr_2;
	65	+ u32 ecc_errgenaddr_3;
	66	+};
	67	+
	68	+struct socfpga_noc_ddr_scheduler {
	69	+ u32 ddr_t_main_scheduler_id_coreid;
	70	+ u32 ddr_t_main_scheduler_id_revisionid;
	71	+ u32 ddr_t_main_scheduler_ddrconf;
	72	+ u32 ddr_t_main_scheduler_ddrtiming;
	73	+ u32 ddr_t_main_scheduler_ddrmode;
	74	+ u32 ddr_t_main_scheduler_readlatency;
	75	+ u32 _pad_0x20_0x34[8];
	76	+ u32 ddr_t_main_scheduler_activate;
	77	+ u32 ddr_t_main_scheduler_devtodev;
	78	+};
	79	+
	80	+/*
	81	+ * OCRAM firewall
	82	+ */
	83	+struct socfpga_noc_fw_ocram {
	84	+ u32 enable;
	85	+ u32 enable_set;
	86	+ u32 enable_clear;
	87	+ u32 region0;
	88	+ u32 region1;
	89	+ u32 region2;
	90	+ u32 region3;
	91	+ u32 region4;
	92	+ u32 region5;
	93	+};
	94	+
	95	+/* for master such as MPU and FPGA */
	96	+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
	97	+ u32 enable;
	98	+ u32 enable_set;
	99	+ u32 enable_clear;
	100	+ u32 _pad_0xc_0xf;
	101	+ u32 mpuregion0addr;
	102	+ u32 mpuregion1addr;
	103	+ u32 mpuregion2addr;
	104	+ u32 mpuregion3addr;
	105	+ u32 fpga2sdram0region0addr;
	106	+ u32 fpga2sdram0region1addr;
	107	+ u32 fpga2sdram0region2addr;
	108	+ u32 fpga2sdram0region3addr;
	109	+ u32 fpga2sdram1region0addr;
	110	+ u32 fpga2sdram1region1addr;
	111	+ u32 fpga2sdram1region2addr;
	112	+ u32 fpga2sdram1region3addr;
	113	+ u32 fpga2sdram2region0addr;
	114	+ u32 fpga2sdram2region1addr;
	115	+ u32 fpga2sdram2region2addr;
	116	+ u32 fpga2sdram2region3addr;
	117	+};
	118	+
	119	+/* for L3 master */
	120	+struct socfpga_noc_fw_ddr_l3 {
	121	+ u32 enable;
	122	+ u32 enable_set;
	123	+ u32 enable_clear;
	124	+ u32 hpsregion0addr;
	125	+ u32 hpsregion1addr;
	126	+ u32 hpsregion2addr;
	127	+ u32 hpsregion3addr;
	128	+ u32 hpsregion4addr;
	129	+ u32 hpsregion5addr;
	130	+ u32 hpsregion6addr;
	131	+ u32 hpsregion7addr;
	132	+};
	133	+
	134	+struct socfpga_io48_mmr {
	135	+ u32 dbgcfg0;
	136	+ u32 dbgcfg1;
	137	+ u32 dbgcfg2;
	138	+ u32 dbgcfg3;
	139	+ u32 dbgcfg4;
	140	+ u32 dbgcfg5;
	141	+ u32 dbgcfg6;
	142	+ u32 reserve0;
	143	+ u32 reserve1;
	144	+ u32 reserve2;
	145	+ u32 ctrlcfg0;
	146	+ u32 ctrlcfg1;
	147	+ u32 ctrlcfg2;
	148	+ u32 ctrlcfg3;
	149	+ u32 ctrlcfg4;
	150	+ u32 ctrlcfg5;
	151	+ u32 ctrlcfg6;
	152	+ u32 ctrlcfg7;
	153	+ u32 ctrlcfg8;
	154	+ u32 ctrlcfg9;
	155	+ u32 dramtiming0;
	156	+ u32 dramodt0;
	157	+ u32 dramodt1;
	158	+ u32 sbcfg0;
	159	+ u32 sbcfg1;
	160	+ u32 sbcfg2;
	161	+ u32 sbcfg3;
	162	+ u32 sbcfg4;
	163	+ u32 sbcfg5;
	164	+ u32 sbcfg6;
	165	+ u32 sbcfg7;
	166	+ u32 caltiming0;
	167	+ u32 caltiming1;
	168	+ u32 caltiming2;
	169	+ u32 caltiming3;
	170	+ u32 caltiming4;
	171	+ u32 caltiming5;
	172	+ u32 caltiming6;
	173	+ u32 caltiming7;
	174	+ u32 caltiming8;
	175	+ u32 caltiming9;
	176	+ u32 caltiming10;
	177	+ u32 dramaddrw;
	178	+ u32 sideband0;
	179	+ u32 sideband1;
	180	+ u32 sideband2;
	181	+ u32 sideband3;
	182	+ u32 sideband4;
	183	+ u32 sideband5;
	184	+ u32 sideband6;
	185	+ u32 sideband7;
	186	+ u32 sideband8;
	187	+ u32 sideband9;
	188	+ u32 sideband10;
	189	+ u32 sideband11;
	190	+ u32 sideband12;
	191	+ u32 sideband13;
	192	+ u32 sideband14;
	193	+ u32 sideband15;
	194	+ u32 dramsts;
	195	+ u32 dbgdone;
	196	+ u32 dbgsignals;
	197	+ u32 dbgreset;
	198	+ u32 dbgmatch;
	199	+ u32 counter0mask;
	200	+ u32 counter1mask;
	201	+ u32 counter0match;
	202	+ u32 counter1match;
	203	+ u32 niosreserve0;
	204	+ u32 niosreserve1;
	205	+ u32 niosreserve2;
	206	+};
	207	+#endif /__ASSEMBLY__/
	208	+
	209	+#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000
	210	+#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_SHIFT 24
	211	+#define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK 0x00F80000
	212	+#define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_SHIFT 19
	213	+#define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK 0x0007C000
	214	+#define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_SHIFT 14
	215	+#define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK 0x00003E00
	216	+#define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT 9
	217	+#define IO48_MMR_CTRLCFG0_AC_POS_MASK 0x00000180
	218	+#define IO48_MMR_CTRLCFG0_AC_POS_SHIFT 7
	219	+#define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK 0x00000070
	220	+#define IO48_MMR_CTRLCFG0_DIM_TYPE_SHIFT 4
	221	+#define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK 0x0000000F
	222	+#define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT 0
	223	+
	224	+#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_DM BIT(30)
	225	+#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_DM BIT(29)
	226	+#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_DM BIT(28)
	227	+#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_DM BIT(27)
	228	+#define IO48_MMR_CTRLCFG1_CTRL_ENABLE_DM BIT(26)
	229	+#define IO48_MMR_CTRLCFG1_DQSTRK_EN BIT(25)
	230	+#define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK 0x01F80000
	231	+#define IO48_MMR_CTRLCFG1_STARVE_LIMIT_SHIFT 19
	232	+#define IO48_MMR_CTRLCFG1_REORDER_READ BIT(18)
	233	+#define IO48_MMR_CTRLCFG1_DBC3_REORDER_RDATA BIT(17)
	234	+#define IO48_MMR_CTRLCFG1_DBC2_REORDER_RDATA BIT(16)
	235	+#define IO48_MMR_CTRLCFG1_DBC1_REORDER_RDATA BIT(15)
	236	+#define IO48_MMR_CTRLCFG1_DBC0_REORDER_RDATA BIT(14)
	237	+#define IO48_MMR_CTRLCFG1_CTRL_REORDER_RDATA BIT(13)
	238	+#define IO48_MMR_CTRLCFG1_REORDER_DATA BIT(12)
	239	+#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_ECC BIT(11)
	240	+#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_ECC BIT(10)
	241	+#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_ECC BIT(9)
	242	+#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_ECC BIT(8)
	243	+#define IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC BIT(7)
	244	+#define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK 0x00000060
	245	+#define IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT 5
	246	+#define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_MASK 0x0000001F
	247	+#define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_SHIFT 0
	248	+
	249	+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_MASK 0x3F000000
	250	+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_SHIFT 24
	251	+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK 0x00FC0000
	252	+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT 18
	253	+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK 0x0003F000
	254	+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT 12
	255	+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_MASK 0x00000FC0
	256	+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_SHIFT 6
	257	+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK 0x0000003F
	258	+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_SHIFT 0
	259	+
	260	+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK 0x3F000000
	261	+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT 24
	262	+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK 0x00FC0000
	263	+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT 18
	264	+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_MASK 0x0003F000
	265	+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_SHIFT 12
	266	+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK 0x00000FC0
	267	+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT 6
	268	+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_MASK 0x0000003F
	269	+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_SHIFT 0
	270	+
	271	+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_MASK 0x3F000000
	272	+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_SHIFT 24
	273	+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_MASK 0x00FC0000
	274	+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_SHIFT 18
	275	+#define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_MASK 0x0003F000
	276	+#define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_SHIFT 12
	277	+#define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK 0x00000FC0
	278	+#define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT 6
	279	+#define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_MASK 0x0000003F
	280	+#define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_SHIFT 0
	281	+
	282	+#define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_MASK 0x3F000000
	283	+#define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_SHIFT 24
	284	+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_MASK 0x00FC0000
	285	+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_SHIFT 18
	286	+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK 0x0003F000
	287	+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT 12
	288	+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK 0x00000FC0
	289	+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT 6
	290	+#define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_MASK 0x0000003F
	291	+#define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_SHIFT 0
	292	+
	293	+#define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_MASK 0xFC000000
	294	+#define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_SHIFT 26
	295	+#define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_MASK 0x03FC0000
	296	+#define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_SHIFT 18
	297	+#define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_MASK 0x0003F000
	298	+#define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_SHIFT 12
	299	+#define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK 0x00000FC0
	300	+#define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT 6
	301	+#define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_MASK 0x0000003F
	302	+#define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_SHIFT 0
	303	+
	304	+#define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK 0x000000FF
	305	+#define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_SHIFT 0
	306	+
	307	+#define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK 0x00070000
	308	+#define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT 16
	309	+#define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK 0x0000C000
	310	+#define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT 14
	311	+#define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK 0x00003C00
	312	+#define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT 10
	313	+#define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK 0x000003E0
	314	+#define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT 5
	315	+#define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK 0x0000001F
	316	+#define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SHIFT 0
	317	+
	318	+#define ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK 0x00000003
	319	+
	320	+#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK BIT(0)
	321	+#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET_MSK BIT(1)
	322	+#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK BIT(0)
	323	+#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET_MSK BIT(1)
	324	+#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET_MSK BIT(16)
	325	+#define ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16)
	326	+#define ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK BIT(8)
	327	+#define ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK BIT(0)
	328	+#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK BIT(8)
	329	+#define ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK BIT(0)
	330	+
	331	+#define ALT_ECC_HMC_OCP_SERRCNTREG_VALUE 8
	332	+
	333	+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 0
	334	+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB 6
	335	+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB 12
	336	+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB 18
	337	+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB 21
	338	+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB 26
	339	+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB 31
	340	+
	341	+#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB 0
	342	+#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB 1
	343	+
	344	+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB 0
	345	+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB 4
	346	+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB 10
	347	+
	348	+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB 0
	349	+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB 2
	350	+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB 4
	351	+
	352	+#define ALT_NOC_FW_DDR_END_ADDR_LSB 16
	353	+#define ALT_NOC_FW_DDR_ADDR_MASK 0xFFFF
	354	+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK BIT(0)
	355	+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK BIT(1)
	356	+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK BIT(2)
	357	+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK BIT(3)
	358	+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK BIT(4)
	359	+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK BIT(5)
	360	+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK BIT(6)
	361	+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK BIT(7)
	362	+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK BIT(0)
	363	+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK BIT(1)
	364	+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK BIT(2)
	365	+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK BIT(3)
	366	+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK BIT(4)
	367	+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK BIT(5)
	368	+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK BIT(6)
	369	+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK BIT(7)
	370	+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK BIT(8)
	371	+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK BIT(9)
	372	+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK BIT(10)
	373	+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK BIT(11)
	374	+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK BIT(12)
	375	+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK BIT(13)
	376	+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK BIT(14)
	377	+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK BIT(15)
	378	+
	379	+#define ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK 0x0000003F
	380	+#endif /* _SOCFPGA_SDRAM_ARRIA10_H_ */