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Commit c8d4b2f8266fac1bcbf9101838939054b8a23011

Authored by Marek Vasut
1 parent e317de6b08
Exists in master and in 49 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: IXP: Remove the IXP architecture support 

The architecture is unmaintained and dead, remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michael Schwingen <michael@schwingen.org>
Cc: Tom Rini <trini@ti.com>

Showing 13 changed files with 0 additions and 1547 deletions Side-by-side Diff

... ... @@ -398,8 +398,6 @@
398 398  
399 399 LIST_pxa="$(targets_by_cpu pxa)"
400 400  
401   -LIST_ixp="$(targets_by_cpu ixp)"
402   -
403 401 #########################################################################
404 402 ## SPEAr Systems
405 403 #########################################################################
... ... @@ -141,7 +141,6 @@
141 141 /s3c24x0 Files specific to Samsung S3C24X0 CPUs
142 142 /arm926ejs Files specific to ARM 926 CPUs
143 143 /arm1136 Files specific to ARM 1136 CPUs
144   - /ixp Files specific to Intel XScale IXP CPUs
145 144 /pxa Files specific to Intel XScale PXA CPUs
146 145 /sa1100 Files specific to Intel StrongARM SA1100 CPUs
147 146 /lib Architecture specific library files
arch/arm/cpu/ixp/Makefile
View file @ c8d4b2f
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -extra-y = start.o
9   -
10   -obj-y += cpu.o
11   -obj-$(CONFIG_USE_IRQ) += interrupts.o
12   -obj-y += timer.o
arch/arm/cpu/ixp/config.mk
View file @ c8d4b2f
1   -#
2   -# (C) Copyright 2002
3   -# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4   -# Marius Groeger <mgroeger@sysgo.de>
5   -#
6   -# SPDX-License-Identifier: GPL-2.0+
7   -#
8   -
9   -BIG_ENDIAN = y
10   -
11   -PLATFORM_RELFLAGS += -mbig-endian
12   -
13   -PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
14   -
15   -PLATFORM_LDFLAGS += -EB
16   -USE_PRIVATE_LIBGCC = yes
arch/arm/cpu/ixp/cpu.c
View file @ c8d4b2f
1   -/*
2   - * (C) Copyright 2002
3   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4   - * Marius Groeger <mgroeger@sysgo.de>
5   - *
6   - * (C) Copyright 2002
7   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8   - * Alex Zuepke <azu@sysgo.de>
9   - *
10   - * SPDX-License-Identifier: GPL-2.0+
11   - */
12   -
13   -/*
14   - * CPU specific code
15   - */
16   -
17   -#include <common.h>
18   -#include <command.h>
19   -#include <netdev.h>
20   -#include <asm/arch/ixp425.h>
21   -#include <asm/system.h>
22   -
23   -static void cache_flush(void);
24   -
25   -#if defined(CONFIG_DISPLAY_CPUINFO)
26   -int print_cpuinfo (void)
27   -{
28   - unsigned long id;
29   - int speed = 0;
30   -
31   - asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
32   -
33   - puts("CPU: Intel IXP425 at ");
34   - switch ((id & 0x000003f0) >> 4) {
35   - case 0x1c:
36   - speed = 533;
37   - break;
38   -
39   - case 0x1d:
40   - speed = 400;
41   - break;
42   -
43   - case 0x1f:
44   - speed = 266;
45   - break;
46   - }
47   -
48   - if (speed)
49   - printf("%d MHz\n", speed);
50   - else
51   - puts("unknown revision\n");
52   -
53   - return 0;
54   -}
55   -#endif /* CONFIG_DISPLAY_CPUINFO */
56   -
57   -int cleanup_before_linux (void)
58   -{
59   - /*
60   - * this function is called just before we call linux
61   - * it prepares the processor for linux
62   - *
63   - * just disable everything that can disturb booting linux
64   - */
65   -
66   - disable_interrupts ();
67   -
68   - /* turn off I-cache */
69   - icache_disable();
70   - dcache_disable();
71   -
72   - /* flush I-cache */
73   - cache_flush();
74   -
75   - return 0;
76   -}
77   -
78   -/* flush I/D-cache */
79   -static void cache_flush (void)
80   -{
81   - unsigned long i = 0;
82   -
83   - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
84   -}
85   -
86   -/* FIXME */
87   -/*
88   -void pci_init(void)
89   -{
90   - return;
91   -}
92   -*/
93   -
94   -int cpu_eth_init(bd_t *bis)
95   -{
96   -#ifdef CONFIG_IXP4XX_NPE
97   - npe_initialize(bis);
98   -#endif
99   - return 0;
100   -}
arch/arm/cpu/ixp/interrupts.c
View file @ c8d4b2f
1   -/*
2   - * (C) Copyright 2006
3   - * Stefan Roese, DENX Software Engineering, sr@denx.de.
4   - *
5   - * (C) Copyright 2002
6   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7   - * Marius Groeger <mgroeger@sysgo.de>
8   - *
9   - * (C) Copyright 2002
10   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11   - * Alex Zuepke <azu@sysgo.de>
12   - *
13   - * SPDX-License-Identifier: GPL-2.0+
14   - */
15   -
16   -#include <common.h>
17   -#include <asm/arch/ixp425.h>
18   -#include <asm/proc-armv/ptrace.h>
19   -
20   -struct _irq_handler {
21   - void *m_data;
22   - void (*m_func)( void *data);
23   -};
24   -
25   -static struct _irq_handler IRQ_HANDLER[N_IRQS];
26   -
27   -static void default_isr(void *data)
28   -{
29   - printf("default_isr(): called for IRQ %d, Interrupt Status=%x PR=%x\n",
30   - (int)data, *IXP425_ICIP, *IXP425_ICIH);
31   -}
32   -
33   -static int next_irq(void)
34   -{
35   - return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1);
36   -}
37   -
38   -void do_irq (struct pt_regs *pt_regs)
39   -{
40   - int irq = next_irq();
41   -
42   - IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data);
43   -}
44   -
45   -void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data)
46   -{
47   - if (irq >= N_IRQS || !handle_irq)
48   - return;
49   -
50   - IRQ_HANDLER[irq].m_data = data;
51   - IRQ_HANDLER[irq].m_func = handle_irq;
52   -}
53   -
54   -int arch_interrupt_init (void)
55   -{
56   - int i;
57   -
58   - /* install default interrupt handlers */
59   - for (i = 0; i < N_IRQS; i++)
60   - irq_install_handler(i, default_isr, (void *)i);
61   -
62   - /* configure interrupts for IRQ mode */
63   - *IXP425_ICLR = 0x00000000;
64   -
65   - return (0);
66   -}
arch/arm/cpu/ixp/start.S
View file @ c8d4b2f
1   -/* vi: set ts=8 sw=8 noet: */
2   -/*
3   - * u-boot - Startup Code for XScale IXP
4   - *
5   - * Copyright (C) 2003 Kyle Harris <kharris@nexus-tech.net>
6   - *
7   - * Based on startup code example contained in the
8   - * Intel IXP4xx Programmer's Guide and past u-boot Start.S
9   - * samples.
10   - *
11   - * SPDX-License-Identifier: GPL-2.0+
12   - */
13   -
14   -#include <asm-offsets.h>
15   -#include <config.h>
16   -#include <version.h>
17   -#include <asm/arch/ixp425.h>
18   -
19   -#define MMU_Control_M 0x001 /* Enable MMU */
20   -#define MMU_Control_A 0x002 /* Enable address alignment faults */
21   -#define MMU_Control_C 0x004 /* Enable cache */
22   -#define MMU_Control_W 0x008 /* Enable write-buffer */
23   -#define MMU_Control_P 0x010 /* Compatability: 32 bit code */
24   -#define MMU_Control_D 0x020 /* Compatability: 32 bit data */
25   -#define MMU_Control_L 0x040 /* Compatability: */
26   -#define MMU_Control_B 0x080 /* Enable Big-Endian */
27   -#define MMU_Control_S 0x100 /* Enable system protection */
28   -#define MMU_Control_R 0x200 /* Enable ROM protection */
29   -#define MMU_Control_I 0x1000 /* Enable Instruction cache */
30   -#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
31   -#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
32   -
33   -
34   -/*
35   - * Macro definitions
36   - */
37   - /* Delay a bit */
38   - .macro DELAY_FOR cycles, reg0
39   - ldr \reg0, =\cycles
40   - subs \reg0, \reg0, #1
41   - subne pc, pc, #0xc
42   - .endm
43   -
44   - /* wait for coprocessor write complete */
45   - .macro CPWAIT reg
46   - mrc p15,0,\reg,c2,c0,0
47   - mov \reg,\reg
48   - sub pc,pc,#4
49   - .endm
50   -
51   -.globl _start
52   -_start:
53   - ldr pc, _reset
54   - ldr pc, _undefined_instruction
55   - ldr pc, _software_interrupt
56   - ldr pc, _prefetch_abort
57   - ldr pc, _data_abort
58   - ldr pc, _not_used
59   - ldr pc, _irq
60   - ldr pc, _fiq
61   -
62   -_reset: .word reset
63   -_undefined_instruction: .word undefined_instruction
64   -_software_interrupt: .word software_interrupt
65   -_prefetch_abort: .word prefetch_abort
66   -_data_abort: .word data_abort
67   -_not_used: .word not_used
68   -_irq: .word irq
69   -_fiq: .word fiq
70   -
71   - .balignl 16,0xdeadbeef
72   -
73   -
74   -/*
75   - * Startup Code (reset vector)
76   - *
77   - * do important init only if we don't start from memory!
78   - * - relocate armboot to ram
79   - * - setup stack
80   - * - jump to second stage
81   - */
82   -
83   -.globl _TEXT_BASE
84   -_TEXT_BASE:
85   -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
86   - .word CONFIG_SPL_TEXT_BASE
87   -#else
88   - .word CONFIG_SYS_TEXT_BASE
89   -#endif
90   -
91   -/*
92   - * These are defined in the board-specific linker script.
93   - * Subtracting _start from them lets the linker put their
94   - * relative position in the executable instead of leaving
95   - * them null.
96   - */
97   -.globl _bss_start_ofs
98   -_bss_start_ofs:
99   - .word __bss_start - _start
100   -
101   -.globl _bss_end_ofs
102   -_bss_end_ofs:
103   - .word __bss_end - _start
104   -
105   -.globl _end_ofs
106   -_end_ofs:
107   - .word _end - _start
108   -
109   -#ifdef CONFIG_USE_IRQ
110   -/* IRQ stack memory (calculated at run-time) */
111   -.globl IRQ_STACK_START
112   -IRQ_STACK_START:
113   - .word 0x0badc0de
114   -
115   -/* IRQ stack memory (calculated at run-time) */
116   -.globl FIQ_STACK_START
117   -FIQ_STACK_START:
118   - .word 0x0badc0de
119   -#endif
120   -
121   -/* IRQ stack memory (calculated at run-time) + 8 bytes */
122   -.globl IRQ_STACK_START_IN
123   -IRQ_STACK_START_IN:
124   - .word 0x0badc0de
125   -
126   -/*
127   - * the actual reset code
128   - */
129   -
130   -reset:
131   - /* disable mmu, set big-endian */
132   - mov r0, #0xf8
133   - mcr p15, 0, r0, c1, c0, 0
134   - CPWAIT r0
135   -
136   - /* invalidate I & D caches & BTB */
137   - mcr p15, 0, r0, c7, c7, 0
138   - CPWAIT r0
139   -
140   - /* invalidate I & Data TLB */
141   - mcr p15, 0, r0, c8, c7, 0
142   - CPWAIT r0
143   -
144   - /* drain write and fill buffers */
145   - mcr p15, 0, r0, c7, c10, 4
146   - CPWAIT r0
147   -
148   - /* disable write buffer coalescing */
149   - mrc p15, 0, r0, c1, c0, 1
150   - orr r0, r0, #1
151   - mcr p15, 0, r0, c1, c0, 1
152   - CPWAIT r0
153   -
154   - /* set EXP CS0 to the optimum timing */
155   - ldr r1, =CONFIG_SYS_EXP_CS0
156   - ldr r2, =IXP425_EXP_CS0
157   - str r1, [r2]
158   -
159   - /* make sure flash is visible at 0 */
160   - mov r1, #CONFIG_SYS_SDR_CONFIG
161   - ldr r2, =IXP425_SDR_CONFIG
162   - str r1, [r2]
163   -
164   - /* disable refresh cycles */
165   - mov r1, #0
166   - ldr r3, =IXP425_SDR_REFRESH
167   - str r1, [r3]
168   -
169   - /* send nop command */
170   - mov r1, #3
171   - ldr r4, =IXP425_SDR_IR
172   - str r1, [r4]
173   - DELAY_FOR 0x4000, r0
174   -
175   - /* set SDRAM internal refresh val */
176   - ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
177   - str r1, [r3]
178   - DELAY_FOR 0x4000, r0
179   -
180   - /* send precharge-all command to close all open banks */
181   - mov r1, #2
182   - str r1, [r4]
183   - DELAY_FOR 0x4000, r0
184   -
185   - /* provide 8 auto-refresh cycles */
186   - mov r1, #4
187   - mov r5, #8
188   -111: str r1, [r4]
189   - DELAY_FOR 0x100, r0
190   - subs r5, r5, #1
191   - bne 111b
192   -
193   - /* set mode register in sdram */
194   - mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
195   - str r1, [r4]
196   - DELAY_FOR 0x4000, r0
197   -
198   - /* send normal operation command */
199   - mov r1, #6
200   - str r1, [r4]
201   - DELAY_FOR 0x4000, r0
202   -
203   - /* invalidate I & D caches & BTB */
204   - mcr p15, 0, r0, c7, c7, 0
205   - CPWAIT r0
206   -
207   - /* invalidate I & Data TLB */
208   - mcr p15, 0, r0, c8, c7, 0
209   - CPWAIT r0
210   -
211   - /* drain write and fill buffers */
212   - mcr p15, 0, r0, c7, c10, 4
213   - CPWAIT r0
214   -
215   - /* remove flash mirror at 0x00000000 */
216   - ldr r2, =IXP425_EXP_CFG0
217   - ldr r1, [r2]
218   - bic r1, r1, #0x80000000
219   - str r1, [r2]
220   -
221   - /* invalidate I & Data TLB */
222   - mcr p15, 0, r0, c8, c7, 0
223   - CPWAIT r0
224   -
225   - /* enable I cache */
226   - mrc p15, 0, r0, c1, c0, 0
227   - orr r0, r0, #MMU_Control_I
228   - mcr p15, 0, r0, c1, c0, 0
229   - CPWAIT r0
230   -
231   - mrs r0,cpsr /* set the cpu to SVC32 mode */
232   - bic r0,r0,#0x1f /* (superviser mode, M=10011) */
233   - orr r0,r0,#0x13
234   - msr cpsr,r0
235   -
236   - bl _main
237   -
238   -/*------------------------------------------------------------------------------*/
239   -
240   - .globl c_runtime_cpu_setup
241   -c_runtime_cpu_setup:
242   -
243   - bx lr
244   -
245   -/****************************************************************************/
246   -/* */
247   -/* Interrupt handling */
248   -/* */
249   -/****************************************************************************/
250   -
251   -/* IRQ stack frame */
252   -
253   -#define S_FRAME_SIZE 72
254   -
255   -#define S_OLD_R0 68
256   -#define S_PSR 64
257   -#define S_PC 60
258   -#define S_LR 56
259   -#define S_SP 52
260   -
261   -#define S_IP 48
262   -#define S_FP 44
263   -#define S_R10 40
264   -#define S_R9 36
265   -#define S_R8 32
266   -#define S_R7 28
267   -#define S_R6 24
268   -#define S_R5 20
269   -#define S_R4 16
270   -#define S_R3 12
271   -#define S_R2 8
272   -#define S_R1 4
273   -#define S_R0 0
274   -
275   -#define MODE_SVC 0x13
276   -
277   - /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
278   -
279   - .macro bad_save_user_regs
280   - sub sp, sp, #S_FRAME_SIZE
281   - stmia sp, {r0 - r12} /* Calling r0-r12 */
282   - add r8, sp, #S_PC
283   -
284   - ldr r2, IRQ_STACK_START_IN
285   - ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
286   - add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
287   -
288   - add r5, sp, #S_SP
289   - mov r1, lr
290   - stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
291   - mov r0, sp
292   - .endm
293   -
294   -
295   - /* use irq_save_user_regs / irq_restore_user_regs for */
296   - /* IRQ/FIQ handling */
297   -
298   - .macro irq_save_user_regs
299   - sub sp, sp, #S_FRAME_SIZE
300   - stmia sp, {r0 - r12} /* Calling r0-r12 */
301   - add r8, sp, #S_PC
302   - stmdb r8, {sp, lr}^ /* Calling SP, LR */
303   - str lr, [r8, #0] /* Save calling PC */
304   - mrs r6, spsr
305   - str r6, [r8, #4] /* Save CPSR */
306   - str r0, [r8, #8] /* Save OLD_R0 */
307   - mov r0, sp
308   - .endm
309   -
310   - .macro irq_restore_user_regs
311   - ldmia sp, {r0 - lr}^ @ Calling r0 - lr
312   - mov r0, r0
313   - ldr lr, [sp, #S_PC] @ Get PC
314   - add sp, sp, #S_FRAME_SIZE
315   - subs pc, lr, #4 @ return & move spsr_svc into cpsr
316   - .endm
317   -
318   - .macro get_bad_stack
319   - ldr r13, IRQ_STACK_START_IN @ setup our mode stack
320   -
321   - str lr, [r13] @ save caller lr / spsr
322   - mrs lr, spsr
323   - str lr, [r13, #4]
324   -
325   - mov r13, #MODE_SVC @ prepare SVC-Mode
326   - msr spsr_c, r13
327   - mov lr, pc
328   - movs pc, lr
329   - .endm
330   -
331   - .macro get_irq_stack @ setup IRQ stack
332   - ldr sp, IRQ_STACK_START
333   - .endm
334   -
335   - .macro get_fiq_stack @ setup FIQ stack
336   - ldr sp, FIQ_STACK_START
337   - .endm
338   -
339   -
340   -/****************************************************************************/
341   -/* */
342   -/* exception handlers */
343   -/* */
344   -/****************************************************************************/
345   -
346   - .align 5
347   -undefined_instruction:
348   - get_bad_stack
349   - bad_save_user_regs
350   - bl do_undefined_instruction
351   -
352   - .align 5
353   -software_interrupt:
354   - get_bad_stack
355   - bad_save_user_regs
356   - bl do_software_interrupt
357   -
358   - .align 5
359   -prefetch_abort:
360   - get_bad_stack
361   - bad_save_user_regs
362   - bl do_prefetch_abort
363   -
364   - .align 5
365   -data_abort:
366   - get_bad_stack
367   - bad_save_user_regs
368   - bl do_data_abort
369   -
370   - .align 5
371   -not_used:
372   - get_bad_stack
373   - bad_save_user_regs
374   - bl do_not_used
375   -
376   -#ifdef CONFIG_USE_IRQ
377   -
378   - .align 5
379   -irq:
380   - get_irq_stack
381   - irq_save_user_regs
382   - bl do_irq
383   - irq_restore_user_regs
384   -
385   - .align 5
386   -fiq:
387   - get_fiq_stack
388   - irq_save_user_regs /* someone ought to write a more */
389   - bl do_fiq /* effiction fiq_save_user_regs */
390   - irq_restore_user_regs
391   -
392   -#else
393   -
394   - .align 5
395   -irq:
396   - get_bad_stack
397   - bad_save_user_regs
398   - bl do_irq
399   -
400   - .align 5
401   -fiq:
402   - get_bad_stack
403   - bad_save_user_regs
404   - bl do_fiq
405   -
406   -#endif
407   -
408   -/****************************************************************************/
409   -/* */
410   -/* Reset function: Use Watchdog to reset */
411   -/* */
412   -/****************************************************************************/
413   -
414   - .align 5
415   -.globl reset_cpu
416   -
417   -reset_cpu:
418   - ldr r1, =0x482e
419   - ldr r2, =IXP425_OSWK
420   - str r1, [r2]
421   - ldr r1, =0x0fff
422   - ldr r2, =IXP425_OSWT
423   - str r1, [r2]
424   - ldr r1, =0x5
425   - ldr r2, =IXP425_OSWE
426   - str r1, [r2]
427   - b reset_endless
428   -
429   -reset_endless:
430   - b reset_endless
arch/arm/cpu/ixp/timer.c
View file @ c8d4b2f
1   -/*
2   - * (C) Copyright 2010
3   - * Michael Schwingen, michael@schwingen.org
4   - *
5   - * (C) Copyright 2006
6   - * Stefan Roese, DENX Software Engineering, sr@denx.de.
7   - *
8   - * (C) Copyright 2002
9   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10   - * Marius Groeger <mgroeger@sysgo.de>
11   - *
12   - * (C) Copyright 2002
13   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14   - * Alex Zuepke <azu@sysgo.de>
15   - *
16   - * SPDX-License-Identifier: GPL-2.0+
17   - */
18   -
19   -#include <common.h>
20   -#include <asm/arch/ixp425.h>
21   -#include <asm/io.h>
22   -#include <div64.h>
23   -
24   -DECLARE_GLOBAL_DATA_PTR;
25   -
26   -/*
27   - * The IXP42x time-stamp timer runs at 2*OSC_IN (66.666MHz when using a
28   - * 33.333MHz crystal).
29   - */
30   -static inline unsigned long long tick_to_time(unsigned long long tick)
31   -{
32   - tick *= CONFIG_SYS_HZ;
33   - do_div(tick, CONFIG_IXP425_TIMER_CLK);
34   - return tick;
35   -}
36   -
37   -static inline unsigned long long time_to_tick(unsigned long long time)
38   -{
39   - time *= CONFIG_IXP425_TIMER_CLK;
40   - do_div(time, CONFIG_SYS_HZ);
41   - return time;
42   -}
43   -
44   -static inline unsigned long long us_to_tick(unsigned long long us)
45   -{
46   - us = us * CONFIG_IXP425_TIMER_CLK + 999999;
47   - do_div(us, 1000000);
48   - return us;
49   -}
50   -
51   -unsigned long long get_ticks(void)
52   -{
53   - ulong now = readl(IXP425_OSTS_B);
54   -
55   - if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) {
56   - /* rollover of timestamp timer register */
57   - gd->arch.timestamp += (0xFFFFFFFF - gd->arch.lastinc) + now + 1;
58   - writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
59   - } else {
60   - /* move stamp forward with absolut diff ticks */
61   - gd->arch.timestamp += (now - gd->arch.lastinc);
62   - }
63   - gd->arch.lastinc = now;
64   - return gd->arch.timestamp;
65   -}
66   -
67   -
68   -void reset_timer_masked(void)
69   -{
70   - /* capture current timestamp counter */
71   - gd->arch.lastinc = readl(IXP425_OSTS_B);
72   - /* start "advancing" time stamp from 0 */
73   - gd->arch.timestamp = 0;
74   -}
75   -
76   -ulong get_timer_masked(void)
77   -{
78   - return tick_to_time(get_ticks());
79   -}
80   -
81   -ulong get_timer(ulong base)
82   -{
83   - return get_timer_masked() - base;
84   -}
85   -
86   -/* delay x useconds AND preserve advance timestamp value */
87   -void __udelay(unsigned long usec)
88   -{
89   - unsigned long long tmp;
90   -
91   - tmp = get_ticks() + us_to_tick(usec);
92   -
93   - while (get_ticks() < tmp)
94   - ;
95   -}
96   -
97   -int timer_init(void)
98   -{
99   - writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
100   - return 0;
101   -}
arch/arm/cpu/ixp/u-boot.lds
View file @ c8d4b2f
1   -/*
2   - * (C) Copyright 2000-2006
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
9   -OUTPUT_ARCH(arm)
10   -ENTRY(_start)
11   -SECTIONS
12   -{
13   - . = 0x00000000;
14   -
15   - . = ALIGN(4);
16   - .text :
17   - {
18   - *(.__image_copy_start)
19   - arch/arm/cpu/ixp/start.o(.text*)
20   - *(.text*)
21   - }
22   -
23   - . = ALIGN(4);
24   - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
25   -
26   - . = ALIGN(4);
27   - .data : {
28   - *(.data*)
29   - }
30   -
31   - . = ALIGN(4);
32   -
33   - . = .;
34   -
35   - . = ALIGN(4);
36   - .u_boot_list : {
37   - KEEP(*(SORT(.u_boot_list*)));
38   - }
39   -
40   - . = ALIGN(4);
41   -
42   - .image_copy_end :
43   - {
44   - *(.__image_copy_end)
45   - }
46   -
47   - .rel_dyn_start :
48   - {
49   - *(.__rel_dyn_start)
50   - }
51   -
52   - .rel.dyn : {
53   - *(.rel*)
54   - }
55   -
56   - .rel_dyn_end :
57   - {
58   - *(.__rel_dyn_end)
59   - }
60   -
61   - _end = .;
62   -
63   -/*
64   - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
65   - * __bss_base and __bss_limit are for linker only (overlay ordering)
66   - */
67   -
68   - .bss_start __rel_dyn_start (OVERLAY) : {
69   - KEEP(*(.__bss_start));
70   - __bss_base = .;
71   - }
72   -
73   - .bss __bss_base (OVERLAY) : {
74   - *(.bss*)
75   - . = ALIGN(4);
76   - __bss_limit = .;
77   - }
78   - .bss_end __bss_limit (OVERLAY) : {
79   - KEEP(*(.__bss_end));
80   - }
81   -
82   - .dynsym _end : { *(.dynsym) }
83   - .dynbss : { *(.dynbss) }
84   - .dynstr : { *(.dynstr*) }
85   - .dynamic : { *(.dynamic*) }
86   - .hash : { *(.hash*) }
87   - .plt : { *(.plt*) }
88   - .interp : { *(.interp*) }
89   - .gnu : { *(.gnu*) }
90   - .ARM.exidx : { *(.ARM.exidx*) }
91   -}
arch/arm/include/asm/arch-ixp/ixp425.h
View file @ c8d4b2f
1   -/*
2   - * include/asm-arm/arch-ixp425/ixp425.h
3   - *
4   - * Register definitions for IXP425
5   - *
6   - * Copyright (C) 2002 Intel Corporation.
7   - *
8   - * This program is free software; you can redistribute it and/or modify
9   - * it under the terms of the GNU General Public License version 2 as
10   - * published by the Free Software Foundation.
11   - *
12   - */
13   -
14   -#ifndef _ASM_ARM_IXP425_H_
15   -#define _ASM_ARM_IXP425_H_
16   -
17   -#define BIT(x) (1<<(x))
18   -
19   -/* FIXME: Only this does work for u-boot... find out why... [RS] */
20   -#define UBOOT_REG_FIX 1
21   -#ifdef UBOOT_REG_FIX
22   -# undef io_p2v
23   -# undef __REG
24   -# ifndef __ASSEMBLY__
25   -# define io_p2v(PhAdd) (PhAdd)
26   -# define __REG(x) (*((volatile u32 *)io_p2v(x)))
27   -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
28   -# else
29   -# define __REG(x) (x)
30   -# endif
31   -#endif /* UBOOT_REG_FIX */
32   -
33   -/*
34   - *
35   - * IXP425 Memory map:
36   - *
37   - * Phy Phy Size Map Size Virt Description
38   - * =========================================================================
39   - *
40   - * 0x00000000 0x10000000 SDRAM 1
41   - *
42   - * 0x10000000 0x10000000 SDRAM 2
43   - *
44   - * 0x20000000 0x10000000 SDRAM 3
45   - *
46   - * 0x30000000 0x10000000 SDRAM 4
47   - *
48   - * The above four are aliases to the same memory location (0x00000000)
49   - *
50   - * 0x48000000 0x4000000 PCI Memory
51   - *
52   - * 0x50000000 0x10000000 Not Mapped EXP BUS
53   - *
54   - * 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr
55   - *
56   - * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG
57   - *
58   - * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG
59   - *
60   - * 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL
61   - *
62   - * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG
63   - */
64   -
65   -/*
66   - * SDRAM
67   - */
68   -#define IXP425_SDRAM_BASE (0x00000000)
69   -#define IXP425_SDRAM_BASE_ALT (0x10000000)
70   -
71   -
72   -/*
73   - * PCI Configuration space
74   - */
75   -#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000)
76   -#define IXP425_PCI_CFG_REGION_SIZE (0x00001000)
77   -
78   -/*
79   - * Expansion BUS Configuration registers
80   - */
81   -#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000)
82   -#define IXP425_EXP_CFG_REGION_SIZE (0x00001000)
83   -
84   -/*
85   - * Peripheral space
86   - */
87   -#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000)
88   -#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000)
89   -
90   -/*
91   - * SDRAM configuration registers
92   - */
93   -#define IXP425_SDRAM_CFG_BASE_PHYS (0xCC000000)
94   -
95   -/*
96   - * Q Manager space .. not static mapped
97   - */
98   -#define IXP425_QMGR_BASE_PHYS (0x60000000)
99   -#define IXP425_QMGR_REGION_SIZE (0x00004000)
100   -
101   -/*
102   - * Expansion BUS
103   - *
104   - * Expansion Bus 'lives' at either base1 or base 2 depending on the value of
105   - * Exp Bus config registers:
106   - *
107   - * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero,
108   - * and The expansion bus to IXP425_EXP_BUS_BASE2
109   - */
110   -#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000)
111   -#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000)
112   -
113   -#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS
114   -
115   -#define IXP425_EXP_BUS_REGION_SIZE (0x08000000)
116   -#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000)
117   -
118   -#define IXP425_EXP_BUS_CS0_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x00000000)
119   -#define IXP425_EXP_BUS_CS1_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x01000000)
120   -#define IXP425_EXP_BUS_CS2_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x02000000)
121   -#define IXP425_EXP_BUS_CS3_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x03000000)
122   -#define IXP425_EXP_BUS_CS4_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x04000000)
123   -#define IXP425_EXP_BUS_CS5_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x05000000)
124   -#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
125   -#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
126   -
127   -#define IXP425_FLASH_WRITABLE (0x2)
128   -#define IXP425_FLASH_DEFAULT (0xbcd23c40)
129   -#define IXP425_FLASH_WRITE (0xbcd23c42)
130   -
131   -#define IXP425_EXP_CS0_OFFSET 0x00
132   -#define IXP425_EXP_CS1_OFFSET 0x04
133   -#define IXP425_EXP_CS2_OFFSET 0x08
134   -#define IXP425_EXP_CS3_OFFSET 0x0C
135   -#define IXP425_EXP_CS4_OFFSET 0x10
136   -#define IXP425_EXP_CS5_OFFSET 0x14
137   -#define IXP425_EXP_CS6_OFFSET 0x18
138   -#define IXP425_EXP_CS7_OFFSET 0x1C
139   -#define IXP425_EXP_CFG0_OFFSET 0x20
140   -#define IXP425_EXP_CFG1_OFFSET 0x24
141   -#define IXP425_EXP_CFG2_OFFSET 0x28
142   -#define IXP425_EXP_CFG3_OFFSET 0x2C
143   -
144   -/*
145   - * Expansion Bus Controller registers.
146   - */
147   -#ifndef __ASSEMBLY__
148   -#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x)))
149   -#else
150   -#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
151   -#endif
152   -
153   -#define IXP425_EXP_CS0 IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
154   -#define IXP425_EXP_CS1 IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
155   -#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
156   -#define IXP425_EXP_CS3 IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET)
157   -#define IXP425_EXP_CS4 IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET)
158   -#define IXP425_EXP_CS5 IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET)
159   -#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
160   -#define IXP425_EXP_CS7 IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET)
161   -
162   -#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
163   -#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
164   -#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
165   -#define IXP425_EXP_CFG3 IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
166   -
167   -/*
168   - * SDRAM Controller registers.
169   - */
170   -#define IXP425_SDR_CONFIG_OFFSET 0x00
171   -#define IXP425_SDR_REFRESH_OFFSET 0x04
172   -#define IXP425_SDR_IR_OFFSET 0x08
173   -
174   -#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x))
175   -
176   -#define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET)
177   -#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
178   -#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
179   -
180   -/*
181   - * UART registers
182   - */
183   -#define IXP425_UART1 0
184   -#define IXP425_UART2 0x1000
185   -
186   -#define IXP425_UART_RBR_OFFSET 0x00
187   -#define IXP425_UART_THR_OFFSET 0x00
188   -#define IXP425_UART_DLL_OFFSET 0x00
189   -#define IXP425_UART_IER_OFFSET 0x04
190   -#define IXP425_UART_DLH_OFFSET 0x04
191   -#define IXP425_UART_IIR_OFFSET 0x08
192   -#define IXP425_UART_FCR_OFFSET 0x00
193   -#define IXP425_UART_LCR_OFFSET 0x0c
194   -#define IXP425_UART_MCR_OFFSET 0x10
195   -#define IXP425_UART_LSR_OFFSET 0x14
196   -#define IXP425_UART_MSR_OFFSET 0x18
197   -#define IXP425_UART_SPR_OFFSET 0x1c
198   -#define IXP425_UART_ISR_OFFSET 0x20
199   -
200   -#define IXP425_UART_CFG_BASE_PHYS (0xc8000000)
201   -
202   -#define RBR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET)
203   -#define THR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET)
204   -#define DLL(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET)
205   -#define IER(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET)
206   -#define DLH(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET)
207   -#define IIR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET)
208   -#define FCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET)
209   -#define LCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET)
210   -#define MCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET)
211   -#define LSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET)
212   -#define MSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET)
213   -#define SPR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET)
214   -#define ISR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET)
215   -
216   -#define IER_DMAE (1 << 7) /* DMA Requests Enable */
217   -#define IER_UUE (1 << 6) /* UART Unit Enable */
218   -#define IER_NRZE (1 << 5) /* NRZ coding Enable */
219   -#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
220   -#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
221   -#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
222   -#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
223   -#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
224   -
225   -#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
226   -#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
227   -#define IIR_TOD (1 << 3) /* Time Out Detected */
228   -#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
229   -#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
230   -#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
231   -
232   -#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
233   -#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
234   -#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
235   -#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
236   -#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
237   -#define FCR_ITL_1 (0)
238   -#define FCR_ITL_8 (FCR_ITL1)
239   -#define FCR_ITL_16 (FCR_ITL2)
240   -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
241   -
242   -#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
243   -#define LCR_SB (1 << 6) /* Set Break */
244   -#define LCR_STKYP (1 << 5) /* Sticky Parity */
245   -#define LCR_EPS (1 << 4) /* Even Parity Select */
246   -#define LCR_PEN (1 << 3) /* Parity Enable */
247   -#define LCR_STB (1 << 2) /* Stop Bit */
248   -#define LCR_WLS1 (1 << 1) /* Word Length Select */
249   -#define LCR_WLS0 (1 << 0) /* Word Length Select */
250   -
251   -#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
252   -#define LSR_TEMT (1 << 6) /* Transmitter Empty */
253   -#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
254   -#define LSR_BI (1 << 4) /* Break Interrupt */
255   -#define LSR_FE (1 << 3) /* Framing Error */
256   -#define LSR_PE (1 << 2) /* Parity Error */
257   -#define LSR_OE (1 << 1) /* Overrun Error */
258   -#define LSR_DR (1 << 0) /* Data Ready */
259   -
260   -#define MCR_LOOP (1 << 4) */
261   -#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
262   -#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
263   -#define MCR_RTS (1 << 1) /* Request to Send */
264   -#define MCR_DTR (1 << 0) /* Data Terminal Ready */
265   -
266   -#define MSR_DCD (1 << 7) /* Data Carrier Detect */
267   -#define MSR_RI (1 << 6) /* Ring Indicator */
268   -#define MSR_DSR (1 << 5) /* Data Set Ready */
269   -#define MSR_CTS (1 << 4) /* Clear To Send */
270   -#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
271   -#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
272   -#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
273   -#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
274   -
275   -#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
276   -/*
277   - * Peripheral Space Registers
278   - */
279   -#define IXP425_UART1_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x0000)
280   -#define IXP425_UART2_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x1000)
281   -#define IXP425_PMU_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x2000)
282   -#define IXP425_INTC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x3000)
283   -#define IXP425_GPIO_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x4000)
284   -#define IXP425_TIMER_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x5000)
285   -#define IXP425_NPEA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x6000)
286   -#define IXP425_NPEB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x7000)
287   -#define IXP425_NPEC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x8000)
288   -#define IXP425_EthA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x9000)
289   -#define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000)
290   -#define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000)
291   -
292   -/*
293   - * UART Register Definitions , Offsets only as there are 2 UARTS.
294   - * IXP425_UART1_BASE , IXP425_UART2_BASE.
295   - */
296   -
297   -#undef UART_NO_RX_INTERRUPT
298   -
299   -#define IXP425_UART_XTAL 14745600
300   -
301   -/*
302   - * Constants to make it easy to access Interrupt Controller registers
303   - */
304   -#define IXP425_ICPR_OFFSET 0x00 /* Interrupt Status */
305   -#define IXP425_ICMR_OFFSET 0x04 /* Interrupt Enable */
306   -#define IXP425_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */
307   -#define IXP425_ICIP_OFFSET 0x0C /* IRQ Status */
308   -#define IXP425_ICFP_OFFSET 0x10 /* FIQ Status */
309   -#define IXP425_ICHR_OFFSET 0x14 /* Interrupt Priority */
310   -#define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
311   -#define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
312   -
313   -#define N_IRQS 32
314   -#define IXP425_TIMER_2_IRQ 11
315   -
316   -/*
317   - * Interrupt Controller Register Definitions.
318   - */
319   -#ifndef __ASSEMBLY__
320   -#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x)))
321   -#else
322   -#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x))
323   -#endif
324   -
325   -#define IXP425_ICPR IXP425_INTC_REG(IXP425_ICPR_OFFSET)
326   -#define IXP425_ICMR IXP425_INTC_REG(IXP425_ICMR_OFFSET)
327   -#define IXP425_ICLR IXP425_INTC_REG(IXP425_ICLR_OFFSET)
328   -#define IXP425_ICIP IXP425_INTC_REG(IXP425_ICIP_OFFSET)
329   -#define IXP425_ICFP IXP425_INTC_REG(IXP425_ICFP_OFFSET)
330   -#define IXP425_ICHR IXP425_INTC_REG(IXP425_ICHR_OFFSET)
331   -#define IXP425_ICIH IXP425_INTC_REG(IXP425_ICIH_OFFSET)
332   -#define IXP425_ICFH IXP425_INTC_REG(IXP425_ICFH_OFFSET)
333   -
334   -/*
335   - * Constants to make it easy to access GPIO registers
336   - */
337   -#define IXP425_GPIO_GPOUTR_OFFSET 0x00
338   -#define IXP425_GPIO_GPOER_OFFSET 0x04
339   -#define IXP425_GPIO_GPINR_OFFSET 0x08
340   -#define IXP425_GPIO_GPISR_OFFSET 0x0C
341   -#define IXP425_GPIO_GPIT1R_OFFSET 0x10
342   -#define IXP425_GPIO_GPIT2R_OFFSET 0x14
343   -#define IXP425_GPIO_GPCLKR_OFFSET 0x18
344   -#define IXP425_GPIO_GPDBSELR_OFFSET 0x1C
345   -
346   -/*
347   - * GPIO Register Definitions.
348   - * [Only perform 32bit reads/writes]
349   - */
350   -#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x)))
351   -
352   -#define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET)
353   -#define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET)
354   -#define IXP425_GPIO_GPINR IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET)
355   -#define IXP425_GPIO_GPISR IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET)
356   -#define IXP425_GPIO_GPIT1R IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET)
357   -#define IXP425_GPIO_GPIT2R IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET)
358   -#define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET)
359   -#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET)
360   -
361   -#define IXP425_GPIO_GPITR(line) (((line) >= 8) ? \
362   - IXP425_GPIO_GPIT2R : IXP425_GPIO_GPIT1R)
363   -
364   -/*
365   - * Macros to make it easy to access the GPIO registers
366   - */
367   -#define GPIO_OUTPUT_ENABLE(line) *IXP425_GPIO_GPOER &= ~(1 << (line))
368   -#define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line))
369   -#define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line))
370   -#define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line))
371   -#define GPIO_INT_ACT_LOW_SET(line) \
372   - *IXP425_GPIO_GPITR(line) = \
373   - (*IXP425_GPIO_GPITR(line) & \
374   - ~(0x7 << (((line) & 0x7) * 3))) | \
375   - (0x1 << (((line) & 0x7) * 3)) \
376   -
377   -/*
378   - * Constants to make it easy to access Timer Control/Status registers
379   - */
380   -#define IXP425_OSTS_OFFSET 0x00 /* Continious TimeStamp */
381   -#define IXP425_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
382   -#define IXP425_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
383   -#define IXP425_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
384   -#define IXP425_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
385   -#define IXP425_OSWT_OFFSET 0x14 /* Watchdog Timer */
386   -#define IXP425_OSWE_OFFSET 0x18 /* Watchdog Enable */
387   -#define IXP425_OSWK_OFFSET 0x1C /* Watchdog Key */
388   -#define IXP425_OSST_OFFSET 0x20 /* Timer Status */
389   -
390   -/*
391   - * Operating System Timer Register Definitions.
392   - */
393   -
394   -#ifndef __ASSEMBLY__
395   -#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x)))
396   -#else
397   -#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
398   -#endif
399   -
400   -/* _B to avoid collision: also defined in npe/include/... */
401   -#define IXP425_OSTS_B IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
402   -#define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET)
403   -#define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
404   -#define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET)
405   -#define IXP425_OSRT2 IXP425_TIMER_REG(IXP425_OSRT2_OFFSET)
406   -#define IXP425_OSWT IXP425_TIMER_REG(IXP425_OSWT_OFFSET)
407   -#define IXP425_OSWE IXP425_TIMER_REG(IXP425_OSWE_OFFSET)
408   -#define IXP425_OSWK IXP425_TIMER_REG(IXP425_OSWK_OFFSET)
409   -#define IXP425_OSST IXP425_TIMER_REG(IXP425_OSST_OFFSET)
410   -
411   -/*
412   - * Timer register values and bit definitions
413   - */
414   -#define IXP425_OST_ENABLE BIT(0)
415   -#define IXP425_OST_ONE_SHOT BIT(1)
416   -/* Low order bits of reload value ignored */
417   -#define IXP425_OST_RELOAD_MASK (0x3)
418   -#define IXP425_OST_DISABLED (0x0)
419   -#define IXP425_OSST_TIMER_1_PEND BIT(0)
420   -#define IXP425_OSST_TIMER_2_PEND BIT(1)
421   -#define IXP425_OSST_TIMER_TS_PEND BIT(2)
422   -#define IXP425_OSST_TIMER_WDOG_PEND BIT(3)
423   -#define IXP425_OSST_TIMER_WARM_RESET BIT(4)
424   -
425   -/*
426   - * Constants to make it easy to access PCI Control/Status registers
427   - */
428   -#define PCI_NP_AD_OFFSET 0x00
429   -#define PCI_NP_CBE_OFFSET 0x04
430   -#define PCI_NP_WDATA_OFFSET 0x08
431   -#define PCI_NP_RDATA_OFFSET 0x0c
432   -#define PCI_CRP_AD_CBE_OFFSET 0x10
433   -#define PCI_CRP_WDATA_OFFSET 0x14
434   -#define PCI_CRP_RDATA_OFFSET 0x18
435   -#define PCI_CSR_OFFSET 0x1c
436   -#define PCI_ISR_OFFSET 0x20
437   -#define PCI_INTEN_OFFSET 0x24
438   -#define PCI_DMACTRL_OFFSET 0x28
439   -#define PCI_AHBMEMBASE_OFFSET 0x2c
440   -#define PCI_AHBIOBASE_OFFSET 0x30
441   -#define PCI_PCIMEMBASE_OFFSET 0x34
442   -#define PCI_AHBDOORBELL_OFFSET 0x38
443   -#define PCI_PCIDOORBELL_OFFSET 0x3C
444   -#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
445   -#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
446   -#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
447   -#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
448   -#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
449   -#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
450   -
451   -/*
452   - * PCI Control/Status Registers
453   - */
454   -#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x)))
455   -
456   -#define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET)
457   -#define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET)
458   -#define PCI_NP_WDATA IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET)
459   -#define PCI_NP_RDATA IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET)
460   -#define PCI_CRP_AD_CBE IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
461   -#define PCI_CRP_WDATA IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET)
462   -#define PCI_CRP_RDATA IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET)
463   -#define PCI_CSR IXP425_PCI_CSR(PCI_CSR_OFFSET)
464   -#define PCI_ISR IXP425_PCI_CSR(PCI_ISR_OFFSET)
465   -#define PCI_INTEN IXP425_PCI_CSR(PCI_INTEN_OFFSET)
466   -#define PCI_DMACTRL IXP425_PCI_CSR(PCI_DMACTRL_OFFSET)
467   -#define PCI_AHBMEMBASE IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
468   -#define PCI_AHBIOBASE IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET)
469   -#define PCI_PCIMEMBASE IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
470   -#define PCI_AHBDOORBELL IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
471   -#define PCI_PCIDOORBELL IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
472   -#define PCI_ATPDMA0_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
473   -#define PCI_ATPDMA0_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
474   -#define PCI_ATPDMA0_LENADDR IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
475   -#define PCI_ATPDMA1_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
476   -#define PCI_ATPDMA1_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
477   -#define PCI_ATPDMA1_LENADDR IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
478   -
479   -/*
480   - * PCI register values and bit definitions
481   - */
482   -
483   -/* CSR bit definitions */
484   -#define PCI_CSR_HOST BIT(0)
485   -#define PCI_CSR_ARBEN BIT(1)
486   -#define PCI_CSR_ADS BIT(2)
487   -#define PCI_CSR_PDS BIT(3)
488   -#define PCI_CSR_ABE BIT(4)
489   -#define PCI_CSR_DBT BIT(5)
490   -#define PCI_CSR_ASE BIT(8)
491   -#define PCI_CSR_IC BIT(15)
492   -
493   -/* ISR (Interrupt status) Register bit definitions */
494   -#define PCI_ISR_PSE BIT(0)
495   -#define PCI_ISR_PFE BIT(1)
496   -#define PCI_ISR_PPE BIT(2)
497   -#define PCI_ISR_AHBE BIT(3)
498   -#define PCI_ISR_APDC BIT(4)
499   -#define PCI_ISR_PADC BIT(5)
500   -#define PCI_ISR_ADB BIT(6)
501   -#define PCI_ISR_PDB BIT(7)
502   -
503   -/* INTEN (Interrupt Enable) Register bit definitions */
504   -#define PCI_INTEN_PSE BIT(0)
505   -#define PCI_INTEN_PFE BIT(1)
506   -#define PCI_INTEN_PPE BIT(2)
507   -#define PCI_INTEN_AHBE BIT(3)
508   -#define PCI_INTEN_APDC BIT(4)
509   -#define PCI_INTEN_PADC BIT(5)
510   -#define PCI_INTEN_ADB BIT(6)
511   -#define PCI_INTEN_PDB BIT(7)
512   -
513   -/*
514   - * Shift value for byte enable on NP cmd/byte enable register
515   - */
516   -#define IXP425_PCI_NP_CBE_BESL 4
517   -
518   -/*
519   - * PCI commands supported by NP access unit
520   - */
521   -#define NP_CMD_IOREAD 0x2
522   -#define NP_CMD_IOWRITE 0x3
523   -#define NP_CMD_CONFIGREAD 0xa
524   -#define NP_CMD_CONFIGWRITE 0xb
525   -#define NP_CMD_MEMREAD 0x6
526   -#define NP_CMD_MEMWRITE 0x7
527   -
528   -#if 0
529   -#ifndef __ASSEMBLY__
530   -extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data);
531   -extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data);
532   -extern void ixp425_pci_init(void *);
533   -#endif
534   -#endif
535   -
536   -/*
537   - * Constants for CRP access into local config space
538   - */
539   -#define CRP_AD_CBE_BESL 20
540   -#define CRP_AD_CBE_WRITE BIT(16)
541   -
542   -/*
543   - * Clock Speed Definitions.
544   - */
545   -#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
546   -
547   -
548   -#endif
arch/arm/include/asm/arch-ixp/ixp425pci.h
View file @ c8d4b2f
1   -/*
2   - * IXP PCI Init
3   - * (C) Copyright 2004 eslab.whut.edu.cn
4   - * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef _IXP425PCI_H
10   -#define _IXP425PCI_H
11   -
12   -#define OK 0
13   -#define ERROR -1
14   -
15   -struct pci_controller;
16   -extern void pci_ixp_init(struct pci_controller *hose);
17   -
18   -/* Mask definitions*/
19   -#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f
20   -
21   -#define PCI_NP_CBE_BESL (4)
22   -#define PCI_NP_AD_FUNCSL (8)
23   -
24   -/*Register addressing definitions for PCI controller configuration
25   - and status registers*/
26   -
27   -#define PCI_CSR_BASE (0xC0000000)
28   -/*
29   -#define PCI_NP_AD_OFFSET (0x00)
30   -#define PCI_NP_CBE_OFFSET (0x04)
31   -#define PCI_NP_WDATA_OFFSET (0x08)
32   -#define PCI_NP_RDATA_OFFSET (0x0C)
33   -#define PCI_CRP_OFFSET (0x10)
34   -#define PCI_CRP_WDATA_OFFSET (0x14)
35   -#define PCI_CRP_RDATA_OFFSET (0x18)
36   -#define PCI_CSR_OFFSET (0x1C)
37   -#define PCI_ISR_OFFSET (0x20)
38   -#define PCI_INTEN_OFFSET (0x24)
39   -#define PCI_DMACTRL_OFFSET (0x28)
40   -#define PCI_AHBMEMBASE_OFFSET (0x2C)
41   -#define PCI_AHBIOBASE_OFFSET (0x30)
42   -#define PCI_PCIMEMBASE_OFFSET (0x34)
43   -#define PCI_AHBDOORBELL_OFFSET (0x38)
44   -#define PCI_PCIDOORBELL_OFFSET (0x3C)
45   -#define PCI_ATPDMA0_AHBADDR (0x40)
46   -#define PCI_ATPDMA0_PCIADDR (0x44)
47   -#define PCI_ATPDMA0_LENADDR (0x48)
48   -#define PCI_ATPDMA1_AHBADDR (0x4C)
49   -#define PCI_ATPDMA1_PCIADDR (0x50)
50   -#define PCI_ATPDMA1_LENADDR (0x54)
51   -#define PCI_PTADMA0_AHBADDR (0x58)
52   -#define PCI_PTADMA0_PCIADDR (0x5C)
53   -#define PCI_PTADMA0_LENADDR (0x60)
54   -#define PCI_PTADMA1_AHBADDR (0x64)
55   -#define PCI_PTADMA1_PCIADDR (0x68)
56   -#define PCI_PTADMA1_LENADDR (0x6C)
57   -*/
58   -/*Non prefetch registers bit definitions*/
59   -/*
60   -#define NP_CMD_INTACK (0x0)
61   -#define NP_CMD_SPECIAL (0x1)
62   -#define NP_CMD_IOREAD (0x2)
63   -#define NP_CMD_IOWRITE (0x3)
64   -#define NP_CMD_MEMREAD (0x6)
65   -#define NP_CMD_MEMWRITE (0x7)
66   -#define NP_CMD_CONFIGREAD (0xa)
67   -#define NP_CMD_CONFIGWRITE (0xb)
68   -*/
69   -
70   -/*Configuration Port register bit definitions*/
71   -#define PCI_CRP_WRITE BIT(16)
72   -
73   -/*ISR (Interrupt status) Register bit definitions*/
74   -#define PCI_ISR_PSE BIT(0)
75   -#define PCI_ISR_PFE BIT(1)
76   -#define PCI_ISR_PPE BIT(2)
77   -#define PCI_ISR_AHBE BIT(3)
78   -#define PCI_ISR_APDC BIT(4)
79   -#define PCI_ISR_PADC BIT(5)
80   -#define PCI_ISR_ADB BIT(6)
81   -#define PCI_ISR_PDB BIT(7)
82   -
83   -/*INTEN (Interrupt Enable) Register bit definitions*/
84   -#define PCI_INTEN_PSE BIT(0)
85   -#define PCI_INTEN_PFE BIT(1)
86   -#define PCI_INTEN_PPE BIT(2)
87   -#define PCI_INTEN_AHBE BIT(3)
88   -#define PCI_INTEN_APDC BIT(4)
89   -#define PCI_INTEN_PADC BIT(5)
90   -#define PCI_INTEN_ADB BIT(6)
91   -#define PCI_INTEN_PDB BIT(7)
92   -
93   -/*PCI configuration regs.*/
94   -
95   -#define PCI_CFG_VENDOR_ID 0x00
96   -#define PCI_CFG_DEVICE_ID 0x02
97   -#define PCI_CFG_COMMAND 0x04
98   -#define PCI_CFG_STATUS 0x06
99   -#define PCI_CFG_REVISION 0x08
100   -#define PCI_CFG_PROGRAMMING_IF 0x09
101   -#define PCI_CFG_SUBCLASS 0x0a
102   -#define PCI_CFG_CLASS 0x0b
103   -#define PCI_CFG_CACHE_LINE_SIZE 0x0c
104   -#define PCI_CFG_LATENCY_TIMER 0x0d
105   -#define PCI_CFG_HEADER_TYPE 0x0e
106   -#define PCI_CFG_BIST 0x0f
107   -#define PCI_CFG_BASE_ADDRESS_0 0x10
108   -#define PCI_CFG_BASE_ADDRESS_1 0x14
109   -#define PCI_CFG_BASE_ADDRESS_2 0x18
110   -#define PCI_CFG_BASE_ADDRESS_3 0x1c
111   -#define PCI_CFG_BASE_ADDRESS_4 0x20
112   -#define PCI_CFG_BASE_ADDRESS_5 0x24
113   -#define PCI_CFG_CIS 0x28
114   -#define PCI_CFG_SUB_VENDOR_ID 0x2c
115   -#define PCI_CFG_SUB_SYSTEM_ID 0x2e
116   -#define PCI_CFG_EXPANSION_ROM 0x30
117   -#define PCI_CFG_RESERVED_0 0x34
118   -#define PCI_CFG_RESERVED_1 0x38
119   -#define PCI_CFG_DEV_INT_LINE 0x3c
120   -#define PCI_CFG_DEV_INT_PIN 0x3d
121   -#define PCI_CFG_MIN_GRANT 0x3e
122   -#define PCI_CFG_MAX_LATENCY 0x3f
123   -#define PCI_CFG_SPECIAL_USE 0x41
124   -#define PCI_CFG_MODE 0x43
125   -
126   -#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */
127   -#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */
128   -#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
129   -#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */
130   -#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */
131   -#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */
132   -#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */
133   -#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */
134   -#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */
135   -#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */
136   -
137   -
138   -/*CSR Register bit definitions*/
139   -#define PCI_CSR_HOST BIT(0)
140   -#define PCI_CSR_ARBEN BIT(1)
141   -#define PCI_CSR_ADS BIT(2)
142   -#define PCI_CSR_PDS BIT(3)
143   -#define PCI_CSR_ABE BIT(4)
144   -#define PCI_CSR_DBT BIT(5)
145   -#define PCI_CSR_ASE BIT(8)
146   -#define PCI_CSR_IC BIT(15)
147   -
148   -/*Configuration command bit definitions*/
149   -#define PCI_CFG_CMD_IOAE BIT(0)
150   -#define PCI_CFG_CMD_MAE BIT(1)
151   -#define PCI_CFG_CMD_BME BIT(2)
152   -#define PCI_CFG_CMD_MWIE BIT(4)
153   -#define PCI_CFG_CMD_SER BIT(8)
154   -#define PCI_CFG_CMD_FBBE BIT(9)
155   -#define PCI_CFG_CMD_MDPE BIT(24)
156   -#define PCI_CFG_CMD_STA BIT(27)
157   -#define PCI_CFG_CMD_RTA BIT(28)
158   -#define PCI_CFG_CMD_RMA BIT(29)
159   -#define PCI_CFG_CMD_SSE BIT(30)
160   -#define PCI_CFG_CMD_DPE BIT(31)
161   -
162   -/*DMACTRL DMA Control and status Register*/
163   -#define PCI_DMACTRL_APDCEN BIT(0)
164   -#define PCI_DMACTRL_APDC0 BIT(4)
165   -#define PCI_DMACTRL_APDE0 BIT(5)
166   -#define PCI_DMACTRL_APDC1 BIT(6)
167   -#define PCI_DMACTRL_APDE1 BIT(7)
168   -#define PCI_DMACTRL_PADCEN BIT(8)
169   -#define PCI_DMACTRL_PADC0 BIT(12)
170   -#define PCI_DMACTRL_PADE0 BIT(13)
171   -#define PCI_DMACTRL_PADC1 BIT(14)
172   -#define PCI_DMACTRL_PADE1 BIT(15)
173   -
174   -#endif
arch/arm/include/asm/global_data.h
Diff comments   View file @ c8d4b2f
... ... @@ -32,9 +32,6 @@
32 32 unsigned long tbl;
33 33 unsigned long lastinc;
34 34 unsigned long long timer_reset_value;
35   -#ifdef CONFIG_IXP425
36   - unsigned long timestamp;
37   -#endif
38 35 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
39 36 unsigned long tlb_addr;
40 37 unsigned long tlb_size;
drivers/i2c/soft_i2c.c
Diff comments   View file @ c8d4b2f
... ... @@ -29,9 +29,6 @@
29 29 #include <asm/arch/gpio.h>
30 30 #endif
31 31 #endif
32   -#ifdef CONFIG_IXP425 /* only valid for IXP425 */
33   -#include <asm/arch/ixp425.h>
34   -#endif
35 32 #if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
36 33 #include <asm/io.h>
37 34 #endif