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Commit c91e90db8c3f4abbe28d7ec196b2499234ec8d68

Authored by Wolfgang Denk
Committed by Albert ARIBAUD
1 parent 689d0fa36a
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: remove broken "assabet" board 

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: George G. Davis <gdavis@mvista.com>

Showing 8 changed files with 1 additions and 502 deletions Side-by-side Diff

... ... @@ -632,7 +632,6 @@
632 632  
633 633 George G. Davis <gdavis@mvista.com>
634 634  
635   - assabet SA1100
636 635 gcplus SA1100
637 636  
638 637 Wolfgang Denk <wd@denx.de>
board/assabet/Makefile
View file @ c91e90d
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# 2004 (c) MontaVista Software, Inc.
6   -#
7   -# See file CREDITS for list of people who contributed to this
8   -# project.
9   -#
10   -# This program is free software; you can redistribute it and/or
11   -# modify it under the terms of the GNU General Public License as
12   -# published by the Free Software Foundation; either version 2 of
13   -# the License, or (at your option) any later version.
14   -#
15   -# This program is distributed in the hope that it will be useful,
16   -# but WITHOUT ANY WARRANTY; without even the implied warranty of
17   -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18   -# GNU General Public License for more details.
19   -#
20   -# You should have received a copy of the GNU General Public License
21   -# along with this program; if not, write to the Free Software
22   -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23   -# MA 02111-1307 USA
24   -#
25   -
26   -include $(TOPDIR)/config.mk
27   -
28   -LIB = $(obj)lib$(BOARD).o
29   -
30   -COBJS := assabet.o
31   -SOBJS := setup.o
32   -
33   -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
34   -OBJS := $(addprefix $(obj),$(COBJS))
35   -SOBJS := $(addprefix $(obj),$(SOBJS))
36   -
37   -$(LIB): $(obj).depend $(OBJS) $(SOBJS)
38   - $(call cmd_link_o_target, $(OBJS) $(SOBJS))
39   -
40   -clean:
41   - rm -f $(SOBJS) $(OBJS)
42   -
43   -distclean: clean
44   - rm -f $(LIB) core *.bak $(obj).depend
45   -
46   -#########################################################################
47   -
48   -# defines $(obj).depend target
49   -include $(SRCTREE)/rules.mk
50   -
51   -sinclude $(obj).depend
52   -
53   -#########################################################################
board/assabet/assabet.c
View file @ c91e90d
1   -/*
2   - * (C) Copyright 2002
3   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4   - * Marius Groeger <mgroeger@sysgo.de>
5   - *
6   - * 2004 (c) MontaVista Software, Inc.
7   - *
8   - * See file CREDITS for list of people who contributed to this
9   - * project.
10   - *
11   - * This program is free software; you can redistribute it and/or
12   - * modify it under the terms of the GNU General Public License as
13   - * published by the Free Software Foundation; either version 2 of
14   - * the License, or (at your option) any later version.
15   - *
16   - * This program is distributed in the hope that it will be useful,
17   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
18   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19   - * GNU General Public License for more details.
20   - *
21   - * You should have received a copy of the GNU General Public License
22   - * along with this program; if not, write to the Free Software
23   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24   - * MA 02111-1307 USA
25   - */
26   -
27   -#include <common.h>
28   -#include <netdev.h>
29   -#include <SA-1100.h>
30   -
31   -DECLARE_GLOBAL_DATA_PTR;
32   -
33   -/* ------------------------------------------------------------------------- */
34   -
35   -/*
36   - * Board dependent initialisation
37   - */
38   -
39   -#define ECOR 0x8000
40   -#define ECOR_RESET 0x80
41   -#define ECOR_LEVEL_IRQ 0x40
42   -#define ECOR_WR_ATTRIB 0x04
43   -#define ECOR_ENABLE 0x01
44   -
45   -#define ECSR 0x8002
46   -#define ECSR_IOIS8 0x20
47   -#define ECSR_PWRDWN 0x04
48   -#define ECSR_INT 0x02
49   -#define SMC_IO_SHIFT 2
50   -#define NCR_0 (*((volatile u_char *)(0x100000a0)))
51   -#define NCR_ENET_OSC_EN (1<<3)
52   -
53   -static inline u8
54   -readb(volatile u8 * p)
55   -{
56   - return *p;
57   -}
58   -
59   -static inline void
60   -writeb(u8 v, volatile u8 * p)
61   -{
62   - *p = v;
63   -}
64   -
65   -static void
66   -smc_init(void)
67   -{
68   - u8 ecor;
69   - u8 ecsr;
70   - volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25));
71   -
72   - NCR_0 |= NCR_ENET_OSC_EN;
73   - udelay(100);
74   -
75   - ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
76   - writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
77   - udelay(100);
78   -
79   - /*
80   - * The device will ignore all writes to the enable bit while
81   - * reset is asserted, even if the reset bit is cleared in the
82   - * same write. Must clear reset first, then enable the device.
83   - */
84   - writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
85   - writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
86   -
87   - /*
88   - * Set the appropriate byte/word mode.
89   - */
90   - ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
91   - ecsr |= ECSR_IOIS8;
92   - writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
93   - udelay(100);
94   -}
95   -
96   -static void
97   -neponset_init(void)
98   -{
99   - smc_init();
100   -}
101   -
102   -int
103   -board_init(void)
104   -{
105   - gd->bd->bi_arch_number = MACH_TYPE_ASSABET;
106   - gd->bd->bi_boot_params = 0xc0000100;
107   -
108   - neponset_init();
109   -
110   - return 0;
111   -}
112   -
113   -int
114   -dram_init(void)
115   -{
116   - gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
117   - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
118   -
119   - return (0);
120   -}
121   -
122   -#ifdef CONFIG_CMD_NET
123   -int board_eth_init(bd_t *bis)
124   -{
125   - int rc = 0;
126   -#ifdef CONFIG_LAN91C96
127   - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
128   -#endif
129   - return rc;
130   -}
131   -#endif
board/assabet/config.mk
View file @ c91e90d
1   -#
2   -# SA-1110 based Intel Assabet board
3   -#
4   -# The Intel Assabet 1 bank of 32 MiB SDRAM
5   -#
6   -
7   -CONFIG_SYS_TEXT_BASE = 0xc1f00000
board/assabet/setup.S
View file @ c91e90d
1   -/*
2   - * Memory Setup stuff - taken from blob memsetup.S
3   - *
4   - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5   - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6   - * 2004 (c) MontaVista Software, Inc.
7   - *
8   - * See file CREDITS for list of people who contributed to this
9   - * project.
10   - *
11   - * This program is free software; you can redistribute it and/or
12   - * modify it under the terms of the GNU General Public License as
13   - * published by the Free Software Foundation; either version 2 of
14   - * the License, or (at your option) any later version.
15   - *
16   - * This program is distributed in the hope that it will be useful,
17   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
18   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19   - * GNU General Public License for more details.
20   - *
21   - * You should have received a copy of the GNU General Public License
22   - * along with this program; if not, write to the Free Software
23   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24   - * MA 02111-1307 USA
25   - */
26   -
27   -
28   -#include "config.h"
29   -#include "version.h"
30   -
31   -
32   -/*-----------------------------------------------------------------------
33   - * Board defines:
34   - */
35   -
36   -#define MDCNFG 0x00
37   -#define MDCAS00 0x04
38   -#define MDCAS01 0x08
39   -#define MDCAS02 0x0C
40   -#define MSC0 0x10
41   -#define MSC1 0x14
42   -#define MECR 0x18
43   -#define MDREFR 0x1C
44   -#define MDCAS20 0x20
45   -#define MDCAS21 0x24
46   -#define MDCAS22 0x28
47   -#define MSC2 0x2C
48   -#define SMCNFG 0x30
49   -
50   -#define ASSABET_BCR (0x12000000)
51   -#define ASSABET_BCR_DB1110 (0x00a07490 | (0<<16) | (0<<17))
52   -#define ASSABET_SCR_nNEPONSET (1 << 9)
53   -#define NEPONSET_LEDS (0x10000010)
54   -
55   -
56   -/*-----------------------------------------------------------------------
57   - * Setup parameters for the board:
58   - */
59   -
60   -
61   -MEM_BASE: .long 0xa0000000
62   -MEM_START: .long 0xc0000000
63   -
64   -mdcnfg: .long 0x72547254
65   -mdcas00: .long 0xaaaaaa7f
66   -mdcas01: .long 0xaaaaaaaa
67   -mdcas02: .long 0xaaaaaaaa
68   -msc0: .long 0x4b384370
69   -msc1: .long 0x22212419
70   -mecr: .long 0x994a994a
71   -mdrefr: .long 0x04340327
72   -mdcas20: .long 0xaaaaaa7f
73   -mdcas21: .long 0xaaaaaaaa
74   -mdcas22: .long 0xaaaaaaaa
75   -msc2: .long 0x42196669
76   -smcnfg: .long 0x00000000
77   -
78   -BCR: .long ASSABET_BCR
79   -BCR_DB1110: .long ASSABET_BCR_DB1110
80   -LEDS: .long NEPONSET_LEDS
81   -
82   -
83   - .globl lowlevel_init
84   -lowlevel_init:
85   -
86   - /* Setting up the memory and stuff */
87   -
88   - ldr r0, MEM_BASE
89   - ldr r1, mdcas00
90   - str r1, [r0, #MDCAS00]
91   - ldr r1, mdcas01
92   - str r1, [r0, #MDCAS01]
93   - ldr r1, mdcas02
94   - str r1, [r0, #MDCAS02]
95   - ldr r1, mdcas20
96   - str r1, [r0, #MDCAS20]
97   - ldr r1, mdcas21
98   - str r1, [r0, #MDCAS21]
99   - ldr r1, mdcas22
100   - str r1, [r0, #MDCAS22]
101   - ldr r1, mdrefr
102   - str r1, [r0, #MDREFR]
103   - ldr r1, mecr
104   - str r1, [r0, #MECR]
105   - ldr r1, msc0
106   - str r1, [r0, #MSC0]
107   - ldr r1, msc1
108   - str r1, [r0, #MSC1]
109   - ldr r1, msc2
110   - str r1, [r0, #MSC2]
111   - ldr r1, smcnfg
112   - str r1, [r0, #SMCNFG]
113   -
114   - ldr r1, mdcnfg
115   - str r1, [r0, #MDCNFG]
116   -
117   - /* Load something to activate bank */
118   - ldr r2, MEM_START
119   -.rept 8
120   - ldr r3, [r2]
121   -.endr
122   -
123   - /* Enable SDRAM */
124   - orr r1, r1, #0x00000001
125   - str r1, [r0, #MDCNFG]
126   -
127   - ldr r1, BCR
128   - ldr r2, BCR_DB1110
129   - str r2, [r1]
130   -
131   - ldr r1, LEDS
132   - mov r0, #0x3
133   - str r0, [r1]
134   -
135   - /* All done... */
136   - mov pc, lr
... ... @@ -236,7 +236,6 @@
236 236 zipitz2 arm pxa
237 237 zylonite arm pxa
238 238 B2 arm s3c44b0 - dave
239   -assabet arm sa1100
240 239 dnp1110 arm sa1100
241 240 gcplus arm sa1100
242 241 jornada arm sa1100
doc/README.scrapyard
Diff comments   View file @ c91e90d
... ... @@ -11,6 +11,7 @@
11 11  
12 12 Board Arch CPU removed Commit last known maintainer/contact
13 13 =============================================================================
  14 +assabet arm sa1100 - 2011-07-16 George G. Davis <gdavis@mvista.com>
14 15 trab arm S3C2400 - 2011-05-01 Gary Jennejohn <garyj@denx.de>
15 16 xsengine ARM PXA2xx 4262a7c 2010-10-20
16 17 wepep250 ARM PXA2xx 7369478 2010-10-20 Peter Figuli <peposh@etc.sk>
include/configs/assabet.h
View file @ c91e90d
1   -/*
2   - * (C) Copyright 2002
3   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4   - * Marius Groeger <mgroeger@sysgo.de>
5   - *
6   - * 2004 (c) MontaVista Software, Inc.
7   - *
8   - * Configuation settings for the Intel Assabet board.
9   - *
10   - * See file CREDITS for list of people who contributed to this
11   - * project.
12   - *
13   - * This program is free software; you can redistribute it and/or
14   - * modify it under the terms of the GNU General Public License as
15   - * published by the Free Software Foundation; either version 2 of
16   - * the License, or (at your option) any later version.
17   - *
18   - * This program is distributed in the hope that it will be useful,
19   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
20   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21   - * GNU General Public License for more details.
22   - *
23   - * You should have received a copy of the GNU General Public License
24   - * along with this program; if not, write to the Free Software
25   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26   - * MA 02111-1307 USA
27   - */
28   -
29   -#ifndef __CONFIG_H
30   -#define __CONFIG_H
31   -
32   -/*
33   - * High Level Configuration Options
34   - * (easy to change)
35   - */
36   -#define CONFIG_SA1110 1 /* This is an SA1100 CPU */
37   -#define CONFIG_ASSABET 1 /* on an Intel Assabet Board */
38   -
39   -#undef CONFIG_USE_IRQ
40   -/* we will never enable dcache, because we have to setup MMU first */
41   -#define CONFIG_SYS_DCACHE_OFF
42   -
43   -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
44   -#define CONFIG_SETUP_MEMORY_TAGS 1
45   -#define CONFIG_INITRD_TAG 1
46   -
47   -/*
48   - * Size of malloc() pool
49   - */
50   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
51   -
52   -/*
53   - * Hardware drivers
54   - */
55   -#define CONFIG_NET_MULTI
56   -#define CONFIG_LAN91C96 /* we have an SMC9194 on-board */
57   -#define CONFIG_LAN91C96_BASE 0x18000000
58   -
59   -/*
60   - * select serial console configuration
61   - */
62   -#define CONFIG_SA1100_SERIAL
63   -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on Intel Assabet */
64   -
65   -/* allow to overwrite serial and ethaddr */
66   -#define CONFIG_ENV_OVERWRITE
67   -
68   -#define CONFIG_BAUDRATE 115200
69   -
70   -
71   -/*
72   - * Command line configuration.
73   - */
74   -#include <config_cmd_default.h>
75   -
76   -#define CONFIG_CMD_DHCP
77   -
78   -
79   -/*
80   - * BOOTP options
81   - */
82   -#define CONFIG_BOOTP_SUBNETMASK
83   -#define CONFIG_BOOTP_GATEWAY
84   -#define CONFIG_BOOTP_HOSTNAME
85   -#define CONFIG_BOOTP_BOOTPATH
86   -
87   -
88   -#define CONFIG_BOOTDELAY 3
89   -#define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp"
90   -#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
91   -#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
92   -
93   -#if defined(CONFIG_CMD_KGDB)
94   -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
95   -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
96   -#endif
97   -
98   -/*
99   - * Miscellaneous configurable options
100   - */
101   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
102   -#define CONFIG_SYS_PROMPT "Intel Assabet # " /* Monitor Command Prompt */
103   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
104   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
105   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
106   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
107   -
108   -#define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */
109   -#define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */
110   -
111   -#define CONFIG_SYS_LOAD_ADDR 0xc0000000 /* default load address */
112   -
113   -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
114   -#define CONFIG_SYS_CPUSPEED 0x0a /* set core clock to 206MHz */
115   -
116   - /* valid baudrates */
117   -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
118   -
119   -/*-----------------------------------------------------------------------
120   - * Stack sizes
121   - *
122   - * The stack sizes are set up in start.S using the settings below
123   - */
124   -#define CONFIG_STACKSIZE (128*1024) /* regular stack */
125   -#ifdef CONFIG_USE_IRQ
126   -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
127   -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
128   -#endif
129   -
130   -/*-----------------------------------------------------------------------
131   - * Physical Memory Map
132   - */
133   -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
134   -#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
135   -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
136   -
137   -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
138   -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
139   -#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
140   -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
141   -
142   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
143   -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
144   -
145   -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
146   -#define CONFIG_SYS_RAMSTART
147   -#endif
148   -
149   -/*-----------------------------------------------------------------------
150   - * FLASH and environment organization
151   - */
152   -
153   -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
154   -#define CONFIG_SYS_FLASH_SIZE PHYS_FLASH_SIZE
155   -#define CONFIG_SYS_FLASH_CFI 1 /* flash is CFI conformant */
156   -#define CONFIG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
157   -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
158   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
159   -#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
160   -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
161   -#undef CONFIG_SYS_FLASH_PROTECTION
162   -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
163   -
164   -#define CONFIG_ENV_IS_IN_FLASH 1
165   -
166   -#if defined(CONFIG_ENV_IS_IN_FLASH)
167   -#define CONFIG_ENV_IN_OWN_SECTOR 1
168   -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
169   -#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE
170   -#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
171   -#endif
172   -
173   -#endif /* __CONFIG_H */