Patch by Kurt Stremerch, 28 May 2004:

Add support for Exys XSEngine board Some code cleanup.

Patch by Kurt Stremerch, 28 May 2004:
Add support for Exys XSEngine board Some code cleanup.
wdenk
1 parent 697037fe9b
Showing 15 changed files with 1177 additions and 6 deletions Side-by-side Diff
CHANGELOG
CREDITS
MAKEALL
Makefile
board/omap1610inn/omap1610innovator.c
board/xsengine/Makefile
board/xsengine/config.mk
board/xsengine/flash.c
board/xsengine/memsetup.S
board/xsengine/u-boot.lds
board/xsengine/xsengine.c
drivers/smc91111.h
include/configs/omap1610h2.h
include/configs/omap1610inn.h
include/configs/xsengine.h
@@ -2,6 +2,9 @@
 Changes since U-Boot 1.1.1:
 ======================================================================
  
+* Patch by Kurt Stremerch, 28 May 2004:
+  Add support for Exys XSEngine board
+
 * Patch by Martin Krause, 27 May 2004:
   Fix a MPC5xxx I2C timing issue in i2c_probe().
  
@@ -319,6 +319,10 @@
 E: r.schwebel@pengutronix.de
 D: Support for csb226, logodl and innokom boards (PXA2xx)
  
+N: Kurt Stremerch
+E: kurt@exys.be
+D: Support for Exys XSEngine board
+
 N: Rob Taylor
 E: robt@flyingpig.com
 D: Port to MBX860T and Sandpoint8240
@@ -149,7 +149,7 @@
 ## Xscale Systems
 #########################################################################
  
-LIST_pxa="cradle csb226 innokom lubbock wepep250 xm250"
+LIST_pxa="cradle csb226 innokom lubbock wepep250 xm250 xsengine"
  
 LIST_ixp="ixdp425"
  
@@ -1166,6 +1166,9 @@
 xm250_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa xm250
  
+xsengine_config :	unconfig
+	@./mkconfig $(@:_config=) arm pxa xsengine
+
 #========================================================================
 # i386
 #========================================================================
@@ -102,8 +102,8 @@
  
 #ifdef CONFIG_CS_AUTOBOOT
 	 /* Check swapping of CS0 and CS3, set flash base accordingly */
-        omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
-			                PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
+	omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
+					PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
 #endif
 	regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
 	/* Turn off write protection for flash devices. */
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= xsengine.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M --disassemble-all $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
+TEXT_BASE = 0xA3F80000
+/*
+ * (C) Copyright 2002
+ * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#if defined CFG_JFFS_CUSTOM_PART
+#include <jffs2/jffs2.h>
+#endif
+
+#define SWAP(x)               __swab32(x)
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/* Functions */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+#if defined CFG_JFFS_CUSTOM_PART
+
+/*
+ * jffs2_part_info - get information about a JFFS2 partition
+ *
+ * @part_num: number of the partition you want to get info about
+ * @return:   struct part_info* in case of success, 0 if failure
+ */
+
+static struct part_info part;
+static int current_part = -1;
+
+struct part_info* jffs2_part_info(int part_num) {
+	void *jffs2_priv_saved = part.jffs2_priv;
+
+	printf("jffs2_part_info: part_num=%i\n",part_num);
+
+	if (current_part == part_num)
+		return &part;
+
+	/* u-boot partition                                                 */
+	if(part_num==0){
+		memset(&part, 0, sizeof(part));
+
+		part.offset=(char*)0x00000000;
+		part.size=256*1024;
+
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		printf("part.offset = 0x%08x\n",(unsigned int)part.offset);
+		printf("part.size   = 0x%08x\n",(unsigned int)part.size);
+	}
+
+	/* primary OS+firmware partition                                    */
+	if(part_num==1){
+		memset(&part, 0, sizeof(part));
+
+		part.offset=(char*)0x00040000;
+		part.size=1024*1024;
+
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		printf("part.offset = 0x%08x\n",(unsigned int)part.offset);
+		printf("part.size   = 0x%08x\n",(unsigned int)part.size);
+	}
+
+	/* secondary OS+firmware partition                                  */
+	if(part_num==2){
+		memset(&part, 0, sizeof(part));
+
+		part.offset=(char*)0x00140000;
+		part.size=8*1024*1024;
+
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		printf("part.offset = 0x%08x\n",(unsigned int)part.offset);
+		printf("part.size   = 0x%08x\n",(unsigned int)part.size);
+	}
+
+	if (current_part == part_num) {
+		part.usr_priv = &current_part;
+		part.jffs2_priv = jffs2_priv_saved;
+		return &part;
+	}
+
+	printf("jffs2_part_info: end of partition table\n");
+	return 0;
+}
+#endif
+
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((long *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((long *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors */
+	flash_protect ( FLAG_PROTECT_SET,CFG_FLASH_BASE,CFG_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] );
+	flash_protect ( FLAG_PROTECT_SET,CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AMLV128U:	printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
+				break;
+	case FLASH_AMLV320U:	printf ("AM29LV320ML (32Mbit, uniform sector size)\n");
+				break;
+	case FLASH_AMLV640U:	printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
+				break;
+	case FLASH_AMLV320B:	printf ("AM29LV320MB (32Mbit, bottom boot sect)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00900090;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case AMD_MANUFACT:
+		debug ("Manufacturer: AMD\n");
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case FUJ_MANUFACT:
+		debug ("Manufacturer: FUJITSU\n");
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		debug ("Manufacturer: *** unknown ***\n");
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1];			/* device ID		*/
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+
+	case AMD_ID_MIRROR:
+		debug ("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
+			addr[14], addr[15]);
+		switch(addr[14]) {
+		case AMD_ID_LV128U_2:
+			if (addr[15] != AMD_ID_LV128U_3) {
+				debug ("Chip: AMLV128U -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: AMLV128U\n");
+				info->flash_id += FLASH_AMLV128U;
+				info->sector_count = 256;
+				info->size = 0x02000000;
+			}
+			break;				/* => 32 MB	*/
+		case AMD_ID_LV640U_2:
+			if (addr[15] != AMD_ID_LV640U_3) {
+				debug ("Chip: AMLV640U -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: AMLV640U\n");
+				info->flash_id += FLASH_AMLV640U;
+				info->sector_count = 128;
+				info->size = 0x01000000;
+			}
+			break;				/* => 16 MB	*/
+		case AMD_ID_LV320B_2:
+			if (addr[15] != AMD_ID_LV320B_3) {
+				debug ("Chip: AMLV320B -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: AMLV320B\n");
+				info->flash_id += FLASH_AMLV320B;
+				info->sector_count = 71;
+				info->size = 0x00800000;
+			}
+			break;				/* =>  8 MB	*/
+		default:
+			debug ("Chip: *** unknown ***\n");
+			info->flash_id = FLASH_UNKNOWN;
+			break;
+		}
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	switch (value) {
+	case AMD_ID_MIRROR:
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		/* only known types here - no default */
+		case FLASH_AMLV128U:
+		case FLASH_AMLV640U:
+		case FLASH_AMLV320U:
+			for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base;
+				base += 0x20000;
+			}
+			break;
+		case FLASH_AMLV320B:
+			for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base;
+				/*
+				 * The first 8 sectors are 8 kB,
+				 * all the other ones  are 64 kB
+				 */
+				base += (i < 8)
+					?  2 * ( 8 << 10)
+					:  2 * (64 << 10);
+			}
+			break;
+		}
+		break;
+
+	default:
+		return (0);
+		break;
+	}
+
+#if 0
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+#endif
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00800080;
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long*)(info->start[sect]);
+			addr[0] = 0x00300030;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long*)(info->start[l_sect]);
+	while ((addr[0] & 0x00800080) != 0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 100000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (volatile unsigned long *)info->start[0];
+	addr[0] = 0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, SWAP(data))) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, SWAP(data))) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, SWAP(data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	ulong start;
+	ulong rev;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0x00AA00AA;
+	addr[0x02AA] = 0x00550055;
+	addr[0x0555] = 0x00A000A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+.globl memsetup
+memsetup:
+
+   mov      r10, lr
+
+/* ---- GPIO INITIALISATION ---- */
+/* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */
+
+   /* General purpose set registers */
+   ldr      r0,   =GPSR0
+   ldr      r1,   =CFG_GPSR0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPSR1
+   ldr      r1,   =CFG_GPSR1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPSR2
+   ldr      r1,   =CFG_GPSR2_VAL
+   str      r1,   [r0]
+
+   /* General purpose clear registers */
+   ldr      r0,   =GPCR0
+   ldr      r1,   =CFG_GPCR0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPCR1
+   ldr      r1,   =CFG_GPCR1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPCR2
+   ldr      r1,   =CFG_GPCR2_VAL
+   str      r1,   [r0]
+
+   /* General rising edge registers */
+   ldr      r0,   =GRER0
+   ldr      r1,   =CFG_GRER0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GRER1
+   ldr      r1,   =CFG_GRER1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GRER2
+   ldr      r1,   =CFG_GRER2_VAL
+   str      r1,   [r0]
+
+   /* General falling edge registers */
+   ldr      r0,   =GFER0
+   ldr      r1,   =CFG_GFER0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GFER1
+   ldr      r1,   =CFG_GFER1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GFER2
+   ldr      r1,   =CFG_GFER2_VAL
+   str      r1,   [r0]
+
+   /* General edge detect registers */
+   ldr      r0,   =GPDR0
+   ldr      r1,   =CFG_GPDR0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPDR1
+   ldr      r1,   =CFG_GPDR1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPDR2
+   ldr      r1,   =CFG_GPDR2_VAL
+   str      r1,   [r0]
+
+   /* General alternate function registers */
+   ldr      r0,   =GAFR0_L		/* [0:15] */
+   ldr      r1,   =CFG_GAFR0_L_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR0_U		/* [31:16] */
+   ldr      r1,   =CFG_GAFR0_U_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR1_L		/* [47:32] */
+   ldr      r1,   =CFG_GAFR1_L_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR1_U		/* [63:48] */
+   ldr      r1,   =CFG_GAFR1_U_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR2_L		/* [79:64] */
+   ldr      r1,   =CFG_GAFR2_L_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GAFR2_U		/* [80] */
+   ldr      r1,   =CFG_GAFR2_U_VAL
+   str      r1,   [r0]
+
+   /* General purpose direction registers */
+   ldr      r0,   =GPDR0
+   ldr      r1,   =CFG_GPDR0_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPDR1
+   ldr      r1,   =CFG_GPDR1_VAL
+   str      r1,   [r0]
+   ldr      r0,   =GPDR2
+   ldr      r1,   =CFG_GPDR2_VAL
+   str      r1,   [r0]
+
+   /* Power manager sleep status */
+   ldr      r0,   =PSSR
+   ldr      r1,   =CFG_PSSR_VAL
+   str      r1,   [r0]
+
+/* ---- MEMORY INITIALISATION ---- */
+/* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */
+/* pause for 200 uSecs- allow internal clocks to settle */
+   ldr r3, =OSCR	/* reset the OS Timer Count to zero */
+   mov r2, #0
+   str r2, [r3]
+   ldr r4, =0x300  	/* really 0x2E1 is about 200usec, so 0x300 should be plenty */
+1:
+   ldr r2, [r3]
+   cmp r4, r2
+   bgt 1b
+
+mem_init:
+/* get memory controller base address */
+   ldr     r1,  =MEMC_BASE
+
+/* ---- FLASH INITIALISATION ---- */
+/* Write MSC0 and read back to ensure data change is accepted by cpu */
+   ldr     r2,   =CFG_MSC0_VAL
+   str     r2,   [r1, #MSC0_OFFSET]
+   ldr     r2,   [r1, #MSC0_OFFSET]
+
+/* ---- SDRAM INITIALISATION ---- */
+/* get the MDREFR settings */
+   ldr     r2,  =CFG_MDREFR_VAL
+   str     r2,  [r1, #MDREFR_OFFSET]
+
+/* fetch platform value of MDCNFG */
+   ldr     r2,  =CFG_MDCNFG_VAL
+
+/* disable all sdram banks */
+   bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
+   bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)
+
+/* write initial value of MDCNFG, w/o enabling sdram banks */
+   str     r2,  [r1, #MDCNFG_OFFSET]
+
+/* pause for 200 uSecs */
+   ldr r3, =OSCR	/* reset the OS Timer Count to zero */
+   mov r2, #0
+   str r2, [r3]
+   ldr r4, =0x300  	/* about 200 usec */
+1:
+   ldr r2, [r3]
+   cmp r4, r2
+   bgt 1b
+
+/* Access memory *not yet enabled* for CBR refresh cycles (8) */
+/* CBR is generated for all banks */
+
+   ldr     r2, =CFG_DRAM_BASE
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+   str     r2, [r2]
+
+/* get memory controller base address */
+   ldr     r2,  =MEMC_BASE
+
+/* Enable SDRAM bank 0 in MDCNFG register */
+   ldr     r2,  [r1, #MDCNFG_OFFSET]
+   orr     r2,  r2,  #MDCNFG_DE0
+   str     r2,  [r1, #MDCNFG_OFFSET]
+
+/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
+   ldr     r2,  =CFG_MDMRS_VAL
+   str     r2,  [r1, #MDMRS_OFFSET]
+
+/* ---- INTERRUPT INITIALISATION ---- */
+/* Disable (mask) all interrupts at the interrupt controller */
+/* clear the interrupt level register (use IRQ, not FIQ) */
+   mov     r1, #0
+   ldr     r2,  =ICLR
+   str     r1,  [r2]
+
+/* Set interrupt mask register */
+   ldr     r1,  =CFG_ICMR_VAL
+   ldr     r2,  =ICMR
+   str     r1,  [r2]
+
+/* ---- CLOCK INITIALISATION ---- */
+/* Disable the peripheral clocks, and set the core clock */
+
+/* Turn Off ALL on-chip peripheral clocks for re-configuration */
+   ldr     r1,  =CKEN
+   mov     r2,  #0
+   str     r2,  [r1]
+
+/* set core clocks */
+   ldr     r2,  =CFG_CCCR_VAL
+   ldr     r1,  =CCCR
+   str     r2,  [r1]
+
+#ifdef ENABLE32KHZ
+/* enable the 32Khz oscillator for RTC and PowerManager */
+   ldr     r1,  =OSCC
+   mov     r2,  #OSCC_OON
+   str     r2,  [r1]
+
+/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL has settled. */
+60:
+   ldr     r2, [r1]
+   ands    r2, r2, #1
+   beq     60b
+#endif
+
+/* Turn on needed clocks */
+   ldr     r1,  =CKEN
+   ldr     r2,  =CFG_CKEN_VAL
+   str     r2,  [r1]
+
+   mov   pc, r10
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number */
+	gd->bd->bi_arch_number = 532;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_post_init (void)
+{
+	setenv ("stdout", "serial");
+	setenv ("stderr", "serial");
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
@@ -76,6 +76,16 @@
  
 #ifdef CONFIG_PXA250
  
+#ifdef CONFIG_XSENGINE
+#define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
+#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))))
+#define SMC_inb(p)	({ \
+	unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \
+	unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
+	if (__p & 2) __v >>= 8; \
+	else __v &= 0xff; \
+	__v; })
+#else
 #define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
 #define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
 #define SMC_inb(p)	({ \
  
  
@@ -84,9 +94,16 @@
 	if (__p & 1) __v >>= 8; \
 	else __v &= 0xff; \
 	__v; })
+#endif
  
+#ifdef CONFIG_XSENGINE
+#define	SMC_outl(d,r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d)
+#define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))) = d)
+#else
 #define	SMC_outl(d,r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
 #define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
+#endif
+
 #define	SMC_outb(d,r)	({	word __d = (byte)(d);  \
 				word __w = SMC_inw((r)&~1);  \
 				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
  
@@ -191,7 +208,11 @@
  
 #if defined(CONFIG_SMC_USE_32_BIT)
  
+#ifdef CONFIG_XSENGINE
+#define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
+#else
 #define	SMC_inl(r) 	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
+#endif
  
 #define SMC_insl(r,b,l) 	({	int __i ;  \
 					dword *__b2;  \
  
@@ -202,8 +223,11 @@
 					};  \
 				})
  
+#ifdef CONFIG_XSENGINE
+#define	SMC_outl(d,r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d)
+#else
 #define	SMC_outl(d,r)	(*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
-
+#endif
 #define SMC_outsl(r,b,l)	({	int __i; \
 					dword *__b2; \
 					__b2 = (dword *) b; \
@@ -150,7 +150,7 @@
 #define PHYS_FLASH_1_BM0	0x0C000000	/* Flash Bank #1 if booting from RAM */
  
 #ifdef CONFIG_CS_AUTOBOOT			/* Determine CS assignment in runtime */
-				
+
 #ifndef __ASSEMBLY__
 extern unsigned long omap_flash_base;		/* set in flash__init */
 #endif
@@ -155,7 +155,7 @@
 #define PHYS_FLASH_1_BM0	0x0C000000	/* Flash Bank #1 if booting from RAM */
  
 #ifdef CONFIG_CS_AUTOBOOT			/* Determine CS assignment in runtime */
-				
+
 #ifndef __ASSEMBLY__
 extern unsigned long omap_flash_base;		/* set in flash__init */
 #endif
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#define CONFIG_INIT_CRITICAL				/* undef for developing */
+
+/* High Level Configuration Options */
+#define CONFIG_PXA250			1		/* This is an PXA250 CPU    */
+#define CONFIG_XSENGINE			1
+#define CONFIG_MMC			1
+#define BOARD_POST_INIT			1
+#undef  CONFIG_USE_IRQ					/* we don't need IRQ/FIQ stuff */
+#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
+
+#undef  CONFIG_USE_IRQ					/* we don't need IRQ/FIQ stuff */
+#define CFG_HZ				3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED			0x161           /* set core clock to 400/200/100 MHz */
+
+#define CONFIG_NR_DRAM_BANKS		1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
+#define PHYS_SDRAM_2			0xa4000000	/* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 MB */
+#define PHYS_SDRAM_3			0xa8000000	/* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE		0x00000000	/* 0 MB */
+#define PHYS_SDRAM_4			0xac000000	/* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE		0x00000000	/* 0 MB */
+#define CFG_DRAM_BASE			0xa0000000
+#define CFG_DRAM_SIZE			0x04000000
+
+/* FLASH organization */
+#define CFG_MAX_FLASH_BANKS		1		/* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT		128		/* max number of sectors on one chip    */
+#define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
+#define PHYS_FLASH_2			0x00000000	/* Flash Bank #2 */
+#define PHYS_FLASH_SECT_SIZE		0x00020000	/* 127 KB sectors */
+#define CFG_FLASH_BASE			PHYS_FLASH_1
+#define CFG_JFFS2_NUM_BANKS		1
+#define CFG_JFFS2_FIRST_BANK		0
+#define CFG_JFFS_CUSTOM_PART		1
+
+/* Environment settings */
+#define CONFIG_ENV_OVERWRITE
+#define CFG_ENV_IS_IN_FLASH             1
+#define CFG_ENV_ADDR                    (PHYS_FLASH_1 + 0x40000)	/* Addr of Environment Sector (after monitor)*/
+#define CFG_ENV_SECT_SIZE               PHYS_FLASH_SECT_SIZE		/* Size of the Environment Sector */
+#define CFG_ENV_SIZE                    0x4000				/* 16kB Total Size of Environment Sector */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT		(75*CFG_HZ) 	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT		(50*CFG_HZ) 	/* Timeout for Flash Write */
+
+/* Size of malloc() pool */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 256*1024)
+#define CFG_GBL_DATA_SIZE		128		/* size in bytes reserved for initial data */
+
+/* Hardware drivers */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE		0x04000300
+#define CONFIG_SMC_USE_32_BIT 		1
+
+/* select serial console configuration */
+#define CONFIG_FFUART			1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_COMMANDS			(CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_PING | CFG_CMD_JFFS2)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ETHADDR			FF:FF:FF:FF:FF:FF
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_IPADDR			192.168.1.50
+#define CONFIG_SERVERIP			192.168.1.2
+#define CONFIG_BOOTARGS			"root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
+#define CONFIG_CMDLINE_TAG
+
+/* Miscellaneous configurable options */
+#define CFG_HUSH_PARSER			1
+#define CFG_PROMPT_HUSH_PS2		"> "
+#define CFG_LONGHELP								/* undef to save memory	*/
+#define CFG_PROMPT			"XS-Engine u-boot> "			/* Monitor Command Prompt */
+#define CFG_CBSIZE			256					/* Console I/O Buffer Size */
+#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) 	/* Print Buffer Size */
+#define CFG_MAXARGS			16					/* max number of command args */
+#define CFG_BARGSIZE			CFG_CBSIZE				/* Boot Argument Buffer Size */
+#define CFG_MEMTEST_START		0xA0400000				/* memtest works on     */
+#define CFG_MEMTEST_END			0xA0800000				/* 4 ... 8 MB in DRAM   */
+#undef  CFG_CLKS_IN_HZ          						/* everything, incl board info, in Hz */
+#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }	/* valid baudrates */
+#define CFG_MMC_BASE			0xF0000000
+#define CFG_LOAD_ADDR           	0xA0000000				/* load kernel to this address   */
+
+/* Stack sizes - The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
+#ifdef  CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
+#endif
+
+/* GP set register */
+#define CFG_GPSR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
+#define CFG_GPSR1_VAL			0x00020000	/* nPWE */
+#define CFG_GPSR2_VAL			0x0000C000	/* CS2, CS3 */
+
+/* GP clear register */
+#define CFG_GPCR0_VAL			0x00000000
+#define CFG_GPCR1_VAL			0x00000000
+#define CFG_GPCR2_VAL			0x00000000
+
+/* GP direction register */
+#define CFG_GPDR0_VAL			0x0000A000	/* CS1, PROG(FPGA) */
+#define CFG_GPDR1_VAL			0x00022A80	/* nPWE, FFUART + BTUART pins */
+#define CFG_GPDR2_VAL			0x0000C000  	/* CS2, CS3 */
+
+/* GP rising edge detect register */
+#define CFG_GRER0_VAL			0x00000000
+#define CFG_GRER1_VAL			0x00000000
+#define CFG_GRER2_VAL			0x00000000
+
+/* GP falling edge detect register */
+#define CFG_GFER0_VAL			0x00000000
+#define CFG_GFER1_VAL			0x00000000
+#define CFG_GFER2_VAL			0x00000000
+
+/* GP alternate function register */
+#define CFG_GAFR0_L_VAL			0x80000000	/* CS1 */
+#define CFG_GAFR0_U_VAL			0x00000010	/* RDY */
+#define CFG_GAFR1_L_VAL			0x09988050	/* FFUART + BTUART pins */
+#define CFG_GAFR1_U_VAL			0x00000008	/* nPWE */
+#define CFG_GAFR2_L_VAL			0xA0000000  	/* CS2, CS3 */
+#define CFG_GAFR2_U_VAL			0x00000000
+
+#define CFG_PSSR_VAL			0x00000020	/* Power manager sleep status */
+#define CFG_CCCR_VAL			0x00000161	/* 100 MHz memory, 400 MHz CPU  */
+#define CFG_CKEN_VAL			0x000000C0	/* BTUART and FFUART enabled    */
+#define CFG_ICMR_VAL			0x00000000	/* No interrupts enabled        */
+
+/* Memory settings */
+#define CFG_MSC0_VAL			0x25F425F0
+
+/* MDCNFG: SDRAM Configuration Register */
+#define CFG_MDCNFG_VAL			0x000009C9
+
+/* MDREFR: SDRAM Refresh Control Register */
+#define CFG_MDREFR_VAL			0x00018018
+
+/* MDMRS: Mode Register Set Configuration Register */
+#define CFG_MDMRS_VAL			0x00220022
+
+#endif	/* __CONFIG_H */
...	...	@@ -2,6 +2,9 @@
2	2	Changes since U-Boot 1.1.1:
3	3	======================================================================
4	4
	5	+* Patch by Kurt Stremerch, 28 May 2004:
	6	+ Add support for Exys XSEngine board
	7	+
5	8	* Patch by Martin Krause, 27 May 2004:
6	9	Fix a MPC5xxx I2C timing issue in i2c_probe().
7	10
...	...	@@ -319,6 +319,10 @@
319	319	E: r.schwebel@pengutronix.de
320	320	D: Support for csb226, logodl and innokom boards (PXA2xx)
321	321
	322	+N: Kurt Stremerch
	323	+E: kurt@exys.be
	324	+D: Support for Exys XSEngine board
	325	+
322	326	N: Rob Taylor
323	327	E: robt@flyingpig.com
324	328	D: Port to MBX860T and Sandpoint8240
...	...	@@ -149,7 +149,7 @@
149	149	## Xscale Systems
150	150	#########################################################################
151	151
152		-LIST_pxa="cradle csb226 innokom lubbock wepep250 xm250"
	152	+LIST_pxa="cradle csb226 innokom lubbock wepep250 xm250 xsengine"
153	153
154	154	LIST_ixp="ixdp425"
155	155
...	...	@@ -1166,6 +1166,9 @@
1166	1166	xm250_config : unconfig
1167	1167	@./mkconfig $(@:_config=) arm pxa xm250
1168	1168
	1169	+xsengine_config : unconfig
	1170	+ @./mkconfig $(@:_config=) arm pxa xsengine
	1171	+
1169	1172	#========================================================================
1170	1173	# i386
1171	1174	#========================================================================
...	...	@@ -102,8 +102,8 @@
102	102
103	103	#ifdef CONFIG_CS_AUTOBOOT
104	104	/* Check swapping of CS0 and CS3, set flash base accordingly */
105		- omap_flash_base = ((((u32 )OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
106		- PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
	105	+ omap_flash_base = ((((u32 )OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ?
	106	+ PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1;
107	107	#endif
108	108	regval = ((volatile unsigned int ) EMIFS_GlB_Config_REG);
109	109	/* Turn off write protection for flash devices. */
	1	+#
	2	+# (C) Copyright 2000-2004
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+include $(TOPDIR)/config.mk
	25	+
	26	+LIB = lib$(BOARD).a
	27	+
	28	+OBJS := xsengine.o flash.o
	29	+SOBJS := memsetup.o
	30	+
	31	+$(LIB): $(OBJS) $(SOBJS)
	32	+ $(AR) crv $@ $(OBJS) $(SOBJS)
	33	+
	34	+clean:
	35	+ rm -f $(SOBJS) $(OBJS)
	36	+
	37	+distclean: clean
	38	+ rm -f $(LIB) core *.bak .depend
	39	+
	40	+#########################################################################
	41	+
	42	+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
	43	+ $(CC) -M --disassemble-all $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
	44	+
	45	+-include .depend
	46	+
	47	+#########################################################################
	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de>
	4	+ *
	5	+ * (C) Copyright 2000-2004
	6	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	+ *
	8	+ * See file CREDITS for list of people who contributed to this
	9	+ * project.
	10	+ *
	11	+ * This program is free software; you can redistribute it and/or
	12	+ * modify it under the terms of the GNU General Public License as
	13	+ * published by the Free Software Foundation; either version 2 of
	14	+ * the License, or (at your option) any later version.
	15	+ *
	16	+ * This program is distributed in the hope that it will be useful,
	17	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	+ * GNU General Public License for more details.
	20	+ *
	21	+ * You should have received a copy of the GNU General Public License
	22	+ * along with this program; if not, write to the Free Software
	23	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	+ * MA 02111-1307 USA
	25	+ */
	26	+
	27	+#include <common.h>
	28	+#include <linux/byteorder/swab.h>
	29	+
	30	+#if defined CFG_JFFS_CUSTOM_PART
	31	+#include <jffs2/jffs2.h>
	32	+#endif
	33	+
	34	+#define SWAP(x) __swab32(x)
	35	+
	36	+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
	37	+
	38	+/* Functions */
	39	+static ulong flash_get_size (vu_long addr, flash_info_t info);
	40	+static int write_word (flash_info_t *info, ulong dest, ulong data);
	41	+static void flash_get_offsets (ulong base, flash_info_t *info);
	42	+
	43	+#if defined CFG_JFFS_CUSTOM_PART
	44	+
	45	+/*
	46	+ * jffs2_part_info - get information about a JFFS2 partition
	47	+ *
	48	+ * @part_num: number of the partition you want to get info about
	49	+ * @return: struct part_info* in case of success, 0 if failure
	50	+ */
	51	+
	52	+static struct part_info part;
	53	+static int current_part = -1;
	54	+
	55	+struct part_info* jffs2_part_info(int part_num) {
	56	+ void *jffs2_priv_saved = part.jffs2_priv;
	57	+
	58	+ printf("jffs2_part_info: part_num=%i\n",part_num);
	59	+
	60	+ if (current_part == part_num)
	61	+ return ∂
	62	+
	63	+ /* u-boot partition */
	64	+ if(part_num==0){
	65	+ memset(&part, 0, sizeof(part));
	66	+
	67	+ part.offset=(char*)0x00000000;
	68	+ part.size=256*1024;
	69	+
	70	+ /* Mark the struct as ready */
	71	+ current_part = part_num;
	72	+
	73	+ printf("part.offset = 0x%08x\n",(unsigned int)part.offset);
	74	+ printf("part.size = 0x%08x\n",(unsigned int)part.size);
	75	+ }
	76	+
	77	+ /* primary OS+firmware partition */
	78	+ if(part_num==1){
	79	+ memset(&part, 0, sizeof(part));
	80	+
	81	+ part.offset=(char*)0x00040000;
	82	+ part.size=1024*1024;
	83	+
	84	+ /* Mark the struct as ready */
	85	+ current_part = part_num;
	86	+
	87	+ printf("part.offset = 0x%08x\n",(unsigned int)part.offset);
	88	+ printf("part.size = 0x%08x\n",(unsigned int)part.size);
	89	+ }
	90	+
	91	+ /* secondary OS+firmware partition */
	92	+ if(part_num==2){
	93	+ memset(&part, 0, sizeof(part));
	94	+
	95	+ part.offset=(char*)0x00140000;
	96	+ part.size=810241024;
	97	+
	98	+ /* Mark the struct as ready */
	99	+ current_part = part_num;
	100	+
	101	+ printf("part.offset = 0x%08x\n",(unsigned int)part.offset);
	102	+ printf("part.size = 0x%08x\n",(unsigned int)part.size);
	103	+ }
	104	+
	105	+ if (current_part == part_num) {
	106	+ part.usr_priv = &current_part;
	107	+ part.jffs2_priv = jffs2_priv_saved;
	108	+ return ∂
	109	+ }
	110	+
	111	+ printf("jffs2_part_info: end of partition table\n");
	112	+ return 0;
	113	+}
	114	+#endif
	115	+
	116	+
	117	+/*-----------------------------------------------------------------------
	118	+ */
	119	+unsigned long flash_init (void)
	120	+{
	121	+ int i;
	122	+ ulong size = 0;
	123	+
	124	+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
	125	+ switch (i) {
	126	+ case 0:
	127	+ flash_get_size ((long *) PHYS_FLASH_1, &flash_info[i]);
	128	+ flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
	129	+ break;
	130	+ case 1:
	131	+ flash_get_size ((long *) PHYS_FLASH_2, &flash_info[i]);
	132	+ flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
	133	+ break;
	134	+ default:
	135	+ panic ("configured too many flash banks!\n");
	136	+ break;
	137	+ }
	138	+ size += flash_info[i].size;
	139	+ }
	140	+
	141	+ /* Protect monitor and environment sectors */
	142	+ flash_protect ( FLAG_PROTECT_SET,CFG_FLASH_BASE,CFG_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] );
	143	+ flash_protect ( FLAG_PROTECT_SET,CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
	144	+
	145	+ return size;
	146	+}
	147	+
	148	+/*-----------------------------------------------------------------------
	149	+ */
	150	+static void flash_get_offsets (ulong base, flash_info_t *info)
	151	+{
	152	+ int i;
	153	+
	154	+ if (info->flash_id == FLASH_UNKNOWN) return;
	155	+
	156	+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
	157	+ for (i = 0; i < info->sector_count; i++) {
	158	+ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
	159	+ info->protect[i] = 0;
	160	+ }
	161	+ }
	162	+}
	163	+
	164	+/*-----------------------------------------------------------------------
	165	+ */
	166	+void flash_print_info (flash_info_t *info)
	167	+{
	168	+ int i;
	169	+
	170	+ if (info->flash_id == FLASH_UNKNOWN) {
	171	+ printf ("missing or unknown FLASH type\n");
	172	+ return;
	173	+ }
	174	+
	175	+ switch (info->flash_id & FLASH_VENDMASK) {
	176	+ case FLASH_MAN_AMD: printf ("AMD "); break;
	177	+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
	178	+ default: printf ("Unknown Vendor "); break;
	179	+ }
	180	+
	181	+ switch (info->flash_id & FLASH_TYPEMASK) {
	182	+ case FLASH_AMLV128U: printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
	183	+ break;
	184	+ case FLASH_AMLV320U: printf ("AM29LV320ML (32Mbit, uniform sector size)\n");
	185	+ break;
	186	+ case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
	187	+ break;
	188	+ case FLASH_AMLV320B: printf ("AM29LV320MB (32Mbit, bottom boot sect)\n");
	189	+ break;
	190	+ default: printf ("Unknown Chip Type\n");
	191	+ break;
	192	+ }
	193	+
	194	+ printf (" Size: %ld MB in %d Sectors\n",
	195	+ info->size >> 20, info->sector_count);
	196	+
	197	+ printf (" Sector Start Addresses:");
	198	+ for (i=0; i<info->sector_count; ++i) {
	199	+ if ((i % 5) == 0)
	200	+ printf ("\n ");
	201	+ printf (" %08lX%s",
	202	+ info->start[i],
	203	+ info->protect[i] ? " (RO)" : " "
	204	+ );
	205	+ }
	206	+ printf ("\n");
	207	+ return;
	208	+}
	209	+
	210	+/*
	211	+ * The following code cannot be run from FLASH!
	212	+ */
	213	+static ulong flash_get_size (vu_long addr, flash_info_t info)
	214	+{
	215	+ short i;
	216	+ ulong value;
	217	+ ulong base = (ulong)addr;
	218	+
	219	+ /* Write auto select command: read Manufacturer ID */
	220	+ addr[0x0555] = 0x00AA00AA;
	221	+ addr[0x02AA] = 0x00550055;
	222	+ addr[0x0555] = 0x00900090;
	223	+
	224	+ value = addr[0];
	225	+
	226	+ debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
	227	+
	228	+ switch (value) {
	229	+ case AMD_MANUFACT:
	230	+ debug ("Manufacturer: AMD\n");
	231	+ info->flash_id = FLASH_MAN_AMD;
	232	+ break;
	233	+ case FUJ_MANUFACT:
	234	+ debug ("Manufacturer: FUJITSU\n");
	235	+ info->flash_id = FLASH_MAN_FUJ;
	236	+ break;
	237	+ default:
	238	+ debug ("Manufacturer: * unknown *\n");
	239	+ info->flash_id = FLASH_UNKNOWN;
	240	+ info->sector_count = 0;
	241	+ info->size = 0;
	242	+ return (0); /* no or unknown flash */
	243	+ }
	244	+
	245	+ value = addr[1]; /* device ID */
	246	+
	247	+ debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
	248	+
	249	+ switch (value) {
	250	+
	251	+ case AMD_ID_MIRROR:
	252	+ debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
	253	+ addr[14], addr[15]);
	254	+ switch(addr[14]) {
	255	+ case AMD_ID_LV128U_2:
	256	+ if (addr[15] != AMD_ID_LV128U_3) {
	257	+ debug ("Chip: AMLV128U -> unknown\n");
	258	+ info->flash_id = FLASH_UNKNOWN;
	259	+ } else {
	260	+ debug ("Chip: AMLV128U\n");
	261	+ info->flash_id += FLASH_AMLV128U;
	262	+ info->sector_count = 256;
	263	+ info->size = 0x02000000;
	264	+ }
	265	+ break; /* => 32 MB */
	266	+ case AMD_ID_LV640U_2:
	267	+ if (addr[15] != AMD_ID_LV640U_3) {
	268	+ debug ("Chip: AMLV640U -> unknown\n");
	269	+ info->flash_id = FLASH_UNKNOWN;
	270	+ } else {
	271	+ debug ("Chip: AMLV640U\n");
	272	+ info->flash_id += FLASH_AMLV640U;
	273	+ info->sector_count = 128;
	274	+ info->size = 0x01000000;
	275	+ }
	276	+ break; /* => 16 MB */
	277	+ case AMD_ID_LV320B_2:
	278	+ if (addr[15] != AMD_ID_LV320B_3) {
	279	+ debug ("Chip: AMLV320B -> unknown\n");
	280	+ info->flash_id = FLASH_UNKNOWN;
	281	+ } else {
	282	+ debug ("Chip: AMLV320B\n");
	283	+ info->flash_id += FLASH_AMLV320B;
	284	+ info->sector_count = 71;
	285	+ info->size = 0x00800000;
	286	+ }
	287	+ break; /* => 8 MB */
	288	+ default:
	289	+ debug ("Chip: * unknown *\n");
	290	+ info->flash_id = FLASH_UNKNOWN;
	291	+ break;
	292	+ }
	293	+ break;
	294	+
	295	+ default:
	296	+ info->flash_id = FLASH_UNKNOWN;
	297	+ return (0); /* => no or unknown flash */
	298	+ }
	299	+
	300	+ /* set up sector start address table */
	301	+ switch (value) {
	302	+ case AMD_ID_MIRROR:
	303	+ switch (info->flash_id & FLASH_TYPEMASK) {
	304	+ /* only known types here - no default */
	305	+ case FLASH_AMLV128U:
	306	+ case FLASH_AMLV640U:
	307	+ case FLASH_AMLV320U:
	308	+ for (i = 0; i < info->sector_count; i++) {
	309	+ info->start[i] = base;
	310	+ base += 0x20000;
	311	+ }
	312	+ break;
	313	+ case FLASH_AMLV320B:
	314	+ for (i = 0; i < info->sector_count; i++) {
	315	+ info->start[i] = base;
	316	+ /*
	317	+ * The first 8 sectors are 8 kB,
	318	+ * all the other ones are 64 kB
	319	+ */
	320	+ base += (i < 8)
	321	+ ? 2 * ( 8 << 10)
	322	+ : 2 * (64 << 10);
	323	+ }
	324	+ break;
	325	+ }
	326	+ break;
	327	+
	328	+ default:
	329	+ return (0);
	330	+ break;
	331	+ }
	332	+
	333	+#if 0
	334	+ /* check for protected sectors */
	335	+ for (i = 0; i < info->sector_count; i++) {
	336	+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
	337	+ /* D0 = 1 if protected */
	338	+ addr = (volatile unsigned long *)(info->start[i]);
	339	+ info->protect[i] = addr[2] & 1;
	340	+ }
	341	+#endif
	342	+
	343	+ /*
	344	+ * Prevent writes to uninitialized FLASH.
	345	+ */
	346	+ if (info->flash_id != FLASH_UNKNOWN) {
	347	+ addr = (volatile unsigned long *)info->start[0];
	348	+
	349	+ addr = 0x00F000F0; / reset bank */
	350	+ }
	351	+
	352	+ return (info->size);
	353	+}
	354	+
	355	+
	356	+/*-----------------------------------------------------------------------
	357	+ */
	358	+
	359	+int flash_erase (flash_info_t *info, int s_first, int s_last)
	360	+{
	361	+ vu_long addr = (vu_long)(info->start[0]);
	362	+ int flag, prot, sect, l_sect;
	363	+ ulong start, now, last;
	364	+
	365	+ debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
	366	+
	367	+ if ((s_first < 0) \|\| (s_first > s_last)) {
	368	+ if (info->flash_id == FLASH_UNKNOWN) {
	369	+ printf ("- missing\n");
	370	+ } else {
	371	+ printf ("- no sectors to erase\n");
	372	+ }
	373	+ return 1;
	374	+ }
	375	+
	376	+ if ((info->flash_id == FLASH_UNKNOWN) \|\|
	377	+ (info->flash_id > FLASH_AMD_COMP)) {
	378	+ printf ("Can't erase unknown flash type %08lx - aborted\n",
	379	+ info->flash_id);
	380	+ return 1;
	381	+ }
	382	+
	383	+ prot = 0;
	384	+ for (sect=s_first; sect<=s_last; ++sect) {
	385	+ if (info->protect[sect]) {
	386	+ prot++;
	387	+ }
	388	+ }
	389	+
	390	+ if (prot) {
	391	+ printf ("- Warning: %d protected sectors will not be erased!\n",
	392	+ prot);
	393	+ } else {
	394	+ printf ("\n");
	395	+ }
	396	+
	397	+ l_sect = -1;
	398	+
	399	+ /* Disable interrupts which might cause a timeout here */
	400	+ flag = disable_interrupts();
	401	+
	402	+ addr[0x0555] = 0x00AA00AA;
	403	+ addr[0x02AA] = 0x00550055;
	404	+ addr[0x0555] = 0x00800080;
	405	+ addr[0x0555] = 0x00AA00AA;
	406	+ addr[0x02AA] = 0x00550055;
	407	+
	408	+ /* Start erase on unprotected sectors */
	409	+ for (sect = s_first; sect<=s_last; sect++) {
	410	+ if (info->protect[sect] == 0) { /* not protected */
	411	+ addr = (vu_long*)(info->start[sect]);
	412	+ addr[0] = 0x00300030;
	413	+ l_sect = sect;
	414	+ }
	415	+ }
	416	+
	417	+ /* re-enable interrupts if necessary */
	418	+ if (flag)
	419	+ enable_interrupts();
	420	+
	421	+ /* wait at least 80us - let's wait 1 ms */
	422	+ udelay (1000);
	423	+
	424	+ /*
	425	+ * We wait for the last triggered sector
	426	+ */
	427	+ if (l_sect < 0)
	428	+ goto DONE;
	429	+
	430	+ start = get_timer (0);
	431	+ last = start;
	432	+ addr = (vu_long*)(info->start[l_sect]);
	433	+ while ((addr[0] & 0x00800080) != 0x00800080) {
	434	+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
	435	+ printf ("Timeout\n");
	436	+ return 1;
	437	+ }
	438	+ /* show that we're waiting */
	439	+ if ((now - last) > 100000) { /* every second */
	440	+ putc ('.');
	441	+ last = now;
	442	+ }
	443	+ }
	444	+
	445	+DONE:
	446	+ /* reset to read mode */
	447	+ addr = (volatile unsigned long *)info->start[0];
	448	+ addr[0] = 0x00F000F0; /* reset bank */
	449	+
	450	+ printf (" done\n");
	451	+ return 0;
	452	+}
	453	+
	454	+/*-----------------------------------------------------------------------
	455	+ * Copy memory to flash, returns:
	456	+ * 0 - OK
	457	+ * 1 - write timeout
	458	+ * 2 - Flash not erased
	459	+ */
	460	+
	461	+int write_buff (flash_info_t info, uchar src, ulong addr, ulong cnt)
	462	+{
	463	+ ulong cp, wp, data;
	464	+ int i, l, rc;
	465	+
	466	+ wp = (addr & ~3); /* get lower word aligned address */
	467	+
	468	+ /*
	469	+ * handle unaligned start bytes
	470	+ */
	471	+ if ((l = addr - wp) != 0) {
	472	+ data = 0;
	473	+ for (i=0, cp=wp; i<l; ++i, ++cp) {
	474	+ data = (data << 8) \| ((uchar )cp);
	475	+ }
	476	+ for (; i<4 && cnt>0; ++i) {
	477	+ data = (data << 8) \| *src++;
	478	+ --cnt;
	479	+ ++cp;
	480	+ }
	481	+ for (; cnt==0 && i<4; ++i, ++cp) {
	482	+ data = (data << 8) \| ((uchar )cp);
	483	+ }
	484	+
	485	+ if ((rc = write_word(info, wp, SWAP(data))) != 0) {
	486	+ return (rc);
	487	+ }
	488	+ wp += 4;
	489	+ }
	490	+
	491	+ /*
	492	+ * handle word aligned part
	493	+ */
	494	+ while (cnt >= 4) {
	495	+ data = 0;
	496	+ for (i=0; i<4; ++i) {
	497	+ data = (data << 8) \| *src++;
	498	+ }
	499	+ if ((rc = write_word(info, wp, SWAP(data))) != 0) {
	500	+ return (rc);
	501	+ }
	502	+ wp += 4;
	503	+ cnt -= 4;
	504	+ }
	505	+
	506	+ if (cnt == 0) {
	507	+ return (0);
	508	+ }
	509	+
	510	+ /*
	511	+ * handle unaligned tail bytes
	512	+ */
	513	+ data = 0;
	514	+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
	515	+ data = (data << 8) \| *src++;
	516	+ --cnt;
	517	+ }
	518	+ for (; i<4; ++i, ++cp) {
	519	+ data = (data << 8) \| ((uchar )cp);
	520	+ }
	521	+
	522	+ return (write_word(info, wp, SWAP(data)));
	523	+}
	524	+
	525	+/*-----------------------------------------------------------------------
	526	+ * Write a word to Flash, returns:
	527	+ * 0 - OK
	528	+ * 1 - write timeout
	529	+ * 2 - Flash not erased
	530	+ */
	531	+static int write_word (flash_info_t *info, ulong dest, ulong data)
	532	+{
	533	+ vu_long addr = (vu_long)(info->start[0]);
	534	+ ulong start;
	535	+ ulong rev;
	536	+ int flag;
	537	+ int i;
	538	+
	539	+ /* Check if Flash is (sufficiently) erased */
	540	+ if ((((vu_long )dest) & data) != data) {
	541	+ return (2);
	542	+ }
	543	+
	544	+ /* Disable interrupts which might cause a timeout here */
	545	+ flag = disable_interrupts();
	546	+
	547	+ addr[0x0555] = 0x00AA00AA;
	548	+ addr[0x02AA] = 0x00550055;
	549	+ addr[0x0555] = 0x00A000A0;
	550	+
	551	+ ((vu_long )dest) = data;
	552	+
	553	+ /* re-enable interrupts if necessary */
	554	+ if (flag)
	555	+ enable_interrupts();
	556	+
	557	+ /* data polling for D7 */
	558	+ start = get_timer (0);
	559	+ while ((((vu_long )dest) & 0x00800080) != (data & 0x00800080)) {
	560	+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
	561	+ return (1);
	562	+ }
	563	+ }
	564	+ return (0);
	565	+}
	1	+#include <config.h>
	2	+#include <version.h>
	3	+#include <asm/arch/pxa-regs.h>
	4	+
	5	+DRAM_SIZE: .long CFG_DRAM_SIZE
	6	+
	7	+.globl memsetup
	8	+memsetup:
	9	+
	10	+ mov r10, lr
	11	+
	12	+/* ---- GPIO INITIALISATION ---- */
	13	+/* Set up GPIO pins first (3 groups [31:0] [63:32] [80:64]) */
	14	+
	15	+ /* General purpose set registers */
	16	+ ldr r0, =GPSR0
	17	+ ldr r1, =CFG_GPSR0_VAL
	18	+ str r1, [r0]
	19	+ ldr r0, =GPSR1
	20	+ ldr r1, =CFG_GPSR1_VAL
	21	+ str r1, [r0]
	22	+ ldr r0, =GPSR2
	23	+ ldr r1, =CFG_GPSR2_VAL
	24	+ str r1, [r0]
	25	+
	26	+ /* General purpose clear registers */
	27	+ ldr r0, =GPCR0
	28	+ ldr r1, =CFG_GPCR0_VAL
	29	+ str r1, [r0]
	30	+ ldr r0, =GPCR1
	31	+ ldr r1, =CFG_GPCR1_VAL
	32	+ str r1, [r0]
	33	+ ldr r0, =GPCR2
	34	+ ldr r1, =CFG_GPCR2_VAL
	35	+ str r1, [r0]
	36	+
	37	+ /* General rising edge registers */
	38	+ ldr r0, =GRER0
	39	+ ldr r1, =CFG_GRER0_VAL
	40	+ str r1, [r0]
	41	+ ldr r0, =GRER1
	42	+ ldr r1, =CFG_GRER1_VAL
	43	+ str r1, [r0]
	44	+ ldr r0, =GRER2
	45	+ ldr r1, =CFG_GRER2_VAL
	46	+ str r1, [r0]
	47	+
	48	+ /* General falling edge registers */
	49	+ ldr r0, =GFER0
	50	+ ldr r1, =CFG_GFER0_VAL
	51	+ str r1, [r0]
	52	+ ldr r0, =GFER1
	53	+ ldr r1, =CFG_GFER1_VAL
	54	+ str r1, [r0]
	55	+ ldr r0, =GFER2
	56	+ ldr r1, =CFG_GFER2_VAL
	57	+ str r1, [r0]
	58	+
	59	+ /* General edge detect registers */
	60	+ ldr r0, =GPDR0
	61	+ ldr r1, =CFG_GPDR0_VAL
	62	+ str r1, [r0]
	63	+ ldr r0, =GPDR1
	64	+ ldr r1, =CFG_GPDR1_VAL
	65	+ str r1, [r0]
	66	+ ldr r0, =GPDR2
	67	+ ldr r1, =CFG_GPDR2_VAL
	68	+ str r1, [r0]
	69	+
	70	+ /* General alternate function registers */
	71	+ ldr r0, =GAFR0_L /* [0:15] */
	72	+ ldr r1, =CFG_GAFR0_L_VAL
	73	+ str r1, [r0]
	74	+ ldr r0, =GAFR0_U /* [31:16] */
	75	+ ldr r1, =CFG_GAFR0_U_VAL
	76	+ str r1, [r0]
	77	+ ldr r0, =GAFR1_L /* [47:32] */
	78	+ ldr r1, =CFG_GAFR1_L_VAL
	79	+ str r1, [r0]
	80	+ ldr r0, =GAFR1_U /* [63:48] */
	81	+ ldr r1, =CFG_GAFR1_U_VAL
	82	+ str r1, [r0]
	83	+ ldr r0, =GAFR2_L /* [79:64] */
	84	+ ldr r1, =CFG_GAFR2_L_VAL
	85	+ str r1, [r0]
	86	+ ldr r0, =GAFR2_U /* [80] */
	87	+ ldr r1, =CFG_GAFR2_U_VAL
	88	+ str r1, [r0]
	89	+
	90	+ /* General purpose direction registers */
	91	+ ldr r0, =GPDR0
	92	+ ldr r1, =CFG_GPDR0_VAL
	93	+ str r1, [r0]
	94	+ ldr r0, =GPDR1
	95	+ ldr r1, =CFG_GPDR1_VAL
	96	+ str r1, [r0]
	97	+ ldr r0, =GPDR2
	98	+ ldr r1, =CFG_GPDR2_VAL
	99	+ str r1, [r0]
	100	+
	101	+ /* Power manager sleep status */
	102	+ ldr r0, =PSSR
	103	+ ldr r1, =CFG_PSSR_VAL
	104	+ str r1, [r0]
	105	+
	106	+/* ---- MEMORY INITIALISATION ---- */
	107	+/* Initialize Memory Controller, see PXA250 Operating System Developer's Guide */
	108	+/* pause for 200 uSecs- allow internal clocks to settle */
	109	+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
	110	+ mov r2, #0
	111	+ str r2, [r3]
	112	+ ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */
	113	+1:
	114	+ ldr r2, [r3]
	115	+ cmp r4, r2
	116	+ bgt 1b
	117	+
	118	+mem_init:
	119	+/* get memory controller base address */
	120	+ ldr r1, =MEMC_BASE
	121	+
	122	+/* ---- FLASH INITIALISATION ---- */
	123	+/* Write MSC0 and read back to ensure data change is accepted by cpu */
	124	+ ldr r2, =CFG_MSC0_VAL
	125	+ str r2, [r1, #MSC0_OFFSET]
	126	+ ldr r2, [r1, #MSC0_OFFSET]
	127	+
	128	+/* ---- SDRAM INITIALISATION ---- */
	129	+/* get the MDREFR settings */
	130	+ ldr r2, =CFG_MDREFR_VAL
	131	+ str r2, [r1, #MDREFR_OFFSET]
	132	+
	133	+/* fetch platform value of MDCNFG */
	134	+ ldr r2, =CFG_MDCNFG_VAL
	135	+
	136	+/* disable all sdram banks */
	137	+ bic r2, r2, #(MDCNFG_DE0 \| MDCNFG_DE1)
	138	+ bic r2, r2, #(MDCNFG_DE2 \| MDCNFG_DE3)
	139	+
	140	+/* write initial value of MDCNFG, w/o enabling sdram banks */
	141	+ str r2, [r1, #MDCNFG_OFFSET]
	142	+
	143	+/* pause for 200 uSecs */
	144	+ ldr r3, =OSCR /* reset the OS Timer Count to zero */
	145	+ mov r2, #0
	146	+ str r2, [r3]
	147	+ ldr r4, =0x300 /* about 200 usec */
	148	+1:
	149	+ ldr r2, [r3]
	150	+ cmp r4, r2
	151	+ bgt 1b
	152	+
	153	+/* Access memory not yet enabled for CBR refresh cycles (8) */
	154	+/* CBR is generated for all banks */
	155	+
	156	+ ldr r2, =CFG_DRAM_BASE
	157	+ str r2, [r2]
	158	+ str r2, [r2]
	159	+ str r2, [r2]
	160	+ str r2, [r2]
	161	+ str r2, [r2]
	162	+ str r2, [r2]
	163	+ str r2, [r2]
	164	+ str r2, [r2]
	165	+
	166	+/* get memory controller base address */
	167	+ ldr r2, =MEMC_BASE
	168	+
	169	+/* Enable SDRAM bank 0 in MDCNFG register */
	170	+ ldr r2, [r1, #MDCNFG_OFFSET]
	171	+ orr r2, r2, #MDCNFG_DE0
	172	+ str r2, [r1, #MDCNFG_OFFSET]
	173	+
	174	+/* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
	175	+ ldr r2, =CFG_MDMRS_VAL
	176	+ str r2, [r1, #MDMRS_OFFSET]
	177	+
	178	+/* ---- INTERRUPT INITIALISATION ---- */
	179	+/* Disable (mask) all interrupts at the interrupt controller */
	180	+/* clear the interrupt level register (use IRQ, not FIQ) */
	181	+ mov r1, #0
	182	+ ldr r2, =ICLR
	183	+ str r1, [r2]
	184	+
	185	+/* Set interrupt mask register */
	186	+ ldr r1, =CFG_ICMR_VAL
	187	+ ldr r2, =ICMR
	188	+ str r1, [r2]
	189	+
	190	+/* ---- CLOCK INITIALISATION ---- */
	191	+/* Disable the peripheral clocks, and set the core clock */
	192	+
	193	+/* Turn Off ALL on-chip peripheral clocks for re-configuration */
	194	+ ldr r1, =CKEN
	195	+ mov r2, #0
	196	+ str r2, [r1]
	197	+
	198	+/* set core clocks */
	199	+ ldr r2, =CFG_CCCR_VAL
	200	+ ldr r1, =CCCR
	201	+ str r2, [r1]
	202	+
	203	+#ifdef ENABLE32KHZ
	204	+/* enable the 32Khz oscillator for RTC and PowerManager */
	205	+ ldr r1, =OSCC
	206	+ mov r2, #OSCC_OON
	207	+ str r2, [r1]
	208	+
	209	+/* NOTE: spin here until OSCC.OOK get set, meaning the PLL has settled. */
	210	+60:
	211	+ ldr r2, [r1]
	212	+ ands r2, r2, #1
	213	+ beq 60b
	214	+#endif
	215	+
	216	+/* Turn on needed clocks */
	217	+ ldr r1, =CKEN
	218	+ ldr r2, =CFG_CKEN_VAL
	219	+ str r2, [r1]
	220	+
	221	+ mov pc, r10
	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
	4	+ *
	5	+ * (C) Copyright 2002
	6	+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	7	+ * Marius Groeger <mgroeger@sysgo.de>
	8	+ *
	9	+ * See file CREDITS for list of people who contributed to this
	10	+ * project.
	11	+ *
	12	+ * This program is free software; you can redistribute it and/or
	13	+ * modify it under the terms of the GNU General Public License as
	14	+ * published by the Free Software Foundation; either version 2 of
	15	+ * the License, or (at your option) any later version.
	16	+ *
	17	+ * This program is distributed in the hope that it will be useful,
	18	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	+ * GNU General Public License for more details.
	21	+ *
	22	+ * You should have received a copy of the GNU General Public License
	23	+ * along with this program; if not, write to the Free Software
	24	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	+ * MA 02111-1307 USA
	26	+ */
	27	+
	28	+#include <common.h>
	29	+
	30	+/*
	31	+ * Miscelaneous platform dependent initialisations
	32	+ */
	33	+
	34	+int board_init (void)
	35	+{
	36	+ DECLARE_GLOBAL_DATA_PTR;
	37	+
	38	+ /* memory and cpu-speed are setup before relocation */
	39	+ /* so we do _nothing_ here */
	40	+
	41	+ /* arch number */
	42	+ gd->bd->bi_arch_number = 532;
	43	+
	44	+ /* adress of boot parameters */
	45	+ gd->bd->bi_boot_params = 0xa0000100;
	46	+
	47	+ return 0;
	48	+}
	49	+
	50	+int board_post_init (void)
	51	+{
	52	+ setenv ("stdout", "serial");
	53	+ setenv ("stderr", "serial");
	54	+ return 0;
	55	+}
	56	+
	57	+int dram_init (void)
	58	+{
	59	+ DECLARE_GLOBAL_DATA_PTR;
	60	+
	61	+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	62	+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
	63	+
	64	+ return 0;
	65	+}
...	...	@@ -76,6 +76,16 @@
76	76
77	77	#ifdef CONFIG_PXA250
78	78
	79	+#ifdef CONFIG_XSENGINE
	80	+#define SMC_inl(r) (((volatile dword )(SMC_BASE_ADDRESS+(r<<1))))
	81	+#define SMC_inw(r) (((volatile word )(SMC_BASE_ADDRESS+(r<<1))))
	82	+#define SMC_inb(p) ({ \
	83	+ unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \
	84	+ unsigned int __v = (volatile unsigned short )((__p) & ~2); \
	85	+ if (__p & 2) __v >>= 8; \
	86	+ else __v &= 0xff; \
	87	+ __v; })
	88	+#else
79	89	#define SMC_inl(r) (((volatile dword )(SMC_BASE_ADDRESS+(r))))
80	90	#define SMC_inw(r) (((volatile word )(SMC_BASE_ADDRESS+(r))))
81	91	#define SMC_inb(p) ({ \
82	92
83	93
...	...	@@ -84,9 +94,16 @@
84	94	if (__p & 1) __v >>= 8; \
85	95	else __v &= 0xff; \
86	96	__v; })
	97	+#endif
87	98
	99	+#ifdef CONFIG_XSENGINE
	100	+#define SMC_outl(d,r) (((volatile dword )(SMC_BASE_ADDRESS+(r<<1))) = d)
	101	+#define SMC_outw(d,r) (((volatile word )(SMC_BASE_ADDRESS+(r<<1))) = d)
	102	+#else
88	103	#define SMC_outl(d,r) (((volatile dword )(SMC_BASE_ADDRESS+(r))) = d)
89	104	#define SMC_outw(d,r) (((volatile word )(SMC_BASE_ADDRESS+(r))) = d)
	105	+#endif
	106	+
90	107	#define SMC_outb(d,r) ({ word __d = (byte)(d); \
91	108	word __w = SMC_inw((r)&~1); \
92	109	__w &= ((r)&1) ? 0x00FF : 0xFF00; \
93	110
...	...	@@ -191,7 +208,11 @@
191	208
192	209	#if defined(CONFIG_SMC_USE_32_BIT)
193	210
	211	+#ifdef CONFIG_XSENGINE
	212	+#define SMC_inl(r) (((volatile dword )(SMC_BASE_ADDRESS+(r<<1))))
	213	+#else
194	214	#define SMC_inl(r) (((volatile dword )(SMC_BASE_ADDRESS+(r))))
	215	+#endif
195	216
196	217	#define SMC_insl(r,b,l) ({ int __i ; \
197	218	dword *__b2; \
198	219
...	...	@@ -202,8 +223,11 @@
202	223	}; \
203	224	})
204	225
	226	+#ifdef CONFIG_XSENGINE
	227	+#define SMC_outl(d,r) (((volatile dword )(SMC_BASE_ADDRESS+(r<<1))) = d)
	228	+#else
205	229	#define SMC_outl(d,r) (((volatile dword )(SMC_BASE_ADDRESS+(r))) = d)
206		-
	230	+#endif
207	231	#define SMC_outsl(r,b,l) ({ int __i; \
208	232	dword *__b2; \
209	233	__b2 = (dword *) b; \