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Commit ca93e321392d6f045036d6084ce3b31f1647d1ec

Authored by YouMin Chen
Committed by Kever Yang
1 parent 39edfaa758
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ram: rk3328: use common sdram driver 

RK3328 has a similar controller and phy with PX30, so we can use the
common driver for it and remove the duplicate codes.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

Showing 9 changed files with 295 additions and 906 deletions Side-by-side Diff

arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
Diff comments   View file @ ca93e32
... ... @@ -14,6 +14,8 @@
14 14 0x0
15 15 0x10
16 16 0x10
  17 + 0x10
  18 + 0x10
17 19 0
18 20  
19 21 0x9028b189
... ... @@ -26,6 +28,8 @@
26 28  
27 29 333
28 30 3
  31 + 1
  32 + 0
29 33 0
30 34  
31 35 0x00000000
arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
Diff comments   View file @ ca93e32
... ... @@ -14,6 +14,8 @@
14 14 0x0
15 15 0x10
16 16 0x10
  17 + 0x10
  18 + 0x10
17 19 0
18 20  
19 21 0x98899459
... ... @@ -26,6 +28,8 @@
26 28  
27 29 800
28 30 6
  31 + 1
  32 + 0
29 33 1
30 34  
31 35 0x00000000
arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
Diff comments   View file @ ca93e32
... ... @@ -14,6 +14,8 @@
14 14 0x0
15 15 0x10
16 16 0x10
  17 + 0x10
  18 + 0x10
17 19 0
18 20  
19 21 0x0c48a18a
... ... @@ -26,6 +28,8 @@
26 28  
27 29 333
28 30 6
  31 + 1
  32 + 0
29 33 0
30 34  
31 35 0x00000000
arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
Diff comments   View file @ ca93e32
... ... @@ -7,198 +7,14 @@
7 7 #ifndef _ASM_ARCH_SDRAM_RK3328_H
8 8 #define _ASM_ARCH_SDRAM_RK3328_H
9 9 #include <asm/arch-rockchip/sdram_common.h>
  10 +#include <asm/arch-rockchip/sdram_pctl_px30.h>
  11 +#include <asm/arch-rockchip/sdram_phy_px30.h>
  12 +#include <asm/arch-rockchip/sdram_phy_ron_rtt_px30.h>
10 13  
11 14 #define SR_IDLE 93
12 15 #define PD_IDLE 13
13 16 #define SDRAM_ADDR 0x00000000
14   -#define PATTERN (0x5aa5f00f)
15 17  
16   -/* ddr pctl registers define */
17   -#define DDR_PCTL2_MSTR 0x0
18   -#define DDR_PCTL2_STAT 0x4
19   -#define DDR_PCTL2_MSTR1 0x8
20   -#define DDR_PCTL2_MRCTRL0 0x10
21   -#define DDR_PCTL2_MRCTRL1 0x14
22   -#define DDR_PCTL2_MRSTAT 0x18
23   -#define DDR_PCTL2_MRCTRL2 0x1c
24   -#define DDR_PCTL2_DERATEEN 0x20
25   -#define DDR_PCTL2_DERATEINT 0x24
26   -#define DDR_PCTL2_PWRCTL 0x30
27   -#define DDR_PCTL2_PWRTMG 0x34
28   -#define DDR_PCTL2_HWLPCTL 0x38
29   -#define DDR_PCTL2_RFSHCTL0 0x50
30   -#define DDR_PCTL2_RFSHCTL1 0x54
31   -#define DDR_PCTL2_RFSHCTL2 0x58
32   -#define DDR_PCTL2_RFSHCTL4 0x5c
33   -#define DDR_PCTL2_RFSHCTL3 0x60
34   -#define DDR_PCTL2_RFSHTMG 0x64
35   -#define DDR_PCTL2_RFSHTMG1 0x68
36   -#define DDR_PCTL2_RFSHCTL5 0x6c
37   -#define DDR_PCTL2_INIT0 0xd0
38   -#define DDR_PCTL2_INIT1 0xd4
39   -#define DDR_PCTL2_INIT2 0xd8
40   -#define DDR_PCTL2_INIT3 0xdc
41   -#define DDR_PCTL2_INIT4 0xe0
42   -#define DDR_PCTL2_INIT5 0xe4
43   -#define DDR_PCTL2_INIT6 0xe8
44   -#define DDR_PCTL2_INIT7 0xec
45   -#define DDR_PCTL2_DIMMCTL 0xf0
46   -#define DDR_PCTL2_RANKCTL 0xf4
47   -#define DDR_PCTL2_CHCTL 0xfc
48   -#define DDR_PCTL2_DRAMTMG0 0x100
49   -#define DDR_PCTL2_DRAMTMG1 0x104
50   -#define DDR_PCTL2_DRAMTMG2 0x108
51   -#define DDR_PCTL2_DRAMTMG3 0x10c
52   -#define DDR_PCTL2_DRAMTMG4 0x110
53   -#define DDR_PCTL2_DRAMTMG5 0x114
54   -#define DDR_PCTL2_DRAMTMG6 0x118
55   -#define DDR_PCTL2_DRAMTMG7 0x11c
56   -#define DDR_PCTL2_DRAMTMG8 0x120
57   -#define DDR_PCTL2_DRAMTMG9 0x124
58   -#define DDR_PCTL2_DRAMTMG10 0x128
59   -#define DDR_PCTL2_DRAMTMG11 0x12c
60   -#define DDR_PCTL2_DRAMTMG12 0x130
61   -#define DDR_PCTL2_DRAMTMG13 0x134
62   -#define DDR_PCTL2_DRAMTMG14 0x138
63   -#define DDR_PCTL2_DRAMTMG15 0x13c
64   -#define DDR_PCTL2_DRAMTMG16 0x140
65   -#define DDR_PCTL2_ZQCTL0 0x180
66   -#define DDR_PCTL2_ZQCTL1 0x184
67   -#define DDR_PCTL2_ZQCTL2 0x188
68   -#define DDR_PCTL2_ZQSTAT 0x18c
69   -#define DDR_PCTL2_DFITMG0 0x190
70   -#define DDR_PCTL2_DFITMG1 0x194
71   -#define DDR_PCTL2_DFILPCFG0 0x198
72   -#define DDR_PCTL2_DFILPCFG1 0x19c
73   -#define DDR_PCTL2_DFIUPD0 0x1a0
74   -#define DDR_PCTL2_DFIUPD1 0x1a4
75   -#define DDR_PCTL2_DFIUPD2 0x1a8
76   -#define DDR_PCTL2_DFIMISC 0x1b0
77   -#define DDR_PCTL2_DFITMG2 0x1b4
78   -#define DDR_PCTL2_DFITMG3 0x1b8
79   -#define DDR_PCTL2_DFISTAT 0x1bc
80   -#define DDR_PCTL2_DBICTL 0x1c0
81   -#define DDR_PCTL2_ADDRMAP0 0x200
82   -#define DDR_PCTL2_ADDRMAP1 0x204
83   -#define DDR_PCTL2_ADDRMAP2 0x208
84   -#define DDR_PCTL2_ADDRMAP3 0x20c
85   -#define DDR_PCTL2_ADDRMAP4 0x210
86   -#define DDR_PCTL2_ADDRMAP5 0x214
87   -#define DDR_PCTL2_ADDRMAP6 0x218
88   -#define DDR_PCTL2_ADDRMAP7 0x21c
89   -#define DDR_PCTL2_ADDRMAP8 0x220
90   -#define DDR_PCTL2_ADDRMAP9 0x224
91   -#define DDR_PCTL2_ADDRMAP10 0x228
92   -#define DDR_PCTL2_ADDRMAP11 0x22c
93   -#define DDR_PCTL2_ODTCFG 0x240
94   -#define DDR_PCTL2_ODTMAP 0x244
95   -#define DDR_PCTL2_SCHED 0x250
96   -#define DDR_PCTL2_SCHED1 0x254
97   -#define DDR_PCTL2_PERFHPR1 0x25c
98   -#define DDR_PCTL2_PERFLPR1 0x264
99   -#define DDR_PCTL2_PERFWR1 0x26c
100   -#define DDR_PCTL2_DQMAP0 0x280
101   -#define DDR_PCTL2_DQMAP1 0x284
102   -#define DDR_PCTL2_DQMAP2 0x288
103   -#define DDR_PCTL2_DQMAP3 0x28c
104   -#define DDR_PCTL2_DQMAP4 0x290
105   -#define DDR_PCTL2_DQMAP5 0x294
106   -#define DDR_PCTL2_DBG0 0x300
107   -#define DDR_PCTL2_DBG1 0x304
108   -#define DDR_PCTL2_DBGCAM 0x308
109   -#define DDR_PCTL2_DBGCMD 0x30c
110   -#define DDR_PCTL2_DBGSTAT 0x310
111   -#define DDR_PCTL2_SWCTL 0x320
112   -#define DDR_PCTL2_SWSTAT 0x324
113   -#define DDR_PCTL2_POISONCFG 0x36c
114   -#define DDR_PCTL2_POISONSTAT 0x370
115   -#define DDR_PCTL2_ADVECCINDEX 0x374
116   -#define DDR_PCTL2_ADVECCSTAT 0x378
117   -#define DDR_PCTL2_PSTAT 0x3fc
118   -#define DDR_PCTL2_PCCFG 0x400
119   -#define DDR_PCTL2_PCFGR_n 0x404
120   -#define DDR_PCTL2_PCFGW_n 0x408
121   -#define DDR_PCTL2_PCTRL_n 0x490
122   -
123   -/* PCTL2_MRSTAT */
124   -#define MR_WR_BUSY BIT(0)
125   -
126   -/* PHY_REG0 */
127   -#define DIGITAL_DERESET BIT(3)
128   -#define ANALOG_DERESET BIT(2)
129   -#define DIGITAL_RESET (0 << 3)
130   -#define ANALOG_RESET (0 << 2)
131   -
132   -/* PHY_REG1 */
133   -#define PHY_DDR2 (0)
134   -#define PHY_LPDDR2 (1)
135   -#define PHY_DDR3 (2)
136   -#define PHY_LPDDR3 (3)
137   -#define PHY_DDR4 (4)
138   -#define PHY_BL_4 (0 << 2)
139   -#define PHY_BL_8 BIT(2)
140   -
141   -/* PHY_REG2 */
142   -#define PHY_DTT_EN BIT(0)
143   -#define PHY_DTT_DISB (0 << 0)
144   -#define PHY_WRITE_LEVELING_EN BIT(2)
145   -#define PHY_WRITE_LEVELING_DISB (0 << 2)
146   -#define PHY_SELECT_CS0 (2)
147   -#define PHY_SELECT_CS1 (1)
148   -#define PHY_SELECT_CS0_1 (0)
149   -#define PHY_WRITE_LEVELING_SELECTCS(n) (n << 6)
150   -#define PHY_DATA_TRAINING_SELECTCS(n) (n << 4)
151   -
152   -#define PHY_DDR3_RON_RTT_DISABLE (0)
153   -#define PHY_DDR3_RON_RTT_451ohm (1)
154   -#define PHY_DDR3_RON_RTT_225ohm (2)
155   -#define PHY_DDR3_RON_RTT_150ohm (3)
156   -#define PHY_DDR3_RON_RTT_112ohm (4)
157   -#define PHY_DDR3_RON_RTT_90ohm (5)
158   -#define PHY_DDR3_RON_RTT_75ohm (6)
159   -#define PHY_DDR3_RON_RTT_64ohm (7)
160   -#define PHY_DDR3_RON_RTT_56ohm (16)
161   -#define PHY_DDR3_RON_RTT_50ohm (17)
162   -#define PHY_DDR3_RON_RTT_45ohm (18)
163   -#define PHY_DDR3_RON_RTT_41ohm (19)
164   -#define PHY_DDR3_RON_RTT_37ohm (20)
165   -#define PHY_DDR3_RON_RTT_34ohm (21)
166   -#define PHY_DDR3_RON_RTT_33ohm (22)
167   -#define PHY_DDR3_RON_RTT_30ohm (23)
168   -#define PHY_DDR3_RON_RTT_28ohm (24)
169   -#define PHY_DDR3_RON_RTT_26ohm (25)
170   -#define PHY_DDR3_RON_RTT_25ohm (26)
171   -#define PHY_DDR3_RON_RTT_23ohm (27)
172   -#define PHY_DDR3_RON_RTT_22ohm (28)
173   -#define PHY_DDR3_RON_RTT_21ohm (29)
174   -#define PHY_DDR3_RON_RTT_20ohm (30)
175   -#define PHY_DDR3_RON_RTT_19ohm (31)
176   -
177   -#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
178   -#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1)
179   -#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2)
180   -#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3)
181   -#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4)
182   -#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5)
183   -#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6)
184   -#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7)
185   -#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16)
186   -#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17)
187   -#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18)
188   -#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19)
189   -#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20)
190   -#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21)
191   -#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22)
192   -#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23)
193   -#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24)
194   -#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25)
195   -#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26)
196   -#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27)
197   -#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28)
198   -#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29)
199   -#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30)
200   -#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31)
201   -
202 18 /* noc registers define */
203 19 #define DDRCONF 0x8
204 20 #define DDRTIMING 0xc
205 21  
... ... @@ -220,16 +36,16 @@
220 36 #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4)
221 37  
222 38 /* CRU_SOFTRESET_CON5 */
223   -#define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | (n << 15))
224   -#define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | (n << 14))
225   -#define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | (n << 13))
226   -#define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | (n << 12))
227   -#define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | (n << 11))
228   -#define msch_srstn_req(n) (((0x1 << 9) << 16) | (n << 9))
229   -#define dfimon_srstn_req(n) (((0x1 << 8) << 16) | (n << 8))
230   -#define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | (n << 7))
  39 +#define ddrphy_psrstn_req(n) (((0x1 << 15) << 16) | ((n) << 15))
  40 +#define ddrphy_srstn_req(n) (((0x1 << 14) << 16) | ((n) << 14))
  41 +#define ddrctrl_psrstn_req(n) (((0x1 << 13) << 16) | ((n) << 13))
  42 +#define ddrctrl_srstn_req(n) (((0x1 << 12) << 16) | ((n) << 12))
  43 +#define ddrmsch_srstn_req(n) (((0x1 << 11) << 16) | ((n) << 11))
  44 +#define msch_srstn_req(n) (((0x1 << 9) << 16) | ((n) << 9))
  45 +#define dfimon_srstn_req(n) (((0x1 << 8) << 16) | ((n) << 8))
  46 +#define grf_ddr_srstn_req(n) (((0x1 << 7) << 16) | ((n) << 7))
231 47 /* CRU_SOFTRESET_CON9 */
232   -#define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | (n << 9))
  48 +#define ddrctrl_asrstn_req(n) (((0x1 << 9) << 16) | ((n) << 9))
233 49  
234 50 /* CRU register */
235 51 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4)
236 52  
237 53  
... ... @@ -256,58 +72,48 @@
256 72 #define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6))
257 73 #define REFDIV(n) ((0x3F << 16) | (n))
258 74  
259   -union noc_ddrtiming {
260   - u32 d32;
261   - struct {
262   - unsigned acttoact:6;
263   - unsigned rdtomiss:6;
264   - unsigned wrtomiss:6;
265   - unsigned burstlen:3;
266   - unsigned rdtowr:5;
267   - unsigned wrtord:5;
268   - unsigned bwratio:1;
269   - } b;
270   -} NOC_TIMING_T;
271   -
272   -union noc_activate {
273   - u32 d32;
274   - struct {
275   - unsigned rrd:4;
276   - unsigned faw:6;
277   - unsigned fawbank:1;
278   - unsigned reserved1:21;
279   - } b;
  75 +u16 ddr_cfg_2_rbc[] = {
  76 + /*
  77 + * [5:4] row(13+n)
  78 + * [3] cs(0:0 cs, 1:2 cs)
  79 + * [2] bank(0:0bank,1:8bank)
  80 + * [1:0] col(11+n)
  81 + */
  82 + /* row, cs, bank, col */
  83 + ((3 << 4) | (0 << 3) | (1 << 2) | 0),
  84 + ((3 << 4) | (0 << 3) | (1 << 2) | 1),
  85 + ((2 << 4) | (0 << 3) | (1 << 2) | 2),
  86 + ((3 << 4) | (0 << 3) | (1 << 2) | 2),
  87 + ((2 << 4) | (0 << 3) | (1 << 2) | 3),
  88 + ((3 << 4) | (1 << 3) | (1 << 2) | 0),
  89 + ((3 << 4) | (1 << 3) | (1 << 2) | 1),
  90 + ((2 << 4) | (1 << 3) | (1 << 2) | 2),
  91 + ((3 << 4) | (0 << 3) | (0 << 2) | 1),
  92 + ((2 << 4) | (0 << 3) | (1 << 2) | 1),
280 93 };
281 94  
282   -union noc_devtodev {
283   - u32 d32;
284   - struct {
285   - unsigned busrdtord:2;
286   - unsigned busrdtowr:2;
287   - unsigned buswrtord:2;
288   - unsigned reserved2:26;
289   - } b;
  95 +u16 ddr4_cfg_2_rbc[] = {
  96 + /***************************
  97 + * [6] cs 0:0cs 1:2 cs
  98 + * [5:3] row(13+n)
  99 + * [2] cs(0:0 cs, 1:2 cs)
  100 + * [1] bw 0: 16bit 1:32bit
  101 + * [0] diebw 0:8bit 1:16bit
  102 + ***************************/
  103 + /* cs, row, cs, bw, diebw */
  104 + ((0 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 0),
  105 + ((1 << 6) | (2 << 3) | (0 << 2) | (1 << 1) | 0),
  106 + ((0 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 0),
  107 + ((1 << 6) | (3 << 3) | (0 << 2) | (0 << 1) | 0),
  108 + ((0 << 6) | (4 << 3) | (0 << 2) | (1 << 1) | 1),
  109 + ((1 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 1),
  110 + ((1 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 1),
  111 + ((0 << 6) | (2 << 3) | (1 << 2) | (1 << 1) | 0),
  112 + ((0 << 6) | (3 << 3) | (1 << 2) | (0 << 1) | 0),
  113 + ((0 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | 1),
  114 + ((0 << 6) | (4 << 3) | (1 << 2) | (0 << 1) | 1),
290 115 };
291 116  
292   -union noc_ddr4timing {
293   - u32 d32;
294   - struct {
295   - unsigned ccdl:3;
296   - unsigned wrtordl:5;
297   - unsigned rrdl:4;
298   - unsigned reserved2:20;
299   - } b;
300   -};
301   -
302   -union noc_ddrmode {
303   - u32 d32;
304   - struct {
305   - unsigned autoprecharge:1;
306   - unsigned bwratioextended:1;
307   - unsigned reserved3:30;
308   - } b;
309   -};
310   -
311 117 u32 addrmap[21][9] = {
312 118 /* map0 map1 map2 map3 map4 map5 map6 map7 map8 */
313 119 {22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606,
314 120  
... ... @@ -356,17 +162,65 @@
356 162 0x07070707, 0x00000f07, 0x3f00}
357 163 };
358 164  
359   -struct rk3328_msch_timings {
360   - union noc_ddrtiming ddrtiming;
361   - union noc_ddrmode ddrmode;
362   - u32 readlatency;
363   - union noc_activate activate;
364   - union noc_devtodev devtodev;
365   - union noc_ddr4timing ddr4timing;
366   - u32 agingx0;
  165 +struct rk3328_ddr_grf_regs {
  166 + u32 ddr_grf_con[4];
  167 + u32 reserved[(0x100 - 0x10) / 4];
  168 + u32 ddr_grf_status[11];
367 169 };
368 170  
369   -struct rk3328_msch_regs {
  171 +union noc_ddrtiming {
  172 + u32 d32;
  173 + struct {
  174 + unsigned acttoact:6;
  175 + unsigned rdtomiss:6;
  176 + unsigned wrtomiss:6;
  177 + unsigned burstlen:3;
  178 + unsigned rdtowr:5;
  179 + unsigned wrtord:5;
  180 + unsigned bwratio:1;
  181 + } b;
  182 +};
  183 +
  184 +union noc_activate {
  185 + u32 d32;
  186 + struct {
  187 + unsigned rrd:4;
  188 + unsigned faw:6;
  189 + unsigned fawbank:1;
  190 + unsigned reserved1:21;
  191 + } b;
  192 +};
  193 +
  194 +union noc_devtodev {
  195 + u32 d32;
  196 + struct {
  197 + unsigned busrdtord:2;
  198 + unsigned busrdtowr:2;
  199 + unsigned buswrtord:2;
  200 + unsigned reserved2:26;
  201 + } b;
  202 +};
  203 +
  204 +union noc_ddr4timing {
  205 + u32 d32;
  206 + struct {
  207 + unsigned ccdl:3;
  208 + unsigned wrtordl:5;
  209 + unsigned rrdl:4;
  210 + unsigned reserved2:20;
  211 + } b;
  212 +};
  213 +
  214 +union noc_ddrmode {
  215 + u32 d32;
  216 + struct {
  217 + unsigned autoprecharge:1;
  218 + unsigned bwratioextended:1;
  219 + unsigned reserved3:30;
  220 + } b;
  221 +};
  222 +
  223 +struct msch_regs {
370 224 u32 coreid;
371 225 u32 revisionid;
372 226 u32 ddrconf;
373 227  
374 228  
375 229  
376 230  
... ... @@ -385,59 +239,28 @@
385 239 u32 ddr4_timing;
386 240 };
387 241  
388   -struct rk3328_ddr_grf_regs {
389   - u32 ddr_grf_con[4];
390   - u32 reserved[(0x100 - 0x10) / 4];
391   - u32 ddr_grf_status[11];
  242 +struct sdram_msch_timings {
  243 + union noc_ddrtiming ddrtiming;
  244 + union noc_ddrmode ddrmode;
  245 + u32 readlatency;
  246 + union noc_activate activate;
  247 + union noc_devtodev devtodev;
  248 + union noc_ddr4timing ddr4timing;
  249 + u32 agingx0;
392 250 };
393 251  
394   -struct rk3328_ddr_pctl_regs {
395   - u32 pctl[30][2];
396   -};
397   -
398   -struct rk3328_ddr_phy_regs {
399   - u32 phy[5][2];
400   -};
401   -
402   -struct rk3328_ddr_skew {
403   - u32 a0_a1_skew[15];
404   - u32 cs0_dm0_skew[11];
405   - u32 cs0_dm1_skew[11];
406   - u32 cs0_dm2_skew[11];
407   - u32 cs0_dm3_skew[11];
408   - u32 cs1_dm0_skew[11];
409   - u32 cs1_dm1_skew[11];
410   - u32 cs1_dm2_skew[11];
411   - u32 cs1_dm3_skew[11];
412   -};
413   -
414 252 struct rk3328_sdram_channel {
415   - unsigned int rank;
416   - unsigned int col;
417   - /* 3:8bank, 2:4bank */
418   - unsigned int bk;
419   - /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
420   - unsigned int bw;
421   - /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
422   - unsigned int dbw;
423   - unsigned int row_3_4;
424   - unsigned int cs0_row;
425   - unsigned int cs1_row;
426   - unsigned int ddrconfig;
427   - struct rk3328_msch_timings noc_timings;
  253 + struct sdram_cap_info cap_info;
  254 + struct sdram_msch_timings noc_timings;
428 255 };
429 256  
430 257 struct rk3328_sdram_params {
431 258 struct rk3328_sdram_channel ch;
432   - unsigned int ddr_freq;
433   - unsigned int dramtype;
434   - unsigned int odt;
435   - struct rk3328_ddr_pctl_regs pctl_regs;
436   - struct rk3328_ddr_phy_regs phy_regs;
437   - struct rk3328_ddr_skew skew;
  259 + struct sdram_base_params base;
  260 + struct ddr_pctl_regs pctl_regs;
  261 + struct ddr_phy_regs phy_regs;
  262 + struct ddr_phy_skew skew;
438 263 };
439   -
440   -#define PHY_REG(base, n) (base + 4 * (n))
441 264  
442 265 #endif
arch/arm/mach-rockchip/Kconfig
Diff comments   View file @ ca93e32
... ... @@ -115,6 +115,7 @@
115 115 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
116 116 select TPL_NEEDS_SEPARATE_STACK if TPL
117 117 imply ROCKCHIP_COMMON_BOARD
  118 + imply ROCKCHIP_SDRAM_COMMON
118 119 imply SPL_ROCKCHIP_COMMON_BOARD
119 120 imply SPL_SERIAL_SUPPORT
120 121 imply TPL_SERIAL_SUPPORT
configs/evb-rk3328_defconfig
Diff comments   View file @ ca93e32
... ... @@ -45,7 +45,6 @@
45 45 CONFIG_TPL_SYSCON=y
46 46 CONFIG_CLK=y
47 47 CONFIG_SPL_CLK=y
48   -CONFIG_TPL_CLK=y
49 48 CONFIG_FASTBOOT_BUF_ADDR=0x800800
50 49 CONFIG_FASTBOOT_FLASH=y
51 50 CONFIG_FASTBOOT_FLASH_MMC_DEV=1
... ... @@ -75,6 +74,7 @@
75 74 CONFIG_DEBUG_UART_ANNOUNCE=y
76 75 CONFIG_DEBUG_UART_SKIP_INIT=y
77 76 CONFIG_SYSRESET=y
  77 +# CONFIG_TPL_SYSRESET is not set
78 78 CONFIG_USB=y
79 79 CONFIG_USB_XHCI_HCD=y
80 80 CONFIG_USB_XHCI_DWC3=y
configs/rock64-rk3328_defconfig
Diff comments   View file @ ca93e32
... ... @@ -47,7 +47,6 @@
47 47 CONFIG_TPL_SYSCON=y
48 48 CONFIG_CLK=y
49 49 CONFIG_SPL_CLK=y
50   -CONFIG_TPL_CLK=y
51 50 CONFIG_FASTBOOT_BUF_ADDR=0x800800
52 51 CONFIG_FASTBOOT_FLASH=y
53 52 CONFIG_FASTBOOT_FLASH_MMC_DEV=1
... ... @@ -76,6 +75,7 @@
76 75 CONFIG_BAUDRATE=1500000
77 76 CONFIG_DEBUG_UART_SHIFT=2
78 77 CONFIG_SYSRESET=y
  78 +# CONFIG_TPL_SYSRESET is not set
79 79 CONFIG_USB=y
80 80 CONFIG_USB_XHCI_HCD=y
81 81 CONFIG_USB_XHCI_DWC3=y
drivers/ram/rockchip/Makefile
Diff comments   View file @ ca93e32
... ... @@ -9,7 +9,7 @@
9 9 obj-$(CONFIG_ROCKCHIP_RK3188) = sdram_rk3188.o
10 10 obj-$(CONFIG_ROCKCHIP_RK322X) = sdram_rk322x.o
11 11 obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
12   -obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o
  12 +obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
13 13 obj-$(CONFIG_RAM_RK3399) += sdram_rk3399.o
14 14 obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o
drivers/ram/rockchip/sdram_rk3328.c
Diff comments   View file @ ca93e32
Changes suppressed. Click to show
... ... @@ -20,11 +20,11 @@
20 20  
21 21 struct dram_info {
22 22 #ifdef CONFIG_TPL_BUILD
23   - struct rk3328_ddr_pctl_regs *pctl;
24   - struct rk3328_ddr_phy_regs *phy;
  23 + struct ddr_pctl_regs *pctl;
  24 + struct ddr_phy_regs *phy;
25 25 struct clk ddr_clk;
26 26 struct rk3328_cru *cru;
27   - struct rk3328_msch_regs *msch;
  27 + struct msch_regs *msch;
28 28 struct rk3328_ddr_grf_regs *ddr_grf;
29 29 #endif
30 30 struct ram_info info;
31 31  
... ... @@ -71,10 +71,11 @@
71 71 writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]);
72 72 }
73 73  
74   -static void rkclk_set_dpll(struct dram_info *dram, unsigned int mhz)
  74 +static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz)
75 75 {
76 76 unsigned int refdiv, postdiv1, postdiv2, fbdiv;
77 77 int delay = 1000;
  78 + u32 mhz = hz / MHZ;
78 79  
79 80 refdiv = 1;
80 81 if (mhz <= 300) {
81 82  
82 83  
83 84  
84 85  
85 86  
86 87  
... ... @@ -122,115 +123,47 @@
122 123 clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7);
123 124  
124 125 /* for inno ddr phy need 2*freq */
125   - rkclk_set_dpll(dram, sdram_params->ddr_freq * 2);
  126 + rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ * 2);
126 127 }
127 128  
128   -static void phy_soft_reset(struct dram_info *dram)
129   -{
130   - void __iomem *phy_base = dram->phy;
131   -
132   - clrbits_le32(PHY_REG(phy_base, 0), 0x3 << 2);
133   - udelay(1);
134   - setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET);
135   - udelay(5);
136   - setbits_le32(PHY_REG(phy_base, 0), DIGITAL_DERESET);
137   - udelay(1);
138   -}
139   -
140   -static int pctl_cfg(struct dram_info *dram,
141   - struct rk3328_sdram_params *sdram_params)
142   -{
143   - u32 i;
144   - void __iomem *pctl_base = dram->pctl;
145   -
146   - for (i = 0; sdram_params->pctl_regs.pctl[i][0] != 0xFFFFFFFF; i++) {
147   - writel(sdram_params->pctl_regs.pctl[i][1],
148   - pctl_base + sdram_params->pctl_regs.pctl[i][0]);
149   - }
150   - clrsetbits_le32(pctl_base + DDR_PCTL2_PWRTMG,
151   - (0xff << 16) | 0x1f,
152   - ((SR_IDLE & 0xff) << 16) | (PD_IDLE & 0x1f));
153   - /*
154   - * dfi_lp_en_pd=1,dfi_lp_wakeup_pd=2
155   - * hw_lp_idle_x32=1
156   - */
157   - if (sdram_params->dramtype == LPDDR3) {
158   - setbits_le32(pctl_base + DDR_PCTL2_DFILPCFG0, 1);
159   - clrsetbits_le32(pctl_base + DDR_PCTL2_DFILPCFG0,
160   - 0xf << 4,
161   - 2 << 4);
162   - }
163   - clrsetbits_le32(pctl_base + DDR_PCTL2_HWLPCTL,
164   - 0xfff << 16,
165   - 1 << 16);
166   - /* disable zqcs */
167   - setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1u << 31);
168   - setbits_le32(pctl_base + 0x2000 + DDR_PCTL2_ZQCTL0, 1u << 31);
169   -
170   - return 0;
171   -}
172   -
173 129 /* return ddrconfig value
174 130 * (-1), find ddrconfig fail
175 131 * other, the ddrconfig value
176 132 * only support cs0_row >= cs1_row
177 133 */
178   -static unsigned int calculate_ddrconfig(struct rk3328_sdram_params *sdram_params)
  134 +static u32 calculate_ddrconfig(struct rk3328_sdram_params *sdram_params)
179 135 {
180   - static const u16 ddr_cfg_2_rbc[] = {
181   - /***************************
182   - * [5:4] row(13+n)
183   - * [3] cs(0:0 cs, 1:2 cs)
184   - * [2] bank(0:0bank,1:8bank)
185   - * [1:0] col(11+n)
186   - ****************************/
187   - /* row, cs, bank, col */
188   - ((3 << 4) | (0 << 3) | (1 << 2) | 0),
189   - ((3 << 4) | (0 << 3) | (1 << 2) | 1),
190   - ((2 << 4) | (0 << 3) | (1 << 2) | 2),
191   - ((3 << 4) | (0 << 3) | (1 << 2) | 2),
192   - ((2 << 4) | (0 << 3) | (1 << 2) | 3),
193   - ((3 << 4) | (1 << 3) | (1 << 2) | 0),
194   - ((3 << 4) | (1 << 3) | (1 << 2) | 1),
195   - ((2 << 4) | (1 << 3) | (1 << 2) | 2),
196   - ((3 << 4) | (0 << 3) | (0 << 2) | 1),
197   - ((2 << 4) | (0 << 3) | (1 << 2) | 1),
198   - };
199   -
200   - static const u16 ddr4_cfg_2_rbc[] = {
201   - /***************************
202   - * [6] cs 0:0cs 1:2 cs
203   - * [5:3] row(13+n)
204   - * [2] cs(0:0 cs, 1:2 cs)
205   - * [1] bw 0: 16bit 1:32bit
206   - * [0] diebw 0:8bit 1:16bit
207   - ***************************/
208   - /* cs, row, cs, bw, diebw */
209   - ((0 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 0),
210   - ((1 << 6) | (2 << 3) | (0 << 2) | (1 << 1) | 0),
211   - ((0 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 0),
212   - ((1 << 6) | (3 << 3) | (0 << 2) | (0 << 1) | 0),
213   - ((0 << 6) | (4 << 3) | (0 << 2) | (1 << 1) | 1),
214   - ((1 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 1),
215   - ((1 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 1),
216   - ((0 << 6) | (2 << 3) | (1 << 2) | (1 << 1) | 0),
217   - ((0 << 6) | (3 << 3) | (1 << 2) | (0 << 1) | 0),
218   - ((0 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | 1),
219   - ((0 << 6) | (4 << 3) | (1 << 2) | (0 << 1) | 1),
220   - };
221   -
  136 + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
222 137 u32 cs, bw, die_bw, col, row, bank;
  138 + u32 cs1_row;
223 139 u32 i, tmp;
224 140 u32 ddrconf = -1;
225 141  
226   - cs = sdram_ch.rank;
227   - bw = sdram_ch.bw;
228   - die_bw = sdram_ch.dbw;
229   - col = sdram_ch.col;
230   - row = sdram_ch.cs0_row;
231   - bank = sdram_ch.bk;
  142 + cs = cap_info->rank;
  143 + bw = cap_info->bw;
  144 + die_bw = cap_info->dbw;
  145 + col = cap_info->col;
  146 + row = cap_info->cs0_row;
  147 + cs1_row = cap_info->cs1_row;
  148 + bank = cap_info->bk;
232 149  
233   - if (sdram_params->dramtype == DDR4) {
  150 + if (sdram_params->base.dramtype == DDR4) {
  151 + /* when DDR_TEST, CS always at MSB position for easy test */
  152 + if (cs == 2 && row == cs1_row) {
  153 + /* include 2cs cap both 2^n or both (2^n - 2^(n-2)) */
  154 + tmp = ((row - 13) << 3) | (1 << 2) | (bw & 0x2) |
  155 + die_bw;
  156 + for (i = 17; i < 21; i++) {
  157 + if (((tmp & 0x7) ==
  158 + (ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
  159 + ((tmp & 0x3c) <=
  160 + (ddr4_cfg_2_rbc[i - 10] & 0x3c))) {
  161 + ddrconf = i;
  162 + goto out;
  163 + }
  164 + }
  165 + }
  166 +
234 167 tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw;
235 168 for (i = 10; i < 17; i++) {
236 169 if (((tmp & 0x7) == (ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
... ... @@ -246,6 +179,18 @@
246 179 goto out;
247 180 }
248 181  
  182 + /* when DDR_TEST, CS always at MSB position for easy test */
  183 + if (cs == 2 && row == cs1_row) {
  184 + /* include 2cs cap both 2^n or both (2^n - 2^(n-2)) */
  185 + for (i = 5; i < 8; i++) {
  186 + if ((bw + col - 11) == (ddr_cfg_2_rbc[i] &
  187 + 0x3)) {
  188 + ddrconf = i;
  189 + goto out;
  190 + }
  191 + }
  192 + }
  193 +
249 194 tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0);
250 195 for (i = 0; i < 5; i++)
251 196 if (((tmp & 0xf) == (ddr_cfg_2_rbc[i] & 0xf)) &&
252 197  
... ... @@ -257,23 +202,11 @@
257 202  
258 203 out:
259 204 if (ddrconf > 20)
260   - printf("calculate_ddrconfig error\n");
  205 + printf("calculate ddrconfig error\n");
261 206  
262 207 return ddrconf;
263 208 }
264 209  
265   -/* n: Unit bytes */
266   -static void copy_to_reg(u32 *dest, u32 *src, u32 n)
267   -{
268   - int i;
269   -
270   - for (i = 0; i < n / sizeof(u32); i++) {
271   - writel(*src, dest);
272   - src++;
273   - dest++;
274   - }
275   -}
276   -
277 210 /*******
278 211 * calculate controller dram address map, and setting to register.
279 212 * argument sdram_ch.ddrconf must be right value before
280 213  
281 214  
282 215  
283 216  
284 217  
285 218  
286 219  
287 220  
288 221  
289 222  
290 223  
291 224  
292 225  
... ... @@ -282,274 +215,43 @@
282 215 static void set_ctl_address_map(struct dram_info *dram,
283 216 struct rk3328_sdram_params *sdram_params)
284 217 {
  218 + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
285 219 void __iomem *pctl_base = dram->pctl;
286 220  
287   - copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0),
288   - &addrmap[sdram_ch.ddrconfig][0], 9 * 4);
289   - if (sdram_params->dramtype == LPDDR3 && sdram_ch.row_3_4)
  221 + sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0),
  222 + &addrmap[cap_info->ddrconfig][0], 9 * 4);
  223 + if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4)
290 224 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31);
291   - if (sdram_params->dramtype == DDR4 && sdram_ch.bw == 0x1)
  225 + if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1)
292 226 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8);
293 227  
294   - if (sdram_ch.rank == 1)
  228 + if (cap_info->rank == 1)
295 229 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f);
296 230 }
297 231  
298   -static void phy_dll_bypass_set(struct dram_info *dram, u32 freq)
  232 +static int data_training(struct dram_info *dram, u32 cs, u32 dramtype)
299 233 {
300   - u32 tmp;
301   - void __iomem *phy_base = dram->phy;
302   -
303   - setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4);
304   - clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3);
305   - setbits_le32(PHY_REG(phy_base, 0x26), 1 << 4);
306   - clrbits_le32(PHY_REG(phy_base, 0x27), 1 << 3);
307   - setbits_le32(PHY_REG(phy_base, 0x36), 1 << 4);
308   - clrbits_le32(PHY_REG(phy_base, 0x37), 1 << 3);
309   - setbits_le32(PHY_REG(phy_base, 0x46), 1 << 4);
310   - clrbits_le32(PHY_REG(phy_base, 0x47), 1 << 3);
311   - setbits_le32(PHY_REG(phy_base, 0x56), 1 << 4);
312   - clrbits_le32(PHY_REG(phy_base, 0x57), 1 << 3);
313   -
314   - if (freq <= 400)
315   - /* DLL bypass */
316   - setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);
317   - else
318   - clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);
319   - if (freq <= 680)
320   - tmp = 2;
321   - else
322   - tmp = 1;
323   - writel(tmp, PHY_REG(phy_base, 0x28));
324   - writel(tmp, PHY_REG(phy_base, 0x38));
325   - writel(tmp, PHY_REG(phy_base, 0x48));
326   - writel(tmp, PHY_REG(phy_base, 0x58));
327   -}
328   -
329   -static void set_ds_odt(struct dram_info *dram,
330   - struct rk3328_sdram_params *sdram_params)
331   -{
332   - u32 cmd_drv, clk_drv, dqs_drv, dqs_odt;
333   - void __iomem *phy_base = dram->phy;
334   -
335   - if (sdram_params->dramtype == DDR3) {
336   - cmd_drv = PHY_DDR3_RON_RTT_34ohm;
337   - clk_drv = PHY_DDR3_RON_RTT_45ohm;
338   - dqs_drv = PHY_DDR3_RON_RTT_34ohm;
339   - dqs_odt = PHY_DDR3_RON_RTT_225ohm;
340   - } else {
341   - cmd_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm;
342   - clk_drv = PHY_DDR4_LPDDR3_RON_RTT_43ohm;
343   - dqs_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm;
344   - dqs_odt = PHY_DDR4_LPDDR3_RON_RTT_240ohm;
345   - }
346   - /* DS */
347   - writel(cmd_drv, PHY_REG(phy_base, 0x11));
348   - clrsetbits_le32(PHY_REG(phy_base, 0x12), 0x1f << 3, cmd_drv << 3);
349   - writel(clk_drv, PHY_REG(phy_base, 0x16));
350   - writel(clk_drv, PHY_REG(phy_base, 0x18));
351   - writel(dqs_drv, PHY_REG(phy_base, 0x20));
352   - writel(dqs_drv, PHY_REG(phy_base, 0x2f));
353   - writel(dqs_drv, PHY_REG(phy_base, 0x30));
354   - writel(dqs_drv, PHY_REG(phy_base, 0x3f));
355   - writel(dqs_drv, PHY_REG(phy_base, 0x40));
356   - writel(dqs_drv, PHY_REG(phy_base, 0x4f));
357   - writel(dqs_drv, PHY_REG(phy_base, 0x50));
358   - writel(dqs_drv, PHY_REG(phy_base, 0x5f));
359   - /* ODT */
360   - writel(dqs_odt, PHY_REG(phy_base, 0x21));
361   - writel(dqs_odt, PHY_REG(phy_base, 0x2e));
362   - writel(dqs_odt, PHY_REG(phy_base, 0x31));
363   - writel(dqs_odt, PHY_REG(phy_base, 0x3e));
364   - writel(dqs_odt, PHY_REG(phy_base, 0x41));
365   - writel(dqs_odt, PHY_REG(phy_base, 0x4e));
366   - writel(dqs_odt, PHY_REG(phy_base, 0x51));
367   - writel(dqs_odt, PHY_REG(phy_base, 0x5e));
368   -}
369   -
370   -static void phy_cfg(struct dram_info *dram,
371   - struct rk3328_sdram_params *sdram_params)
372   -{
373   - u32 i;
374   - void __iomem *phy_base = dram->phy;
375   -
376   - phy_dll_bypass_set(dram, sdram_params->ddr_freq);
377   - for (i = 0; sdram_params->phy_regs.phy[i][0] != 0xFFFFFFFF; i++) {
378   - writel(sdram_params->phy_regs.phy[i][1],
379   - phy_base + sdram_params->phy_regs.phy[i][0]);
380   - }
381   - if (sdram_ch.bw == 2) {
382   - clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4);
383   - } else {
384   - clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4);
385   - /* disable DQS2,DQS3 tx dll for saving power */
386   - clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);
387   - clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);
388   - }
389   - set_ds_odt(dram, sdram_params);
390   - /* deskew */
391   - setbits_le32(PHY_REG(phy_base, 2), 8);
392   - copy_to_reg(PHY_REG(phy_base, 0xb0),
393   - &sdram_params->skew.a0_a1_skew[0], 15 * 4);
394   - copy_to_reg(PHY_REG(phy_base, 0x70),
395   - &sdram_params->skew.cs0_dm0_skew[0], 44 * 4);
396   - copy_to_reg(PHY_REG(phy_base, 0xc0),
397   - &sdram_params->skew.cs1_dm0_skew[0], 44 * 4);
398   -}
399   -
400   -static int update_refresh_reg(struct dram_info *dram)
401   -{
402 234 void __iomem *pctl_base = dram->pctl;
  235 + u32 dis_auto_zq = 0;
  236 + u32 pwrctl;
403 237 u32 ret;
404 238  
405   - ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1);
406   - writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3);
  239 + /* disable auto low-power */
  240 + pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL);
  241 + writel(0, pctl_base + DDR_PCTL2_PWRCTL);
407 242  
408   - return 0;
409   -}
  243 + dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl);
410 244  
411   -static int data_training(struct dram_info *dram, u32 cs, u32 dramtype)
412   -{
413   - u32 ret;
414   - u32 dis_auto_zq = 0;
415   - void __iomem *pctl_base = dram->pctl;
416   - void __iomem *phy_base = dram->phy;
  245 + ret = phy_data_training(dram->phy, cs, dramtype);
417 246  
418   - /* disable zqcs */
419   - if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &
420   - (1ul << 31))) {
421   - dis_auto_zq = 1;
422   - setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
423   - }
424   - /* disable auto refresh */
425   - setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
426   - update_refresh_reg(dram);
  247 + pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq);
427 248  
428   - if (dramtype == DDR4) {
429   - clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0);
430   - clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0);
431   - clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0);
432   - clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0);
433   - }
434   - /* choose training cs */
435   - clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs));
436   - /* enable gate training */
437   - clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1);
438   - udelay(50);
439   - ret = readl(PHY_REG(phy_base, 0xff));
440   - /* disable gate training */
441   - clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0);
442   - /* restore zqcs */
443   - if (dis_auto_zq)
444   - clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
445   - /* restore auto refresh */
446   - clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
447   - update_refresh_reg(dram);
  249 + /* restore auto low-power */
  250 + writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL);
448 251  
449   - if (dramtype == DDR4) {
450   - clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0x2);
451   - clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0x2);
452   - clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0x2);
453   - clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0x2);
454   - }
455   -
456   - if (ret & 0x10) {
457   - ret = -1;
458   - } else {
459   - ret = (ret & 0xf) ^ (readl(PHY_REG(phy_base, 0)) >> 4);
460   - ret = (ret == 0) ? 0 : -1;
461   - }
462 252 return ret;
463 253 }
464 254  
465   -/* rank = 1: cs0
466   - * rank = 2: cs1
467   - * rank = 3: cs0 & cs1
468   - * note: be careful of keep mr original val
469   - */
470   -static int write_mr(struct dram_info *dram, u32 rank, u32 mr_num, u32 arg,
471   - u32 dramtype)
472   -{
473   - void __iomem *pctl_base = dram->pctl;
474   -
475   - while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
476   - continue;
477   - if (dramtype == DDR3 || dramtype == DDR4) {
478   - writel((mr_num << 12) | (rank << 4) | (0 << 0),
479   - pctl_base + DDR_PCTL2_MRCTRL0);
480   - writel(arg, pctl_base + DDR_PCTL2_MRCTRL1);
481   - } else {
482   - writel((rank << 4) | (0 << 0),
483   - pctl_base + DDR_PCTL2_MRCTRL0);
484   - writel((mr_num << 8) | (arg & 0xff),
485   - pctl_base + DDR_PCTL2_MRCTRL1);
486   - }
487   -
488   - setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
489   - while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
490   - continue;
491   - while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
492   - continue;
493   -
494   - return 0;
495   -}
496   -
497   -/*
498   - * rank : 1:cs0, 2:cs1, 3:cs0&cs1
499   - * vrefrate: 4500: 45%,
500   - */
501   -static int write_vrefdq(struct dram_info *dram, u32 rank, u32 vrefrate,
502   - u32 dramtype)
503   -{
504   - u32 tccd_l, value;
505   - u32 dis_auto_zq = 0;
506   - void __iomem *pctl_base = dram->pctl;
507   -
508   - if (dramtype != DDR4 || vrefrate < 4500 || vrefrate > 9200)
509   - return -1;
510   -
511   - tccd_l = (readl(pctl_base + DDR_PCTL2_DRAMTMG4) >> 16) & 0xf;
512   - tccd_l = (tccd_l - 4) << 10;
513   -
514   - if (vrefrate > 7500) {
515   - /* range 1 */
516   - value = ((vrefrate - 6000) / 65) | tccd_l;
517   - } else {
518   - /* range 2 */
519   - value = ((vrefrate - 4500) / 65) | tccd_l | (1 << 6);
520   - }
521   -
522   - /* disable zqcs */
523   - if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &
524   - (1ul << 31))) {
525   - dis_auto_zq = 1;
526   - setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
527   - }
528   - /* disable auto refresh */
529   - setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
530   - update_refresh_reg(dram);
531   -
532   - /* enable vrefdq calibratin */
533   - write_mr(dram, rank, 6, value | (1 << 7), dramtype);
534   - udelay(1);/* tvrefdqe */
535   - /* write vrefdq value */
536   - write_mr(dram, rank, 6, value | (1 << 7), dramtype);
537   - udelay(1);/* tvref_time */
538   - write_mr(dram, rank, 6, value | (0 << 7), dramtype);
539   - udelay(1);/* tvrefdqx */
540   -
541   - /* restore zqcs */
542   - if (dis_auto_zq)
543   - clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
544   - /* restore auto refresh */
545   - clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
546   - update_refresh_reg(dram);
547   -
548   - return 0;
549   -}
550   -
551   -#define _MAX_(x, y) ((x) > (y) ? (x) : (y))
552   -
553 255 static void rx_deskew_switch_adjust(struct dram_info *dram)
554 256 {
555 257 u32 i, deskew_val;
... ... @@ -557,7 +259,7 @@
557 259 void __iomem *phy_base = dram->phy;
558 260  
559 261 for (i = 0; i < 4; i++)
560   - gate_val = _MAX_(readl(PHY_REG(phy_base, 0xfb + i)), gate_val);
  262 + gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val);
561 263  
562 264 deskew_val = (gate_val >> 3) + 1;
563 265 deskew_val = (deskew_val > 0x1f) ? 0x1f : deskew_val;
... ... @@ -566,8 +268,6 @@
566 268 (deskew_val & 0x1c) << 2);
567 269 }
568 270  
569   -#undef _MAX_
570   -
571 271 static void tx_deskew_switch_adjust(struct dram_info *dram)
572 272 {
573 273 void __iomem *phy_base = dram->phy;
574 274  
575 275  
576 276  
577 277  
578 278  
579 279  
... ... @@ -580,40 +280,39 @@
580 280 writel(ddrconfig, &dram->msch->ddrconf);
581 281 }
582 282  
583   -static void dram_all_config(struct dram_info *dram,
584   - struct rk3328_sdram_params *sdram_params)
  283 +static void sdram_msch_config(struct msch_regs *msch,
  284 + struct sdram_msch_timings *noc_timings)
585 285 {
586   - u32 sys_reg = 0, tmp = 0;
  286 + writel(noc_timings->ddrtiming.d32, &msch->ddrtiming);
587 287  
588   - set_ddrconfig(dram, sdram_ch.ddrconfig);
  288 + writel(noc_timings->ddrmode.d32, &msch->ddrmode);
  289 + writel(noc_timings->readlatency, &msch->readlatency);
589 290  
590   - sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->dramtype);
591   - sys_reg |= SYS_REG_ENC_ROW_3_4(sdram_ch.row_3_4, 0);
592   - sys_reg |= SYS_REG_ENC_RANK(sdram_ch.rank, 0);
593   - sys_reg |= SYS_REG_ENC_COL(sdram_ch.col, 0);
594   - sys_reg |= SYS_REG_ENC_BK(sdram_ch.bk, 0);
595   - SYS_REG_ENC_CS0_ROW(sdram_ch.cs0_row, sys_reg, tmp, 0);
596   - if (sdram_ch.cs1_row)
597   - SYS_REG_ENC_CS1_ROW(sdram_ch.cs1_row, sys_reg, tmp, 0);
598   - sys_reg |= SYS_REG_ENC_BW(sdram_ch.bw, 0);
599   - sys_reg |= SYS_REG_ENC_DBW(sdram_ch.dbw, 0);
  291 + writel(noc_timings->activate.d32, &msch->activate);
  292 + writel(noc_timings->devtodev.d32, &msch->devtodev);
  293 + writel(noc_timings->ddr4timing.d32, &msch->ddr4_timing);
  294 + writel(noc_timings->agingx0, &msch->aging0);
  295 + writel(noc_timings->agingx0, &msch->aging1);
  296 + writel(noc_timings->agingx0, &msch->aging2);
  297 + writel(noc_timings->agingx0, &msch->aging3);
  298 + writel(noc_timings->agingx0, &msch->aging4);
  299 + writel(noc_timings->agingx0, &msch->aging5);
  300 +}
600 301  
601   - writel(sys_reg, &dram->grf->os_reg[2]);
  302 +static void dram_all_config(struct dram_info *dram,
  303 + struct rk3328_sdram_params *sdram_params)
  304 +{
  305 + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
  306 + u32 sys_reg2 = 0;
  307 + u32 sys_reg3 = 0;
602 308  
603   - writel(sdram_ch.noc_timings.ddrtiming.d32, &dram->msch->ddrtiming);
  309 + set_ddrconfig(dram, cap_info->ddrconfig);
  310 + sdram_org_config(cap_info, &sdram_params->base, &sys_reg2,
  311 + &sys_reg3, 0);
  312 + writel(sys_reg2, &dram->grf->os_reg[2]);
  313 + writel(sys_reg3, &dram->grf->os_reg[3]);
604 314  
605   - writel(sdram_ch.noc_timings.ddrmode.d32, &dram->msch->ddrmode);
606   - writel(sdram_ch.noc_timings.readlatency, &dram->msch->readlatency);
607   -
608   - writel(sdram_ch.noc_timings.activate.d32, &dram->msch->activate);
609   - writel(sdram_ch.noc_timings.devtodev.d32, &dram->msch->devtodev);
610   - writel(sdram_ch.noc_timings.ddr4timing.d32, &dram->msch->ddr4_timing);
611   - writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging0);
612   - writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging1);
613   - writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging2);
614   - writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging3);
615   - writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging4);
616   - writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging5);
  315 + sdram_msch_config(dram->msch, &sdram_ch.noc_timings);
617 316 }
618 317  
619 318 static void enable_low_power(struct dram_info *dram,
... ... @@ -641,6 +340,7 @@
641 340 static int sdram_init(struct dram_info *dram,
642 341 struct rk3328_sdram_params *sdram_params, u32 pre_init)
643 342 {
  343 + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
644 344 void __iomem *pctl_base = dram->pctl;
645 345  
646 346 rkclk_ddr_reset(dram, 1, 1, 1, 1);
647 347  
648 348  
649 349  
... ... @@ -652,30 +352,18 @@
652 352 */
653 353 rkclk_ddr_reset(dram, 1, 1, 1, 0);
654 354 rkclk_configure_ddr(dram, sdram_params);
655   - if (pre_init == 0) {
656   - switch (sdram_params->dramtype) {
657   - case DDR3:
658   - printf("DDR3\n");
659   - break;
660   - case DDR4:
661   - printf("DDR4\n");
662   - break;
663   - case LPDDR3:
664   - default:
665   - printf("LPDDR3\n");
666   - break;
667   - }
668   - }
  355 +
669 356 /* release phy srst to provide clk to ctrl */
670 357 rkclk_ddr_reset(dram, 1, 1, 0, 0);
671 358 udelay(10);
672   - phy_soft_reset(dram);
  359 + phy_soft_reset(dram->phy);
673 360 /* release ctrl presetn, and config ctl registers */
674 361 rkclk_ddr_reset(dram, 1, 0, 0, 0);
675   - pctl_cfg(dram, sdram_params);
676   - sdram_ch.ddrconfig = calculate_ddrconfig(sdram_params);
  362 + pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE);
  363 + cap_info->ddrconfig = calculate_ddrconfig(sdram_params);
677 364 set_ctl_address_map(dram, sdram_params);
678   - phy_cfg(dram, sdram_params);
  365 + phy_cfg(dram->phy, &sdram_params->phy_regs, &sdram_params->skew,
  366 + &sdram_params->base, cap_info->bw);
679 367  
680 368 /* enable dfi_init_start to init phy after ctl srstn deassert */
681 369 setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4));
682 370  
683 371  
... ... @@ -685,13 +373,18 @@
685 373 continue;
686 374  
687 375 /* do ddr gate training */
688   - if (data_training(dram, 0, sdram_params->dramtype) != 0) {
  376 + if (data_training(dram, 0, sdram_params->base.dramtype) != 0) {
689 377 printf("data training error\n");
690 378 return -1;
691 379 }
  380 + if (data_training(dram, 1, sdram_params->base.dramtype) != 0) {
  381 + printf("data training error\n");
  382 + return -1;
  383 + }
692 384  
693   - if (sdram_params->dramtype == DDR4)
694   - write_vrefdq(dram, 0x3, 5670, sdram_params->dramtype);
  385 + if (sdram_params->base.dramtype == DDR4)
  386 + pctl_write_vrefdq(dram->pctl, 0x3, 5670,
  387 + sdram_params->base.dramtype);
695 388  
696 389 if (pre_init == 0) {
697 390 rx_deskew_switch_adjust(dram);
... ... @@ -708,7 +401,7 @@
708 401 struct rk3328_sdram_params *sdram_params,
709 402 unsigned char channel)
710 403 {
711   - void __iomem *pctl_base = dram->pctl;
  404 + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
712 405  
713 406 /*
714 407 * for ddr3: ddrconf = 3
715 408  
... ... @@ -718,14 +411,10 @@
718 411 */
719 412 u32 bk, bktmp;
720 413 u32 col, coltmp;
721   - u32 row, rowtmp, row_3_4;
722   - void __iomem *test_addr, *test_addr1;
723   - u32 dbw;
  414 + u32 rowtmp;
724 415 u32 cs;
725 416 u32 bw = 1;
726   - u64 cap = 0;
727   - u32 dram_type = sdram_params->dramtype;
728   - u32 pwrctl;
  417 + u32 dram_type = sdram_params->base.dramtype;
729 418  
730 419 if (dram_type != DDR4) {
731 420 /* detect col and bk for ddr3/lpddr3 */
732 421  
... ... @@ -733,33 +422,10 @@
733 422 bktmp = 3;
734 423 rowtmp = 16;
735 424  
736   - for (col = coltmp; col >= 9; col -= 1) {
737   - writel(0, SDRAM_ADDR);
738   - test_addr = (void __iomem *)(SDRAM_ADDR +
739   - (1ul << (col + bw - 1ul)));
740   - writel(PATTERN, test_addr);
741   - if ((readl(test_addr) == PATTERN) &&
742   - (readl(SDRAM_ADDR) == 0))
743   - break;
744   - }
745   - if (col == 8) {
746   - printf("col error\n");
  425 + if (sdram_detect_col(cap_info, coltmp) != 0)
747 426 goto cap_err;
748   - }
749   -
750   - test_addr = (void __iomem *)(SDRAM_ADDR +
751   - (1ul << (coltmp + bktmp + bw - 1ul)));
752   - writel(0, SDRAM_ADDR);
753   - writel(PATTERN, test_addr);
754   - if ((readl(test_addr) == PATTERN) &&
755   - (readl(SDRAM_ADDR) == 0))
756   - bk = 3;
757   - else
758   - bk = 2;
759   - if (dram_type == LPDDR3)
760   - dbw = 2;
761   - else
762   - dbw = 1;
  427 + sdram_detect_bank(cap_info, coltmp, bktmp);
  428 + sdram_detect_dbw(cap_info, dram_type);
763 429 } else {
764 430 /* detect bg for ddr4 */
765 431 coltmp = 10;
766 432  
767 433  
768 434  
769 435  
770 436  
771 437  
772 438  
773 439  
774 440  
775 441  
776 442  
777 443  
... ... @@ -768,178 +434,49 @@
768 434  
769 435 col = 10;
770 436 bk = 2;
771   - test_addr = (void __iomem *)(SDRAM_ADDR +
772   - (1ul << (coltmp + bw + 1ul)));
773   - writel(0, SDRAM_ADDR);
774   - writel(PATTERN, test_addr);
775   - if ((readl(test_addr) == PATTERN) &&
776   - (readl(SDRAM_ADDR) == 0))
777   - dbw = 0;
778   - else
779   - dbw = 1;
  437 + cap_info->col = col;
  438 + cap_info->bk = bk;
  439 + sdram_detect_bg(cap_info, coltmp);
780 440 }
  441 +
781 442 /* detect row */
782   - for (row = rowtmp; row > 12; row--) {
783   - writel(0, SDRAM_ADDR);
784   - test_addr = (void __iomem *)(SDRAM_ADDR +
785   - (1ul << (row + bktmp + coltmp + bw - 1ul)));
786   - writel(PATTERN, test_addr);
787   - if ((readl(test_addr) == PATTERN) &&
788   - (readl(SDRAM_ADDR) == 0))
789   - break;
790   - }
791   - if (row == 12) {
792   - printf("row error");
  443 + if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0)
793 444 goto cap_err;
794   - }
  445 +
795 446 /* detect row_3_4 */
796   - test_addr = SDRAM_ADDR;
797   - test_addr1 = (void __iomem *)(SDRAM_ADDR +
798   - (0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul)));
  447 + sdram_detect_row_3_4(cap_info, coltmp, bktmp);
799 448  
800   - writel(0, test_addr);
801   - writel(PATTERN, test_addr1);
802   - if ((readl(test_addr) == 0) &&
803   - (readl(test_addr1) == PATTERN))
804   - row_3_4 = 0;
805   - else
806   - row_3_4 = 1;
807   -
808   - /* disable auto low-power */
809   - pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL);
810   - writel(0, pctl_base + DDR_PCTL2_PWRCTL);
811   -
812   - /* bw and cs detect using phy read gate training */
  449 + /* bw and cs detect using data training */
813 450 if (data_training(dram, 1, dram_type) == 0)
814 451 cs = 1;
815 452 else
816 453 cs = 0;
  454 + cap_info->rank = cs + 1;
817 455  
818 456 bw = 2;
  457 + cap_info->bw = bw;
819 458  
820   - /* restore auto low-power */
821   - writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL);
822   -
823   - sdram_ch.rank = cs + 1;
824   - sdram_ch.col = col;
825   - sdram_ch.bk = bk;
826   - sdram_ch.dbw = dbw;
827   - sdram_ch.bw = bw;
828   - sdram_ch.cs0_row = row;
829   - if (cs)
830   - sdram_ch.cs1_row = row;
831   - else
832   - sdram_ch.cs1_row = 0;
833   - sdram_ch.row_3_4 = row_3_4;
834   -
835   - if (dram_type == DDR4)
836   - cap = 1llu << (cs + row + bk + col + ((dbw == 0) ? 2 : 1) + bw);
837   - else
838   - cap = 1llu << (cs + row + bk + col + bw);
839   -
840   - return cap;
841   -
842   -cap_err:
843   - return 0;
844   -}
845   -
846   -static u32 remodify_sdram_params(struct rk3328_sdram_params *sdram_params)
847   -{
848   - u32 tmp = 0, tmp_adr = 0, i;
849   -
850   - for (i = 0; sdram_params->pctl_regs.pctl[i][0] != 0xFFFFFFFF; i++) {
851   - if (sdram_params->pctl_regs.pctl[i][0] == 0) {
852   - tmp = sdram_params->pctl_regs.pctl[i][1];/* MSTR */
853   - tmp_adr = i;
854   - }
  459 + cap_info->cs0_high16bit_row = cap_info->cs0_row;
  460 + if (cs) {
  461 + cap_info->cs1_row = cap_info->cs0_row;
  462 + cap_info->cs1_high16bit_row = cap_info->cs0_row;
  463 + } else {
  464 + cap_info->cs1_row = 0;
  465 + cap_info->cs1_high16bit_row = 0;
855 466 }
856 467  
857   - tmp &= ~((3ul << 30) | (3ul << 24) | (3ul << 12));
858   -
859   - switch (sdram_ch.dbw) {
860   - case 2:
861   - tmp |= (3ul << 30);
862   - break;
863   - case 1:
864   - tmp |= (2ul << 30);
865   - break;
866   - case 0:
867   - default:
868   - tmp |= (1ul << 30);
869   - break;
870   - }
871   -
872   - if (sdram_ch.rank == 2)
873   - tmp |= 3 << 24;
874   - else
875   - tmp |= 1 << 24;
876   -
877   - tmp |= (2 - sdram_ch.bw) << 12;
878   -
879   - sdram_params->pctl_regs.pctl[tmp_adr][1] = tmp;
880   -
881   - if (sdram_ch.bw == 2)
882   - sdram_ch.noc_timings.ddrtiming.b.bwratio = 0;
883   - else
884   - sdram_ch.noc_timings.ddrtiming.b.bwratio = 1;
885   -
886 468 return 0;
  469 +cap_err:
  470 + return -1;
887 471 }
888 472  
889   -static int dram_detect_cs1_row(struct rk3328_sdram_params *sdram_params,
890   - unsigned char channel)
891   -{
892   - u32 ret = 0;
893   - u32 cs1_bit;
894   - void __iomem *test_addr, *cs1_addr;
895   - u32 row, bktmp, coltmp, bw;
896   - u32 ddrconf = sdram_ch.ddrconfig;
897   -
898   - if (sdram_ch.rank == 2) {
899   - cs1_bit = addrmap[ddrconf][0] + 8;
900   -
901   - if (cs1_bit > 31)
902   - goto out;
903   -
904   - cs1_addr = (void __iomem *)(1ul << cs1_bit);
905   - if (cs1_bit < 20)
906   - cs1_bit = 1;
907   - else
908   - cs1_bit = 0;
909   -
910   - if (sdram_params->dramtype == DDR4) {
911   - if (sdram_ch.dbw == 0)
912   - bktmp = sdram_ch.bk + 2;
913   - else
914   - bktmp = sdram_ch.bk + 1;
915   - } else {
916   - bktmp = sdram_ch.bk;
917   - }
918   - bw = sdram_ch.bw;
919   - coltmp = sdram_ch.col;
920   -
921   - /* detect cs1 row */
922   - for (row = sdram_ch.cs0_row; row > 12; row--) {
923   - test_addr = (void __iomem *)(SDRAM_ADDR + cs1_addr +
924   - (1ul << (row + cs1_bit + bktmp +
925   - coltmp + bw - 1ul)));
926   - writel(0, SDRAM_ADDR + cs1_addr);
927   - writel(PATTERN, test_addr);
928   - if ((readl(test_addr) == PATTERN) &&
929   - (readl(SDRAM_ADDR + cs1_addr) == 0)) {
930   - ret = row;
931   - break;
932   - }
933   - }
934   - }
935   -
936   -out:
937   - return ret;
938   -}
939   -
940 473 static int sdram_init_detect(struct dram_info *dram,
941 474 struct rk3328_sdram_params *sdram_params)
942 475 {
  476 + u32 sys_reg = 0;
  477 + u32 sys_reg3 = 0;
  478 + struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
  479 +
943 480 debug("Starting SDRAM initialization...\n");
944 481  
945 482 memcpy(&sdram_ch, &sdram_params->ch,
946 483  
... ... @@ -949,13 +486,29 @@
949 486 dram_detect_cap(dram, sdram_params, 0);
950 487  
951 488 /* modify bw, cs related timing */
952   - remodify_sdram_params(sdram_params);
  489 + pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info,
  490 + sdram_params->base.dramtype);
  491 +
  492 + if (cap_info->bw == 2)
  493 + sdram_ch.noc_timings.ddrtiming.b.bwratio = 0;
  494 + else
  495 + sdram_ch.noc_timings.ddrtiming.b.bwratio = 1;
  496 +
953 497 /* reinit sdram by real dram cap */
954 498 sdram_init(dram, sdram_params, 0);
955 499  
956 500 /* redetect cs1 row */
957   - sdram_ch.cs1_row =
958   - dram_detect_cs1_row(sdram_params, 0);
  501 + sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype);
  502 + if (cap_info->cs1_row) {
  503 + sys_reg = readl(&dram->grf->os_reg[2]);
  504 + sys_reg3 = readl(&dram->grf->os_reg[3]);
  505 + SYS_REG_ENC_CS1_ROW(cap_info->cs1_row,
  506 + sys_reg, sys_reg3, 0);
  507 + writel(sys_reg, &dram->grf->os_reg[2]);
  508 + writel(sys_reg3, &dram->grf->os_reg[3]);
  509 + }
  510 +
  511 + sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base);
959 512  
960 513 return 0;
961 514 }