MLK-12066 imx: mx7: default enable MDIO open drain

The management data input/output (MDIO) requires open-drain, i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports this feature. So to TO1.1, need to enable open drain by setting bits GPR0[8:7] for TO1.1. Signed-off-by: Peng Fan <peng.fan@nxp.com>

MLK-12066 imx: mx7: default enable MDIO open drain
The management data input/output (MDIO) requires open-drain, i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports this feature. So to TO1.1, need to enable open drain by setting bits GPR0[8:7] for TO1.1. Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan · guoyin.chen
1 parent 945bc1c963
Showing 2 changed files with 22 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/mx7/soc.c
arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -170,6 +170,24 @@
 	writew(enable, &wdog4->wmcr);
 }
  
+static void imx_enet_mdio_fixup(void)
+{
+	struct iomuxc_gpr_base_regs *gpr_regs =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/*
+	 * The management data input/output (MDIO) requires open-drain,
+	 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
+	 * this feature. So to TO1.1, need to enable open drain by setting
+	 * bits GPR0[8:7].
+	 */
+
+	if (is_soc_rev(CHIP_REV_1_1) >= 0) {
+		setbits_le32(&gpr_regs->gpr[0],
+			     IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
+	}
+}
+
 static void set_epdc_qos(void)
 {
 #define REGS_QOS_BASE     QOSC_IPS_BASE_ADDR
@@ -207,6 +225,8 @@
 	imx_set_wdog_powerdown(false);
  
 	imx_set_pcie_phy_power_down();
+
+	imx_enet_mdio_fixup();
  
 #ifdef CONFIG_APBH_DMA
 	/* Start APBH DMA */
@@ -273,6 +273,8 @@
 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT    5
 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK     0x40u
 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT    6
+#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7)
+#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7
 /* GPR1 Bit Fields */
 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK    0x1u
 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT   0
...	...	@@ -170,6 +170,24 @@
170	170	writew(enable, &wdog4->wmcr);
171	171	}
172	172
	173	+static void imx_enet_mdio_fixup(void)
	174	+{
	175	+ struct iomuxc_gpr_base_regs *gpr_regs =
	176	+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
	177	+
	178	+ /*
	179	+ * The management data input/output (MDIO) requires open-drain,
	180	+ * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
	181	+ * this feature. So to TO1.1, need to enable open drain by setting
	182	+ * bits GPR0[8:7].
	183	+ */
	184	+
	185	+ if (is_soc_rev(CHIP_REV_1_1) >= 0) {
	186	+ setbits_le32(&gpr_regs->gpr[0],
	187	+ IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
	188	+ }
	189	+}
	190	+
173	191	static void set_epdc_qos(void)
174	192	{
175	193	#define REGS_QOS_BASE QOSC_IPS_BASE_ADDR
...	...	@@ -207,6 +225,8 @@
207	225	imx_set_wdog_powerdown(false);
208	226
209	227	imx_set_pcie_phy_power_down();
	228	+
	229	+ imx_enet_mdio_fixup();
210	230
211	231	#ifdef CONFIG_APBH_DMA
212	232	/* Start APBH DMA */
...	...	@@ -273,6 +273,8 @@
273	273	#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5
274	274	#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u
275	275	#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6
	276	+#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7)
	277	+#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7
276	278	/* GPR1 Bit Fields */
277	279	#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u
278	280	#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0