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Commit cae7c1b56b4f59289a1b2f10532c2c6a0b12c6c1

Authored by York Sun
Committed by Kumar Gala
1 parent f8bc7bb5a7
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en 

Check second DIMM slot in case the first one is empty.
Honor DQS enable option for SDRAM mode register.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Showing 2 changed files with 14 additions and 9 deletions Side-by-side Diff

arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
Diff comments   View file @ cae7c1b
... ... @@ -160,7 +160,7 @@
160 160 break;
161 161 case 2:
162 162 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
163   - (dimm_number > 1 && dimm_params[dimm_number].n_ranks > 0))
  163 + (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
164 164 go_config = 1;
165 165 break;
166 166 case 3:
... ... @@ -631,7 +631,7 @@
631 631 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
632 632 unsigned int dll_rst_dis; /* DLL reset disable */
633 633 unsigned int dqs_cfg; /* DQS configuration */
634   - unsigned int odt_cfg; /* ODT configuration */
  634 + unsigned int odt_cfg = 0; /* ODT configuration */
635 635 unsigned int num_pr; /* Number of posted refreshes */
636 636 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
637 637 unsigned int ap_en; /* Address Parity Enable */
638 638  
... ... @@ -639,15 +639,16 @@
639 639 unsigned int rcw_en = 0; /* Register Control Word Enable */
640 640 unsigned int md_en = 0; /* Mirrored DIMM Enable */
641 641 unsigned int qd_en = 0; /* quad-rank DIMM Enable */
  642 + int i;
642 643  
643 644 dll_rst_dis = 1; /* Make this configurable */
644 645 dqs_cfg = popts->DQS_config;
645   - if (popts->cs_local_opts[0].odt_rd_cfg
646   - || popts->cs_local_opts[0].odt_wr_cfg) {
647   - /* FIXME */
648   - odt_cfg = 2;
649   - } else {
650   - odt_cfg = 0;
  646 + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  647 + if (popts->cs_local_opts[i].odt_rd_cfg
  648 + || popts->cs_local_opts[i].odt_wr_cfg) {
  649 + odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
  650 + break;
  651 + }
651 652 }
652 653  
653 654 num_pr = 1; /* Make this configurable */
... ... @@ -1032,7 +1033,7 @@
1032 1033 #if defined(CONFIG_FSL_DDR2)
1033 1034 const unsigned int mclk_ps = get_memory_clk_period_ps();
1034 1035 #endif
1035   -
  1036 + dqs_en = !popts->DQS_config;
1036 1037 rtt = fsl_ddr_get_rtt();
1037 1038  
1038 1039 al = additive_latency;
arch/powerpc/include/asm/fsl_ddr_sdram.h
Diff comments   View file @ cae7c1b
... ... @@ -92,6 +92,10 @@
92 92  
93 93 #define SDRAM_CFG2_D_INIT 0x00000010
94 94 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
  95 +#define SDRAM_CFG2_ODT_NEVER 0
  96 +#define SDRAM_CFG2_ODT_ONLY_WRITE 1
  97 +#define SDRAM_CFG2_ODT_ONLY_READ 2
  98 +#define SDRAM_CFG2_ODT_ALWAYS 3
95 99  
96 100 #define TIMING_CFG_2_CPO_MASK 0x0F800000
97 101