Incorporate Patch by Lutz Dennig, 15 Jul 2003.

wdenk
1 parent ad12965db5
Showing 5 changed files with 54 additions and 35 deletions Side-by-side Diff
board/r360mpi/r360mpi.c
cpu/mpc8xx/lcd.c
doc/README.POST
include/configs/R360MPI.h
include/version.h
 /*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -37,9 +37,9 @@
 /*
  *  Memory Controller Using
  *
- *  CS0 - Flash memory            (0x40000000)
- *  CS1 - SDRAM                   (0x00000000}
- *  CS2 -
+ *  CS0 - Flash memory		(0x40000000)
+ *  CS1 - FLASH memory		(0x????????)
+ *  CS2 - SDRAM			(0x00000000)
  *  CS3 -
  *  CS4 -
  *  CS5 -
@@ -148,7 +148,7 @@
 	udelay (1000);
  
 	/*
-	 * Check Bank 0 Memory Size for re-configuration
+	 * Check Bank 2 Memory Size for re-configuration
 	 *
 	 * try 8 column mode
 	 */
@@ -1044,11 +1044,25 @@
 #if defined(CONFIG_R360MPI)
     {
 	extern void r360_i2c_lcd_write (uchar data0, uchar data1);
+	unsigned long bgi, ctr;
+	char *p;
  
+	if ((p = getenv("lcdbgi")) != NULL) {
+		bgi = simple_strtoul (p, 0, 10) & 0xFFF;
+	} else {
+		bgi = 0xFFF;
+	}
+
+	if ((p = getenv("lcdctr")) != NULL) {
+		ctr = simple_strtoul (p, 0, 10) & 0xFFF;
+	} else {
+		ctr=0x7FF;
+	}
+
 	r360_i2c_lcd_write(0x10, 0x01);
 	r360_i2c_lcd_write(0x20, 0x01);
-	r360_i2c_lcd_write(0x3F, 0xFF);
-	r360_i2c_lcd_write(0x47, 0xFF);
+	r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF);
+	r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
     }
 #endif /* CONFIG_R360MPI */
 #ifdef CONFIG_RBC823
@@ -72,20 +72,20 @@
      This group will contain those tests that do not take much
      time and can be run on the regular basis (e.g. CPU test)
  
-  3) Tests running on power-fail booting only
+  3) Tests running on in special "slow test more" only
  
      This group will contain POST tests that consume much time
-     and cannot be run regularly (e.g. I2C test)
+     and cannot be run regularly (e.g. strong memory test, I2C test)
  
   4) Manually executed tests
  
      This group will contain those tests that can be run manually.
  
 If necessary, some tests may belong to several groups simultaneously.
-For example, SDRAM test may run on both noarmal and power-fail
-booting. On normal booting, SDRAM test may perform a fast superficial
-memory test only, while running on power-fail booting it may perform
-a full memory check-up.
+For example, SDRAM test may run in both normal and "slow test" mode.
+In normal mode, SDRAM test may perform a fast superficial memory test
+only, while running in slow test mode it may perform a full memory
+check-up.
  
 Also, all tests will be discriminated by the moment they run at.
 Specifically, the following groups will be singled out:
@@ -114,13 +114,15 @@
  
 The following flags will be defined:
  
-#define POST_ROM		0x01	/* test runs in ROM */
-#define POST_RAM		0x02	/* test runs in RAM */
-#define POST_POWERON		0x04	/* test runs on power-on booting */
-#define POST_NORMAL		0x08	/* test runs on normal booting */
-#define POST_SHUTDOWN		0x10	/* test runs on power-fail booting */
-#define POST_MANUAL		0x20	/* test can be executed manually */
-#define POST_REBOOT		0x80	/* test may cause rebooting */
+#define POST_POWERON		0x01	/* test runs on power-on booting */
+#define POST_NORMAL		0x02	/* test runs on normal booting */
+#define POST_SLOWTEST		0x04	/* test is slow, enabled by key press */
+#define POST_POWERTEST		0x08	/* test runs after watchdog reset */
+#define POST_ROM		0x100	/* test runs in ROM */
+#define POST_RAM		0x200	/* test runs in RAM */
+#define POST_MANUAL		0x400	/* test can be executed manually */
+#define POST_REBOOT		0x800	/* test may cause rebooting */
+#define POST_PREREL             0x1000  /* test runs before relocation */
  
 The POST layer will export the following interface routines:
  
@@ -168,6 +170,13 @@
      will be called on power-fail booting after running all POST
      tests.
  
+  o) int post_hotkeys_pressed(gd_t *gd)
+
+     This routine will scan the keyboard to detect if a magic key
+     combination has been pressed, or otherwise detect if the
+     power-on long-running tests shall be executed or not ("normal"
+     versus "slow" test mode).
+
 The list of available POST tests be kept in the post_tests array
 filled at U-Boot build time. The format of entry in this array will
 be as follows:
@@ -725,9 +734,4 @@
 2.2.3.4. SPI test
  
 TBD
-
-2.3. Design notes
-
-Currently it is unknown how we will power off the board after running
-all power-fail POST tests. This point needs further clarification.
@@ -51,7 +51,7 @@
 #undef	CONFIG_8xx_CONS_NONE
 #define CONFIG_BAUDRATE		115200	/* console baudrate in bps	*/
 #if 0
-#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#define CONFIG_BOOTDELAY	0	/* immediate boot		*/
 #else
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #endif
@@ -77,14 +77,6 @@
  
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
  
-#if 0
-#ifdef CONFIG_LCD
-# undef	 CONFIG_STATUS_LED		/* disturbs display		*/
-#else
-# define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-#endif	/* CONFIG_LCD */
-#endif
-
 #define	CONFIG_CAN_DRIVER		/* CAN Driver support enabled	*/
  
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
@@ -125,6 +117,7 @@
 				CFG_CMD_DATE	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_IDE	| \
+				CFG_CMD_JFFS2	| \
 				CFG_CMD_PCMCIA	| \
 				CFG_CMD_BSP	)
  
@@ -134,6 +127,9 @@
 /*
  * Miscellaneous configurable options
  */
+#define CFG_DEVICE_NULLDEV	1	/* we need the null device	*/
+#define CFG_CONSOLE_IS_IN_ENV	1	/* must set console from env	*/
+
 #define	CFG_LONGHELP			/* undef to save memory		*/
 #define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
@@ -153,6 +149,11 @@
 #define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
  
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* JFFS2 stuff */
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	1
+#define CFG_JFFS2_FIRST_SECTOR	24
  
 /*
  * Low Level Configuration Settings
@@ -24,7 +24,7 @@
 #ifndef	__VERSION_H__
 #define	__VERSION_H__
  
-#define	U_BOOT_VERSION	"U-Boot 0.4.3"
+#define	U_BOOT_VERSION	"U-Boot 0.4.4"
  
 #endif	/* __VERSION_H__ */
1	1	/*
2		- * (C) Copyright 2001
	2	+ * (C) Copyright 2001-2003
3	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	4	*
5	5	* See file CREDITS for list of people who contributed to this
...	...	@@ -37,9 +37,9 @@
37	37	/*
38	38	* Memory Controller Using
39	39	*
40		- * CS0 - Flash memory (0x40000000)
41		- * CS1 - SDRAM (0x00000000}
42		- * CS2 -
	40	+ * CS0 - Flash memory (0x40000000)
	41	+ * CS1 - FLASH memory (0x????????)
	42	+ * CS2 - SDRAM (0x00000000)
43	43	* CS3 -
44	44	* CS4 -
45	45	* CS5 -
...	...	@@ -148,7 +148,7 @@
148	148	udelay (1000);
149	149
150	150	/*
151		- * Check Bank 0 Memory Size for re-configuration
	151	+ * Check Bank 2 Memory Size for re-configuration
152	152	*
153	153	* try 8 column mode
154	154	*/
...	...	@@ -1044,11 +1044,25 @@
1044	1044	#if defined(CONFIG_R360MPI)
1045	1045	{
1046	1046	extern void r360_i2c_lcd_write (uchar data0, uchar data1);
	1047	+ unsigned long bgi, ctr;
	1048	+ char *p;
1047	1049
	1050	+ if ((p = getenv("lcdbgi")) != NULL) {
	1051	+ bgi = simple_strtoul (p, 0, 10) & 0xFFF;
	1052	+ } else {
	1053	+ bgi = 0xFFF;
	1054	+ }
	1055	+
	1056	+ if ((p = getenv("lcdctr")) != NULL) {
	1057	+ ctr = simple_strtoul (p, 0, 10) & 0xFFF;
	1058	+ } else {
	1059	+ ctr=0x7FF;
	1060	+ }
	1061	+
1048	1062	r360_i2c_lcd_write(0x10, 0x01);
1049	1063	r360_i2c_lcd_write(0x20, 0x01);
1050		- r360_i2c_lcd_write(0x3F, 0xFF);
1051		- r360_i2c_lcd_write(0x47, 0xFF);
	1064	+ r360_i2c_lcd_write(0x30 \| ((bgi>>8) & 0xF), bgi & 0xFF);
	1065	+ r360_i2c_lcd_write(0x40 \| ((ctr>>8) & 0xF), ctr & 0xFF);
1052	1066	}
1053	1067	#endif /* CONFIG_R360MPI */
1054	1068	#ifdef CONFIG_RBC823
...	...	@@ -72,20 +72,20 @@
72	72	This group will contain those tests that do not take much
73	73	time and can be run on the regular basis (e.g. CPU test)
74	74
75		- 3) Tests running on power-fail booting only
	75	+ 3) Tests running on in special "slow test more" only
76	76
77	77	This group will contain POST tests that consume much time
78		- and cannot be run regularly (e.g. I2C test)
	78	+ and cannot be run regularly (e.g. strong memory test, I2C test)
79	79
80	80	4) Manually executed tests
81	81
82	82	This group will contain those tests that can be run manually.
83	83
84	84	If necessary, some tests may belong to several groups simultaneously.
85		-For example, SDRAM test may run on both noarmal and power-fail
86		-booting. On normal booting, SDRAM test may perform a fast superficial
87		-memory test only, while running on power-fail booting it may perform
88		-a full memory check-up.
	85	+For example, SDRAM test may run in both normal and "slow test" mode.
	86	+In normal mode, SDRAM test may perform a fast superficial memory test
	87	+only, while running in slow test mode it may perform a full memory
	88	+check-up.
89	89
90	90	Also, all tests will be discriminated by the moment they run at.
91	91	Specifically, the following groups will be singled out:
...	...	@@ -114,13 +114,15 @@
114	114
115	115	The following flags will be defined:
116	116
117		-#define POST_ROM 0x01 /* test runs in ROM */
118		-#define POST_RAM 0x02 /* test runs in RAM */
119		-#define POST_POWERON 0x04 /* test runs on power-on booting */
120		-#define POST_NORMAL 0x08 /* test runs on normal booting */
121		-#define POST_SHUTDOWN 0x10 /* test runs on power-fail booting */
122		-#define POST_MANUAL 0x20 /* test can be executed manually */
123		-#define POST_REBOOT 0x80 /* test may cause rebooting */
	117	+#define POST_POWERON 0x01 /* test runs on power-on booting */
	118	+#define POST_NORMAL 0x02 /* test runs on normal booting */
	119	+#define POST_SLOWTEST 0x04 /* test is slow, enabled by key press */
	120	+#define POST_POWERTEST 0x08 /* test runs after watchdog reset */
	121	+#define POST_ROM 0x100 /* test runs in ROM */
	122	+#define POST_RAM 0x200 /* test runs in RAM */
	123	+#define POST_MANUAL 0x400 /* test can be executed manually */
	124	+#define POST_REBOOT 0x800 /* test may cause rebooting */
	125	+#define POST_PREREL 0x1000 /* test runs before relocation */
124	126
125	127	The POST layer will export the following interface routines:
126	128
...	...	@@ -168,6 +170,13 @@
168	170	will be called on power-fail booting after running all POST
169	171	tests.
170	172
	173	+ o) int post_hotkeys_pressed(gd_t *gd)
	174	+
	175	+ This routine will scan the keyboard to detect if a magic key
	176	+ combination has been pressed, or otherwise detect if the
	177	+ power-on long-running tests shall be executed or not ("normal"
	178	+ versus "slow" test mode).
	179	+
171	180	The list of available POST tests be kept in the post_tests array
172	181	filled at U-Boot build time. The format of entry in this array will
173	182	be as follows:
...	...	@@ -725,9 +734,4 @@
725	734	2.2.3.4. SPI test
726	735
727	736	TBD
728		-
729		-2.3. Design notes
730		-
731		-Currently it is unknown how we will power off the board after running
732		-all power-fail POST tests. This point needs further clarification.
...	...	@@ -51,7 +51,7 @@
51	51	#undef CONFIG_8xx_CONS_NONE
52	52	#define CONFIG_BAUDRATE 115200 /* console baudrate in bps */
53	53	#if 0
54		-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	54	+#define CONFIG_BOOTDELAY 0 /* immediate boot */
55	55	#else
56	56	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
57	57	#endif
...	...	@@ -77,14 +77,6 @@
77	77
78	78	#undef CONFIG_WATCHDOG /* watchdog disabled */
79	79
80		-#if 0
81		-#ifdef CONFIG_LCD
82		-# undef CONFIG_STATUS_LED /* disturbs display */
83		-#else
84		-# define CONFIG_STATUS_LED 1 /* Status LED enabled */
85		-#endif /* CONFIG_LCD */
86		-#endif
87		-
88	80	#define CONFIG_CAN_DRIVER /* CAN Driver support enabled */
89	81
90	82	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT \| CONFIG_BOOTP_BOOTFILESIZE)
...	...	@@ -125,6 +117,7 @@
125	117	CFG_CMD_DATE \| \
126	118	CFG_CMD_I2C \| \
127	119	CFG_CMD_IDE \| \
	120	+ CFG_CMD_JFFS2 \| \
128	121	CFG_CMD_PCMCIA \| \
129	122	CFG_CMD_BSP )
130	123
...	...	@@ -134,6 +127,9 @@
134	127	/*
135	128	* Miscellaneous configurable options
136	129	*/
	130	+#define CFG_DEVICE_NULLDEV 1 /* we need the null device */
	131	+#define CFG_CONSOLE_IS_IN_ENV 1 /* must set console from env */
	132	+
137	133	#define CFG_LONGHELP /* undef to save memory */
138	134	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
139	135	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
...	...	@@ -153,6 +149,11 @@
153	149	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
154	150
155	151	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	152	+
	153	+/* JFFS2 stuff */
	154	+#define CFG_JFFS2_FIRST_BANK 0
	155	+#define CFG_JFFS2_NUM_BANKS 1
	156	+#define CFG_JFFS2_FIRST_SECTOR 24
156	157
157	158	/*
158	159	* Low Level Configuration Settings
...	...	@@ -24,7 +24,7 @@
24	24	#ifndef __VERSION_H__
25	25	#define __VERSION_H__
26	26
27		-#define U_BOOT_VERSION "U-Boot 0.4.3"
	27	+#define U_BOOT_VERSION "U-Boot 0.4.4"
28	28
29	29	#endif /* __VERSION_H__ */