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Commit cb7e5a72e20b2eb427f5bb6ec9e77161cd98938c

Authored by Nishanth Menon
Committed by Lokesh Vutla
1 parent d20abd36f0
Exists in v2015.07-smarct4x and in 3 other branches ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc

ARM: DRA74-evm: Add iodelay values for SR2.0 

Silicon revision 2.0 has new signal routing hence has an updated set of
iodelay parameters to be used. Update the configuration for the same.
Padmux remains the same.

Based on data from VayuES2_EVM_Base_Config-20150807.

NOTE: With respect to the RGMII values, the Manual IODelay values
are used for the fine adjusments needed to meet the tight RGMII
specification.

Signed-off-by: Nishanth Menon <nm@ti.com>

Showing 2 changed files with 83 additions and 11 deletions Side-by-side Diff

board/ti/dra7xx/evm.c
Diff comments   View file @ cb7e5a7
... ... @@ -85,17 +85,33 @@
85 85 #ifdef CONFIG_IODELAY_RECALIBRATION
86 86 void recalibrate_iodelay(void)
87 87 {
88   - if (is_dra72x()) {
89   - __recalibrate_iodelay(dra72x_core_padconf_array,
90   - ARRAY_SIZE(dra72x_core_padconf_array),
91   - iodelay_cfg_array,
92   - ARRAY_SIZE(iodelay_cfg_array));
93   - } else {
94   - __recalibrate_iodelay(dra74x_core_padconf_array,
95   - ARRAY_SIZE(dra74x_core_padconf_array),
96   - dra742_iodelay_cfg_array,
97   - ARRAY_SIZE(dra742_iodelay_cfg_array));
  88 + struct pad_conf_entry const *pads;
  89 + struct iodelay_cfg_entry const *iodelay;
  90 + int npads, niodelays;
  91 +
  92 + switch (omap_revision()) {
  93 + case DRA722_ES1_0:
  94 + pads = dra72x_core_padconf_array;
  95 + npads = ARRAY_SIZE(dra72x_core_padconf_array);
  96 + iodelay = iodelay_cfg_array;
  97 + niodelays = ARRAY_SIZE(iodelay_cfg_array);
  98 + break;
  99 + case DRA752_ES1_0:
  100 + case DRA752_ES1_1:
  101 + pads = dra74x_core_padconf_array;
  102 + npads = ARRAY_SIZE(dra74x_core_padconf_array);
  103 + iodelay = dra742_es1_1_iodelay_cfg_array;
  104 + niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
  105 + break;
  106 + default:
  107 + case DRA752_ES2_0:
  108 + pads = dra74x_core_padconf_array;
  109 + npads = ARRAY_SIZE(dra74x_core_padconf_array);
  110 + iodelay = dra742_es2_0_iodelay_cfg_array;
  111 + niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
  112 + break;
98 113 }
  114 + __recalibrate_iodelay(pads, npads, iodelay, niodelays);
99 115 }
100 116 #endif
101 117  
board/ti/dra7xx/mux_data.h
Diff comments   View file @ cb7e5a7
... ... @@ -397,7 +397,7 @@
397 397 };
398 398  
399 399 #ifdef CONFIG_IODELAY_RECALIBRATION
400   -const struct iodelay_cfg_entry dra742_iodelay_cfg_array[] = {
  400 +const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = {
401 401 {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
402 402 {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
403 403 {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
... ... @@ -451,6 +451,62 @@
451 451 {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
452 452 {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
453 453 {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
  454 +};
  455 +
  456 +const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = {
  457 + {0x06F0, 471, 0}, /* CFG_RGMII0_RXC_IN */
  458 + {0x06FC, 30, 1919}, /* CFG_RGMII0_RXCTL_IN */
  459 + {0x0708, 74, 1688}, /* CFG_RGMII0_RXD0_IN */
  460 + {0x0714, 94, 1697}, /* CFG_RGMII0_RXD1_IN */
  461 + {0x0720, 0, 1703}, /* CFG_RGMII0_RXD2_IN */
  462 + {0x072C, 70, 1804}, /* CFG_RGMII0_RXD3_IN */
  463 + {0x0740, 70, 70}, /* CFG_RGMII0_TXC_OUT */
  464 + {0x074C, 35, 70}, /* CFG_RGMII0_TXCTL_OUT */
  465 + {0x0758, 100, 130}, /* CFG_RGMII0_TXD0_OUT */
  466 + {0x0764, 0, 70}, /* CFG_RGMII0_TXD1_OUT */
  467 + {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
  468 + {0x077C, 100, 130}, /* CFG_RGMII0_TXD3_OUT */
  469 + {0x08D0, 0, 0}, /* CFG_VIN1A_CLK0_IN */
  470 + {0x08DC, 2105, 619}, /* CFG_VIN1A_D0_IN */
  471 + {0x08E8, 2107, 739}, /* CFG_VIN1A_D10_IN */
  472 + {0x08F4, 2005, 788}, /* CFG_VIN1A_D11_IN */
  473 + {0x0900, 2059, 1297}, /* CFG_VIN1A_D12_IN */
  474 + {0x090C, 2027, 1141}, /* CFG_VIN1A_D13_IN */
  475 + {0x0918, 2071, 1332}, /* CFG_VIN1A_D14_IN */
  476 + {0x0924, 1995, 1764}, /* CFG_VIN1A_D15_IN */
  477 + {0x0930, 1999, 1542}, /* CFG_VIN1A_D16_IN */
  478 + {0x093C, 2072, 1540}, /* CFG_VIN1A_D17_IN */
  479 + {0x0948, 2034, 1629}, /* CFG_VIN1A_D18_IN */
  480 + {0x0954, 2026, 1761}, /* CFG_VIN1A_D19_IN */
  481 + {0x0960, 2017, 757}, /* CFG_VIN1A_D1_IN */
  482 + {0x096C, 2037, 1469}, /* CFG_VIN1A_D20_IN */
  483 + {0x0978, 2077, 1349}, /* CFG_VIN1A_D21_IN */
  484 + {0x0984, 2022, 1545}, /* CFG_VIN1A_D22_IN */
  485 + {0x0990, 2168, 784}, /* CFG_VIN1A_D23_IN */
  486 + {0x099C, 1996, 962}, /* CFG_VIN1A_D2_IN */
  487 + {0x09A8, 1993, 901}, /* CFG_VIN1A_D3_IN */
  488 + {0x09B4, 2098, 499}, /* CFG_VIN1A_D4_IN */
  489 + {0x09C0, 2038, 844}, /* CFG_VIN1A_D5_IN */
  490 + {0x09CC, 2002, 863}, /* CFG_VIN1A_D6_IN */
  491 + {0x09D8, 2063, 873}, /* CFG_VIN1A_D7_IN */
  492 + {0x09E4, 2088, 759}, /* CFG_VIN1A_D8_IN */
  493 + {0x09F0, 2152, 701}, /* CFG_VIN1A_D9_IN */
  494 + {0x09FC, 1926, 728}, /* CFG_VIN1A_DE0_IN */
  495 + {0x0A08, 2043, 937}, /* CFG_VIN1A_FLD0_IN */
  496 + {0x0A14, 1978, 909}, /* CFG_VIN1A_HSYNC0_IN */
  497 + {0x0A20, 1926, 987}, /* CFG_VIN1A_VSYNC0_IN */
  498 + {0x0A70, 140, 0}, /* CFG_VIN2A_D12_OUT */
  499 + {0x0A7C, 90, 70}, /* CFG_VIN2A_D13_OUT */
  500 + {0x0A88, 0, 0}, /* CFG_VIN2A_D14_OUT */
  501 + {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
  502 + {0x0AA0, 0, 70}, /* CFG_VIN2A_D16_OUT */
  503 + {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
  504 + {0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */
  505 + {0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */
  506 + {0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */
  507 + {0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */
  508 + {0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */
  509 + {0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */
454 510 };
455 511 #endif
456 512