Eric Lee / smarc-uboot

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Commit cba69eeeaa67d3fb93ec6f3abab1f653abf895a9

Authored by Ian Campbell
Committed by Albert ARIBAUD
1 parent 286c3c3a5e
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

sunxi: add sun7i cpu, board and start of day support 

This patch adds generic board, start of day and basic build system support for
the Allwinner A20 (sun7i) processor. This code will not been compiled until the
build is hooked up in a later patch. It has been split out to keep the patches
manageable.

Signed-off-by: Adam Sampson <ats@offog.org>
Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Patrick Wood <patrickhwood@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>

Showing 12 changed files with 572 additions and 1 deletions Side-by-side Diff

arch/arm/cpu/armv7/Makefile
Diff comments   View file @ cba69ee
... ... @@ -12,7 +12,7 @@
12 12 obj-y += cpu.o
13 13 obj-y += syslib.o
14 14  
15   -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),)
  15 +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
16 16 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
17 17 obj-y += lowlevel_init.o
18 18 endif
arch/arm/cpu/armv7/sunxi/Makefile
Diff comments   View file @ cba69ee
... ... @@ -8,8 +8,19 @@
8 8 # SPDX-License-Identifier: GPL-2.0+
9 9 #
10 10 obj-y += timer.o
  11 +obj-y += board.o
11 12 obj-y += clock.o
12 13 obj-y += pinmux.o
13 14 obj-$(CONFIG_SUN7I) += clock_sun4i.o
  15 +
  16 +ifndef CONFIG_SPL_BUILD
  17 +obj-y += cpu_info.o
  18 +endif
  19 +
  20 +ifdef CONFIG_SPL_BUILD
14 21 obj-$(CONFIG_SUN7I) += dram.o
  22 +ifdef CONFIG_SPL_FEL
  23 +obj-y += start.o
  24 +endif
  25 +endif
arch/arm/cpu/armv7/sunxi/board.c
Diff comments   View file @ cba69ee
  1 +/*
  2 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
  3 + *
  4 + * (C) Copyright 2007-2011
  5 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  6 + * Tom Cubie <tangliang@allwinnertech.com>
  7 + *
  8 + * Some init for sunxi platform.
  9 + *
  10 + * SPDX-License-Identifier: GPL-2.0+
  11 + */
  12 +
  13 +#include <common.h>
  14 +#include <serial.h>
  15 +#ifdef CONFIG_SPL_BUILD
  16 +#include <spl.h>
  17 +#endif
  18 +#include <asm/gpio.h>
  19 +#include <asm/io.h>
  20 +#include <asm/arch/clock.h>
  21 +#include <asm/arch/gpio.h>
  22 +#include <asm/arch/sys_proto.h>
  23 +#include <asm/arch/timer.h>
  24 +
  25 +#ifdef CONFIG_SPL_BUILD
  26 +/* Pointer to the global data structure for SPL */
  27 +DECLARE_GLOBAL_DATA_PTR;
  28 +
  29 +/* The sunxi internal brom will try to loader external bootloader
  30 + * from mmc0, nand flash, mmc2.
  31 + * Unfortunately we can't check how SPL was loaded so assume
  32 + * it's always the first SD/MMC controller
  33 + */
  34 +u32 spl_boot_device(void)
  35 +{
  36 + return BOOT_DEVICE_MMC1;
  37 +}
  38 +
  39 +/* No confirmation data available in SPL yet. Hardcode bootmode */
  40 +u32 spl_boot_mode(void)
  41 +{
  42 + return MMCSD_MODE_RAW;
  43 +}
  44 +#endif
  45 +
  46 +int gpio_init(void)
  47 +{
  48 + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
  49 + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
  50 + sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
  51 +
  52 + return 0;
  53 +}
  54 +
  55 +void reset_cpu(ulong addr)
  56 +{
  57 +}
  58 +
  59 +/* do some early init */
  60 +void s_init(void)
  61 +{
  62 +#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
  63 + /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
  64 + asm volatile(
  65 + "mrc p15, 0, r0, c1, c0, 1\n"
  66 + "orr r0, r0, #1 << 6\n"
  67 + "mcr p15, 0, r0, c1, c0, 1\n");
  68 +#endif
  69 +
  70 + clock_init();
  71 + timer_init();
  72 + gpio_init();
  73 +
  74 +#ifdef CONFIG_SPL_BUILD
  75 + gd = &gdata;
  76 + preloader_console_init();
  77 +
  78 + sunxi_board_init();
  79 +#endif
  80 +}
  81 +
  82 +#ifndef CONFIG_SYS_DCACHE_OFF
  83 +void enable_caches(void)
  84 +{
  85 + /* Enable D-cache. I-cache is already enabled in start.S */
  86 + dcache_enable();
  87 +}
  88 +#endif
arch/arm/cpu/armv7/sunxi/cpu_info.c
Diff comments   View file @ cba69ee
  1 +/*
  2 + * (C) Copyright 2007-2011
  3 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  4 + * Tom Cubie <tangliang@allwinnertech.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <asm/io.h>
  11 +#include <asm/arch/cpu.h>
  12 +
  13 +#ifdef CONFIG_DISPLAY_CPUINFO
  14 +int print_cpuinfo(void)
  15 +{
  16 + puts("CPU: Allwinner A20 (SUN7I)\n");
  17 + return 0;
  18 +}
  19 +#endif
arch/arm/cpu/armv7/sunxi/start.c
Diff comments   View file @ cba69ee
  1 +/* Intentionally empty. Only needed to get FEL SPL link line right */
arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
Diff comments   View file @ cba69ee
  1 +/*
  2 + * (C) Copyright 2013
  3 + * Henrik Nordstrom <henrik@henriknordstrom.net>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
  8 +OUTPUT_ARCH(arm)
  9 +ENTRY(s_init)
  10 +SECTIONS
  11 +{
  12 + . = 0x00002000;
  13 +
  14 + . = ALIGN(4);
  15 + .text :
  16 + {
  17 + *(.text.s_init)
  18 + *(.text*)
  19 + }
  20 +
  21 + . = ALIGN(4);
  22 + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
  23 +
  24 + . = ALIGN(4);
  25 + .data : {
  26 + *(.data*)
  27 + }
  28 +
  29 + . = ALIGN(4);
  30 + . = .;
  31 +
  32 + . = ALIGN(4);
  33 + .rel.dyn : {
  34 + __rel_dyn_start = .;
  35 + *(.rel*)
  36 + __rel_dyn_end = .;
  37 + }
  38 +
  39 + .dynsym : {
  40 + __dynsym_start = .;
  41 + *(.dynsym)
  42 + }
  43 +
  44 + . = ALIGN(4);
  45 + .note.gnu.build-id :
  46 + {
  47 + *(.note.gnu.build-id)
  48 + }
  49 + _end = .;
  50 +
  51 + . = ALIGN(4096);
  52 + .mmutable : {
  53 + *(.mmutable)
  54 + }
  55 +
  56 + .bss_start __rel_dyn_start (OVERLAY) : {
  57 + KEEP(*(.__bss_start));
  58 + __bss_base = .;
  59 + }
  60 +
  61 + .bss __bss_base (OVERLAY) : {
  62 + *(.bss*)
  63 + . = ALIGN(4);
  64 + __bss_limit = .;
  65 + }
  66 +
  67 + .bss_end __bss_limit (OVERLAY) : {
  68 + KEEP(*(.__bss_end));
  69 + }
  70 +
  71 + /DISCARD/ : { *(.dynstr*) }
  72 + /DISCARD/ : { *(.dynamic*) }
  73 + /DISCARD/ : { *(.plt*) }
  74 + /DISCARD/ : { *(.interp*) }
  75 + /DISCARD/ : { *(.gnu*) }
  76 + /DISCARD/ : { *(.note*) }
  77 +}
arch/arm/include/asm/arch-sunxi/cpu.h
Diff comments   View file @ cba69ee
  1 +/*
  2 + * (C) Copyright 2007-2011
  3 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  4 + * Tom Cubie <tangliang@allwinnertech.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef _SUNXI_CPU_H
  10 +#define _SUNXI_CPU_H
  11 +
  12 +#define SUNXI_SRAM_A1_BASE 0x00000000
  13 +#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
  14 +
  15 +#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
  16 +#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
  17 +#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
  18 +#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
  19 +#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
  20 +
  21 +#define SUNXI_SRAMC_BASE 0x01c00000
  22 +#define SUNXI_DRAMC_BASE 0x01c01000
  23 +#define SUNXI_DMA_BASE 0x01c02000
  24 +#define SUNXI_NFC_BASE 0x01c03000
  25 +#define SUNXI_TS_BASE 0x01c04000
  26 +#define SUNXI_SPI0_BASE 0x01c05000
  27 +#define SUNXI_SPI1_BASE 0x01c06000
  28 +#define SUNXI_MS_BASE 0x01c07000
  29 +#define SUNXI_TVD_BASE 0x01c08000
  30 +#define SUNXI_CSI0_BASE 0x01c09000
  31 +#define SUNXI_TVE0_BASE 0x01c0a000
  32 +#define SUNXI_EMAC_BASE 0x01c0b000
  33 +#define SUNXI_LCD0_BASE 0x01c0C000
  34 +#define SUNXI_LCD1_BASE 0x01c0d000
  35 +#define SUNXI_VE_BASE 0x01c0e000
  36 +#define SUNXI_MMC0_BASE 0x01c0f000
  37 +#define SUNXI_MMC1_BASE 0x01c10000
  38 +#define SUNXI_MMC2_BASE 0x01c11000
  39 +#define SUNXI_MMC3_BASE 0x01c12000
  40 +#define SUNXI_USB0_BASE 0x01c13000
  41 +#define SUNXI_USB1_BASE 0x01c14000
  42 +#define SUNXI_SS_BASE 0x01c15000
  43 +#define SUNXI_HDMI_BASE 0x01c16000
  44 +#define SUNXI_SPI2_BASE 0x01c17000
  45 +#define SUNXI_SATA_BASE 0x01c18000
  46 +#define SUNXI_PATA_BASE 0x01c19000
  47 +#define SUNXI_ACE_BASE 0x01c1a000
  48 +#define SUNXI_TVE1_BASE 0x01c1b000
  49 +#define SUNXI_USB2_BASE 0x01c1c000
  50 +#define SUNXI_CSI1_BASE 0x01c1d000
  51 +#define SUNXI_TZASC_BASE 0x01c1e000
  52 +#define SUNXI_SPI3_BASE 0x01c1f000
  53 +
  54 +#define SUNXI_CCM_BASE 0x01c20000
  55 +#define SUNXI_INTC_BASE 0x01c20400
  56 +#define SUNXI_PIO_BASE 0x01c20800
  57 +#define SUNXI_TIMER_BASE 0x01c20c00
  58 +#define SUNXI_SPDIF_BASE 0x01c21000
  59 +#define SUNXI_AC97_BASE 0x01c21400
  60 +#define SUNXI_IR0_BASE 0x01c21800
  61 +#define SUNXI_IR1_BASE 0x01c21c00
  62 +
  63 +#define SUNXI_IIS_BASE 0x01c22400
  64 +#define SUNXI_LRADC_BASE 0x01c22800
  65 +#define SUNXI_AD_DA_BASE 0x01c22c00
  66 +#define SUNXI_KEYPAD_BASE 0x01c23000
  67 +#define SUNXI_TZPC_BASE 0x01c23400
  68 +#define SUNXI_SID_BASE 0x01c23800
  69 +#define SUNXI_SJTAG_BASE 0x01c23c00
  70 +
  71 +#define SUNXI_TP_BASE 0x01c25000
  72 +#define SUNXI_PMU_BASE 0x01c25400
  73 +#define SUNXI_CPUCFG_BASE 0x01c25c00
  74 +
  75 +#define SUNXI_UART0_BASE 0x01c28000
  76 +#define SUNXI_UART1_BASE 0x01c28400
  77 +#define SUNXI_UART2_BASE 0x01c28800
  78 +#define SUNXI_UART3_BASE 0x01c28c00
  79 +#define SUNXI_UART4_BASE 0x01c29000
  80 +#define SUNXI_UART5_BASE 0x01c29400
  81 +#define SUNXI_UART6_BASE 0x01c29800
  82 +#define SUNXI_UART7_BASE 0x01c29c00
  83 +#define SUNXI_PS2_0_BASE 0x01c2a000
  84 +#define SUNXI_PS2_1_BASE 0x01c2a400
  85 +
  86 +#define SUNXI_TWI0_BASE 0x01c2ac00
  87 +#define SUNXI_TWI1_BASE 0x01c2b000
  88 +#define SUNXI_TWI2_BASE 0x01c2b400
  89 +
  90 +#define SUNXI_CAN_BASE 0x01c2bc00
  91 +
  92 +#define SUNXI_SCR_BASE 0x01c2c400
  93 +
  94 +#define SUNXI_GPS_BASE 0x01c30000
  95 +#define SUNXI_MALI400_BASE 0x01c40000
  96 +#define SUNXI_GMAC_BASE 0x01c50000
  97 +
  98 +/* module sram */
  99 +#define SUNXI_SRAM_C_BASE 0x01d00000
  100 +
  101 +#define SUNXI_DE_FE0_BASE 0x01e00000
  102 +#define SUNXI_DE_FE1_BASE 0x01e20000
  103 +#define SUNXI_DE_BE0_BASE 0x01e60000
  104 +#define SUNXI_DE_BE1_BASE 0x01e40000
  105 +#define SUNXI_MP_BASE 0x01e80000
  106 +#define SUNXI_AVG_BASE 0x01ea0000
  107 +
  108 +/* CoreSight Debug Module */
  109 +#define SUNXI_CSDM_BASE 0x3f500000
  110 +
  111 +#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */
  112 +
  113 +#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */
  114 +
  115 +#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
  116 +
  117 +#ifndef __ASSEMBLY__
  118 +void sunxi_board_init(void);
  119 +void sunxi_reset(void);
  120 +#endif /* __ASSEMBLY__ */
  121 +
  122 +#endif /* _CPU_H */
arch/arm/include/asm/arch-sunxi/spl.h
Diff comments   View file @ cba69ee
  1 +/*
  2 + * This is a copy of omap3/spl.h:
  3 + *
  4 + * (C) Copyright 2012
  5 + * Texas Instruments, <www.ti.com>
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +#ifndef _ASM_ARCH_SPL_H_
  10 +#define _ASM_SPL_H_
  11 +
  12 +#define BOOT_DEVICE_NONE 0
  13 +#define BOOT_DEVICE_XIP 1
  14 +#define BOOT_DEVICE_NAND 2
  15 +#define BOOT_DEVICE_ONE_NAND 3
  16 +#define BOOT_DEVICE_MMC2 5 /*emmc*/
  17 +#define BOOT_DEVICE_MMC1 6
  18 +#define BOOT_DEVICE_XIPWAIT 7
  19 +#define BOOT_DEVICE_MMC2_2 0xff
  20 +#endif
board/sunxi/Makefile
Diff comments   View file @ cba69ee
  1 +#
  2 +# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
  3 +#
  4 +# Based on some other board Makefile
  5 +#
  6 +# (C) Copyright 2000-2003
  7 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8 +#
  9 +# SPDX-License-Identifier: GPL-2.0+
  10 +#
  11 +obj-y += board.o
  1 +/*
  2 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
  3 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  4 + *
  5 + * (C) Copyright 2007-2011
  6 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  7 + * Tom Cubie <tangliang@allwinnertech.com>
  8 + *
  9 + * Some board init for the Allwinner A10-evb board.
  10 + *
  11 + * SPDX-License-Identifier: GPL-2.0+
  12 + */
  13 +
  14 +#include <common.h>
  15 +#include <asm/arch/clock.h>
  16 +#include <asm/arch/dram.h>
  17 +
  18 +DECLARE_GLOBAL_DATA_PTR;
  19 +
  20 +/* add board specific code here */
  21 +int board_init(void)
  22 +{
  23 + int id_pfr1;
  24 +
  25 + gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
  26 +
  27 + asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
  28 + debug("id_pfr1: 0x%08x\n", id_pfr1);
  29 + /* Generic Timer Extension available? */
  30 + if ((id_pfr1 >> 16) & 0xf) {
  31 + debug("Setting CNTFRQ\n");
  32 + /* CNTFRQ == 24 MHz */
  33 + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
  34 + }
  35 +
  36 + return 0;
  37 +}
  38 +
  39 +int dram_init(void)
  40 +{
  41 + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
  42 +
  43 + return 0;
  44 +}
  45 +
  46 +#ifdef CONFIG_SPL_BUILD
  47 +void sunxi_board_init(void)
  48 +{
  49 + unsigned long ramsize;
  50 +
  51 + printf("DRAM:");
  52 + ramsize = sunxi_dram_init();
  53 + printf(" %lu MiB\n", ramsize >> 20);
  54 + if (!ramsize)
  55 + hang();
  56 +}
  57 +#endif
include/configs/sun7i.h
Diff comments   View file @ cba69ee
  1 +/*
  2 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
  3 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  4 + *
  5 + * Configuration settings for the Allwinner A20 (sun7i) CPU
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +#ifndef __CONFIG_H
  10 +#define __CONFIG_H
  11 +
  12 +/*
  13 + * A20 specific configuration
  14 + */
  15 +#define CONFIG_SUN7I /* sun7i SoC generation */
  16 +
  17 +#define CONFIG_SYS_PROMPT "sun7i# "
  18 +
  19 +/*
  20 + * Include common sunxi configuration where most the settings are
  21 + */
  22 +#include <configs/sunxi-common.h>
  23 +
  24 +#endif /* __CONFIG_H */
include/configs/sunxi-common.h
Diff comments   View file @ cba69ee
  1 +/*
  2 + * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
  3 + *
  4 + * (C) Copyright 2007-2011
  5 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  6 + * Tom Cubie <tangliang@allwinnertech.com>
  7 + *
  8 + * Configuration settings for the Allwinner sunxi series of boards.
  9 + *
  10 + * SPDX-License-Identifier: GPL-2.0+
  11 + */
  12 +
  13 +#ifndef _SUNXI_COMMON_CONFIG_H
  14 +#define _SUNXI_COMMON_CONFIG_H
  15 +
  16 +/*
  17 + * High Level Configuration Options
  18 + */
  19 +#define CONFIG_SUNXI /* sunxi family */
  20 +
  21 +#include <asm/arch/cpu.h> /* get chip and board defs */
  22 +
  23 +#define CONFIG_SYS_TEXT_BASE 0x4a000000
  24 +
  25 +/*
  26 + * Display CPU information
  27 + */
  28 +#define CONFIG_DISPLAY_CPUINFO
  29 +
  30 +/* Serial & console */
  31 +#define CONFIG_SYS_NS16550
  32 +#define CONFIG_SYS_NS16550_SERIAL
  33 +/* ns16550 reg in the low bits of cpu reg */
  34 +#define CONFIG_SYS_NS16550_REG_SIZE -4
  35 +#define CONFIG_SYS_NS16550_CLK 24000000
  36 +#define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
  37 +#define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
  38 +#define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
  39 +#define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
  40 +
  41 +/* DRAM Base */
  42 +#define CONFIG_SYS_SDRAM_BASE 0x40000000
  43 +#define CONFIG_SYS_INIT_RAM_ADDR 0x0
  44 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
  45 +
  46 +#define CONFIG_SYS_INIT_SP_OFFSET \
  47 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  48 +#define CONFIG_SYS_INIT_SP_ADDR \
  49 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  50 +
  51 +#define CONFIG_NR_DRAM_BANKS 1
  52 +#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
  53 +#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
  54 +
  55 +#define CONFIG_CMD_MEMORY
  56 +#define CONFIG_CMD_SETEXPR
  57 +
  58 +#define CONFIG_SETUP_MEMORY_TAGS
  59 +#define CONFIG_CMDLINE_TAG
  60 +#define CONFIG_INITRD_TAG
  61 +
  62 +/* 4MB of malloc() pool */
  63 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
  64 +
  65 +/*
  66 + * Miscellaneous configurable options
  67 + */
  68 +#define CONFIG_CMD_ECHO
  69 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  70 +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
  71 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  72 +#define CONFIG_SYS_GENERIC_BOARD
  73 +
  74 +/* Boot Argument Buffer Size */
  75 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  76 +
  77 +#define CONFIG_SYS_LOAD_ADDR 0x48000000 /* default load address */
  78 +
  79 +/* standalone support */
  80 +#define CONFIG_STANDALONE_LOAD_ADDR 0x48000000
  81 +
  82 +#define CONFIG_SYS_HZ 1000
  83 +
  84 +/* baudrate */
  85 +#define CONFIG_BAUDRATE 115200
  86 +
  87 +/* The stack sizes are set up in start.S using the settings below */
  88 +#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
  89 +
  90 +/* FLASH and environment organization */
  91 +
  92 +#define CONFIG_SYS_NO_FLASH
  93 +
  94 +#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KiB */
  95 +#define CONFIG_IDENT_STRING " Allwinner Technology"
  96 +
  97 +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
  98 +
  99 +#define CONFIG_EXTRA_ENV_SETTINGS \
  100 + "bootm_size=0x10000000\0"
  101 +
  102 +#define CONFIG_SYS_BOOT_GET_CMDLINE
  103 +
  104 +#include <config_cmd_default.h>
  105 +
  106 +#define CONFIG_FAT_WRITE /* enable write access */
  107 +
  108 +#define CONFIG_SPL_FRAMEWORK
  109 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  110 +#define CONFIG_SPL_SERIAL_SUPPORT
  111 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
  112 +
  113 +#define CONFIG_SPL
  114 +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds"
  115 +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi"
  116 +#define CONFIG_SPL_TEXT_BASE 0x2000
  117 +#define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */
  118 +/* end of 32 KiB in sram */
  119 +#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */
  120 +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
  121 +#define CONFIG_SYS_SPL_MALLOC_START 0x4ff00000
  122 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */
  123 +
  124 +#undef CONFIG_CMD_FPGA
  125 +#undef CONFIG_CMD_NET
  126 +#undef CONFIG_CMD_NFS
  127 +
  128 +#define CONFIG_CONS_INDEX 1 /* UART0 */
  129 +
  130 +#if !defined CONFIG_ENV_IS_IN_MMC && \
  131 + !defined CONFIG_ENV_IS_IN_NAND && \
  132 + !defined CONFIG_ENV_IS_IN_FAT && \
  133 + !defined CONFIG_ENV_IS_IN_SPI_FLASH
  134 +#define CONFIG_ENV_IS_NOWHERE
  135 +#endif
  136 +
  137 +#ifndef CONFIG_SPL_BUILD
  138 +#include <config_distro_defaults.h>
  139 +#endif
  140 +
  141 +#endif /* _SUNXI_COMMON_CONFIG_H */