Commit cc19c25e2752bb8b446463eb627e258e659d73d9
Committed by
York Sun
York Sun
1 parent
48c6f328f0
Exists in
v2017.01-smarct4x
and in
37 other branches
net/fman: update 10GEC to fit new SoC
fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER. but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs. on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Showing 6 changed files with 38 additions and 2 deletions Side-by-side Diff
arch/powerpc/include/asm/config_mpc85xx.h
| ... | ... | @@ -812,6 +812,7 @@ |
| 812 | 812 | #define CONFIG_SYS_NUM_FMAN 1 |
| 813 | 813 | #define CONFIG_SYS_NUM_FM1_DTSEC 4 |
| 814 | 814 | #define CONFIG_SYS_NUM_FM1_10GEC 1 |
| 815 | +#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION | |
| 815 | 816 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 816 | 817 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
| 817 | 818 | #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 |
arch/powerpc/include/asm/immap_85xx.h
| ... | ... | @@ -1626,10 +1626,15 @@ |
| 1626 | 1626 | #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000 |
| 1627 | 1627 | #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000 |
| 1628 | 1628 | #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000 |
| 1629 | +#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION | |
| 1630 | +#define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000 | |
| 1631 | +#define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000 | |
| 1632 | +#else | |
| 1629 | 1633 | #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000 |
| 1630 | 1634 | #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000 |
| 1631 | 1635 | #define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000 |
| 1632 | 1636 | #define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000 |
| 1637 | +#endif | |
| 1633 | 1638 | #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000 |
| 1634 | 1639 | #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000 |
| 1635 | 1640 | #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000 |
doc/README.fsl-dpaa
| 1 | +This file documents Freescale DPAA-specific options. | |
| 2 | + | |
| 3 | +FMan (Frame Manager) | |
| 4 | + - CONFIG_FSL_FM_10GEC_REGULAR_NOTATION | |
| 5 | + on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: | |
| 6 | + 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 | |
| 7 | + on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: | |
| 8 | + 10GEC1->MAC1, 10GEC2->MAC2 | |
| 9 | + so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on | |
| 10 | + which 10GEC enumeration is consistent with MAC enumeration. |
drivers/net/fm/eth.c
| ... | ... | @@ -565,9 +565,11 @@ |
| 565 | 565 | num = fm_eth->num; |
| 566 | 566 | |
| 567 | 567 | #ifdef CONFIG_SYS_FMAN_V3 |
| 568 | +#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION | |
| 568 | 569 | if (fm_eth->type == FM_ETH_10G_E) { |
| 569 | - /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 | |
| 570 | - * 10GEC3/10GEC4 use mEMAC1/mEMAC2 | |
| 570 | + /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240. | |
| 571 | + * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080. | |
| 572 | + * 10GEC1 uses mEMAC1 on T1024. | |
| 571 | 573 | * so it needs to change the num. |
| 572 | 574 | */ |
| 573 | 575 | if (fm_eth->num >= 2) |
| ... | ... | @@ -575,6 +577,7 @@ |
| 575 | 577 | else |
| 576 | 578 | num += 8; |
| 577 | 579 | } |
| 580 | +#endif | |
| 578 | 581 | base = ®->memac[num].fm_memac; |
| 579 | 582 | phyregs = ®->memac[num].fm_memac_mdio; |
| 580 | 583 | #else |
drivers/net/fm/init.c
| ... | ... | @@ -254,8 +254,10 @@ |
| 254 | 254 | */ |
| 255 | 255 | if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) || |
| 256 | 256 | ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) || |
| 257 | + ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) || | |
| 257 | 258 | ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) || |
| 258 | 259 | ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) || |
| 260 | + ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) || | |
| 259 | 261 | ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) || |
| 260 | 262 | ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) || |
| 261 | 263 | ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) || |
include/fm_eth.h
| ... | ... | @@ -75,8 +75,22 @@ |
| 75 | 75 | offsetof(struct ccsr_fman, memac[n-1]),\ |
| 76 | 76 | } |
| 77 | 77 | |
| 78 | +#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION | |
| 78 | 79 | #define FM_TGEC_INFO_INITIALIZER(idx, n) \ |
| 79 | 80 | { \ |
| 81 | + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ | |
| 82 | + .index = idx, \ | |
| 83 | + .num = n - 1, \ | |
| 84 | + .type = FM_ETH_10G_E, \ | |
| 85 | + .port = FM##idx##_10GEC##n, \ | |
| 86 | + .rx_port_id = RX_PORT_10G_BASE2 + n - 1, \ | |
| 87 | + .tx_port_id = TX_PORT_10G_BASE2 + n - 1, \ | |
| 88 | + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ | |
| 89 | + offsetof(struct ccsr_fman, memac[n-1]),\ | |
| 90 | +} | |
| 91 | +#else | |
| 92 | +#define FM_TGEC_INFO_INITIALIZER(idx, n) \ | |
| 93 | +{ \ | |
| 80 | 94 | FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \ |
| 81 | 95 | .index = idx, \ |
| 82 | 96 | .num = n - 1, \ |
| ... | ... | @@ -87,6 +101,7 @@ |
| 87 | 101 | .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ |
| 88 | 102 | offsetof(struct ccsr_fman, memac[n-1+8]),\ |
| 89 | 103 | } |
| 104 | +#endif | |
| 90 | 105 | |
| 91 | 106 | #if (CONFIG_SYS_NUM_FM1_10GEC >= 3) |
| 92 | 107 | #define FM_TGEC_INFO_INITIALIZER2(idx, n) \ |