Commit cc285c565aad1c25612ddfc4690ff201970a68f0
1 parent
87108cf20a
Exists in
v2017.01-smarct4x
and in
34 other branches
x86: Move common Chromebook config into a separate file
Since Chromebooks mostly have similar configuration, put it in a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Showing 2 changed files with 69 additions and 60 deletions Side-by-side Diff
include/configs/chromebook_link.h
| ... | ... | @@ -14,66 +14,7 @@ |
| 14 | 14 | #define __CONFIG_H |
| 15 | 15 | |
| 16 | 16 | #include <configs/x86-common.h> |
| 17 | - | |
| 18 | - | |
| 19 | -#define CONFIG_SYS_MONITOR_LEN (1 << 20) | |
| 20 | - | |
| 21 | -#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 | |
| 22 | -#define CONFIG_BOARD_EARLY_INIT_F | |
| 23 | -#define CONFIG_MISC_INIT_R | |
| 24 | - | |
| 25 | -#define CONFIG_NR_DRAM_BANKS 8 | |
| 26 | -#define CONFIG_X86_MRC_ADDR 0xfffa0000 | |
| 27 | -#define CONFIG_CACHE_MRC_SIZE_KB 512 | |
| 28 | - | |
| 29 | -#define CONFIG_X86_SERIAL | |
| 30 | - | |
| 31 | -#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ | |
| 32 | - PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ | |
| 33 | - {PCI_VENDOR_ID_INTEL, \ | |
| 34 | - PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ | |
| 35 | - {PCI_VENDOR_ID_INTEL, \ | |
| 36 | - PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ | |
| 37 | - {PCI_VENDOR_ID_INTEL, \ | |
| 38 | - PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} | |
| 39 | - | |
| 40 | -#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin | |
| 41 | -#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 | |
| 42 | - | |
| 43 | -#define CONFIG_PCI_MEM_BUS 0xe0000000 | |
| 44 | -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
| 45 | -#define CONFIG_PCI_MEM_SIZE 0x10000000 | |
| 46 | - | |
| 47 | -#define CONFIG_PCI_PREF_BUS 0xd0000000 | |
| 48 | -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS | |
| 49 | -#define CONFIG_PCI_PREF_SIZE 0x10000000 | |
| 50 | - | |
| 51 | -#define CONFIG_PCI_IO_BUS 0x1000 | |
| 52 | -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
| 53 | -#define CONFIG_PCI_IO_SIZE 0xefff | |
| 54 | - | |
| 55 | -#define CONFIG_SYS_EARLY_PCI_INIT | |
| 56 | -#define CONFIG_PCI_PNP | |
| 57 | - | |
| 58 | -#define CONFIG_BIOSEMU | |
| 59 | -#define VIDEO_IO_OFFSET 0 | |
| 60 | -#define CONFIG_X86EMU_RAW_IO | |
| 61 | - | |
| 62 | -#define CONFIG_CROS_EC | |
| 63 | -#define CONFIG_CROS_EC_LPC | |
| 64 | -#define CONFIG_CMD_CROS_EC | |
| 65 | -#define CONFIG_ARCH_EARLY_INIT_R | |
| 66 | - | |
| 67 | -#undef CONFIG_ENV_IS_NOWHERE | |
| 68 | -#undef CONFIG_ENV_SIZE | |
| 69 | -#define CONFIG_ENV_SIZE 0x1000 | |
| 70 | -#define CONFIG_ENV_SECT_SIZE 0x1000 | |
| 71 | -#define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 72 | -#define CONFIG_ENV_OFFSET 0x003f8000 | |
| 73 | - | |
| 74 | -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ | |
| 75 | - "stdout=vga,serial\0" \ | |
| 76 | - "stderr=vga,serial\0" | |
| 17 | +#include <configs/x86-chromebook.h> | |
| 77 | 18 | |
| 78 | 19 | #endif /* __CONFIG_H */ |
include/configs/x86-chromebook.h
| 1 | +/* | |
| 2 | + * | |
| 3 | + * Copyright (c) 2015 Google, Inc | |
| 4 | + * | |
| 5 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | + */ | |
| 7 | + | |
| 8 | +#ifndef _X86_CHROMEBOOK_H | |
| 9 | +#define _X86_CHROMEBOOK_H | |
| 10 | + | |
| 11 | +#define CONFIG_SYS_MONITOR_LEN (1 << 20) | |
| 12 | + | |
| 13 | +#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 | |
| 14 | +#define CONFIG_BOARD_EARLY_INIT_F | |
| 15 | +#define CONFIG_MISC_INIT_R | |
| 16 | + | |
| 17 | +#define CONFIG_NR_DRAM_BANKS 8 | |
| 18 | +#define CONFIG_X86_MRC_ADDR 0xfffa0000 | |
| 19 | +#define CONFIG_CACHE_MRC_SIZE_KB 512 | |
| 20 | + | |
| 21 | +#define CONFIG_X86_SERIAL | |
| 22 | + | |
| 23 | +#define CONFIG_SCSI_DEV_LIST \ | |
| 24 | + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ | |
| 25 | + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ | |
| 26 | + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ | |
| 27 | + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \ | |
| 28 | + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI} | |
| 29 | + | |
| 30 | +#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin | |
| 31 | +#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 | |
| 32 | + | |
| 33 | +#define CONFIG_PCI_MEM_BUS 0xe0000000 | |
| 34 | +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
| 35 | +#define CONFIG_PCI_MEM_SIZE 0x10000000 | |
| 36 | + | |
| 37 | +#define CONFIG_PCI_PREF_BUS 0xd0000000 | |
| 38 | +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS | |
| 39 | +#define CONFIG_PCI_PREF_SIZE 0x10000000 | |
| 40 | + | |
| 41 | +#define CONFIG_PCI_IO_BUS 0x1000 | |
| 42 | +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
| 43 | +#define CONFIG_PCI_IO_SIZE 0xefff | |
| 44 | + | |
| 45 | +#define CONFIG_SYS_EARLY_PCI_INIT | |
| 46 | +#define CONFIG_PCI_PNP | |
| 47 | + | |
| 48 | +#define CONFIG_BIOSEMU | |
| 49 | +#define VIDEO_IO_OFFSET 0 | |
| 50 | +#define CONFIG_X86EMU_RAW_IO | |
| 51 | + | |
| 52 | +#define CONFIG_CROS_EC | |
| 53 | +#define CONFIG_CROS_EC_LPC | |
| 54 | +#define CONFIG_CMD_CROS_EC | |
| 55 | +#define CONFIG_ARCH_EARLY_INIT_R | |
| 56 | + | |
| 57 | +#undef CONFIG_ENV_IS_NOWHERE | |
| 58 | +#undef CONFIG_ENV_SIZE | |
| 59 | +#define CONFIG_ENV_SIZE 0x1000 | |
| 60 | +#define CONFIG_ENV_SECT_SIZE 0x1000 | |
| 61 | +#define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 62 | +#define CONFIG_ENV_OFFSET 0x003f8000 | |
| 63 | + | |
| 64 | +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ | |
| 65 | + "stdout=vga,serial\0" \ | |
| 66 | + "stderr=vga,serial\0" | |
| 67 | + | |
| 68 | +#endif |