Commit cc4d1226585fa2544b5116702b02eacbb7aa48a1

Authored by Kumar Gala
1 parent ffa37fc98d
Exists in master and in 56 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

fsl_esdhc: Always stop clock before changing frequency

We need to stop the clocks on 83xx/85xx as well as imx.  No need to make
this code conditional to just imx.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Stefano Babic <sbabic@denx.de>

Showing 2 changed files with 4 additions and 10 deletions Side-by-side Diff

drivers/mmc/fsl_esdhc.c
1 1 /*
2   - * Copyright 2007, Freescale Semiconductor, Inc
  2 + * Copyright 2007,2010 Freescale Semiconductor, Inc
3 3 * Andy Fleming
4 4 *
5 5 * Based vaguely on the pxa mmc code:
6 6  
... ... @@ -265,18 +265,13 @@
265 265  
266 266 clk = (pre_div << 8) | (div << 4);
267 267  
268   - /* On imx the clock must be stopped before changing frequency */
269   - if (cfg->clk_enable)
270   - esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  268 + esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
271 269  
272 270 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
273 271  
274 272 udelay(10000);
275 273  
276   - clk = SYSCTL_PEREN;
277   - /* On imx systems the clock must be explicitely enabled */
278   - if (cfg->clk_enable)
279   - clk |= SYSCTL_CKEN;
  274 + clk = SYSCTL_PEREN | SYSCTL_CKEN;
280 275  
281 276 esdhc_setbits32(&regs->sysctl, clk);
282 277 }
... ... @@ -2,7 +2,7 @@
2 2 * FSL SD/MMC Defines
3 3 *-------------------------------------------------------------------
4 4 *
5   - * Copyright 2007-2008, Freescale Semiconductor, Inc
  5 + * Copyright 2007-2008,2010 Freescale Semiconductor, Inc
6 6 *
7 7 * This program is free software; you can redistribute it and/or
8 8 * modify it under the terms of the GNU General Public License as
... ... @@ -148,7 +148,6 @@
148 148 struct fsl_esdhc_cfg {
149 149 u32 esdhc_base;
150 150 u32 no_snoop;
151   - u32 clk_enable;
152 151 };
153 152  
154 153 /* Select the correct accessors depending on endianess */