Modify SBC8641D to use new Freescale PCI routines

PCI-Express sockets 1 and 2 verified working with Intel Pro/1000 PT adapter. Signed-off-by: Joe Hamman <joe.hamman@embeddedspecialties.com> Signde-off-by: Jon Loeliger <jdl@freescale.com>

Modify SBC8641D to use new Freescale PCI routines
PCI-Express sockets 1 and 2 verified working with Intel Pro/1000 PT adapter. Signed-off-by: Joe Hamman <joe.hamman@embeddedspecialties.com> Signde-off-by: Jon Loeliger <jdl@freescale.com>
Joe Hamman · Jon Loeliger
1 parent c646bba646
Showing 2 changed files with 125 additions and 40 deletions Side-by-side Diff
board/sbc8641d/sbc8641d.c
include/configs/sbc8641d.h
@@ -33,6 +33,7 @@
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_86xx.h>
+#include <asm/immap_fsl_pci.h>
 #include <spd.h>
  
 #if defined(CONFIG_OF_FLAT_TREE)
@@ -60,36 +61,6 @@
 {
 	puts ("Board: Wind River SBC8641D\n");
  
-#ifdef CONFIG_PCI
-
-	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_pex_t *pex1 = &immap->im_pex1;
-
-	uint devdisr = gur->devdisr;
-	uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
-	uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
-	uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
-
-	if ((io_sel == 2 || io_sel == 3 || io_sel == 5
-	     || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
-	    && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
-		debug ("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
-		debug ("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
-		if (pex1->pme_msg_det) {
-			pex1->pme_msg_det = 0xffffffff;
-			debug (" with errors.  Clearing.  Now 0x%08x",
-			       pex1->pme_msg_det);
-		}
-		debug ("\n");
-	} else {
-		puts ("PCI-EXPRESS 1: Disabled in hardware\n");
-	}
-
-#else
-	puts ("PCI-EXPRESS1: Disabled in configuration\n");
-#endif
-
 	return 0;
 }
  
  
  
  
  
  
  
@@ -244,21 +215,130 @@
 };
 #endif
  
-static struct pci_controller hose = {
+static struct pci_controller pci1_hose = {
 #ifndef CONFIG_PCI_PNP
-      config_table:pci_mpc86xxcts_config_table,
+	config_table:pci_mpc86xxcts_config_table
 #endif
 };
+#endif /* CONFIG_PCI */
  
-#endif				/* CONFIG_PCI */
+#ifdef CONFIG_PCI2
+static struct pci_controller pci2_hose;
+#endif	/* CONFIG_PCI2 */
  
-void pci_init_board (void)
+int first_free_busno = 0;
+
+void pci_init_board(void)
 {
-#ifdef CONFIG_PCI
-	extern void pci_mpc86xx_init (struct pci_controller *hose);
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	uint devdisr = gur->devdisr;
+	uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
  
-	pci_mpc86xx_init (&hose);
-#endif				/* CONFIG_PCI */
+#ifdef CONFIG_PCI1
+{
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	extern void fsl_pci_init(struct pci_controller *hose);
+	struct pci_controller *hose = &pci1_hose;
+#ifdef DEBUG
+	uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
+	uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
+#endif
+	if ((io_sel == 2 || io_sel == 3 || io_sel == 5
+	     || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
+	    && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
+		debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
+		debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
+		if (pci->pme_msg_det) {
+			pci->pme_msg_det = 0xffffffff;
+			debug(" with errors.  Clearing.  Now 0x%08x",
+			      pci->pme_msg_det);
+		}
+		debug("\n");
+
+		/* inbound */
+		pci_set_region(hose->regions + 0,
+			       CFG_PCI_MEMORY_BUS,
+			       CFG_PCI_MEMORY_PHYS,
+			       CFG_PCI_MEMORY_SIZE,
+			       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+		/* outbound memory */
+		pci_set_region(hose->regions + 1,
+			       CFG_PCI1_MEM_BASE,
+			       CFG_PCI1_MEM_PHYS,
+			       CFG_PCI1_MEM_SIZE,
+			       PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(hose->regions + 2,
+			       CFG_PCI1_IO_BASE,
+			       CFG_PCI1_IO_PHYS,
+			       CFG_PCI1_IO_SIZE,
+			       PCI_REGION_IO);
+
+		hose->region_count = 3;
+
+		hose->first_busno=first_free_busno;
+		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+		fsl_pci_init(hose);
+
+		first_free_busno=hose->last_busno+1;
+		printf ("    PCI-EXPRESS 1 on bus %02x - %02x\n",
+			hose->first_busno,hose->last_busno);
+
+	} else {
+		puts("PCI-EXPRESS 1: Disabled\n");
+	}
+}
+#else
+	puts("PCI-EXPRESS1: Disabled\n");
+#endif /* CONFIG_PCI1 */
+
+#ifdef CONFIG_PCI2
+{
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
+	extern void fsl_pci_init(struct pci_controller *hose);
+	struct pci_controller *hose = &pci2_hose;
+
+
+	/* inbound */
+	pci_set_region(hose->regions + 0,
+		       CFG_PCI_MEMORY_BUS,
+		       CFG_PCI_MEMORY_PHYS,
+		       CFG_PCI_MEMORY_SIZE,
+		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+	/* outbound memory */
+	pci_set_region(hose->regions + 1,
+		       CFG_PCI2_MEM_BASE,
+		       CFG_PCI2_MEM_PHYS,
+		       CFG_PCI2_MEM_SIZE,
+		       PCI_REGION_MEM);
+
+	/* outbound io */
+	pci_set_region(hose->regions + 2,
+		       CFG_PCI2_IO_BASE,
+		       CFG_PCI2_IO_PHYS,
+		       CFG_PCI2_IO_SIZE,
+		       PCI_REGION_IO);
+
+	hose->region_count = 3;
+
+	hose->first_busno=first_free_busno;
+	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+	fsl_pci_init(hose);
+
+	first_free_busno=hose->last_busno+1;
+	printf ("    PCI-EXPRESS 2 on bus %02x - %02x\n",
+		hose->first_busno,hose->last_busno);
+}
+#else
+	puts("PCI-EXPRESS 2: Disabled\n");
+#endif /* CONFIG_PCI2 */
+
 }
  
 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
@@ -49,8 +49,10 @@
  
 #define CFG_RESET_ADDRESS    0xfff00100
  
-#undef CONFIG_PCI
-#define CONFIG_FSL_PCI_INIT	1
+#define CONFIG_PCI		1	/* Enable PCIE */
+#define CONFIG_PCI1		1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCI2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
  
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
@@ -94,6 +96,9 @@
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
+
+#define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR		(CFG_CCSRBAR+0x9000)
  
 /*
  * DDR Setup
...	...	@@ -33,6 +33,7 @@
33	33	#include <pci.h>
34	34	#include <asm/processor.h>
35	35	#include <asm/immap_86xx.h>
	36	+#include <asm/immap_fsl_pci.h>
36	37	#include <spd.h>
37	38
38	39	#if defined(CONFIG_OF_FLAT_TREE)
...	...	@@ -60,36 +61,6 @@
60	61	{
61	62	puts ("Board: Wind River SBC8641D\n");
62	63
63		-#ifdef CONFIG_PCI
64		-
65		- volatile immap_t immap = (immap_t ) CFG_CCSRBAR;
66		- volatile ccsr_gur_t *gur = &immap->im_gur;
67		- volatile ccsr_pex_t *pex1 = &immap->im_pex1;
68		-
69		- uint devdisr = gur->devdisr;
70		- uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
71		- uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
72		- uint pex1_agent = (host1_agent == 0) \|\| (host1_agent == 1);
73		-
74		- if ((io_sel == 2 \|\| io_sel == 3 \|\| io_sel == 5
75		- \|\| io_sel == 6 \|\| io_sel == 7 \|\| io_sel == 0xF)
76		- && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
77		- debug ("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
78		- debug ("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
79		- if (pex1->pme_msg_det) {
80		- pex1->pme_msg_det = 0xffffffff;
81		- debug (" with errors. Clearing. Now 0x%08x",
82		- pex1->pme_msg_det);
83		- }
84		- debug ("\n");
85		- } else {
86		- puts ("PCI-EXPRESS 1: Disabled in hardware\n");
87		- }
88		-
89		-#else
90		- puts ("PCI-EXPRESS1: Disabled in configuration\n");
91		-#endif
92		-
93	64	return 0;
94	65	}
95	66
96	67
97	68
98	69
99	70
100	71
101	72
...	...	@@ -244,21 +215,130 @@
244	215	};
245	216	#endif
246	217
247		-static struct pci_controller hose = {
	218	+static struct pci_controller pci1_hose = {
248	219	#ifndef CONFIG_PCI_PNP
249		- config_table:pci_mpc86xxcts_config_table,
	220	+ config_table:pci_mpc86xxcts_config_table
250	221	#endif
251	222	};
	223	+#endif /* CONFIG_PCI */
252	224
253		-#endif /* CONFIG_PCI */
	225	+#ifdef CONFIG_PCI2
	226	+static struct pci_controller pci2_hose;
	227	+#endif /* CONFIG_PCI2 */
254	228
255		-void pci_init_board (void)
	229	+int first_free_busno = 0;
	230	+
	231	+void pci_init_board(void)
256	232	{
257		-#ifdef CONFIG_PCI
258		- extern void pci_mpc86xx_init (struct pci_controller *hose);
	233	+ volatile immap_t immap = (immap_t ) CFG_CCSRBAR;
	234	+ volatile ccsr_gur_t *gur = &immap->im_gur;
	235	+ uint devdisr = gur->devdisr;
	236	+ uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
259	237
260		- pci_mpc86xx_init (&hose);
261		-#endif /* CONFIG_PCI */
	238	+#ifdef CONFIG_PCI1
	239	+{
	240	+ volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CFG_PCI1_ADDR;
	241	+ extern void fsl_pci_init(struct pci_controller *hose);
	242	+ struct pci_controller *hose = &pci1_hose;
	243	+#ifdef DEBUG
	244	+ uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
	245	+ uint pex1_agent = (host1_agent == 0) \|\| (host1_agent == 1);
	246	+#endif
	247	+ if ((io_sel == 2 \|\| io_sel == 3 \|\| io_sel == 5
	248	+ \|\| io_sel == 6 \|\| io_sel == 7 \|\| io_sel == 0xF)
	249	+ && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
	250	+ debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
	251	+ debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
	252	+ if (pci->pme_msg_det) {
	253	+ pci->pme_msg_det = 0xffffffff;
	254	+ debug(" with errors. Clearing. Now 0x%08x",
	255	+ pci->pme_msg_det);
	256	+ }
	257	+ debug("\n");
	258	+
	259	+ /* inbound */
	260	+ pci_set_region(hose->regions + 0,
	261	+ CFG_PCI_MEMORY_BUS,
	262	+ CFG_PCI_MEMORY_PHYS,
	263	+ CFG_PCI_MEMORY_SIZE,
	264	+ PCI_REGION_MEM \| PCI_REGION_MEMORY);
	265	+
	266	+ /* outbound memory */
	267	+ pci_set_region(hose->regions + 1,
	268	+ CFG_PCI1_MEM_BASE,
	269	+ CFG_PCI1_MEM_PHYS,
	270	+ CFG_PCI1_MEM_SIZE,
	271	+ PCI_REGION_MEM);
	272	+
	273	+ /* outbound io */
	274	+ pci_set_region(hose->regions + 2,
	275	+ CFG_PCI1_IO_BASE,
	276	+ CFG_PCI1_IO_PHYS,
	277	+ CFG_PCI1_IO_SIZE,
	278	+ PCI_REGION_IO);
	279	+
	280	+ hose->region_count = 3;
	281	+
	282	+ hose->first_busno=first_free_busno;
	283	+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	284	+
	285	+ fsl_pci_init(hose);
	286	+
	287	+ first_free_busno=hose->last_busno+1;
	288	+ printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
	289	+ hose->first_busno,hose->last_busno);
	290	+
	291	+ } else {
	292	+ puts("PCI-EXPRESS 1: Disabled\n");
	293	+ }
	294	+}
	295	+#else
	296	+ puts("PCI-EXPRESS1: Disabled\n");
	297	+#endif /* CONFIG_PCI1 */
	298	+
	299	+#ifdef CONFIG_PCI2
	300	+{
	301	+ volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CFG_PCI2_ADDR;
	302	+ extern void fsl_pci_init(struct pci_controller *hose);
	303	+ struct pci_controller *hose = &pci2_hose;
	304	+
	305	+
	306	+ /* inbound */
	307	+ pci_set_region(hose->regions + 0,
	308	+ CFG_PCI_MEMORY_BUS,
	309	+ CFG_PCI_MEMORY_PHYS,
	310	+ CFG_PCI_MEMORY_SIZE,
	311	+ PCI_REGION_MEM \| PCI_REGION_MEMORY);
	312	+
	313	+ /* outbound memory */
	314	+ pci_set_region(hose->regions + 1,
	315	+ CFG_PCI2_MEM_BASE,
	316	+ CFG_PCI2_MEM_PHYS,
	317	+ CFG_PCI2_MEM_SIZE,
	318	+ PCI_REGION_MEM);
	319	+
	320	+ /* outbound io */
	321	+ pci_set_region(hose->regions + 2,
	322	+ CFG_PCI2_IO_BASE,
	323	+ CFG_PCI2_IO_PHYS,
	324	+ CFG_PCI2_IO_SIZE,
	325	+ PCI_REGION_IO);
	326	+
	327	+ hose->region_count = 3;
	328	+
	329	+ hose->first_busno=first_free_busno;
	330	+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	331	+
	332	+ fsl_pci_init(hose);
	333	+
	334	+ first_free_busno=hose->last_busno+1;
	335	+ printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
	336	+ hose->first_busno,hose->last_busno);
	337	+}
	338	+#else
	339	+ puts("PCI-EXPRESS 2: Disabled\n");
	340	+#endif /* CONFIG_PCI2 */
	341	+
262	342	}
263	343
264	344	#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
...	...	@@ -49,8 +49,10 @@
49	49
50	50	#define CFG_RESET_ADDRESS 0xfff00100
51	51
52		-#undef CONFIG_PCI
53		-#define CONFIG_FSL_PCI_INIT 1
	52	+#define CONFIG_PCI 1 /* Enable PCIE */
	53	+#define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */
	54	+#define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */
	55	+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
54	56
55	57	#define CONFIG_TSEC_ENET /* tsec ethernet support */
56	58	#define CONFIG_ENV_OVERWRITE
...	...	@@ -94,6 +96,9 @@
94	96	#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
95	97	#define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
96	98	#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
	99	+
	100	+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
	101	+#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
97	102
98	103	/*
99	104	* DDR Setup